LH540205 [SHARP]
CMOS 8192 x 9 Asynchronous FIFO; CMOS 8192 ×9异步FIFO
| 型号： | LH540205 |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | CMOS 8192 x 9 Asynchronous FIFO |
| 文件： | 总17页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH540205
CMOS 8192 × 9 Asynchronous FIFO
Data words are read out from the LH540205’s output
port in precisely the same order that they were written in
at its input port; that is, according to a First-In, First Out
(FIFO) queue discipline. Since the addressing sequence
for a FIFO device’s memory is internally predefined, no
external addressing information is required forthe opera-
tion of the LH540205 device.
FEATURES
• Fast Access Times: 20/25/35/50 ns
• Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology
• Input Port and Output Port Have Entirely
Independent Timing
Drop-in-replacement compatibility is maintained with
both larger sizes and smaller sizes of industry-standard
nine-bit asynchronous FIFOs. The only change is in the
number of internally-stored data words implied by the
states of the Full Flag and the Half-Full Flag.
• Expandable in Width and Depth
• Full, Half-Full, and Empty Status Flags
• Data Retransmission Capability
The Retransmit (RT) control signal causes the internal
FIFO-memory-array read-address pointer to be set back
to zero, to point to the LH540205’s first physical memory
location, without affecting the internal FIFO-memory-
array write-address pointer. Thus, the Retransmit control
signal provides a mechanism whereby a block of data,
delimited by the zero physical address and the current
write-address-pointer value, may be read out repeatedly
anarbitrarynumberoftimes.Theonlyrestrictionsarethat
neither the read-address pointer nor the write-address
pointer may ‘wrap around’ during this entire process, i.e.,
advance past physical location zero after traversing the
entire memory. The retransmit facility is not available
when an LH540205 is operating in a depth-expanded
configuration.
• TTL-Compatible I/O
• Pin and Functionally Compatible with Am/IDT7205
• Control Signals Assertive-LOW for Noise Immunity
• Package: 28-Pin, 300-mil PDIP
FUNCTIONAL DESCRIPTION
The LH540205 is a FIFO (First-In, First-Out) memory
device, based on fully-staticCMOS dual-port SRAMtech-
nology, capable of storing up to 8192 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540205 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.
PIN CONNECTIONS
The input and output ports operate entirely inde-
pendently of each other, unless the LH540205 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOWcontrol inputs:Write (W) fordata entry atthe
inputport, orRead (R) fordata retrieval atthe outputport.
28-PIN PDIP
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W
D8
D3
D2
D1
D0
XI
VCC
D4
1
2
3
D5
4
D6
Full, Half-Full, and Empty status flags monitor the
extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional wordsinto analready-full
LH540205, orbyattemptingtoreadadditional wordsfrom
an already-empty LH540205. When an LH540205 is
operating inadepth-cascadedconfiguration,theHalf-Full
Flag is not available.
5
D7
6
FL/RT
RS
7
8
EF
FF
Q0
Q1
9
XO/HF
Q7
10
11
12
13
14
Q6
Q5
Q2
Q3
Q8
Q4
R
VSS
540205-2D
Figure 1. Pin Connections for PDIP Packages
1
LH540205
CMOS 8192 × 9 Asynchronous FIFO
allows a deeper ‘effective FIFO’ to be implemented by
using two or more individual LH540205 devices, without
incurring additional latency (‘fallthrough’ or ‘bub-
blethrough’) delays, and without the necessity of storing
and retrieving any given datawordmore thanonce. In this
cascaded operating mode, one LH540205 device must
be designated as the ‘first-load’ or ‘master’ device, by
groundingitsFirst-Load(FL/RT) control input;the remain-
ingLH540205devicesaredesignatedas‘slaves,’bytying
their FL/RT inputs HIGH. Because of the need to share
control signals on pins, the Half-Full Flag and the retrans-
mission capability are not available for either ‘master’ or
‘slave’ LH540205 devices operating in cascaded mode.
FUNCTIONAL DESCRIPTION (cont’d)
The Reset (RS) control signal returns the LH540205
to an initial state, empty and ready to be filled. An
LH540205 should beresetduringeverysystem power-up
sequence. A reset operation causes the internal FIFO-
memory-array write-address pointer, as well as the read-
address pointer, to be set back to zero, to point to the
LH540205’s first physical memory location. Any informa-
tion which previously had been stored within the
LH540205 is not recoverable after a reset operation.
Acascading(depth-expansion)scheme maybeimple-
mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/HF) output signal. This scheme
DATA INPUTS
RESET
LOGIC
RS
D0 - D8
INPUT
PORT
CONTROL
OUTPUT
PORT
CONTROL
W
R
DUAL-PORT
RAM
ARRAY
WRITE
POINTER
READ
POINTER
8192 x 9
. . .
DATA OUTPUTS
Q0 - Q8
EF
FF
FLAG
LOGIC
EXPANSION
LOGIC
FL/RT
XI
XO/HF
540205-1
Figure 2. LH540205 Block Diagram
2
CMOS 8192 × 9 Asynchronous FIFO
LH540205
PIN DESCRIPTIONS
PIN
D0 – D8
Q0 – Q8
W
PIN TYPE 1
DESCRIPTION
PIN
XO/HF
XI
PIN TYPE 1
DESCRIPTION
Input Data Bus
Expansion Out/Half-Full Flag
Expansion In
I
O/Z
I
O
I
Output Data Bus
Write Request
Read Request
Empty Flag
FL/RT
RS
First Load/Retransmit
Reset
I
R
I
I
EF
VCC
Positive Power Supply
Ground
O
O
V
V
FF
Full Flag
VSS
NOTE:
1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
operation. The Full Flag is deasserted (FF = HIGH) after
the next rising edge of R releases another memory loca-
tion. (See Table 3.)
OPERATIONAL DESCRIPTION
Reset
The LH540205 is reset wheneverthe Resetinput(RS)
is taken LOW. A reset operation initializes both the read-
address pointer and the write-address pointer to point to
location zero, the first physical memory location. During
a reset operation, the state of the XI and FL/RT inputs
determines whether the device is in standalone mode or
in depth-cascaded mode. (See Tables 1 and 2.) The
reset operation forces the Empty Flag EF to be asserted
(EF = LOW), and the Half-Full Flag HF and the Full Flag
FF to be deasserted (HF = FF = HIGH); the Data Outpins
Read
A read cycle is initiated by a falling edge of the Read
(R) control input. Read data becomes valid at the data
outputs (Q – Q ) after a time t from the falling edge of
R. After R goes HIGH, the data outputs return to a
high-impedance state. Read operations may occur inde-
pendently of any ongoing write operations. However, a
read operation is possible only if the FIFO is not empty
(i.e., if the Empty Flag EF is HIGH).
0
8
A
(D – D ) are forced into a high-impedance state.
0
8
The LH540205’s internal read-address and write-
address pointers operate in such a way that consecutive
read operations always access data words in the same
order that they were written. The Empty Flag is asserted
(EF = LOW) after that falling edge of R which accesses
the last available data word in the FIFO memory. EF is
deasserted (EF = HIGH) after the next rising edge of W
loads another valid data word. (See Table 3.)
A reset operation is required whenever the LH540205
first is powered up. The Read (R) and Write (W) inputs
may be in any state when the reset operation is initiated;
but they must be HIGH, before the reset operation is
terminated by a rising edge of RS, by a time t
(for
RRSS
Read) or t
(for Write) respectively. (See Figure 9.)
WRSS
Write
Data Flow-Through
A write cycle is initiated by a falling edge of the Write
(W) control input. Data setup times and hold times must
Read-data flow-through mode occurs when the Read
(R) control input is broughtLOW while the FIFO is empty,
andis heldLOW in anticipationofa writecycle. Attheend
of the nextwrite cycle, the Empty Flag EF momentarily is
deasserted, and the data word just written becomes
be observed for the data inputs (D – D ). Write opera-
0
8
tions may occur independently of any ongoing read op-
erations. However, a write operation is possible only ifthe
FIFO is not full, (i.e., if the Full Flag FF is HIGH).
available at the data outputs (Q – Q ) after a maxi-
0
8
At thefalling edge of W forthe firstwrite operationafter
the memory is half filled, the Half-Full Flag is asserted
(HF = LOW). It remains asserted until the difference
between the write pointer and the read pointer indicates
that the data words remaining in the LH540205 are filling
the FIFO memory to less than or equal to one-half of its
total capacity. The Half-Full Flag is deasserted
(HF = HIGH) by the appropriate rising edge of R. (See
Table 3.)
mumtimeoft
+t .Additional write operationsmayoccur
A
WEF
while the R input remains LOW; but only data from the
first write operation flows through to the data outputs.
Additional data words, if any, may be accessed only by
toggling R.
Write-data flow-through mode occurs when the Write
(W) input is brought LOW while the FIFO is full, and is
held LOW in anticipation of a read cycle. At the end of the
read cycle, the Full Flag momentarily is deasserted, but
then immediately is reasserted in response to W being
held LOW. A data word is written into the FIFO on the
rising edge of W, which may occur no sooner than
TheFull Flag isasserted(FF = LOW)at thefalling edge
of W for the write operation which fills the last available
location in the FIFO memory array. FF = LOW inhibits
further write operations until FF is cleared by a valid read
t
+ t
after the read operation.
RFF
WPW
3
LH540205
CMOS 8192 × 9 Asynchronous FIFO
Table 2. Expansion-Pin Usage According to
Grouping Mode
OPERATIONAL DESCRIPTION (cont’d)
Retransmit
CASCADED CASCADED
The FIFO can be made to reread previously-read data
by means of the Retransmit function. A retransmit opera-
tion is initiated by pulsing the RT input LOW. Both R and
W must be deasserted (HIGH) for the duration of the
retransmit pulse. The FIFO’s internal read-address
pointer is reset to point to location zero, the first physical
memory location, while the internal write-address
pointer remains unchanged.
I/O
PIN
STANDALONE
MASTER
SLAVE
From XO From XO
XI
Grounded
(n-1st
FIFO)
(n-1st
FIFO)
I
To XI
To XI
Becomes
HF
XO/HF
FL/RT
(n+1st
FIFO)
(n+1st
FIFO)
O
I
After a retransmit operation, those data words in the
region in between the read-address pointer and the
write-address pointer may be reaccessed by subsequent
read operations. A retransmit operation may affect the
state of the status flags FF, HF, and EF, depending on
the relocation of the read-address pointer. There is no
restriction on the number of times that a block of data
within an LH540205 may be read out, by repeating the
retransmit operationand thesubsequent read operations.
Grounded
(Logic
LOW)
Becomes
RT
Logic
HIGH
Table 3. Status Flags
NUMBER OF UNREAD DATA
WORDS PRESENT WITHIN
8192 × 9 FIFO
FF
HF
EF
The maximum length of a data block which may be
retransmitted is 8192 words. Note that if the write-address
pointer ever ‘wraps around’ (i.e., passes location zero
more than once) during a sequence of retransmit opera-
tions, some data words will be lost.
0
H
H
H
L
H
H
L
L
H
H
H
1 to 4096
4097 to 8191
8192
The Retransmit function is not available when the
LH540205 is operating in depth-cascaded mode,
because the FL/RT control pin must be used for first-load
selection rather than for retransmission control.
L
Table 1. Grouping-Mode Determination
During a Reset Operation
FL/
RT
XO/HF
XI
FL/RT
XI
MODE
USAGE USAGE USAGE
Cascaded
Slave 2
1
H
H
XO
XI
FL
Cascaded
Master 2
1
H
L
L
XI
FL
XO
Standalone
X
HF
(none)
RT
NOTES:
1. A reset operation forces XO HIGH for the nth FIFO, thus forcing
XI HIGH for the (n+1)st FIFO.
2. The terms ‘master’ and ‘slave’ refer to operation in depth-cas-
caded grouping mode.
3. H = HIGH; L = LOW; X = Don’t Care.
4
CMOS 8192 × 9 Asynchronous FIFO
LH540205
Width Expansion
OPERATIONAL MODES
Word-width expansion is implementedby placing mul-
tiple LH540205 devices in parallel. Each LH540205
should be configured for standalone mode. In this ar-
rangement, the behaviorof the status flags is identical for
all devices; so, in principle, a representative value for
each oftheseflagscouldbe derivedfromanyonedevice.
In practice, it is better to derive ‘composite’ flag values
using external logic, since there may be minor speed
variations between different actual devices. (See Figures
3 and 4.)
Standalone Configuration
When depth cascading is not required for a given
application, the LH540205 is placed in standalone mode
by tying the Expansion In input (XI) to ground. This
input is internally sampled during a resetoperation. (See
Table 1.)
HF
LH540205
XI
R
W
WRITE
READ
9
9
EF
RT
DATA OUT
Q0 - Q8
DATA IN
D0 - D8
FF
FULL FLAG
RESET
EMPTY FLAG
RETRANSMIT
RS
540205-17
Figure 3. Standalone FIFO (8192 × 9)
DATA IN
D0 - D17
18
HF
HF
9
9
W
FF
RS
W
EF
R
WRITE
EMPTY FLAG
READ
LH540205
R
FULL FLAG
LH540205
RS
RESET
RT
9
RT
9
RETRANSMIT
18
XI
XI
DATA OUT
Q0 - Q17
540205-18
Figure 4. FIFO Word-Width Expansion (8192 × 18)
5
LH540205
CMOS 8192 × 9 Asynchronous FIFO
all devices are tied together. Likewise, only one
LH540205 is enabled during any given read cycle; thus,
the common Data Out outputs of all devices are wire-
ORed together
OPERATIONAL MODES (cont’d)
Depth Cascading
Depth cascading is implemented by configuring the
requirednumber ofLH540205sin depth-cascadedmode.
Inthis arrangement, theFIFOsare connectedin acircular
fashion, with the Expansion Out output (XO) of each
device tied to the Expansion In input (XI) of the next
device. One FIFO in the cascade must be designated as
the ‘first-load’ device, by tying its FirstLoad input (FL/RT)
to ground. All other devices must have their FL/RT inputs
tied HIGH. In this mode, W and R signals are shared by
all devices, whilelogic withineachLH540205 controlsthe
steering of data. Only one LH540205 is enabled during
any given write cycle;thus, the common Data In inputs of
In depth-cascaded mode, external logic should be
used to generate a composite Full Flag and a composite
Empty Flag, by ANDing the FF outputs of all LH540205
devicestogetherandANDingtheEFoutputsofall devices
together. Since FF and EF are assertive-LOW signals,
this ‘ANDing’ actually is implemented using an assertive-
HIGH physical OR gate. The Half-Full Flag and the
Retransmit function are not available in depth-cas-
caded mode.
XO
W
R
9
9
9
9
DATA OUT
Q0 - Q8
DATA IN
D0 - D8
LH540205
FF
EF
FL
Vcc
RS
XI
XO
9
9
FF
EF
FL
LH540205
EMPTY
FULL
Vcc
RS
XI
XO
9
9
FF
EF
FL
LH540205
RS
RS
XI
540205-19
Figure 5. FIFO Depth Cascading (24576 × 9)
6
CMOS 8192 × 9 Asynchronous FIFO
LH540205
of another LH540205, which is operating in the opposite
direction, to formasingle bidirectionalbusinterface.Care
must be taken to assure that the appropriate read, write,
and flag signals are routed to each system. Both word-
width expansion and depth cascading may be used in
bidirectional applications.
OPERATIONAL MODES (cont’d)
Compound FIFO Expansion
A combination of word-width expansion and depth
cascading may be implemented easily by operating
groups of depth-cascaded FIFOs in parallel.
Bidirectional FIFO Operation
Bidirectional data buffering between two systems may
be implemented by operating LH540205 devices in par-
allel, butin oppositedirections. TheData In inputsofeach
LH540205 are tied tothe corresponding DataOut outputs
Q0 - Q8
Q0 - Q17
Q0 - QN-10
Q0 - QN-1
DATA OUT
R
LH540205
DEPTH EXPANSION
BLOCK
LH540205
DEPTH EXPANSION
BLOCK
LH540205
DEPTH EXPANSION
BLOCK
W
RS
ARRAY STORES
N-BIT WORDS.
DATA IN
D9 - DN-1
D18 - DN-1
DN-9 - DN-1
D0 - DN-1
540205-20
Figure 6. Compound FIFO Expansion
Wa
Rb
EFb
FFa
LH540205
HFb
RTb
RS
Da0 - 8
Qb0 - 8
XI
SYSTEM A
SYSTEM B
Qa0 - 8
Db0 - 8
Ra
Wb
LH540205
EFa
FFb
HFa
RTa
RS
XI
540205-21
Figure 7. Bidirectional FIFO Operation
(8192 × 9 × 2)
7
LH540205
CMOS 8192 × 9 Asynchronous FIFO
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
Supply Voltage to VSS Potential
Signal Pin Voltage to VSS Potential 2
DC Output Current 3
–0.5 V to 7 V
–0.5 V to VCC + 0.5 V (not to exceed 7 V)
±50 mA
Storage Temperature Range
Power Dissipation (Package Limit)
–65oC to 150oC
1.0 W
DC Voltage Applied to Outputs In High-Z State
–0.5 V to VCC + 0.5 V (not to exceed 7 V)
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device.
This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions
outside of those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGE
SYMBOL
PARAMETER
Temperature, Ambient
Supply Voltage
MIN
0
MAX
70
UNIT
°C
V
TA
VCC
VSS
4.5
0
5.5
0
Supply Voltage
V
VIL
Logic LOW Input Voltage 1
–0.5
2.0
0.8
V
VIH
Logic HIGH Input Voltage
V
+ 0.5
V
CC
NOTE:
1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL
PARAMETER
TEST CONDITIONS
VCC = 5.5 V, VIN = 0 V to VCC
R ≥ VIH, 0 V ≤ VOUT ≤ VCC
IOH = –2.0 mA
MIN
–10
–10
2.4
MAX
10
UNIT
µA
µA
V
ILI
Input Leakage Current
Output Leakage Current
Output HIGH Voltage
Output LOW Voltage
ILO
10
VOH
VOL
ICC
IOL = 8.0 mA
0.4
110
15
8
V
Average Supply Current 1
Average Standby Current 1
Power Down Current 1
Measured at f = 33 MHz
All Inputs = VIH
mA
mA
mA
ICC2
ICC3
All Inputs = VCC – 0.2 V
NOTE:
1. ICC, ICC2, and ICC3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open.
8
CMOS 8192 × 9 Asynchronous FIFO
LH540205
AC TEST CONDITIONS
PARAMETER
+5 V
RATING
Input Pulse Levels
V
to 3 V
SS
1.1k Ω
680 Ω
Input Rise and Fall Times (10% to 90%)
Input Timing Reference Levels
Output Reference Levels
Output Load, Timing Tests
DEVICE
UNDER
TEST
5 ns
1.5 V
1.5 V
*
30 pF
Figure 8
1,2
CAPACITANCE
*
INCLUDES JIG AND SCOPE CAPACITANCES
540205-4
PARAMETER
CIN (Input Capacitance)
COUT (Output Capacitance)
RATING
5 pF
Figure 8. Output Load Circuit
7 pF
NOTES:
1. Sample tested only.
2. Capacitances are maximum values at 25oC, measured at 1.0 MHz,
with VIN = 0 V.
9
LH540205
CMOS 8192 × 9 Asynchronous FIFO
1
AC ELECTRICAL CHARACTERISTICS (Over Operating Range)
tA = 20 ns
MIN MAX
READ CYCLE TIMING
tA = 25 ns
tA = 35 ns
tA = 50 ns
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
Read Cycle Time
30
–
–
20
–
35
–
–
25
–
45
–
–
35
–
65
–
–
50
–
ns
ns
ns
ns
ns
ns
tA
Access Time
tRR
Read Recovery Time
Read Pulse Width 2
Data Bus Active from Read LOW 3
Data Bus Active from Write HIGH 3,4
10
20
5
10
25
5
10
35
5
15
50
5
tRPW
tRLZ
tWLZ
–
–
–
–
–
–
–
–
10
–
10
–
10
–
10
–
Data Held Valid from Read Pulse
HIGH
Data Bus High-Z from Read HIGH 3
tDV
5
–
–
5
–
–
5
–
–
5
–
–
ns
ns
tRHZ
15
15
15
20
WRITE CYCLE TIMING
tWC
tWPW
tWR
tDS
Write Cycle Time
Write Pulse Width 2
Write Recovery Time
Data Setup Time
Data Hold Time
30
20
10
12
0
–
–
–
–
–
35
25
10
15
0
–
–
–
–
–
45
35
10
18
0
–
–
–
–
–
65
50
15
30
0
–
–
–
–
–
ns
ns
ns
ns
ns
tDH
RESET TIMING
tRSC
tRS
Reset Cycle Time
30
–
–
–
–
–
35
–
–
–
–
–
45
35
10
35
35
–
–
–
–
–
65
50
15
50
50
–
–
–
–
–
ns
ns
ns
ns
ns
Reset Pulse Width 2
Reset Recovery Time
Read HIGH to RS HIGH
Write HIGH to RS HIGH
20
10
20
20
25
10
25
25
tRSR
tRRSS
tWRSS
RETRANSMIT TIMING 5
tRTC
tRT
Retransmit Cycle Time
Retransmit Pulse Width 2
Retransmit Recovery Time
30
20
10
–
–
–
35
25
10
–
–
–
45
35
10
–
–
–
65
50
15
–
–
–
ns
ns
ns
tRTR
FLAG TIMING
tEFL
Reset LOW to Empty Flag LOW
–
–
30
–
–
35
35
–
–
45
45
–
–
65
65
ns
ns
Reset LOW to Half-Full and Full
Flags HIGH
tHFH,FFH
30
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
Read LOW to Empty Flag LOW
Read HIGH to Full Flag HIGH
Write HIGH to Empty Flag HIGH
Write LOW to Full Flag LOW
–
–
–
–
–
–
20
20
20
20
20
20
–
–
–
–
–
–
25
25
25
25
25
25
–
–
–
–
–
–
35
35
35
35
35
35
–
–
–
–
–
–
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
Write LOW to Half-Full Flag LOW
Read HIGH to Half-Full Flag HIGH
EXPANSION TIMING
tXOL
tXOH
tXI
Expansion Out LOW
–
20
20
–
–
–
25
25
–
–
–
35
35
–
–
–
50
50
–
ns
ns
ns
ns
ns
Expansion Out HIGH
–
Expansion In Pulse Width
Expansion In Recovery Time
Expansion in Setup Time
20
10
10
25
10
10
35
10
15
50
10
15
tXIR
–
–
–
–
tXIS
–
–
–
–
NOTES:
1. All timing measurements are performed at ‘AC Test Condition’ levels.
2. Pulse widths less than minimum value are not allowed.
10
CMOS 8192 × 9 Asynchronous FIFO
LH540205
TIMING DIAGRAMS
tRSC
tRS
RS
R,W
tRRSS
tWRSS
tRSR
tEFL
EF
tFFH tHFH
,
FF,HF
NOTES:
1. tRSC = tRS + tRSR
.
2. W and R ≥ VIH around the rising edge of RS.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
540205-14
Figure 9. Reset Timing
tRPW
tRC
tRR
tA
tA
R
tRLZ
t RHZ
tDV
Q0 - Q8
VALID DATA OUT
tWC
VALID DATA OUT
tWPW
tWR
W
t DH
t DS
D0 - D8
VALID DATA IN
VALID DATA IN
540205-5
Figure 10. Asynchronous Write and Read Operation
11
LH540205
CMOS 8192 × 9 Asynchronous FIFO
TIMING DIAGRAMS (cont’d)
LAST WRITE
FIRST READ
R
W
tRFF
tWFF
FF
540205-6
Figure 11. Full Flag From Last Write to First Read
LAST READ
FIRST WRITE
W
R
tREF
tWEF
EF
NOTE: The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
540205-7
Figure 12. Empty Flag From Last Read to First Write
12
CMOS 8192 × 9 Asynchronous FIFO
LH540205
TIMING DIAGRAMS (cont’d)
D0 - D8
VALID DATA IN
W
tRPE
R
EF
tREF
tWEF
tWLZ
tA
Q0 - Q8
VALID DATA OUT
NOTES:
1. tRPE = tRPW
2. tRPE: Effective Read Pulse Width after Empty Flag HIGH.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
540205-8
Figure 13. Read Data Flow-Through
R
tWPF
W
tRFF
FF
t WFF
t DH
t DS
VALID DATA IN
D0 - D8
tA
Q0 - Q8
VALID DATA OUT
NOTES:
1. tWPF = tWPW.
2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
540205-9
Figure 14. Write Data Flow-Through
13
LH540205
CMOS 8192 × 9 Asynchronous FIFO
TIMING DIAGRAMS (cont’d)
W
EF
R
tWEF
tRPE
NOTES:
1. tRPE = tRPW
2. tRPE: Effective Read Pulse Width after Empty Flag HIGH.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
540205-10
Figure 15. Empty Flag Timing
R
tRFF
FF
tWPF
W
NOTES:
1. tWPF = tWPW.
2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
540205-11
Figure 16. Full Flag Timing
14
CMOS 8192 × 9 Asynchronous FIFO
LH540205
TIMING DIAGRAMS (cont’d)
HALF-FULL
OR LESS
MORE THAN
HALF-FULL
HALF-FULL
OR LESS
W
R
tWHF
tRHF
HF
540205-12
Figure 17. Half-Full Flag Timing
tRT
RT
tRTR
R,W
NOTES:
1. tRTC = tRT + tRTR
2. FF, HF, and EF may change state during retransmit; but they will
become valid by tRTC
.
.
540205-13
Figure 18. Retransmit Timing
15
LH540205
CMOS 8192 × 9 Asynchronous FIFO
TIMING DIAGRAMS (cont’d)
WRITE TO LAST
AVAILABLE
LOCATION
W
READ FROM
LAST VALID
LOCATION
R
t XOL
tXOH
t XOL
tXOH
XO
540205-15
Figure 19. Expansion-Out Timing
t XI
tXIR
XI
tXIS
WRITE TO FIRST
AVAILABLE
LOCATION
W
R
tXIS
READ FROM FIRST
VALID
LOCATION
540205-16
Figure 20. Expansion-In Timing
16
CMOS 8192 × 9 Asynchronous FIFO
PACKAGE DIAGRAMS
28DIP (DIP28-W-300)
LH540205
DETAIL
7.49 [0.295]
7.11 [0.280]
0° TO 15°
0.30 [0.012]
0.20 [0.008]
34.80 [1.370]
34.54 [1.360]
7.62 [0.300]
TYP.
3.30 [0.130]
4.57 [0.180]
MAX
3.43 [0.135]
3.18 [0.125]
2.54 [0.100]
TYP.
0.53 [0.021]
0.38 [0.015]
0.51 [0.020] MIN
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28DIP-3
28-pin, 300-mil PDIP
ORDERING INFORMATION
LH540205
D
- ##
Device Type
Package
Speed
20
25
35
50
Access Time (ns)
28-pin, 300-mil Plastic DIP (DIP28-W-300)
CMOS 8192 x 9 FIFO
Example: LH540205D-25 (CMOS 8192 x 9 FIFO, 28-pin, 600-mil DIP, 25 ns)
540205MD
17
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