SGM829 [SGMICRO]
Microprocessor Supervisory Circuit with Programmable Delay Time;
| 型号： | SGM829 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | Microprocessor Supervisory Circuit with Programmable Delay Time |
| 文件： | 总13页 (文件大小：683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM829
Microprocessor Supervisory Circuit
with Programmable Delay Time
GENERAL DESCRIPTION
FEATURES
The SGM829 family can monitor system voltages from
1.8V to 5V. When the VDD voltage falls below the preset
threshold (VIT) or the manual reset (nMR) pin is driven
low, the open-drain nRESET output is asserted. After
the VDD voltage and nMR voltage return higher than
their respective thresholds, the nRESET output
remains low within the user-adjustable delay time.
● Adjustable Reset Timeout Period: 1.25ms to 10s
● Low Quiescent Current: 0.6μA (TYP)
● High Threshold Accuracy: 1% (TYP)
● Factory-Set Detection Voltages: 1.8V to 5V
● Manual Reset (nMR) Input
● Open-Drain nRESET Output
● Available in a Green SOT-23-5 Package
The SGM829 uses a precision reference to achieve 1%
threshold accuracy. The fixed reset timeout period can
be set to 0.29ms by leaving the SRT pin open. The
programmable reset timeout period can be set from
1.25ms to 10s through an external capacitor connected
to the SRT pin. Low quiescent current makes the
SGM829 very suitable for battery-powered applications.
APPLICATIONS
Computers
Portable Equipment
Intelligent Instruments
Microprocessor Systems
Critical μP Power Monitoring
The SGM829 is available in a Green SOT-23-5 package.
TYPICAL APPLICATION
1.8V
3.3V
VDD
VDD
nRESET
SGM829-3.3
nMR SRT
VI/O
SRT
GPIO
VCORE
DSP
SGM829-1.8
nRESET
GND
GND
GND
Figure 1. Typical Application Circuit
SG Micro Corp
AUGUST2022–REV. A.1
www.sg-micro.com
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
PACKAGE/ORDERING INFORMATION
THRESHOLD
VOLTAGE (VIT) (V) DESCRIPTION
PACKAGE
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM829-1.8
SGM829-1.9
SGM829-2.5
SGM829-2.7
SGM829-2.9
SGM829-3.0
SGM829-3.3
SGM829-3.7
SGM829-4.0
SGM829-4.5
SGM829-5.0
1.67
1.77
2.33
2.52
2.7
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-5
SGM829-1.8XN5G/TR
SGM829-1.9XN5G/TR
SGM829-2.5XN5G/TR
SGM829-2.7XN5G/TR
SGM829-2.9XN5G/TR
SGM829-3.0XN5G/TR
SGM829-3.3XN5G/TR
SGM829-3.7XN5G/TR
SGM829-4.0XN5G/TR
SGM829-4.5XN5G/TR
SGM829-5.0XN5G/TR
R70XX
R72XX
R75XX
R77XX
R79XX
R3CXX
R7BXX
R7DXX
R7FXX
R81XX
R83XX
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
Tape and Reel, 3000
2.79
3.07
3.45
3.73
4.2
4.65
MARKING INFORMATION
NOTE: XX = Date Code.
YYY X X
Date Code - Week
Date Code - Year
Serial Number
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
SG Micro Corp
www.sg-micro.com
AUGUST 2022
2
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
ABSOLUTE MAXIMUM RATINGS
OVERSTRESS CAUTION
VDD to GND.......................................................... -0.3V to 7V
SRT to GND.............................................-0.3V to VDD + 0.3V
nRESET, nMR to GND......................................... -0.3V to 7V
nRESET Pin Current.....................................................±5mA
Package Thermal Resistance
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
SOT-23-5, θJA .......................................................... 245℃/W
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................4000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Input Supply Voltage Range, VDD .....................1.65V to 6.5V
SRT Pin Voltage, VSRT ...........................................VDD (MAX)
nMR Pin Voltage, VnMR ..........................................0V to 6.5V
nRESET Pin Voltage, VnRESET ................................0V to 6.5V
nRESET Pin Current, InRESET .....................0.0003mA to 5mA
Operating Junction Temperature Range......-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
AUGUST 2022
3
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
PIN CONFIGURATION
(TOP VIEW)
nRESET
1
2
3
5
4
VDD
GND
nMR
SRT
SOT-23-5
PIN DESCRIPTION
PIN
NAME
I/O
FUNCTION
Active-Low Reset Output Pin. nRESET remains low if the VDD input is below VIT or nMR is logic low. It
goes (or remains) low for the reset timeout period after the VDD voltage exceeds VIT and nMR pin is
driven high. It is recommended to connect a 10kΩ to 1MΩ pull-up resistor to this pin which enables
1
nRESET
O
the reset voltages greater than VDD
.
2
3
GND
nMR
—
I
Ground.
Manual Reset Input Pin. Pulling this pin (nMR) low will assert nRESET. nMR is internally pulled up to
VDD by a 100kΩ resistor.
Set Reset Timeout Input. Connect a capacitor between SRT and ground to set the timeout period.
The pin can be left open, but it cannot be connected to VDD. Determine the period as follows:
TD (μs) = (2.8 × 106) × CSRT (μF) + 290μs.
4
5
SRT
VDD
I
I
Supply Voltage. It is recommended to place a 0.1μF ceramic capacitor close to this pin.
NOTE: I: input, O: output.
SG Micro Corp
www.sg-micro.com
AUGUST 2022
4
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
ELECTRICAL CHARACTERISTICS
(VDD = 1.65V to 6.5V, RLRESET = 100kΩ (1), TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply Voltage Range
VDD
1.65
6.5
V
VDD = 3.3V, nRESET not asserted,
nMR, nRESET, SRT open
VDD = 6.5V, nRESET not asserted,
nMR, nRESET, SRT open
0.6
0.9
1.5
2
Supply Current (Current into VDD Pin)
IDD
μA
1.3V ≤ VDD < 1.8V, IOL = 0.4mA
1.8V ≤ VDD ≤ 6.5V, IOL = 1mA
VOL_MAX = 0.2V, InRESET = 15μA
TJ = +25℃
0.2
0.3
0.8
1.0
1.3
Low-Level Output Voltage
VOL
VPOR
VIT
V
V
Power-On Reset Voltage
-1.0
-1.3
Negative-Going Input Threshold Accuracy
%
TJ = -40℃ to +85℃
(2)
Hysteresis on VIT
VHYS
tRP0
50 × VIT
85
mV
μs
Drop = VIT - 250mV,
TJ = -40℃ to +85℃
VDD Drop to Reset Delay
nMR Internal Pull-Up Resistance
RnMR
VIH
TJ = -40℃ to +85℃
100
kΩ
Logic high
0.7 × VDD
nMR Input
V
VIL
Logic low
0.3 × VDD
SRT pin, VIN = 0V to VDD
TJ = -40℃ to +85℃
Other pins, VIN = 0V to 6.5V,
TJ = -40℃ to +85℃
,
5
5
Input Capacitance, Any Pin
CIN
pF
nMR Glitch Rejection
TJ = -40℃ to +85℃
TJ = -40℃ to +85℃
SRT open
100
240
ns
ns
nMR to Reset Propagation Delay
tnMR
tD
0.15
1.5
0.29
2.8
0.40
4.0
Reset Timeout Period
ms
CSRT = 1nF
SRT Source Current
IRAMP
TJ = -40℃ to +85℃
430
nA
V
SRT Source Threshold Voltage
VTH-RAMP TJ = -40℃ to +85℃
1.205
NOTES:
1. RLRESET is the resistor connected to the nRESET pin.
2. Guaranteed by design and not tested in production.
VDD
VIT + VHYS
VIT
VPOR
0.0V
nRESET
tMR = nMR to Reset Propagation Delay
tRP0 = VDD Drop to Reset Delay
tD = Reset Timeout Period
tRP0
tMR
tD
tD
tD
= Undefined State
nMR
0.7VDD
0.3VDD
Time
Figure 2. SGM829 Timing Diagram Showing nMR and VDD Reset Timing
SG Micro Corp
www.sg-micro.com
AUGUST 2022
5
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
TYPICAL PERFORMANCE CHARACTERISTICS
Test for SGM829-3.0 only, TJ = +25℃, unless otherwise noted.
SRT Threshold Voltage vs. Temperature
VDD Drop Reset Delay Time vs. Temperature
VDD = 5V, SRT Open
1.206
1.205
1.204
1.203
1.202
1.201
1.200
170
150
130
110
90
70
50
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
Detector Threshold vs. Temperature
SRT Open
Power-On Reset Delay Time vs. Temperature
VDD = 5V, SRT Open
3.2
3.1
3.0
2.9
2.8
2.7
2.6
350
340
330
320
310
300
290
Rising
Falling
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
Reset Delay Time vs. Capacitance
VDD = 5V
Supply Current vs. Input Voltage
SRT Open
10000
1000
100
10
1.5
1.2
0.9
0.6
0.3
0
+125℃
+85℃
+25℃
-40℃
1
0.1
0.001 0.01
0.1
1
10
100
1000
0
1.5
3
4.5
6
7.5
Capacitance (nF)
Input Voltage (V)
SG Micro Corp
www.sg-micro.com
AUGUST 2022
6
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
FUNCTIONAL BLOCK DIAGRAM
VDD
100kΩ
nMR
Schmitt
+
-
SRT
VBG
VDD
Control
Logic
R1
nRESET
-
+
VREF
0.405V
R2
R1 + R2 = 26MΩ
GND
Figure 3. Block Diagram
SG Micro Corp
www.sg-micro.com
AUGUST 2022
7
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
DETAILED DESCRIPTION
When the VDD voltage falls below VIT or the nMR pin is
driven low, the open-drain nRESET output is asserted.
After the VDD and nMR voltages exceed their respective
thresholds, the nRESET output remains low within the
user-adjustable delay time.
Therefore, there is a delay time between the point of
VDD reaching its threshold voltage and the nRESET
active-high point. The delay time can be calculated
according to the following equation:
TD (μs) = (2.8 × 106) × CSRT (μF) + 290μs (1)
Feature Description
Manual Reset (nMR) Input
The SGM829 device has a reset delay time adjustment
function and a wide range of detection thresholds, so it
can be widely used in various applications. The
detection threshold voltages are factory-set from 1.8V
to 5V. The reset timeout period can be set from 1.25ms
to 10s through programming an external capacitor which
is connected to the SRT pin.
The manual reset (nMR) input allows the operator, test
technician, or external logic circuit to initiate a reset. A
logic low (0.3 × VDD) on nMR forces the nRESET low.
After nMR returns to a logic high and the VDD voltage
rises above its reset threshold, nRESET is deasserted
after a reset delay time period (tD). nMR is pulled up to
VDD with an internal 100kΩ resistor. This pin can be left
floating if nMR is not used.
Selecting the Reset Delay Time
Figure 4 shows how to use nMR to monitor multiple
system voltages. If the logic signal does not drive nMR
fully to VDD, some extra current will flow into VDD due to
the pull-up resistor on nMR. Figure 5 shows how to use
an external FET to minimize the current draw.
When the VDD voltage exceeds the VDD threshold
voltage, a current source will start to charge the SRT
capacitor and the SRT voltage will rise. When the SRT
voltage exceeds 1.205V, the nRESET voltage will
change from low to high.
1.8V
3.3V
VDD
VDD
nRESET
SGM829-3.3
nMR SRT
VI/O
SRT
GPIO
VCORE
DSP
SGM829-1.8
nRESET
GND
GND
GND
Figure 4. Monitor Multiple System Voltages Using the nMR Pin
3.3V
VDD
100kΩ
nMR
nRESET
SGM829
GND
Figure 5. An External MOSFET is used to Minimize IDD
SG Micro Corp
www.sg-micro.com
AUGUST 2022
8
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
DETAILED DESCRIPTION (continued)
Normal Operation (VDD > VDD_MIN
)
nRESET Output
When the VDD voltage is higher than VDD_MIN, the logic
state of nRESET is determined by VDD and the logic
state of nMR.
As long as VDD voltage exceeds VIT and the nMR is
logic high, nRESET remains high (deasserted). Either
VDD is lower than VIT or nMR is set low, nRESET will be
low (asserted).
• nMR high: When VDD voltage is higher than 1.65V for a
selected time (tD), the nRESET logic state corresponds
to VDD relative to VIT.
If nMR returns to logic high again and VDD voltage
exceeds VIT + VHYS, nRESET will remain low for a fixed
reset delay time due to the delay circuit function. As
soon as the reset delay has expired, the nRESET turns
into logic high. The pull-up resistor between nRESET
and VDD can be used to reset the microprocessor signal
to obtain a voltage above VDD voltage. The pull-up
resistor should be no less than 10kΩ due to the limited
nRESET pull-down ability.
• nMR low: nRESET is held low regardless of VDD
voltage in this mode.
Above Power-On Reset but Lower than VDD_MIN
(VPOR < VDD < VDD_MIN
)
When the VDD voltage is lower than VDD_MIN and higher
than the power-on reset voltage (VPOR), the nRESET is
asserted and driven to a low-impedance state.
Device Functional Modes
Below Power-On Reset (VDD < VPOR
)
Table 1. Matrices of the nRESET Output
When the VDD voltage is lower than the required voltage
(VPOR), the nRESET voltage is undefined. In the case of
nRESET pulling up to VDD through a 100kΩ resistor,
nRESET voltage is equal to or lower than VDD voltage.
nMR
VDD > VIT
nRESET
L
L
0
1
0
1
L
L
H
H
L
H
SG Micro Corp
www.sg-micro.com
AUGUST 2022
9
Microprocessor Supervisory Circuit
with Programmable Delay Time
SGM829
APPLICATION INFORMATION
The SGM829 requires a voltage supply within 1.65V
and 6.5V. Figure 6 shows a typical application of the
Layout Guidelines
It is recommended to connect a 0.1µF ceramic
capacitor to the VDD pin as close as possible. If there is
no connection capacitor, minimize the parasitic
capacitor to avoid a significant impact on the nRESET
delay time.
SGM829-2.5 used with
a
2.5V microprocessor.
Normally, the nRESET output is connected to the
nRESET input of the microprocessor. It is necessary to
connect a 1MΩ pull-up resistor between nRESET and
VDD to keep the nRESET logic high if it is not asserted.
The reset delay time can be set by SRT while it
depends on the requirement of microprocessor. If left it
open, a typical 20ms of reset delay time is set.
2.5V
1MΩ
VDD
nRESET
SGM829-2.5
nMR SRT
VDDSHV1, 3, 6, 7, 9
RESPWRON
Processor
GND
GND
Figure 6. SGM829 Typical Application circuit with a
Microprocessor
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
AUGUST 2022 ‒ REV.A to REV.A.1
Page
Updated General Description section...................................................................................................................................................................1
Updated Detail Description section..................................................................................................................................................................8, 9
Added Application Information section...............................................................................................................................................................10
Changes from Original (MAY 2021) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
www.sg-micro.com
AUGUST 2022
10
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
SOT-23-5
1.90
D
e1
2.59
E1
E
0.99
b
e
0.95
0.69
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
A1
c
θ
0.2
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
1.250
0.100
1.150
0.500
0.200
3.020
1.700
2.950
MIN
MAX
0.049
0.004
0.045
0.020
0.008
0.119
0.067
0.116
A
A1
A2
b
1.050
0.000
1.050
0.300
0.100
2.820
1.500
2.650
0.041
0.000
0.041
0.012
0.004
0.111
0.059
0.104
c
D
E
E1
e
0.950 BSC
1.900 BSC
0.037 BSC
0.075 BSC
e1
L
0.300
0°
0.600
8°
0.012
0°
0.024
8°
θ
SG Micro Corp
www.sg-micro.com
TX00033.000
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
SOT-23-5
7″
9.5
3.20
3.20
1.40
4.0
4.0
2.0
8.0
Q3
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
7″ (Option)
7″
368
442
227
410
224
224
8
18
SG Micro Corp
www.sg-micro.com
TX20000.000
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