SGM5200 [SGMICRO]
12-Bit, 1MSPS, 16 Channels, Single-Ended, Serial Interface ADC;
| 型号： | SGM5200 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 12-Bit, 1MSPS, 16 Channels, Single-Ended, Serial Interface ADC |
| 文件： | 总29页 (文件大小：1050K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM5200
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
GENERAL DESCRIPTION
FEATURES
The SGM5200 is a 12-bit, multi-channel input, successive
approximation (SAR) analog-to-digital converter (ADC).
● 12-Bit Resolution
● 16 Channels
● Sampling Rate: Up to 1MHz
● Supply Voltage Ranges:
The SGM5200 analog power supply range is 2.7V to
5.25V. The SGM5200 has an SPI-compatible interface
that digital power supply range is 1.7V to 5.25V.
Analog Supply: 2.7V to 5.25V
Digital Supply: 1.7V to 5.25V
● Two Software Selectable Unipolar Input Ranges:
Range 1: 0V to VREF
The input signal is sampled on the nCS falling edge.
The ADC conversion is droved by external clock SCLK.
Range 2: 0V to 2 × VREF
The SGM5200 supports manual channel selection and
two kinds of auto channel scan modes.
● Supports Auto and Manual Channel Selections
● Individually Configurable GPIOs Function:
Four GPIOs in TSSOP Package
One GPIO in TQFN Package
● 20MHz SPI-Compatible Serial Interface
● Power-Down Current: 1.4μA (TYP)
● Input Bandwidth: 45MHz (TYP) at -3dB
● Typical Power Consumption:
24mW at 1MSPS (VA = 5V, VBD = 3V)
● Available in Green TSSOP-38 and TQFN-5×5-32L
Packages
The input range of SGM5200 is software configurable,
0 to reference voltage or 0 to two times of reference
voltage. It also supports two programmable alarm
thresholds for each channel.
The SGM5200 provides power-down mode.
The SGM5200 is available in Green TSSOP-38 and
TQFN-5×5-32L packages. It operates over an ambient
temperature range -40℃ to +125℃.
APPLICATIONS
PLC
Optical Module Signal Monitoring
Digital Power Supplies
Industrial Automation Systems
SG Micro Corp
SEPTEMBER 2022 – REV. A. 1
www.sg-micro.com
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM5200
XTS38
XXXXX
TSSOP-38
SGM5200XTS38G/TR
SGM5200XTQL32G/TR
Tape and Reel, 4000
Tape and Reel, 3000
-40℃ to +125℃
-40℃ to +125℃
SGM5200
SGM5200
XTQL32
XXXXX
TQFN-5×5-32L
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
Voltage Range (with Respect to AGND)
OVERSTRESS CAUTION
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
+VA.................................................................... -0.3V to 6V
AINP or CHx ........................................... -0.3V to VA + 0.3V
Voltage Range (with Respect to BGND)
+VBD ................................................................. -0.3V to 6V
Digital Input Voltage........................................... -0.3V to 6V
Digital Output Voltage............................. -0.3V to VA + 0.3V
Input Current to Any Pin except Supply Pins
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
.......................................................................-10mA to 10mA
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
HBM.............................................................................4000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Analog Supply Voltage Range..........................2.7V to 5.25V
Digital I/O Supply Voltage Range ..........................1.7V to VA
Reference Voltage Range.........................................2V to 3V
SCLK Frequency ........................................................20MHz
Operating Temperature Range....................-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
2
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
PIN CONFIGURATIONS
(TOP VIEW)
1
2
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GPIO2
GPIO3
REFN
REFP
+VA
GPIO1
GPIO0
+VBD
BDGND
SDO
SDI
3
4
5
6
AGND
MXO
7
SCLK
nCS
8
AINP
AINN
AGND
CH15
CH14
CH13
CH12
CH11
CH10
CH9
9
AGND
+VA
10
11
12
13
14
15
16
17
18
19
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH8
CH7
AGND
AGND
TSSOP-38
(TOP VIEW)
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
AGND
SCLK
23
22
21
20
19
18
17
MXO
AINP
AINN
CH15
nCS
AGND
+VA
CH0
CH1
CH2
CH3
AGND
CH14
CH13
CH12
9
10 11 12 13 14 15 16
TQFN-5×5-32L
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
3
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
PIN DESCRIPTION
PIN
NAME
TYPE (1)
FUNCTION
TSSOP-38
TQFN-5×5-32L
GPIO2
DIO
General-Purpose Input or Output.
Selects ADC Input Range.
High (1): select Range 2 (0V to 2 × VREF).
Low (0): select Range 1 (0V to VREF).
1
‒
Range
DI
GPIO3
nPD
DIO
DI
AI
AI
‒
General-Purpose Input or Output.
Power-Down Input. Active low.
Reference Ground.
2
‒
3
30
31
21, 32
1, 22
2
REFN
REFP
+VA
4
Reference Input.
5, 29
Analog Power Supply.
Analog Ground.
6, 10, 19, 20, 30
AGND
MXO
AINP
AINN
CH15
CH14
CH13
CH12
CH11
CH10
CH9
‒
7
AO
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
DI
DI
DI
DI
‒
Multiplexer Output.
8
3
ADC Input Signal.
9
4
ADC Input Ground.
11
12
13
14
15
16
17
18
21
22
23
24
25
26
27
28
31
32
33
34
35
36
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
CH8
Analog Channel Inputs for Multiplexer.
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
nCS
Chip Select. Active low.
Serial Clock Input.
SCLK
SDI
Serial Data Input.
SDO
BDGND
+VBD
GPIO0
Serial Data Output.
Digital Ground.
‒
Digital Power Supply.
General-Purpose Input or Output.
DIO
37
38
29
Alarm Output. Active high. Refer to Programming section for a detailed
configuration.
Alarm
DO
GPIO1
DIO
DO
General-Purpose Input or Output.
‒
Low Alarm
Low Alarm Output Indication. Active high.
NOTE:
1. AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input or Output.
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
4
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
ELECTRICAL CHARACTERISTICS
(VA = 2.7V to 5.25V, VBD = 1.7V to VA, VREF = 2.5V ± 0.1V, fSAMPLE = 1MHz, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input
Range 1
0
VREF
Full-Scale Input Span (1)
Absolute Input Range
V
V
Range 2 while 2 × VREF ≤ VA
Range 1
0
2 × VREF
-0.2
-0.2
VREF + 0.2
2 × VREF + 0.2
Range 2 while 2 × VREF ≤ VA
Input Capacitance
Input Leakage Current
System Performance
Resolution
31
60
pF
nA
TA = +125℃
12
Bits
Bits
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
11
No Missing Codes
Integral Linearity
Differential Linearity
Offset Error (3)
12
-3.50
-1.32
-1.00
-0.99
-8.00
-5.60
-5.20
-4.10
±1.6
±0.8
-1/+1.3
±0.5
±1.2
±1.6
±0.8
±0.8
±1.8
±1.9
2.60
1.32
2.20
1.00
8.00
5.60
4.40
3.10
LSB (2)
LSB
LSB
Gain Error
LSB
Total Unadjusted Error
TUE
LSB
Sampling Dynamics
Conversion Time
20MHz SCLK
20MHz SCLK
800
325
ns
ns
Acquisition Time
Maximum Throughput Rate
Aperture Delay
1
MHz
ns
6
Dynamic Characteristics
Range 1
-77
-79
Total Harmonic Distortion (4)
THD
SNR
100kHz
100kHz
100kHz
dB
dB
dB
Range 2
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
66.4
67.9
65.6
66.7
70.4
71.4
69.5
70.7
78
Signal-to-Noise Ratio
Signal-to-Noise + Distortion
Spurious Free Dynamic Range
Small Signal Bandwidth
100kHz
At -3dB
dB
81
45
MHz
Any off-channel with 100kHz, full-scale
input to channel being sampled with DC
input (isolation crosstalk)
-100
-84
Channel-to-Channel Crosstalk
dB
From previously sampled to channel with
100kHz, full-scale input to channel being
sampled with DC input (memory crosstalk)
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
5
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
ELECTRICAL CHARACTERISTICS (continued)
(VA = 2.7V to 5.25V, VBD = 1.7V to VA, VREF = 2.5V ± 0.1V, fSAMPLE = 1MHz, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
External Reference Input
Reference Voltage at REFP (5)
Reference Input Resistance
Alarm Setting
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VREF
2
2.5
31
3
V
fSAMPLE = 1MHz
kΩ
High Threshold Range
Low Threshold Range
Digital Input/Output
0
0
4092
4092
LSB
LSB
VBD = 5.25V
VBD = 1.7V
VBD = 5.25V
VBD = 1.7V
3.10
1.25
High Input Voltage
Low Input Voltage
VIH
VIL
V
V
1.90
0.45
High Output Voltage
VOH
VOL
ISOURCE = 200μA
ISINK = 200μA
VBD - 0.2
V
V
Low Output Voltage
0.4
Data Format MSB First
Power Requirements
Analog Supply Voltage
Digital I/O Supply Voltage
MSB First
VA
2.7
1.7
3.3
3.3
3
5.25
5.25
V
V
VBD
VA = 2.7V to 3.6V and 1MHz throughput
VA = 2.7V to 3.6V static state
1.1
4.1
1.1
Analog Supply Current
(Normal Mode)
IA
mA
VA = 4.7V to 5.25V and 1MHz throughput
VA = 4.7V to 5.25V static state
5.4
2.2
Power-Down State Supply
Current
1.4
μA
Digital I/O Supply Current
Power-Up Time
IBD
VA = 5.25V, fSAMPLE = 1MHz
1.3
1
mA
μs
Invalid Conversions after
Power-Up or Reset
1
Conversion
NOTES:
1. Ideal input span; not consider gain error and offset error.
2. LSB = Least Significant Bit.
3. The measurement is performed relative to the ideal full-scale input.
4. The calculation is performed on the first nine harmonics of the input frequency.
5. The device is designed to operate that reference voltage is 2V to 3V. While, when VREF < 2.4V, it expects lower noise
performance It is due to SNR degradation resulting from lowered signal range.
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
6
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TIMING CHARACTERISTICS
(VA = 2.7V to 5.25V, Full = -40℃ to +125℃, unless otherwise noted.) (1) (2) (See Figure 1 and Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
16
UNITS
V
BD = 1.8V
Conversion Time
tCONV
VBD = 3V
VBD = 5V
16
SCLK
16
V
BD = 1.8V
38
Delay Time
(nCS Low to First Data DO15 Out)
t1
VBD = 3V
VBD = 5V
27
ns
ns
17
V
BD = 1.8V
13
12
12
Hold Time
(SCLK Falling to SDO Data Bit Valid)
t2
VBD = 3V
VBD = 5V
V
BD = 1.8V
35
27
17
Delay Time
(SCLK Falling to SDO Next Data Bit Valid)
t3
VBD = 3V
VBD = 5V
ns
V
BD = 1.8V
2
3
Setup Time
(SDI Valid to Rising Edge of SCLK)
t4
VBD = 3V
VBD = 5V
ns
4
V
BD = 1.8V
12
10
6
Hold Time
(Rising Edge of SCLK to SDI Valid)
t5
VBD = 3V
VBD = 5V
ns
V
BD = 1.8V
26
22
13
Delay Time
t6
VBD = 3V
VBD = 5V
ns
(16th SCLK Falling Edge to SDO 3-State)
V
BD = 1.8V
40
40
40
20
20
20
8
Minimum Quiet Sampling Time Needed from Bus
3-State to Start of Next Conversion
t7
VBD = 3V
VBD = 5V
ns
V
BD = 1.8V
Pulse Duration nCS High
t8
VBD = 3V
VBD = 5V
ns
V
BD = 1.8V
Setup Time
(nCS Low to First Rising Edge of SCLK)
t9
VBD = 3V
VBD = 5V
6
ns
4
V
BD = 1.8V
20
20
20
20
20
20
Pulse Duration SCLK High
Pulse Duration SCLK Low
SCLK Frequency
t10
VBD = 3V
VBD = 5V
ns
V
BD = 1.8V
t11
VBD = 3V
VBD = 5V
ns
V
BD = 1.8V
20
20
20
VBD = 3V
VBD = 5V
MHz
NOTES: 1. 1.6V to 1.9V range is applied for 1.8V specifications; 2.7V to 3.6V range is applied for 3V specifications; 4.75V to 5.25V
range is applied for 5V specifications.
2. With 50pF load.
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
7
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TIMING DIAGRAM
Frame N
Frame N+1
nCS
15
15
14
16
14
16
1
2
3
1
2
3
SCLK
MUX
MUX Channel Change
MUX Channel Change
Analog Input Setting after Channel Change
Acquisition Phase tACQ
Analog Input Setting after Channel Change
Input sampling instance
Acquisition
Conversion
Conversion Phase tCNV
Data Written in Frame N-1 (through SDI)
Conversion Phase tCNV
GPO
GPI
Data Written in Frame N (through SDI)
GPI input is latched on the falling edge of nCS and shifted to SDO in frame N+1
16-Bit Data Output
SDO
SDI
16-Bit Data Output
16-Bit Data Input
16-Bit Data Input
Figure 1. Device Operation Timing Diagram
Single Frame
nCS
t8
t9
t10
1
2
4
5
15
16
SCLK
SDO
SDI
t2
t11
t3
t6
t1
MSB
/DO11
LSB+1
/DO1
LSB
/DO0
DO15
DI15
DO14
DO12
t7
t4
DI0
DI14
t5
DI1
Figure 2. Serial Interface Timing Diagram
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
8
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TYPICAL PERFORMANCE CHARACTERISTICS
Signal-to-Noise Ratio vs. Supply Voltage (Range 2)
Signal-to-Noise Ratio vs. Supply Voltage (Range 1)
VBD = 3V, fS = 1MSPS,
71
70
69
68
67
66
65
73
72
71
70
69
68
67
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
f
IN = 100kHz, TA = +25℃
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
5.0
5.1
5.2
5.3
5.4
5.5
Supply Voltage (V)
Supply Voltage (V)
Signal-to-Noise + Distortion vs. Supply Voltage (Range 1)
Signal-to-Noise + Distortion vs. Supply Voltage (Range 2)
69
72
VBD = 3V, fS = 1MSPS,
VBD = 3V, fS = 1MSPS,
f
IN = 100kHz, TA = +25℃
f
IN = 100kHz, TA = +25℃
68
67
66
65
64
63
71
70
69
68
67
66
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
5.0
5.1
5.2
5.3
5.4
5.5
Supply Voltage (V)
Supply Voltage (V)
Total Harmonic Distortion vs. Supply Voltage (Range 1)
-71
Total Harmonic Distortion vs. Supply Voltage (Range 2)
-73
VBD = 3V, fS = 1MSPS,
IN = 100kHz, TA = +25℃
VBD = 3V, fS = 1MSPS,
IN = 100kHz, TA = +25℃
f
f
-72
-73
-74
-75
-76
-77
-74
-75
-76
-77
-78
-79
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
5.0
5.1
5.2
5.3
5.4
5.5
Supply Voltage (V)
Supply Voltage (V)
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
9
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Spurious Free Dynamic Range vs. Supply Voltage (Range 2)
Spurious Free Dynamic Range vs. Supply Voltage (Range 1)
78
80
79
78
77
76
75
74
VBD = 3V, fS = 1MSPS,
VBD = 3V, fS = 1MSPS,
IN = 100kHz, TA = +25℃
f
IN = 100kHz, TA = +25℃
f
77
76
75
74
73
72
2.7
10
10
3.1
3.5
3.9
4.3
4.7
5.1
5.5
5.0
5.1
5.2
5.3
5.4
5.5
Supply Voltage (V)
Supply Voltage (V)
Signal-to-Noise Ratio vs. Input Frequency
Signal-to-Noise + Distortion vs. Input Frequency
73
72
71
70
69
68
67
72
71
70
69
68
67
66
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
30
50
70
90
110 130 150
10
30
50
70
90
110 130 150
Input Frequency (kHz)
Input Frequency (kHz)
Total Harmonic Distortion vs. Input Frequency
Spurious Free Dynamic Range vs. Input Frequency
-69
-71
-73
-75
-77
-79
-81
85
83
81
79
77
75
73
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
30
50
70
90
110 130 150
10
30
50
70
90
110 130 150
Input Frequency (kHz)
Input Frequency (kHz)
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
10
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Signal-to-Noise Ratio vs. Temperature
Signal-to-Noise + Distortion vs. Temperature
71.5
71.0
70.5
70.0
69.5
69.0
68.5
72
71
70
69
68
67
66
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
Total Harmonic Distortion vs. Temperature
Spurious Free Dynamic Range vs. Temperature
-72
-73
-74
-75
-76
-77
-78
81
80
79
78
77
76
75
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
Differential Nonlinearity Variation Across Channels
VA = 5V, VBD = 5V, fS = 1MSPS
Integral Nonlinearity Variation Across Channels
VA = 5V, VBD = 5V, fS = 1MSPS
1.0
0.8
1.0
0.8
0.6
0.6
INL MAX
0.4
0.4
DNL MAX
DNL MIN
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
INL MIN
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Channel Number
Channel Number
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
11
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Gain Error Variation Across Channels
VA = 5V, VBD = 5V, fS = 1MSPS
Offset Error Variation Across Channels
VA = 5V, VBD = 5V, fS = 1MSPS
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Channel Number
Channel Number
Signal-to-Noise Ratio Variation Across Channels
VA = 5V, VBD = 5V, fS = 1MSPS
Signal-to-Noise + Distortion Variation Across Channels
VA = 5V, VBD = 5V, fS = 1MSPS
71.0
70.5
70.0
69.5
69.0
68.5
68.0
67.5
67.0
66.5
66.0
70.0
69.5
69.0
68.5
68.0
67.5
67.0
66.5
66.0
65.5
65.0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Channel Number
Channel Number
Crosstalk vs. Input Frequency
Isolation
Input Leakage Current vs. Temperature
VA = 5V, VBD = 5V
120
100
80
60
40
20
0
98
78
58
38
18
-2
Memory
VINP = 2.5V
VINP = 1.25V
VINP = 0.12V
VA = 5V, VBD = 5V,
fS = 1MSPS, CH0, CH1
0
50
100
150
200
250
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Input Frequency (kHz)
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
12
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Gain Error vs. Temperature (Range 1)
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
Gain Error vs. Temperature (Range 2)
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
2.0
1.5
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
1.0
0.5
0.0
-0.5
-1.0
-1.5
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
Offset Error vs. Temperature (Range 1)
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
Offset Error vs. Temperature (Range 2)
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
0.6
0.4
0.8
0.6
0.2
0.4
0.0
0.2
-0.2
-0.4
-0.6
-0.8
0.0
-0.2
-0.4
-0.6
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
Total Unadjusted Error (TUE Maximum) (Range 1)
Total Unadjusted Error (TUE Maximum) (Range 2)
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
TUE MAX (LSB)
TUE MAX (LSB)
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
13
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Total Unadjusted Error (TUE Minimum) (Range 1)
Total Unadjusted Error (TUE Minimum) (Range 2)
25
20
15
10
5
30
25
20
15
10
5
0
0
TUE MIN (LSB)
Typical FFT Plot
TUE MIN (LSB)
0
VA = 5V, VBD = 5V,
-20
fS = 1MSPS, fIN = 100kHz,
Npoints = 16384
-40
-60
-80
-100
-120
-140
-160
0
100
200
300
400
500
Frequency (kHz)
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
14
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
FUNCTIONAL BLOCK DIAGRAM
MXO
AINP
+VA
AGND
REFP
CH0
CH1
CH2
SDO
SDI
Control Logic
&
ADC
SCLK
nCS
Sequencing
CH15
GPIO0
GPIO3 (1)
BDGND
+VBD
NOTE:
1. Four GPIOs for TSSOP package and one GPIO for TQFN package.
Figure 3. Block Diagram
TYPICAL APPLICATION CIRCUIT
High Input Impedance PGA
(or Non-Inverting Buffer
Such as SGM8604-1)
MXO
AINP
GPIO3
CH0
GPIO2
GPIO1
GPIO0
CH1
CH2
Logic
ADC
&
SDO
Sequence
SDI
SCLK
nCS
CH15
REFP
REFN
REF
SGM4029-2.5
10μF
Figure 4. Typical Application Circuit
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
15
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION
Overview
16th falling edge of SCLK in the next frame. If D15 is reset,
the chip will be powered up on the nCS falling edge. The
second way is asynchronous control by GPIO3. GPIO3 can
be configured as an nPD input (see Table 9). Its output is
active low. The chip goes to power-down at same time
when nPD is '0'. The chip will be powered up when nPD is
'1'.
The SGM5200 is a 12-bit, SAR ADC. It needs an external
voltage reference. An Amplifier can be used between MXO
and AINP for signal conditioning. Figure 1 and Figure 2
show the chip operating time sequences.
The SGM5200 output data is composed of 4-bit channel
address and 12-bit ADC conversion result. To read and
write GPIOs, more details refer to Table 1, Table 2 and
Table 5.
Device Functional Modes
Channel Sequencing Modes
The SGM5200 has three channel sequencing modes:
manual mode, auto-1 mode and auto-2 mode. Mode
selection is configured by the mode control register (see
Table 1, Table 2 and Table 5). The new channel selection is
valid on the 2nd SCLK falling edge in the next frame in all
three modes (refer to Figure 1).
The SGM5200 switches to new multiplexer channel on the
2nd falling edge of SCLK. The input acquisition phase (equal
input capacitor starts charging) begins on the 14th falling
edge of SCLK. The input signal is sampled on the nCS
falling edge.
The TSSOP package of the SGM5200 has four
general-purpose IO (GPIO) pins, and the TQFN package
has one GPIO pin.
Once the chip is configured to working in a selected mode,
it keeps working in this mode until the chip is powered down,
reset or reprogrammed. Allows it to exit multiple times and
re-enter this mode without disturbing program register
settings.
The chip refreshes the GPIO status (Input and output) at
the nCS falling edge. The GPI data will be in the same
frame starting with the nCS falling edge (if GPI read
enabled).
Manual Mode
When power-up or after reset the default channel is
'channel 0' and the default mode is manual mode.
The operating time sequence is shown in Figure 2, the
falling edge of nCS clocks out DO15, the remain bits are
shifted out on the falling edge of SCLK. The ADC result is a
12-bit binary data, MSB is shifted out on the 4th falling edge
of SCLK, and LSB is shifted out on the 15th falling edge of
SCLK. Refer to Figure 2, when the ADC conversion ends
on the 16th SCLK falling edge, SDO goes to 3-state. The
chip 16-bit data (on SDI pin) is shifted in on the every rising
edge of SCLK.
Auto-1 Mode
In auto-1 mode, the chip scans all selected channels in
ascending order. The selected channels are configured in a
program register. The auto-1 program register setting is
shown in Table 3 and Table 4. The auto-1 program register
is reset to '0hFFFF'.
Auto-2 Mode
In auto-2 mode, the chip scans all selected channels from
channel 0 to the last channel. The last channel is configured
in a program register. The auto-2 program register setting is
shown in Table 6. The auto-2 program register are reset to
'0hF'.
The SGM5200 has threshold alarm function per channel. If
ADC results exceed these limits (high and low), the chip
can give alert on GPIO0/GPIO1 pins (detail configurations
in Table 9). If there is an alarm, the alert will be set on the
12th SCLK falling edge in the same frame of ADC
conversion in progress. It will reset on the 10th SCLK falling
edge in the next frame.
Device Programming and Mode Control
The chip has two kinds of registers named mode registers
and program registers.
Reference
The SGM5200 needs an external reference.
Power-Up Sequence
After power-up, the chip is in default manual mode and
channel 0 is set as default channel. User needs to configure
program register and mode register to set the chip working
in target mode.
Power Saving
The SGM5200 provides two kinds of ways to power down
the chip. The first way is command control. It depends on
setting DI5 = '1', more details see Table 1, Table 2 and
Table 5. If DI5 is set, the chip will be powered down on the
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
16
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Operating in Manual Mode
The mode control register settings for manual mode are
shown in Table 1. In manual mode, no program register is
required.
and channel CH5 is selected, internal MUX is switched to
channel CH3 on the 2nd falling edge of SCLK. In the frame
N+2, keep in manual mode and channel CH7 is selected,
on the falling edge of nCS, channel CH3 input signal is
sampling and conversion result is sent out in this frame,
internal MUX is switched to CH5. And the chip repeats this
sequence and sends out ADC conversion result data of
CH5 and CH7 in the following two frames.
The example for the chip how to work in manual mode and
scan channels CH3, CH5 and CH7 is shown in Figure 5. In
this sequence, in the frame N manual mode and channel
CH3 is selected. In the frame N+1, keep in manual mode
Table 1. Mode Control Register Details for Manual Mode
RESET
STATE
BITS
DESCRIPTION
DI[15:12] 0001 = Selects manual mode
0001
0 = Chip retains values of DI[6:0] from the previous frame
1 = Enables programming of bits DI[6:0]
DI11
DI[10:7]
DI6
0
0000
0
The 4-bit data means the next channel address to be selected in the next frame. DI10 is MSB and DI7 is LSB. For
example, 0000 = channel 0, 0001 = channel 1 and so on.
0 = Selects 0V to VREF input range (Range 1)
1 = Selects 0V to 2 × VREF input range (Range 2)
0 = Normal operation (no power-down).
DI5
0
1 = Powers down on the 16th SCLK falling edge.
0 = SDO outputs current channel address of the channel on DO[15:12], and the 12-bit conversion results on
DO[11:0]
1 = GPIO3 to GPIO0 data (both input and output) corresponds to DO[15:12] in the following order as shown. Lower
data bits DO[11:0] means 12-bit conversion result for the current channel
DI4
0
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data of the channels is used as output. The data of the channel configured as input will be ignored by the
device. The SDI bits and corresponding GPIO are shown below.
DI[3:0]
0000
DI3
DI2
DI1
DI0
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
NOTE: 1. GPIO1 to GPIO3 are available only for TSSOP package. TQFN packaged device offers GPIO0 only.
Sample
CHy
Sample
CHx
Sample
CH5
Sample
CH3
Frame N
Frame N+1
Frame N+2
nCS
MUX Switch to CH3
3
MUX Switch to CH5
3 16
1
2
3
16
1
2
16
1
2
SCLK
Configure Manual Mode and
Select CH3
Keep Manual Mode and
Select CH5
Keep Manual Mode and
Select CH7
SDI
Data CHx
Data CHy
Data CH3
SDO
Figure 5. Example for Manual Mode Timing Diagram
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
17
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Operating in Auto-1 Mode
The mode control register settings for auto-1 mode are
shown in Table 2. There are both mode registers and
program registers for auto-1 mode operation.
the CH2 input and gives out ADC conversion result, and the
MUX is switched to CH3 automatically. In the frame N+3,
the chip samples CH3 and gives out ADC conversion
results, and the MUX is switched to CH5 automatically, and
so on. This process repeats until the last selected channel
is reached, and the process loops back from the first
selected channel.
To let the chip work in auto-1 mode, it is necessary to
configure auto-1 program register firstly to select which
channels are going to be scanned.
In any case, re-entering auto-1 mode (It may be from auto-1
mode, manual mode and auto-2 mode) will cause the chip
channel scan sequence restarts from the first selected
channel.
The program register settings for auto-1 mode are shown in
Table 3 and Table 4.
Before running in auto-1 mode, the target channels CH2,
CH3 and CH5 (examples) must be configured in auto-1
program registers (details see auto-1 program registers
configuration sequence).
Note that changing the auto-1 program register during the
chip is working in auto-1 mode, the chip scan restarts from
the first selected channel in ascending.
The example for the chip how to work in auto-1 mode and
scan channels CH2, CH3 and CH5 automatically is shown
in Figure 6. In this sequence, in the frame N sent entering
auto-1 mode command and channel CH2 is selected
automatically (the chip find the first selected channel in
ascending order automatically). In the frame N+1, the chip
switches MUX to CH2. In the frame N+2, the chip samples
Figure 7 shows how the auto-1 program registers is
configured. It is used to pre-select the channels for auto-1
scanning. It needs two operation frames for a complete
configuration. More setting details are shown in Table 3 and
Table 4.
Table 2. Mode Control Register Details for Auto-1 Mode
RESET
STATE
BITS
DESCRIPTION
DI[15:12] 0010 = Selects auto-1 mode
0001
0 = Chip retains values of DI[10:0] from previous frame
1 = Enables programming of bits DI[10:0]
DI11
0
0 = The channel counter increments every conversion (no reset)
1 = The channel counter is reset to the lowest programmed channel in the auto-1 program register
DI10
DI[9:7]
DI6
0
000
0
xxx = Do not care
0 = Selects 0V to VREF input range (Range 1)
1 = Selects 0V to 2 × VREF input range (Range 2)
0 = Normal operation (no power-down).
DI5
0
1 = Powers down on the 16th SCLK falling edge.
0 = SDO outputs current channel address of the channel on DO[15:12], and the 12-bit conversion results on
DO[11:0]
1 = GPIO3 to GPIO0 data (both input and output) corresponds to DO[15:12] in the following order as shown. Lower
data bits DO[11:0] means 12-bit conversion result for the current channel
DI4
0
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data of the channels is used as output. The data of the channel configured as input will be ignored by the
device. The SDI bits and corresponding GPIO are shown below.
DI[3:0]
0000
DI3
DI2
DI1
DI0
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
NOTE: 1. GPIO1 to GPIO3 are available only for TSSOP package. TQFN packaged device offers GPIO0 only.
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
18
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Sample
CH3
Sample
CH5
Sample
CHy
Sample
CH2
Sample
CHx
Frame N
Frame N+1
Frame N+2
Frame N+3
nCS
MUX Switch to CH5
MUX Switch to CH2
MUX Switch to CH2
16
MUX Switch to CH3
1
2
3
16
1
2
3
16
1
2
3
16
1
2
3
16
1
2
3
SCLK
SDI
Enter Auto-1 Mode
Data CHx
Keep Auto-1 Mode
Data CH2
Keep Auto-1 Mode
Data CH3
Keep Auto-1 Mode
Data CH5
Keep Auto-1 Mode
Data CHy
SDO
Figure 6. Example for Auto-1 Mode Timing Diagram
Frame N
Frame N+1
nCS
1
2
3
16
1
2
3
16
SCLK
DI[15:12] = 1000
Enter auto-1 program register configuration
DI[15:0] = XX
Per Table 3 and Table 4 for channel selected
SDI
SDO
Do Not Care
Do Not Care
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 7. Auto-1 Program Register Setting
Table 3. Program Register Details for Auto-1 Mode
RESET
STATE
BITS
DESCRIPTION
Frame 1
DI[15:12] 1000 = Enters the sequence of auto-1 program. Configuration is done in the next frame
NA
NA
DI[11:0]
Do not care.
Frame 2
1 (Individual Bit) = According bit is set to '1' means the according channel is selected in scanning sequence.
The channel numbers are one-to-one associated with the SDI bits. For example, DI15 corresponds to CH15, DI14
corresponds to CH14 … DI0 corresponds to CH0
0 (Individual Bit) = According bit is set to '0' means the according channel is skipped in scanning sequence.
The channel numbers are one-to-one associated with the SDI bits. For example, DI15 corresponds to CH15, DI14
corresponds to CH14 … DI0 corresponds to CH0
DI[15:0]
All '1'
Table 4. Channels Mapping to SDI Bits for the SGM5200
Device (1)
SDI Bits
DI15 DI14 DI13 DI12 DI11 DI10
DI9
DI8
1/0
DI7
DI6
DI0
DI4
DI3
DI2
DI1
1/0
DI0
16 Chan
1/0 1/0 1/0 1/0 1/0 1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
NOTE:
1. The chip only scans the selected channels when in auto-1 mode.
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
19
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Operating in Auto-2 Mode
The mode control register settings for auto-2 mode are
shown in Table 5. There are both mode registers and
program registers for auto-1 mode operation.
CH02. In the frame N+2, the chip samples the CH0 input
and gives out ADC conversion result, and the MUX is
switched to CH1 automatically. In the frame N+3, the chip
samples CH1 and gives out ADC conversion, and the MUX
is switched to CH2 automatically, and so on. This process
repeats until the last selected channel is reached (In this
example, the last channel is CH2), and the process loops
back from channel CH0.
To let the chip work in auto-2 mode, it is necessary
configure auto-2 program register firstly to configure the last
channel which is going to be reached.
The program register settings for auto-2 mode are shown in
Table 6.
In any case, re-entering auto-2 mode possibly from auto-1
mode, manual mode and auto-2 mode will cause the chip
channel scan sequence to restart from the channel CH0.
Before running in auto-2 mode, the last target channel CH2
(example) must be configured in auto-2 program registers
(details see auto-2 program registers configuration
sequence).
Note that changing the auto-2 program register during the
chip is working in auto-2 mode, the chip scan restarts from
channel CH0.
The example about the chip how to work in auto-2 mode
and scan channels CH0, CH1 and CH2 automatically is
shown in Figure 8. In this sequence, in the frame N sent
entering auto-2 mode command and channel CH0 is
selected automatically (the chip switches to CH0
automatically). In the frame N+1, the chip switches MUX to
Figure 9 shows how the auto-2 program registers is
configured. It’s for pre-select the last channel for auto-2
scanning. It needs one operation frames for a complete
configuration. Refer to Table 6 for more setting details
Table 5. Mode Control Register Details for Auto-2 Mode
RESET
STATE
BITS
DESCRIPTION
DI[15:12] 0011 = Selects auto-2 mode
0001
0 = Chip retains values of DI[10:0] from the previous frame
1 = Enables programming of bits DI[10:0]
DI11
0
0 = Channel counter increments every conversion (no reset)
1 = Channel number is reset to CH0
DI10
DI[9:7]
DI6
0
000
0
xxx = Do not care
0 = Selects VREF input range (Range 1)
1 = Selects 2 × VREF input range (Range 2)
0 = Normal operation (no power-down)
DI5
0
1 = Powers down on the 16th SCLK falling edge
0 = SDO outputs current channel address of the channel on DO[15:12], and the 12-bit conversion results on
DO[11:0]
1 = GPIO3 to GPIO0 data (both input and output) corresponds to DO[15:12] in the following order as shown. Lower
data bits DO[11:0] means 12-bit conversion result for the current channel
DI4
0
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data of the channels is used as output. The data of the channel configured as input will be ignored by the
device. The SDI bits and corresponding GPIO are shown below.
DI[3:0]
0000
DI3
DI2
DI1
DI0
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
NOTE: 1. GPIO1 to GPIO3 are available only for TSSOP package. TQFN packaged device offers GPIO0 only.
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
20
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Sample
CH1
Sample
CH2
Sample
CHy
Sample
CH0
Sample
CHx
Frame N
Frame N+1
Frame N+2
Frame N+3
nCS
MUX Switch to CH0
MUX Switch to CH2
MUX Switch to CH1
MUX Switch to CH0
16
1
2
3
16
1
2
3
16
1
2
3
16
1
2
3
16
1
2
3
SCLK
SDI
Enter Auto-2 Mode
Data CHx
Keep Auto-2 Mode
Data CHy
Keep Auto-2 Mode
Data CH0
Keep Auto-2 Mode
Data CH1
Keep Auto-2 Mode
Data CH2
SDO
Figure 8. Example for Auto-2 Mode Timing Diagram
Frame N
nCS
1
2
3
16
SCLK
DI[15:12] = 1001
DI[9:6] = xxxx, the address of last channel
SDI
SDO
Do Not Care
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 9. Auto-2 Program Register Setting
Table 6. Program Register Details for Auto-2 Mode
RESET
STATE
BITS
DESCRIPTION
DI[15:12] 1001 = Configure auto-2 program register
DI[11:10] Do not care.
NA
NA
NA
NA
aaaa = The 4-bit data means the address of the last channel in the scanning sequence. In auto-2 mode, the
channel counter begins at CH0, increasing each frame until equal to 'aaaa'. The channel counter roles over to CH0
in the next frame
DI[9:6]
DI[5:0]
Do not care.
Continued Operation in a Selected Mode
When the chip is configured to working in one mode, the user may want to keep working in this mode. How to continue operating
in a selected mode is shown in Table 7.
Table 7. Continued Operation in a Selected Mode
RESET
STATE
BITS
DESCRIPTION
0000 = The chip continues to operate in current mode. When in auto-1 and auto-2 modes, the channel counter
increments automatically; when in the manual mode, it continues with the last selected channel. The chip ignores
datas on DI[11:0] and continues operating with the previous settings. SDI can be held low when there is no
changes are required in the mode control register
DI[15:12]
DI[11:0]
0001
Chip ignores these bits when DI[15:12] is '0000'.
All '0'
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
21
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Programming
The GPIO functions and GPO status are set in GPIO
program registers, more details refer to Table 9.
Digital Output
Table 8 shows the theory output codes according to
different input ranges. The ADC codes are in straight binary
format.
The GPO refresh include two steps, first step setting in
operation frame N, second steps the chip refresh GPO data
on the nCS falling edge in frame N+1. More details refer to
Figure 10.
GPIO Registers
The GPIO pins can be used as GPO (general-purpose
output) or GPI (general-purpose input).
The chip samples the GPI input on the falling edge of nCS
in frame N, and outputs GPI data on SDO in the same
frame N.
Table 8. Ideal Input Voltages and Output Codes
Description
Full Scale Range
Analog Value
Digital Output
Straight Binary
Range 1 → VREF
VREF/4096
VREF - 1LSB
VREF/2
Range 2 → 2 × VREF
Least Significant Bit (LSB)
Full Scale
2 × VREF/4096
2 × VREF - 1LSB
VREF
Binary Code
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
Hex Code
FFF
Midscale
800
Midscale - 1LSB
Zero
VREF/2 - 1LSB
0V
VREF - 1LSB
0V
7FF
000
Frame N
Frame N+1
nCS
1
2
3
16
1
2
3
16
SCLK
GPOs are refreshed per previous frame SDI setting
Do Not Care
DI[15:12] = 0100
Per Table 9 for detail setting
SDI
GPIs are sampled and output data on SDO
GPI Status Refreshed
GPIs are sampled and output data on SDO
GPI Status Refreshed
SDO
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 10. GPIO Program Register Setting
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
22
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Table 9. GPIO Program Register Details
RESET
STATE
BITS
DESCRIPTION
DI[15:12] 0100 = Selects GPIO program registers for programming
DI[11:10] 00 = Reserved bits, must be '00'
NA
00
0
0 = Normal operation
DI9
1 = Resets all registers in the next nCS frame to default value (it also resets itself)
0 = GPIO3 is still as general-purpose I/O. Program 0 for TQFN packaged device
1 = Configures GPIO3 as the chip power-down input
DI8
0
0
0 = GPIO2 is still as general-purpose I/O. Program 0 for TQFN packaged device
1 = Configures GPIO2 as device range input
DI7
000 = GPIO1 and GPIO0 are still as general-purpose I/Os. Valid setting for TQFN packaged device
xx1 = Configures GPIO0 as 'high or low' alarm output. It is an active high output. GPIO1 is still as general-purpose
I/O. Valid setting for TQFN packaged device
010 = Configures GPIO0 as high alarm output. It is an active high output. GPIO1 is still as general-purpose I/O. Valid
DI[6:4]
setting for TQFN packaged device
000
100 = Configures GPIO1 as low alarm output. It is an active high output. GPIO0 is still as general-purpose I/O.
Configuration is not valid for TQFN packaged device
110 = Configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high outputs.
Configuration is not valid for TQFN packaged device
0 = GPIO3 pin is configured as GPI (general-purpose input). Setting is not valid for TQFN packaged device
1 = GPIO3 pin is configured as GPO (general-purpose output). Program '1' for TQFN packaged device
DI3 (1)
DI2 (1)
DI1 (1)
DI0 (1)
0
0
0
0
0 = GPIO2 pin is configured as GPI. Setting is not valid for TQFN packaged device
1 = GPIO2 pin is configured as GPO. Program '1' for TQFN packaged device
0 = GPIO1 pin is configured as GPI. Setting is not valid for TQFN packaged device
1 = GPIO1 pin is configured as GPO. Program '1' for TQFN packaged device
0 = GPIO0 pin is configured as GPI. Valid setting for TQFN packaged device
1 = GPIO0 pin is configured as GPO. Valid setting for TQFN packaged device
NOTE:
1. The bits are valid for GPIOs that are not assigned a specific function by bits DI[8:4].
Alarm Thresholds for GPIO Pins
Each channel has separate high alarm threshold and low
alarm threshold. To configure chip quickly, the input
channels are divided into 4 groups, each group can be
programmed consecutively (8 registers are programmed in
one sequence).
Once DI12 is enabled, the chip quits the configuration
sequence in the next frame.
Table 10. Alarm Program Registers Groups
Alarm
Program
Register
DI[15:12]
Group
Registers
In Table 10, the chip has its input channels divide into 4
groups.
High and low alarm for CH0, CH1, CH2 and
CH3
0
1
2
3
1100
1101
1110
1111
High and low alarm for CH4, CH5, CH6 and
CH7
Table 11 shows details of the alarm program register.
High and low alarm for CH8, CH9, CH10
and CH11
Each group needs 9 operation frames to complete the
alarm thresholds configuration. The chip supports quit the
configuration sequence in middle of progress (DI12 in alarm
program register is enabled, and < 8 registers is configured).
High and low alarm for CH12, CH13, CH14
and CH15
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
23
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Device in any operation mode
Program alarm thresholds?
Yes
Frame N
Enter alarm
program register
setting sequence
SDI: DI[15:12] = 11xx
(xx indicates group of four channels; refer Table 10)
Device enters alarm register programming sequence
Frame N+1
Setting alarm
thresholds
SDI: DI[15:0] as per Table 11
(program alarm thresholds)
No
DI12 is enabled?
Yes, quit current configuration group
Yes
Program another group of four channels?
No
End of alarm programming
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 11. Alarm Program Register Programming Flowchart
Table 11. Alarm Program Register Details
RESET
STATE
BITS
DESCRIPTION
Frame 1
1100 = Alarm programming sequence for group 0
1101 = Alarm programming sequence for group 1
1110 = Alarm programming sequence for group 2
1111 = Alarm programming sequence for group 3
Note: DI[15:12] = 11AA is the alarm programming request for group AA. "AA" means the alarm programming
group number in binary format.
DI[15:12]
DI[11:0]
NA
NA
Do not care.
Frame 2 and Onwards
CC = "CC" means the channel number in binary format in group AA (each group has 4 channels)
DI[15:14] The SGM5200 programs the alarm for the channel represented by the binary number "AACC". "AA" is
programmed in Frame 1.
NA
NA
0 = Configure low alarm register
DI13
1 = Configure high alarm register
0 = Continue alarm programming sequence in the next frame
1 = Exit alarm programming in the next frame
Note: To quit the threshold configure sequence if all threshold registers have been configured, DI12 must be set
to '1' to quit.
DI12
NA
NA
DI[11:10] Do not care.
'1111111111'
for high alarm
register
and
DI[9:0]
The 10-bit alarm threshold is compared with the upper 10-bit of the 12-bit conversion result.
'0000000000'
for low alarm
register
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
24
12-Bit, 1MSPS, 16 Channels,
SGM5200
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION (continued)
Analog Input
Figure 12 shows the equivalent circuit model for the MUX and ADC.
MXO
12pF
AINP
CH0
150Ω
80Ω
6pF
6pF
6pF
7pF
CH15
80MΩ
NOTE: CH0 is assumed to be on, and CH15 is assumed to be off.
Figure 12. Equivalent Circuit for ADC and MUX
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SEPTEMBER 2022 ‒ REV.A to REV.A.1
Page
Update Electrical Characteristics section.............................................................................................................................................................5
Changes from Original (SEPTEMBER 2021) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022
25
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TSSOP-38
D
E1
E
5.94
1.78
b
e
0.30
0.50
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
θ
A1
H
c
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
MIN
MAX
A
A1
A2
b
1.200
0.150
1.000
0.270
0.200
9.800
4.500
6.550
0.047
0.006
0.039
0.011
0.008
0.386
0.177
0.258
0.050
0.800
0.170
0.090
9.600
4.300
6.250
0.002
0.031
0.007
0.004
0.378
0.169
0.246
c
D
E
E1
e
0.500 BSC
0.250 TYP
0.020 BSC
0.010 TYP
H
L
0.450
1°
0.750
7°
0.018
1°
0.030
7°
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
TX00183.001
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-5×5-32L
D
e
N17
L
D1
E
E1
N32
N1
k
b
TOP VIEW
BOTTOM VIEW
3.4
3.4 4.1
5.5
A
A1
A2
SIDE VIEW
0.7
0.24
0.5
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
0.800
0.050
MIN
0.028
0.000
MAX
0.031
0.002
A
A1
A2
D
0.700
0.000
0.203 REF
0.008 REF
4.924
3.300
4.924
3.300
5.076
3.500
5.076
3.500
0.194
0.130
0.194
0.130
0.200
0.138
0.200
0.138
D1
E
E1
k
0.200 MIN
0.500 TYP
0.008 MIN
0.020 TYP
b
0.180
0.324
0.300
0.476
0.007
0.013
0.012
0.019
e
L
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00089.000
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
TSSOP-38
13″
13″
16.4
12.4
6.80
5.30
10.20
5.30
1.60
1.10
4.0
4.0
8.0
8.0
2.0
2.0
16.0
12.0
Q1
Q2
TQFN-5×5-32L
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
相关型号：
©2020 ICPDF网 联系我们和版权申明