SGM41543/SGM41543D [SGMICRO]
High Input Voltage, 3.78A Single-Cell Battery Charger with NVDC Power Path Management;![SGM41543/SGM41543D](http://pdffile.icpdf.com/pdf2/p00358/img/icpdf/SGM41543-SGM_2195811_icpdf.jpg)
型号: | SGM41543/SGM41543D |
厂家: | ![]() |
描述: | High Input Voltage, 3.78A Single-Cell Battery Charger with NVDC Power Path Management 电池 |
文件: | 总8页 (文件大小:449K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SGM41543/SGM41543D
High Input Voltage,
3.78A Single-Cell Battery Charger
with NVDC Power Path Management
● Flexible Autonomous and I2C Operation Modes for
Optimal System Performance
FEATURES
● High Efficiency, 1.5MHz, Synchronous Buck Charger
● Fully Integrated Switches, Current Sense and
Compensation
94% Charge Efficiency at 1A from 5V Input
91% Charge Efficiency at 2A from 9V Input
Optimized for USB Voltage Input (5V)
● External Direct Charging Path Enable Output
● 8μA Ship Mode Low Battery Leakage Current
● High Accuracy
Selectable PFM Mode for Light Load Efficiency
● USB On-The-Go (OTG) Support (Boost Mode)
±0.5% Charge Voltage Regulation (8mV/Step)
±5% Charge Current Regulation at 1.5A
±10% Input Current Regulation at 0.9A
Boost Converter with up to 2A Output
Boost Efficiency of 94.8% at 0.5A and 94.5% at 1A
Accurate Hiccup Mode Over-Current Protection
Output Short Circuit Protection
● Safety
Battery Temperature Sensing (Charge/Boost Modes)
Selectable PFM Mode for Light Load Operations
Thermal Regulation and Thermal Shutdown
Input Under-Voltage Lockout (UVLO)
Input Over-Voltage (ACOV) Protection
● Single Input for USB or High Voltage Adaptors
3.9V to 13.5V Operating Input Voltage Range
22V Absolute Maximum Input Voltage Rating
Programmable Input Current Limit and Dynamic
Power Management (IINDPM, 100mA to 3.1A with
100mA Resolution & 3.8A) to Support USB 2.0 and
USB 3.0 Standards and High Voltage Adaptors
Maximum Power Tracking by Programmable Input
Voltage Limit (VINDPM) with Selectable Offset
VINDPM Tracking of Battery Voltage
APPLICATIONS
Smart Phones, EPOS
Portable Internet Devices and Accessory
SIMPLIFIED SCHEMATIC
Auto Detect USB BC1.2, SDP, CDP, DCP and
Non-Standard Adaptors
Input
PMID
LS/SC
3.9V to 13.5V
USB
VBUS
DCEN
OTG
● High Battery Discharge Efficiency with 16mΩ Switch
● Narrow Voltage DC (NVDC) Power Path Management
5.15V at 2A
VSYS
SW
I2C Bus
BTST
SYS
BAT
Instant-On with No or Highly Depleted Battery
Host
ICHG
Ideal Diode Operation in Battery Supplement Mode
Host Control
REGN
● Ship Mode, Wake-Up and Full System Reset Capability
nQON
TS
by Battery FET Control
SGM41543
SGM41543D
Optional
SG Micro Corp
MAY 2023 – REV. A. 2
www.sg-micro.com
SGM41543
SGM41543D
High Input Voltage, 3.78A Single-Cell Battery Charger
with NVDC Power Path Management
GENERAL DESCRIPTION
The SGM41543/SGM41543D are battery chargers and
system power path management devices with integrated
converter and power switches for using with single-cell Li-Ion
or Li-polymer batteries. This highly integrated 3.78A device is
capable of fast charging and supports a wide input voltage
range suitable for smart phones, tablets and portable systems.
I2C programming makes it a very flexible powering and
charger design solution.
increase after reduction of charge current down to zero, the
power path management provides the deficit from battery by
discharging battery to the system until the system power
demand is fulfilled. This is called supplement mode, which
prevents the input source from overloading.
Starting and termination of a charging cycle can be
accomplished without software control. The sensed battery
voltage is used to decide for starting phase of charging in one
of the three phases of charging cycle: pre-conditioning,
constant current or constant voltage. When the charge
current falls below a preset limit and the battery voltage is
above recharge threshold, the charger function will
automatically terminate and end the charging cycle. If the
voltage of a charged battery falls below the recharge
threshold, the charger begins another charging cycle.
The devices include four main power switches: input reverse
blocking FET (RBFET, Q1), high-side switching FET for Buck
or Boost mode (HSFET, Q2), low-side switching FET for Buck
or Boost mode (LSFET, Q3) and battery FET that controls the
interconnection of the system and battery (BATFET, Q4). The
bootstrap diode for the high-side gate driving is also
integrated. The internal power path has a very low impedance
that reduces the charging time and maximizes the battery
discharge efficiency. Moreover, the input voltage and current
regulations provide maximum charging power delivery to the
battery with various types of input sources.
Several safety features are provided in the SGM41543/
SGM41543D such as over-voltage and over-current
protections, battery temperature monitoring, charging safety
timing, thermal shutdown and input UVLO. TS pin is
connected to an NTC thermistor for battery temperature
monitoring and protection in both charge and Boost modes
according to JEITA profile. This device also features thermal
regulation in which the charge current is reduced, if the
junction temperature exceeds 80℃ or 120℃ (selectable).
A wide range of input sources are supported, including
standard USB hosts, charging ports and USB compliant high
voltage adaptors. The default input current limit is
automatically selected based on the built-in USB interface.
This limit is determined by the detection circuit in the system
(e.g. USB PHY). SGM41543/SGM41543D are USB 2.0 and
USB 3.0 power specifications compliant with input current
and voltage regulation. It also meets USB On-The-Go (OTG)
power rating specification and is capable to boost the battery
voltage to supply 5.15V on VBUS with 2A (or 1.2A) current
limit.
Charging status is reported by the STAT output and
fault/status bits. A negative pulse is sent to the nINT output
pin as soon as a fault occurs to notify the host. BATFET reset
control is provided by nQON pin to exit ship mode or for a full
system reset.
The devices supply a DCEN signal to control an external
P-MOSFET or load switch as a direct charging path for low
voltage PMID, or to control a 2:1 switching capacitor divider
for high voltage PMID.
The system voltage is regulated slightly above the battery
voltage by the power path management circuit and is kept
above the programmable minimum system voltage (3.5V by
default). Therefore, system power is maintained even if the
battery is completely depleted or removed. Dynamic power
management (DPM) feature is also included that
automatically reduces the charge current if the input current
or voltage limit is reached. If the system load continues to
The SGM41543/SGM41543D are available in a Green
TQFN-4×4-24L package.
SG Micro Corp
www.sg-micro.com
MAY 2023
2
SGM41543
SGM41543D
High Input Voltage, 3.78A Single-Cell Battery Charger
with NVDC Power Path Management
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM41543
YTQF24
XXXXX
SGM41543
SGM41543D
TQFN-4×4-24L
SGM41543YTQF24G/TR
SGM41543DYTQF24G/TR
Tape and Reel, 3000
Tape and Reel, 3000
-40℃ to +85℃
-40℃ to +85℃
SGMMCC
YTQF24
XXXXX
TQFN-4×4-24L
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
Voltage Range (with Respect to GND)
RECOMMENDED OPERATING CONDITIONS
Input Voltage Range, VVBUS..............................3.9V to 13.5V
Input Current (VBUS), IIN..................................... 3.8A (MAX)
Output DC Current (SW), ISWOP .............................. 5A (MAX)
Battery Voltage, VBATOP ................................... 4.624V (MAX)
Fast Charging Current, ICHGOP ........................... 3.78A (MAX)
Discharging Current (Continuous), IBATOP............... 6A (MAX)
Ambient Temperature Range......................... -40℃ to +85℃
Junction Temperature Range....................... -40℃ to +125℃
VAC, VBUS (Converter Not Switching)............-2V to 22V (1)
BTST, PMID (Converter Not Switching)........... -0.3V to 22V
SW ...................................................................... -2V to 16V
SW (Peak for 10ns Duration).............................. -3V to 16V
BTST to SW....................................................... -0.3V to 6V
D+, D- ................................................................ -0.3V to 6V
REGN, TS, nCE, BAT, SYS (Converter Not Switching)
........................................................................... -0.3V to 6V
SDA, SCL, nINT, nQON, STAT, DCEN ............. -0.3V to 6V
Output Sink Current
OVERSTRESS CAUTION
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
STAT.............................................................................6mA
nINT..............................................................................6mA
Package Thermal Resistance
TQFN-4×4-24L, θJA.................................................. 35℃/W
TQFN-4×4-24L, θJB............................................................................10℃/W
TQFN-4×4-24L, θJC............................................................................16℃/W
Junction Temperature.................................................+150℃
Storage Temperature Range........................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................2000V
CDM ............................................................................1000V
NOTE: 1. Maximum 28V for 10 seconds.
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
MAY 2023
3
SGM41543
SGM41543D
High Input Voltage, 3.78A Single-Cell Battery Charger
with NVDC Power Path Management
PIN CONFIGURATIONS
SGM41543 (TOP VIEW)
SGM41543D (TOP VIEW)
24 23 22 21 20 19
24 23 22 21 20 19
VAC
1
2
3
4
5
6
18 GND
17 GND
16 SYS
VBUS
D+
1
2
3
4
5
6
18 GND
17 GND
16 SYS
PSEL
D-
nPG
SGM41543
SGM41543D
STAT
SYS
STAT
SYS
15
14 BAT
BAT
15
14 BAT
BAT
SCL
SDA
SCL
SDA
13
13
7
8
9
10 11 12
7
8
9
10 11 12
TQFN-4×4-24L
TQFN-4×4-24L
PIN DESCRIPTION
PIN
NAME
TYPE (1)
FUNCTION
SGM
SGM
41543
41543D
Sense Input for DC Input Voltage (Typically from an AC/DC Adaptor). It must be connected
to VBUS pin. (SGM41543 only)
1
2
—
—
VAC
AI
DI
Power Source Selection Input. If PSEL is pulled high, the input current limit is set to 500mA
(USB 2.0) and if it is pulled low, the limit is set to 2.4A (adaptor). When the I2C link to the
host is established, the host can program a different input current limit value by writing to
the IINDPM[4:0] register. (SGM41543 only)
PSEL
Positive USB Data Line. D+/D- based USB device protocol detection and voltage of this pin
can be set by DP_VSET[1:0]. (SGM41543D only)
—
3
2
—
3
D+
nPG
D-
AIO
DO
Open-Drain Active Low Input Power Good Indicator. Use a 10kΩ pull-up to the logic high
rail. A low state indicates a good input (VVBUS_UVLOZ < VVBUS < VVBUS_OV, VVBUS is above sleep
mode threshold, and VVBUS > VVBUSMIN when IBAD_SRC = 25mA). (SGM41543 only)
Negative USB Data Line. D+/D- based USB device protocol detection and voltage of this
pin can be set by DM_VSET[1:0]. (SGM41543D only)
—
AIO
Open-Drain Charge Status Output. Use a 10kΩ pull-up to the logic high rail (or an LED + a
resistor). The STAT pin acts as follows:
During charge: low (LED ON).
4
4
STAT
DO
Charge completed or charger in sleep mode: high (LED OFF).
Charge suspended (in response to a fault): 1Hz, 50% duty cycle pulses (LED BLINKS).
The function can be disabled via EN_ICHG_MON[1:0] register.
5
6
5
6
SCL
SDA
DI
I2C Clock Signal. Use a 10kΩ pull-up to the logic high rail.
I2C Data Signal. Use a 10kΩ pull-up to the logic high rail.
DIO
Open-Drain Interrupt Output Pin. Use a 10kΩ pull-up to the logic high rail. The nINT pin is
active low and sends a negative 256µs pulse to inform host about a new charger status
update or a fault.
7
8
7
nINT
NC
DO
—
8, 24
Do Not Connect and Leave This Pin Floating.
SG Micro Corp
www.sg-micro.com
MAY 2023
4
SGM41543
SGM41543D
High Input Voltage, 3.78A Single-Cell Battery Charger
with NVDC Power Path Management
PIN DESCRIPTION (continued)
PIN
NAME
TYPE (1)
FUNCTION
SGM
SGM
41543
41543D
Charge Enable Input Pin (Active Low). Battery charging is enabled when CHG_CONFIG bit
is 1 and nCE pin is pulled low.
9
9
nCE
DI
—
External Direct Charge Enable Pin. This pin can be set high to enable an external direct
charging device.
10
10
DCEN
Temperature Sense Input Pin. Connect to the battery NTC thermistor that is grounded on
the other side. To program operating temperature window, it can be biased by a resistor
divider between REGN and GND. Charge suspends if TS voltage goes out of the
programmed range. It is recommended to use a 103AT-2 type thermistor.
11
12
11
12
TS
AI
DI
If NTC or TS pin function is not needed, use a 10kΩ/10kΩ pair for the resistor divider.
BATFET On/Off Control Input. Use an internal pull-up to a small voltage for maintaining the
default high logic (whenever a source or battery is available). In the ship mode, the
BATFET is off. To exit ship mode and turn BATFET on, a logic low pulse with a duration of
tSHIPMODE (1s TYP) can be applied to nQON. When VBUS source is not connected, a logic
low pulse with a duration of tQON_RST (10s TYP) resets the system power (SYS) by turning
BATFET off for tBATFET_RST (320ms TYP) and then backs on to provide a full power reset for
system.
nQON
Battery Positive Terminal Pin. Use a 10µF capacitor between BAT and GND pins close to
the device. SYS and BAT pins are internally connected by BATFET with current sensing
capability.
13, 14
15, 16
13, 14
15, 16
BAT
SYS
P
P
Connection Point to Converter Output. SYS is connected to the converter LC filter output
that powers the system. BAT to SYS internal current (power from battery to system) is
sensed. Connect a 20μF capacitor between SYS pin and GND close to the device.
17, 18
19, 20
17, 18
19, 20
GND
SW
—
P
Ground Pin of the Device.
Switching Node Output. Connect SW pin to the output inductor. Connect a 47nF bootstrap
capacitor from SW pin to BTST pin.
High-side Driver Positive Supply. It is internally connected to the boost-strap diode
cathode. Use a 47nF ceramic capacitor from SW pin to BTST pin.
21
22
21
22
BTST
P
P
LDO Output that Powers LSFET Driver and Internal Circuits. Internally, the REGN pin is
connected to the anode of the bootstrap diode. Place a 4.7μF (10V rating) ceramic
capacitor between REGN pin and GND. It is recommended to place the capacitor close to
the REGN pin.
REGN
PMID Pin. PMID is the actual higher voltage port of converter (Buck or Boost) and is
connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.
Connect a 22μF ceramic capacitor from PMID pin to GND. It is the proper point for
decoupling of high frequency switching currents.
23
24
23
1
PMID
VBUS
—
P
P
P
Charger Input (VIN). The internal N-channel reverse blocking MOSFET (RBFET) is
connected between VBUS and PMID pins. Place a 1μF ceramic capacitor from VBUS pin
to GND close to the device. For SGM41543, this pin senses the input voltage.
Thermal Pad and Ground Reference. It is the ground reference for the device and also the
thermal pad to conduct heat from the device (not suitable for high current return). Tie it
externally to the PCB ground plane (GND). Thermal vias under the pad are needed to
conduct the heat to the PCB ground planes.
Exposed
Pad
Exposed
Pad
NOTE:
1. AI = Analog Input, AO = Analog Output, AIO = Analog Input and Output, DI = Digital Input, DO = Digital Output, DIO = Digital
Input and Output, P = Power.
SG Micro Corp
www.sg-micro.com
MAY 2023
5
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-4×4-24L
D
e
L
D1
E
E1
N24
k
PIN 1#
N1
b
DETAIL A
TOP VIEW
BOTTOM VIEW
3.8
2.7
C
SEATING PLANE
A
A1
A2
eee
C
2.7 3.8
SIDE VIEW
0.7
ALTERNATE A-1
ALTERNATE A-2
0.5
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
0.24
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions In Millimeters
Symbol
MIN
0.700
0.000
MOD
MAX
0.800
0.050
A
A1
A2
b
-
-
0.203 REF
0.180
3.900
3.900
2.600
2.600
-
0.300
4.100
4.100
2.800
2.800
D
-
E
-
D1
E1
e
-
-
0.500 BSC
0.200 MIN
-
k
L
0.300
0.500
eee
0.080
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00086.001
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
TQFN-4×4-24L
13″
12.4
4.30
4.30
1.10
4.0
8.0
2.0
12.0
Q2
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
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