SGM41518_技术文档

SGM41518

High Input Voltage,

1.26A Single-Cell Battery Charger

with NVDC Power Path Management

● External Direct Charging Path Enable Output

● 9μA Ship Mode Low Battery Leakage Current

FEATURES

● High Efficiency, 1.5MHz, Synchronous Buck Charger

● High Accuracy



95% Charge Efficiency at 1A from 5V Input



±0.5% Charge Voltage Regulation (8mV/step)

Selectable PFM Mode for Light Load Efficiency

±5% Charge Current Regulation at 1.26A

±7.5% Input Current Regulation at 0.5A

● Boost Mode Support



Boost Efficiency of 95.5% at 0.5A and 95% at 1A

PMID_GD Pin Control External P-MOSFET for

Protection against Fault Conditions

● Safety



Battery Temperature Sensing (Charge/Boost Modes)

Thermal Regulation and Thermal Shutdown

Input Under-Voltage Lockout (UVLO)

Input Over-Voltage (ACOV) Protection



Selectable PFM Mode for Light Load Operations

● Single Input for USB or High Voltage Adapters



3.9V to 13.5V Operating Input Voltage Range

22V Absolute Maximum Input Voltage Rating

Programmable Input Current Limit and Dynamic

Power Management (IINDPM, 100mA to 3.2A with

100mA Resolution) to Support USB 2.0 and USB 3.0

Standards and High Voltage Adaptors

APPLICATIONS

Smart Phones, EPOS

Portable Internet Devices and Accessory



Maximum Power Tracking by Programmable Input

Voltage Limit (VINDPM) with Selectable Offset

VINDPM Tracking of Battery Voltage

SIMPLIFIED SCHEMATIC

Input

PMID

Earphone

3.9V to 13.5V

● High Battery Discharge Efficiency with 10mΩ Switch

● Narrow Voltage DC (NVDC) Power Path Management

USB

VBUS

VSYS

SW



Instant-On with No or Highly Depleted Battery

I²C Bus

BTST

SYS

BAT

Ideal Diode Operation in Battery Supplement Mode

Host

● Ship Mode, Wake-Up and Full System Reset Capability

by Battery FET Control

● Flexible Autonomous and I²C Operation Modes for

I_CHG

Host Control

REGN

nQON

TS

Optimal System Performance

SGM41518

Optional

● Fully Integrated Switches, Current Sense and

Compensation

SG Micro Corp

SEPTEMBER 2022 – REV. A

www.sg-micro.com

High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

GENERAL DESCRIPTION

The SGM41518 is a battery charger and system power path

management device with integrated converter and power

switches for using with single-cell Li-Ion or Li-polymer

batteries. This highly integrated 1.26A device is capable of

fast charging and supports a wide input voltage range

suitable for wearable and earphone applications. I²C

programming makes it a very flexible powering and charger

design solution.

management (DPM) feature is also included that

automatically reduces the charge current if the input current

or voltage limit is reached. If the system load continues to

increase after reduction of charge current down to zero, the

power path management provides the deficit from battery by

discharging battery to the system until the system power

demand is fulfilled. This is called supplement mode, which

prevents the input source from overloading.

The device includes four main power switches: input reverse

blocking FET (RBFET, Q1), high-side switching FET for Buck

or Boost mode (HSFET, Q2), low-side switching FET for Buck

or Boost mode (LSFET, Q3) and battery FET that controls the

interconnection of the system and battery (BATFET, Q4). The

bootstrap diode for the high-side gate driving is also

integrated. The internal power path has a very low impedance

that reduces the charging time and maximizes the battery

discharge efficiency. Moreover, the input voltage and current

regulations provide maximum charging power delivery to the

battery with various types of input sources.

Starting and termination of a charging cycle can be

accomplished without software control. The sensed battery

voltage is used to decide for starting phase of charging in one

of the three phases of charging cycle: pre-conditioning,

constant current or constant voltage. When the charge

current falls below a preset limit and the battery voltage is

above recharge threshold, the charger function will

automatically terminate and end the charging cycle. If the

voltage of a charged battery falls below the recharge

threshold, the charger begins another charging cycle.

Several safety features are provided in the SGM41518 such

as over-voltage and over-current protections, battery

temperature monitoring, charging safety timing, thermal

shutdown and input UVLO. TS pin is connected to an NTC

thermistor for battery temperature monitoring and protection

in both charge and Boost modes according to JEITA profile.

This device also features thermal regulation in which the

charge current is reduced, if the junction temperature

exceeds 80℃ or 120℃ (selectable).

A wide range of input sources are supported, including

standard USB hosts, charging ports and USB compliant high

voltage adapters. The SGM41518 is USB 2.0 and USB 3.0

power specifications compliant with input current and voltage

regulation. This limit is determined by the detection circuit in

the system (e.g. USB PHY).

The SGM41518 is capable to boost the battery voltage to

supply 5V (adjustable 4.85V/5V/5.15V/5.3V) on PMID. The

Boost mode is used to charge another battery by the control

of PMID_GD. The PMID_GD pin is used to drive an external

P-MOSFET to disconnect Boost output PMID from attached

accessories.

Charging status is reported by the STAT output and

fault/status bits. A negative pulse is sent to the nINT output

pin as soon as a fault occurs to notify the host. BATFET reset

control is provided by nQON pin to exit ship mode or for a full

system reset.

The system voltage is regulated slightly above the battery

voltage by the power path management circuit and is kept

above the programmable minimum system voltage (3.5V by

default). Therefore, system power is maintained even if the

battery is completely depleted or removed. Dynamic power

The SGM41518 is available in a Green WLCSP-2.0×2.4-30B

package.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

2

High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

ORDERING

NUMBER

PACKAGE

MARKING

PACKING

OPTION

MODEL

SGM

41518

XXXXX

XX#XX

SGM41518 WLCSP-2.0×2.4-30B

-40℃ to +85℃

SGM41518YG/TR

Tape and Reel, 3000

MARKING INFORMATION

NOTE: XXXXX = Date Code, Trace Code and Vendor Code.

Date Code - Year

Trace Code

Vendor Code

X X X X X

XX＃XX

Coordinate Information

Wafer ID Number ("A" = 01, "B" = 02, …"Y" = 25)

Coordinate Information

Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If

you have additional comments or questions, please contact your SGMICRO representative directly.

ABSOLUTE MAXIMUM RATINGS

Voltage Range (with Respect to GND)

RECOMMENDED OPERATING CONDITIONS

Input Voltage Range, V_VBUS..............................3.9V to 13.5V

Input Current (VBUS), I_IN..................................... 3.4A (MAX)

Output DC Current (SW), I_SWOP......................... 3.25A (MAX)

Battery Voltage, V_BATOP................................... 4.624V (MAX)

Fast Charging Current, I_CHGOP........................... 1.26A (MAX)

Discharging Current (Continuous), I_BATOP............... 6A (MAX)

Ambient Temperature Range......................... -40℃ to +85℃

Junction Temperature Range....................... -40℃ to +125℃

VAC, VBUS (Converter Not Switching)............-2V to 22V ⁽¹⁾

BTST, PMID (Converter Not Switching)........... -0.3V to 22V

SW ...................................................................... -2V to 16V

SW (Peak for 10ns Duration).............................. -3V to 16V

BTST to SW....................................................... -0.3V to 6V

REGN, TS, nCE, BAT, BATSNS, SYS (Converter Not

Switching) .......................................................... -0.3V to 6V

SDA, SCL, nINT, nQON, STAT, PMID_GD ....... -0.3V to 6V

Output Sink Current

OVERSTRESS CAUTION

STAT..................................................................6mA (MAX)

nINT...................................................................6mA (MAX)

Package Thermal Resistance

Stresses beyond those listed in Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods

may affect reliability. Functional operation of the device at any

conditions beyond those indicated in the Recommended

Operating Conditions section is not implied.

WLCSP-2.0×2.4-30B, θ_JA......................................... 68℃/W

Junction Temperature.................................................+150℃

Storage Temperature Range........................-65℃ to +150℃

Lead Temperature (Soldering, 10s)............................+260℃

ESD Susceptibility

ESD SENSITIVITY CAUTION

HBM.............................................................................2000V

CDM ............................................................................1000V

This integrated circuit can be damaged if ESD protections are

not considered carefully. SGMICRO recommends that all

integrated circuits be handled with appropriate precautions.

Failureto observe proper handlingand installation procedures

can cause damage. ESD damage can range from subtle

performance degradation tocomplete device failure. Precision

integrated circuits may be more susceptible to damage

because even small parametric changes could cause the

device not to meet the published specifications.

NOTE: 1. Maximum 28V for 10 seconds.

DISCLAIMER

SG Micro Corp reserves the right to make any change in

circuit design, or specifications without prior notice.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

3

High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

PIN CONFIGURATION

(TOP VIEW)

1

2

3

4

5

GND

SW

PMID

VBUS

VAC

A

B

C

D

E

F

GND

BAT

SW

SYS

PMID

BTST

TS

VBUS

REGN

nQON

SDA

NC

PSEL

PMID_

GD

nCE

STAT

SCL

BAT

SNS

nINT

WLCSP-2.0×2.4-30B

PIN DESCRIPTION

NAME

TYPE ⁽¹⁾

FUNCTION

A1, B1

GND

—

Ground Pin of the Device.

C1, D1

E1, F1

Battery Positive Terminal Pin. Use a 10µF capacitor between BAT and GND pins close to the device.

SYS and BAT pins are internally connected by BATFET with current sensing capability.

BAT

SW

P

Switching Node Output. Connect SW pin to the output inductor. Connect a 47nF bootstrap capacitor

from SW pin to BTST pin.

A2, B2

Connection Point to Converter Output. SYS is connected to the converter LC filter output that powers

the system. BAT to SYS internal current (power from battery to system) is sensed. Connect a 20μF

capacitor between SYS pin and GND close to the device (in addition to C_OUT).

C2, D2

E2, F2

SYS

P

PMID Pin. PMID is the actual higher voltage port of converter (Buck or Boost) and is connected to the

drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Connect a 22μF ceramic

capacitor from PMID pin to GND. It is the proper point for decoupling of high frequency switching

currents.

A3, B3

C3

PMID

BTST

P

High-side Driver Positive Supply. It is internally connected to the boost-strap diode cathode. Use a

47nF ceramic capacitor from SW pin to BTST pin.

Temperature Sense Input Pin. Connect to the battery NTC thermistor that is grounded on the other

side. To program operating temperature window, it can be biased by a resistor divider between REGN

and GND. Charge suspends if TS voltage goes out of the programmed range. It is recommended to

use a 103AT-2 type thermistor.

D3

TS

AI

If NTC or TS pin function is not needed, use a 10kΩ/10kΩ pair for the resistor divider.

Charge Enable Input Pin (Active Low). Battery charging is enabled when CHG_CONFIG bit is 1 and

nCE pin is pulled low.

E3

F3

nCE

DI

Battery Voltage Sensing Pin for Charge Current Regulation. BATSNS pin is connected to the actual

battery pack as close as possible to reduce the parasitic trace resistance during charging.

BATSNS

AIO

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

4

High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

PIN DESCRIPTION (continued)

NAME

TYPE ⁽¹⁾

FUNCTION

Charger Input (V_IN). The internal N-channel reverse blocking MOSFET (RBFET) is connected between

VBUS and PMID pins. Place a 1μF ceramic capacitor from VBUS pin to GND close to the device.

A4, B4

VBUS

P

LDO Output that Powers LSFET Driver and Internal Circuits. Internally, the REGN pin is connected to

the anode of the bootstrap diode. Place a 4.7μF (10V rating) ceramic capacitor between REGN pin and

GND. It is recommended to place the capacitor close to the REGN pin.

C4

D4

REGN

nQON

P

BATFET On/Off Control Pin. Use an internal pull-up to a small voltage for maintaining the default high

logic (whenever a source or battery is available). In the ship mode, the BATFET is off. To exit ship

mode and turn BATFET on, a logic low pulse with a duration of t_SHIPMODE(1s TYP) can be applied to

nQON. When VBUS source is not connected, a logic low pulse with a duration of t_{QON_RST}(10s TYP)

resets the system power (SYS) by turning BATFET off for t_{BATFET_RST}(320ms TYP) and then back on to

provide a full power reset for system.

DI

E4

F4

SDA

nINT

DIO

DO

I²C Data Signal. Use a 10kΩ pull-up to the logic high rail.

Open-Drain Interrupt Output Pin. Use a 10kΩ pull-up to the logic high rail. The nINT pin is active low

and sends a negative 256µs pulse to inform host about a new charger status update or a fault.

A5

B5

VAC

NC

AI

—

Sense Input for DC Input Voltage (Typically from an AC/DC Adaptor). Must be connected to VBUS pin.

No Connection.

Power Source Selection Input. If PSEL is pulled high, the input current limit is set to 500mA (USB 2.0)

and if it is pulled low, the limit is set to 2.4A (adaptor). When the I²C link to the host is established, the

host can program a different input current limit value by writing to the IINDPM[4:0] register.

C5

D5

PSEL

DI

Open-Drain PMID Good Indicator. Active high. Connect a 10kΩ resistor to the pull-up rail REGN. HIGH

indicates PMID voltage is below 6V and the current through Q1 is below 106% of input current limit. If

the Boost mode output voltage is too high or output current is too high, the signal can be used to drive

external P-MOSFET to disconnect the PMID under charging load.

PMID_GD

DO

Open-Drain Charge Status Output. Use a 10kΩ pull-up to the logic high rail (or an LED + a resistor).

The STAT pin acts as follows:

During charge: low (LED ON).

E5

F5

STAT

SCL

DO

DI

Charge completed or charger in sleep mode: high (LED OFF).

Charge suspended (in response to a fault): 1Hz, 50% duty cycle pulses (LED BLINKS).

The function can be disabled via EN_ICHG_MON[1:0] register.

I²C Clock Signal. Use a 10kΩ pull-up to the logic high rail.

NOTE:

1. AI = Analog Input, AO = Analog Output, AIO = Analog Input and Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input and Output,

P = Power.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

5

High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

ELECTRICAL CHARACTERISTICS

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Quiescent Currents

Battery Discharge Current

(BAT, SW, SYS) in Buck Mode

V_BAT= 4.5V, V_VBUS< V_{VAC_UVLOZ}, leakage between

BAT and VBUS, BATFET off

I_{BQ_VBUS}

I_{BQ_HIZ_BOFF}

I_{BQ_HIZ_BON}

0.1

9

1

µA

Battery Discharge Current

(BAT) in Buck Mode

V_BAT= 4.5V, HIZ mode and BATFET_DIS = 1

or no VBUS, I²C disabled, BATFET disabled

20

30

40

Battery Discharge Current

(BAT, SW, SYS)

V_BAT= 4.5V, HIZ mode and BATFET_DIS = 0

or no VBUS, I²C disabled, BATFET enabled

15

20

V

_VBUS= 5V, HIZ mode and BATFET_DIS = 1,

no battery

I_{VBUS_HIZ}

µA

V_VBUS= 12V, HIZ mode and BATFET_DIS = 1,

no battery

40

2.5

3

65

Input Supply Current

(VBUS) in Buck Mode

V

_VBUS= 12V, V_VBUS> V_BAT, converter not switching

3.5

I_VBUS

mA

V_BAT= 3.8V, I_SYS= 0A, V_VBUS> V_BAT

,

V

_VBUS> V_{VAC_UVLOZ}, converter switching, BATFET off

Battery Discharge Current

in Boost Mode

I_BOOST

V_BAT= 4.2V, I_VBUS= 0A, converter switching

3

BAT Pin, VAC Pin and VBUS Pin Power-Up

VBUS Operating Range

V_{VBUS_OP}

V_VBUSrising

3.9

13.5

3.45

V

VBUS UVLO to Have Active I²C

(with No Battery) Seen by Sense

VAC Pin

V_{VAC_UVLOZ}

3.2

V_VACrising, T_J= +25℃

I²C Active Hysteresis

V_{VAC_UVLOZ_HYS}V_VACfalling from above V_{VAC_UVLOZ}

V_{VAC_PRESENT}

400

3.4

mV

V

V_VACMinimum (as One of the

Conditions) to Turn on REGN

V_VACHysteresis (as One of the

Conditions) to Turn on REGN

3.7

V_VACrising, T_J= +25℃

V_{VAC_PRESENT_HYS}V_VACfalling from above V_{VAC_PRESENT}

400

50

mV

V_VAC- V_BAT, V_{VBUSMIN_FALL}≤ V_BAT≤ V_REG, V_VACfalling,

T_J= +25℃

Sleep Mode Falling Threshold

Sleep Mode Rising Threshold

V_SLEEP

20

80

V_VAC- V_BAT, V_{VBUSMIN_FALL}≤ V_BAT≤ V_REG, V_VACrising,

T_J= +25℃

V_SLEEPZ

145

190

235

mV

V

6.5V Setting

VAC

OVP[1:0] = 01

6.25

10.1

13.5

6.5

10.5

14

6.75

10.9

14.5

Over-Voltage

Rising Threshold

10.5V Setting

14V Setting

6.5V Setting

10.5V Setting

14V Setting

V_{VAC_OV_RISE}

V_VACrising

OVP[1:0] = 10

OVP[1:0] = 11

OVP[1:0] = 01

OVP[1:0] = 10

OVP[1:0] = 11

100

250

300

VAC

Over-Voltage

Hysteresis

V_{VAC_OV_HYS}

mV

BAT Voltage to Have Active I²C

(No Source on VBUS)

V_{BAT_UVLOZ}

V_BATrising

2.65

V

V_{BAT_DPL_FALL}

V_{BAT_DPL_RISE}

V_{BAT_DPL_HYS}

V_BATfalling

V_BATrising

2

2.25

2.5

BAT Depletion Threshold

2.25

2.75

BAT Depletion Rising Hysteresis

260

mV

mA

Bad Adapter Detection Current

(Internal Current Sink)

I_{BAD_SRC}

V_VBUS= 5V, sink current from VBUS to GND

V_VBUSfalling

30

3.8

220

Bad Adapter Detection (VBUS

Voltage Drop) Falling Threshold

V_{VBUSMIN_FALL}

V_{VBUSMIN_HYS}

3.7

3.9

V

Bad Adapter Detection (VBUS

Voltage Drop) Hysteresis

mV

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

6

High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Power Path Management

V_BAT

50mV

+

System Regulation Voltage

V_SYS

V_BAT= 4.4V, V_BAT> V_{SYS_MIN}, BATFET_DIS = 1

V

Minimum DC System Voltage

Output

V_BAT< SYS_MIN[2:0] = 101 (3.5V),

BATFET_DIS = 1

V_{SYS_MIN}

V_{SYS_MAX}

3.6

3.7

Maximum DC System Voltage

Output

V_BAT≤ 4.4V, V_BAT> V_{SYS_MIN}= 3.5V,

BATFET_DIS = 1

4.38

4.45

4.52

Top Reverse Blocking MOSFET

On-Resistance between VBUS

and PMID - Q1

Top Switching MOSFET

On-Resistance between PMID

and SW - Q2

R_{ON_RBFET}

16

22

mΩ

R_{ON_HSFET}

Bottom Switching MOSFET

On-Resistance between SW and

GND - Q3

BATFET Forward Voltage in

Supplement Mode

R_{ON_LSFET}

V_FWD

23

25

mΩ

mV

Battery Charger

Charge Voltage Program Range

Charge Voltage Step

V_{BAT_REG_RANGE}

V_{BAT_REG_STEP}

3.856

4.624

V

Combined with VREG_FT bits

8

mV

4.192

4.184

4.336

4.326

4.386

4.374

-0.4

4.208

4.224

4.232

4.368

4.378

4.414

4.426

0.4

T_J= +25℃

VREG[4:0] = 01011

(4.208V)

T_J= -40℃ to +85℃

T_J= +25℃

4.352

4.4

VREG[4:0] = 01111

(4.352V)

Charge Voltage Setting

V_{BAT_REG}

V

T_J= -40℃ to +85℃

T_J= +25℃

VREG[4:0] = 10001

(4.400V)

T_J= -40℃ to +85℃

T_J= +25℃

V_{BAT_REG}= 4.208V or

V_{BAT_REG}= 4.352V or

V_{BAT_REG}= 4.400V

Charge Voltage Setting Accuracy

V_{BAT_REG_ACC}

%

-0.6

0.6

T_J= -40℃ to +85℃

Charge Current Regulation

Range

I_{CHG_REG_RANGE}

I_{CHG_REG_STEP}

0

1.26

A

Charge Current Regulation Step

20

mA

I_CHG= 20mA

I_CHG= 60mA

I_CHG= 240mA

I_CHG= 720mA

I_CHG= 1.26A

I_CHG= 20mA

I_CHG= 60mA

I_CHG= 240mA

I_CHG= 720mA

I_CHG= 1.26A

0.02

0.063

0.24

0.72

1.26

0.015

0.055

0.235

0.71

1.23

0.05

0.215

0.68

0.076

0.265

0.76

V_BAT= 3.1V,

T_J= +25℃

1.16

1.36

Charge Current Regulation

Setting

I_{CHG_REG}

A

0.035

0.205

0.655

1.105

0.075

0.265

0.76

V_BAT= 3.8V,

T_J= +25℃

1.335

Pre-Charge Current Regulation

Range

I_{PRECHG_RANGE}

With 20mA/step

20

45

260

75

mA

IPRECHG[3:0] = 0010

(60mA)

60

22

Pre-Charge Current Regulation

Setting

I_PRECHG

T_J= +25℃

IPRECHG[3:0] = 0000

(20mA)

11

33

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

7

High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Battery Charger

Battery LOW Falling Threshold

Battery LOW Rising Threshold

V_{BATLOW_FALL}I_CHG= 480mA

2.82

3.07

2.95

3.15

3.08

3.23

V

V_{BATLOW_RISE}Change from pre-charge to fast charging

I_{TERM_RANGE}With 20mA/step

Termination Charge Current

Regulation Range

20

320

mA

ITERM[3:0] = 0010 (60mA)

ITERM[3:0] = 0000 (20mA)

47

11

58

18

69

25

V

_{BAT_REG}= 4.208V,

Termination Current Regulation

Setting

I_TERM

T_J= +25℃

V_SHORT

V_SHORTZ

I_SHORT

1.94

2.15

2

2.06

2.25

V_BATfalling, T_J= +25℃

V_BATrising, T_J= +25℃

V_BAT< V_SHORTZ

Battery Short Voltage

Battery Short Current

V

2.2

30

mA

mV

VRECHG = 0 (100mV)

VRECHG = 1 (200mV)

90

115

225

20

140

250

Recharge Threshold below

V_{BAT_REG}

V_RECHG

V_BATfalling

V_SYS= 4.2V

200

System Discharge Load Current

I_{SYS_LOAD}

mA

BATFET MOSFET

On-Resistance

V_BAT= 4.2V, measured from BAT pin to SYS pin,

T_J= +25℃

R_{ON_BATFET}

10

18

mΩ

Input Voltage and Current Regulation (DPM: Dynamic Power Management)

VINDPM_OS = 00 (4.4V)

4.32

6.3

4.4

6.4

8

4.48

6.5

VINDPM_OS = 01 (6.4V)

VINDPM_OS = 10 (8V)

VINDPM_OS = 11 (11V)

Input Voltage Regulation Limit

V_INDPM

V

VINDPM[3:0] = 0101

7.86

10.79

8.14

11.21

11

Input Voltage Regulation

Accuracy

V_{INDPM_ACC}

V_{DPM_VBAT}

I_INDPM

-2

2

%

V

T_J= +25℃

Input Voltage Regulation Limit

Tracking VBAT

V_BAT= 4V, V_INDPM= 3.9V, T_J= +25℃,

VDPM_BAT_TRACK[1:0] = 11 (300mV)

4.11

0.1

4.35

4.49

3.2

Input Current Regulation Limit

Range

With 100mA/step

A

IINDPM[4:0] = 00100 (500mA)

IINDPM[4:0] = 01000 (900mA)

IINDPM[4:0] = 01110 (1.5A)

400

755

630

1015

1535

V

_VBUS= 5V,

Input Current Regulation Limit

I_INDPM

mA

current pulled from SW,

T_J= +25℃

1245

Input Current Limit during

System Start-Up Sequence

I_{IN_START}

250

BAT Pin Over-Voltage Protection

V_{BATOVP_RISE}

V_BATrising

V_BATfalling

102.8

100.8

103.8

101.8

104.8

102.8

As percentage of

Battery Over-Voltage Threshold

%

V

_{BAT_REG}, T_J= +25℃

V_{BATOVP_FALL}

Thermal Regulation and Thermal Shutdown

120

80

TREG = 1 (120℃)

TREG = 0 (80℃)

Junction Temperature

Regulation Threshold

T_{JUNCTION_REG}Temperature increasing

℃

Thermal Shutdown Rising

Temperature

T_SHUT

Temperature increasing

150

30

℃

Thermal Shutdown Hysteresis

T_{SHUT_HYS}

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

JEITA Thermistor Comparator (Buck Mode)

Charge suspends if temperature T is below T1

(T < T1), as percentage of V_REGN

72.8

71.2

67.6

73.2

71.6

68

73.6

72

T1 (0℃) Threshold Voltage on TS Pin

V_T1

%

V_T1Falling

As percentage of V_REGN

Charge sets to I_CHG/2 and the lower of 4.1V and

68.4

T2 (10℃) Threshold Voltage on TS Pin

V

_REGif T1 < T < T2, as percentage of V_REGN

V_T2

V_T2Falling

V_T3Rising

As percentage of V_REGN

66.2

45.5

66.6

45.9

67

46.3

V_T3

%

Charge sets to the lower of 4.1V and V_REG

if T3 < T < T4, as percentage of V_REGN

44.1

35.1

44.5

44.9

T3 (45℃) Threshold Voltage on TS Pin

V_T4Rising

As percentage of V_REGN

35.5

34.2

35.9

34.6

V_T4

Charge suspends if T > T4, as percentage of V_REGN33.8

T4 (60℃) Threshold Voltage on TS Pin

Cold or Hot Thermistor Comparator (Boost Mode)

Cold Temperature Threshold

(TS Pin Voltage Rising Threshold)

79.5

78.5

34

80

79

80.5

79.5

35

As percentage of V_REGN(approx. -20℃ w/ 103AT)

As percentage of V_REGN

V_BCOLD

%

TS Voltage Falling (Exit Cold Range)

Hot Temperature Threshold

(TS Pin Voltage Falling Threshold)

34.5

31.2

As percentage of V_REGN(approx. 60℃ w/ 103AT)

As percentage of V_REGN

V_BHOT

TS Voltage Rising (Exit Hot Range)

30.7

31.7

Charge Over-Current Comparator (Cycle-by-Cycle)

HSFET Cycle-by-Cycle Over-Current

Threshold

I_{HSFET_OCP}

6.4

5.3

9.3

A

T_J= +25℃

System Overload Threshold

I_{BATFET_OCP}

Charge Under-Current Comparator (Cycle-by-Cycle)

LSFET Under-Current Falling

I_{LSFET_UCP}

Change rectifier from synchronous mode to

non-synchronous mode

180

mA

Threshold

PWM

Buck mode

Oscillator frequency, T_J= +25℃

Boost mode

1380

1500

99

1620

PWM Switching Frequency

f_SW

kHz

%

Maximum PWM Duty Cycle ⁽¹⁾

Boost Mode Operation

D_MAX

Boost Mode Regulation Voltage

V_{BST_REG}

V_BAT= 3.8V, I_PMID= 0A, BOOSTV[1:0] = 01 (5V)

V_BATfalling, MIN_BAT_SEL = 0

V_BATrising, MIN_BAT_SEL = 0

V_BATfalling, MIN_BAT_SEL = 1

V_BATrising, MIN_BAT_SEL = 1

Rising threshold

4.88

2.92

3.08

2.52

2.68

5.85

5

3

5.12

3.08

3.32

2.68

2.92

6.15

V

3.2

2.6

2.8

6

Exit Boost Mode Due to Low Battery

Voltage

V_{BATLOW_BST}

Boost Over-Voltage Threshold

V_{BST_OVP}

V

HSFET Under-Current Falling

Threshold

Change rectifier from synchronous mode to

non-synchronous mode

I_{BST_HSZCP}

320

mA

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

REGN LDO

V_VBUS= 9V, I_REGN= 40mA

V_VBUS= 5V, I_REGN= 20mA

4.3

4.7

5.1

5

REGN LDO Output Voltage

V_REGN

V

4.75

4.85

Logic I/O Pin Characteristics (nCE, PSEL, DCEN, SCL, SDA and nINT)

Input Low Threshold

Input High Threshold

Input Low Threshold

Input High Threshold

V_IL

V_IH

V_IL

0.4

1

V

nCE

1.3

V

PSEL, SCL,

SDA, nINT

V_IH

I_BIAS

V

High-Level Leakage Current

Pull up rail 1.8V

0.1

µA

Logic I/O Pin Characteristics (PMID_GD, STAT) – Open-Drain

Low-Level Output Voltage

V_OL

0.2

V

NOTE:

1. Guaranteed by design. Not production tested.

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

TIMING REQUIREMENTS

(T_J= +25℃, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP MAX UNITS

V_VBUS/V_BATPower-Up

VBUS OVP Reaction Time

t_ACOV

V_VBUSrising above ACOV threshold to turn off Q2

0.1

30

µs

Wait Window for Bad Adapter Detection

Battery Charger

t_BADSRC

ms

Deglitch Time for Charge Termination

Deglitch Time for Recharge

t_{TERM_DGL}

30

ms

t_{RECHG_DGL}

System Over-Current Deglitch Time to Turn

off Q4

t_{SYSOVLD_DGL}

t_BATOVP

112

1

µs

Battery Over-Voltage Deglitch Time to

Disable Charge

CHG_TIMER = 0

18

10

30

20

11.5

35

24

13

40

Typical Charge Safety Timer Range

t_SAFETY

h

CHG_TIMER = 1

Typical Top-off Timer Range

t_{TOP_OFF}

TOPOFF_TIMER[1:0] = 10 (30min)

min

nQON Timing and Ship Mode Timing

nQON Negative Pulse Low Pulse Width to

Turn on BATFET and Exit Ship Mode

t_SHIPMODE

0.8

1

1.2

s

nQON Low Time to Reset BATFET

BATFET off Time during Full System Reset

Wait Delay for Entering Ship Mode

Digital Clock and Watchdog Timer

Watchdog Reset Time

t_{QON_RST}

t_{BATFET_RST}

t_{SM_DLY}

8

10

12

s

ms

s

285

11.5

320

12.5

355

13.5

t_WDT

f_LPDIG

f_DIG

WATCHDOG[1:0] = 01, REGN LDO disabled

REGN LDO disabled

40.9

31

s

Digital Clock Frequency in Low Power

Digital Clock Frequency

kHz

REGN LDO enabled

500

I²C Interface

SCL Clock Frequency

f_SCL

400

kHz

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

TYPICAL PERFORMANCE CHARACTERISTICS

Charge Efficiency vs. Charge Current

System Efficiency vs. System Load Current

98

93

88

83

78

73

68

63

58

97

92

87

82

77

72

67

62

57

V_VBUS= 5V

V_VBUS= 9V

V_VBUS= 12V

V_VBUS= 5V

V_VBUS= 9V

V_VBUS= 12V

V_BAT= 3.8V

I_SYS= 0A

DCR = 5.5mΩ

V_{SYS_MIN}= 3.5V

PFM Enable

Charge Disable

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

Charge Current (A)

System Load Current (A)

Boost Mode Efficiency vs. Output Current

Charge Current Accuracy vs. Charge Current I²C Setting

6

96

91

86

81

76

71

66

61

56

4

V_BAT= 3.1V

V_BAT= 3.8V

V_BAT= 3.2V

2

0

-2

-4

-6

-8

V_VBUS= 5V

PFM Enable

-10

0.02

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

0.28

0.54

0.80

1.06

1.32

Charge Current (A)

Output Current (A)

Constant Charge Voltage vs. Temperature

Input Current Limit vs. Temperature

V_VBUS= 5V

4.25

1400

1200

1000

800

600

400

200

0

V_VBUS= 5V

V_VBUS= 12V

4.23

4.21

4.19

4.17

4.15

I_INDPM= 500mA, V_BAT= 3.8V

I_CHG= 1.26A, Charge Enable

V_REG= 4.208V

-40 -20

0

20

40

60

80 100 120

-40 -20

0

20

40

60

80 100 120

Temperature (℃)

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

System Voltage vs. System Load Current

3.80

3.75

3.70

3.65

3.60

4.35

4.30

4.25

4.20

4.15

V_VBUS= 5V, V_{SYS_MIN}= 3.5V

I_INDPM= 3.2A, V_BAT= 4.2V

PFM Disable

V_VBUS= 5V, V_{SYS_MIN}= 3.5V

I_INDPM= 3.2A, V_BAT= 2.9V

PFM Disable

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

System Load Current (A)

System load current (A)

PWM Switching Waveform

PFM Switching Waveform

AC Coupled

V_SYS

SW

I_L

SW

I_L

V_VBUS= 5V, I_SYS= 5mA, Charge Disable, No Battery

V_VBUS= 12V, V_BAT= 3.8V, I_CHG= 1.26A

Time (500ns/div)

Time (20μs/div)

Boost Mode Switching Waveform

Boost Mode Load Transient

AC Coupled

V_PMID

I_PMID

I_BAT

SW

I_L

V_BAT= 3.8V, V_PMID= 5V, I_PMID= 1A

V_BAT= 3.8V, I_PMID= 0A-1A-0A

Time (500ns/div)

Time (5ms/div)

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Power-Up with Charge Disabled

Power-Up with Charge Enabled

V_VBUS

REGN

V_SYS

V_VBUS

REGN

V_SYS

SW

V_VBUS= 5V, V_BAT= 3.2V

Time (50ms/div)

Charge Enable

Time (50ms/div)

Charge Disable

STAT

nCE

STAT

nCE

SW

I_BAT

V_VBUS= 5V, V_BAT= 3.2V, Charge Enable

V_VBUS= 5V, V_BAT= 3.2V, Charge Disable

Time (500μs/div)

Input Current DPM Response without Battery

Load Transient during Supplement Mode

AC Coupled

V_SYS

V_SYS+ 3V Offset

V_SYS

V_BAT+ 3.5V Offset

I_IN

V_BAT

I_BAT

I_SYS

V_VBUS= 5V, I_INDPM= 1.5A, V_BAT= 3.8V, I_CHG= 1.26A,

V_VBUS= 5V, I_INDPM= 2.4A, I_SYS= 0A-2A-0A, Charge Disable

I_SYS= 0A-3A-0A

Time (2ms/div)

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

TYPICAL APPLICATION CIRCUIT

22µF

Input

3.9V to 13.5V

VAC

PMID

Earphone

REGN

VBUS

20kΩ

15kΩ

100kΩ

1µF

PMID_GD

SW

Optional

1µH

VSYS

PHY

PSEL

10µF × 2

47nF

BTST

REGN

SYS

4.7µF

SGM41518

GND

2.2kΩ

V_REF

SYS

BAT

I_CHG= 1.26A

STAT

10µF

10kΩ

Host

BATSNS

SDA

SCL

nINT

REGN

5.23kΩ

nCE

nQON

TS

Optional

30.9kΩ

10kΩ

Figure 1. Typical Application Circuit

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

FUNCTIONAL BLOCK DIAGRAM

VBUS

PMID

RBFET (Q1)

VAC

REGN

LDO

REGN

BTST

Q1

Control

Protections:

Voltage & Current

Sensing

OVP

UVP

OCP

UCP

OTP

&

DAC Reference

HSFET (Q2)

SW

Converter

Control

Input

REGN

Source

PSEL

Detection

LSFET (Q3)

GND

SYS

Digital

Control

I_CHG

PMID_GD

nINT

Q4 Gate

Control

BATFET (Q4)

BAT

BATSNS

V_PULL-UP

STAT

nQON

nCE

SDA

SCL

Battery

Temperature

Sensing

I²C

Interface

JEITA

Control

TS

SGM41518

Figure 2. Block Diagram

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

DETAILED DESCRIPTION

The SGM41518 is a power management and charger device

for applications such as wearables and earphones with

single-cell Li-Ion or Li-polymer batteries. The SGM41518 can

accommodate a wide range of input sources including USB,

wall adapter and car chargers. It is optimized for 5V input

(USB voltage) but is capable to operate with input voltages

from 3.9V to 13.5V. It also supports JEITA profile for battery

charging safety at high or low temperatures. Automatic power

path selection to power the system (SYS) from the input

source (VBUS), battery (BAT), or both, is another feature of

the device. Battery charge current is programmable and can

reach to a maximum of 1.26A (charge).

Power-Up from Battery Only (No Input

Source)

When only the battery is presented as a source and its

voltage is above depletion threshold (V_{BAT_DPL_RISE}), the

BATFET turns on and connects the battery to the system.

The quiescent current is minimum because the REGN LDO

remains off. Conduction losses are also low due to small

R_DSONof BATFET. Low losses help to extend the battery run

time.

The discharge current through BATFET is continuously

monitored. In the supplement mode, if a system overload (or

short) occurs (I_BAT> I_{BATFET_OCP}), the BATFET is turned off

immediately and BATFET_DIS bit is set to 1. The BATFET

will not enable until the input source is applied or one of the

BATFET Enable Mode (Exit Ship Mode) methods (explained

later) is used to activate the BATFET.

The device may operate in several different modes:

In HIZ mode, the reverse blocking FET (Q1), internal REGN

LDO, converter switches and some other parts of the internal

circuit remain off to save the battery while it is supplying DC

power to the system through BATFET.

Power-Up Process from the Input Source

Upon connection of an input source (VBUS), its voltage

sensed from VAC pin is checked to turn on the internal REGN

LDO regulator and the bias circuits (no matter whether the

battery is present or not). The input current limit is determined

and set before the Buck converter is started. The sequences

of actions when VBUS as input source is powered up are:

In the sleep mode, the switching is stopped. The charger

goes to the sleep mode when the input source voltage (V_VAC

)

is not high enough for charging the battery. In other words,

V_VACis smaller than V_BAT+ V_SLEEP(where V_SLEEPis a small

threshold) and Buck converter is not able to charge, even at

its maximum duty cycle. The Boost may also go to the sleep

mode if similar issue happens in the reverse direction (when

1. REGN LDO power-up.

V

_VACis almost equal or smaller than V_BAT).

2. Poor power source detection (qualification).

3. Input power source type detection. (Based on PSEL input.

It is used to set the default input current limit (IINDPM[4:0]).)

4. Setting of the input voltage limit threshold (VINDPM

threshold).

In supplement mode, the input source power is not enough to

supply system demanded power and the battery assists by

discharging to the system in parallel, and providing the deficit.

Power-On Reset (POR)

5. DC/DC converter power-up.

The internal circuit of the device is powered from the greater

voltage between V_VBUSand V_BAT. When the voltage of the

Details of the power-up steps are explained in the following

sections.

selected source goes above its UVLO level (V_VBUS

>

V_{VAC_UVLOZ}or V_BAT> V_{BAT_UVLOZ}), a POR happens and

activates the sleep comparator, battery depletion comparator

and BATFET driver. Upon activation, the I²C interface will

also be ready for communication and all registers reset to

their default values.

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

DETAILED DESCRIPTION (continued)

REGN LDO Power-Up

The REGN low dropout regulator powers the internal bias

circuits, HSFET and LSFET gate drivers and TS rail

(thermistor pin). The STAT pin can also be pulled up to REGN.

The REGN enables when the following 2 conditions are

satisfied and remain valid for a 220ms delay time, otherwise

the device stays in high impedance mode (HIZ) with REGN

LDO off.

Input Current Limit by PSEL

PSEL pin interfaces with USB physical layer (PHY) for input

current limit setting. The USB PHY device output is used to

detect if the input is a USB host or a charging port. In the

host-control mode, the host must enable IINDET_EN bit for

reading the PSEL value and updating the IINDPM[4:0]. In the

default mode, IINDPM[4:0] is updated automatically by PSEL

value in real-time as given in Table 1.

1. V_VAC> V_{VAC_PRESENT}

.

Table 1. Input Current Limit Setting from PSEL

Input Current

2. V_VAC> V_BAT+ V_SLEEPZ(in Buck mode) or V_VBUS< V_BAT

V_SLEEP(in Boost mode).

+

Input Detection PSEL Pin

VBUS_STAT[2:0]

Limit (I_LIM

)

In HIZ state, the quiescent current drawn from VBUS is very

small (less than I_{VBUS_HIZ}). System is only powered by the

battery in HIZ mode.

USB Host SDP

Adapter

High

Low

500mA

001

011

2400mA

Setting of the Input Voltage Limit Threshold

(VINDPM Threshold)

A wide voltage range (3.9V to 5.4V, 5.9V to 9V, 10.5V to 12V)

is supported for the input voltage limit setting in VINDPM[3:0]

and VINDPM_OS[1:0]. 4.5V is the default for USB.

Poor Power Source Detection (Qualification)

When REGN LDO is powered, the input source (adaptor) is

checked for its type and current capacity. To start the Buck

converter, the input (VBUS) must meet the following

conditions:

The device supports dynamic tracking of the battery voltage

(VINDPM). VDPM_BAT_TRACK[1:0] bits can be used to

enable tracking (00 to disable tracking) and set the tracking

offset value. When the tracking is enabled, the input voltage

limit will be set to the larger value between the VINDPM[3:0] and

V_BAT+ VDPM_BAT_TRACK[1:0]. The VDPM_BAT_TRACK[1:0]

tracking offset can be set to 200mV, 250mV or 300mV. And

this function only takes effect when VINDPM_OS[1:0] = 00.

1. V_VBUS< V_{VAC_OV}

.

2. V_VBUS> V_{VBUS_MIN}during t_BADSRCtest period (30ms TYP) in

which the I_{BAD_SRC}(30mA TYP) current is pulled from VBUS.

If the test is failed, the conditions are repeatedly checked

every 2 seconds. As soon as the input source passes

qualification, the VBUS_GD bit in status register is set to 1

and a pulse is sent to the nINT pin to inform the host. Type

detection will start as next step.

DC/DC Converter Power-Up

The 1.5MHz switching converter composed of LSFET and

HSFET is enabled, which can start switching when the input

current limit is set. Converter is initiated with a soft-start when

the system voltage is ramped up. If SYS voltage is less than

2.2V, the input current is limited to 250mA or IINDPM[4:0],

whichever is smaller, otherwise the limit is set to IINDPM[4:0].

Input Power Source Type Detection

The input source detection will run through the PSEL pin

while REGN LDO is powered and after the VBUS_GD bit is

set. The input current limit of the SGM41518 is set based on

the state of PSEL pin. When the input source type detection is

completed, the PMID_GD pin is asserted to high and the

PG_STAT bit is set to 1. A pulse is sent to nINT pin to inform

the host when the input source type detection is completed.

Some registers and pins are also updated as detailed below:

The BATFET remains on to charge the battery if the battery

charging function is enabled, otherwise BATFET turns off.

When converter operates for battery charging, it acts as an

efficient, fixed frequency synchronous Buck converter

regardless of the input/output voltages and currents. However,

it is capable to switch to PFM mode at light load when

charging is disabled or when the detected battery voltage is

less than minimum system voltage setting. PFM operation

can be enabled or prevented in either Buck or Boost mode

using the PFM_DIS bit.

1. Input current limit register (the value in the IINDPM[4:0]) is

changed to set current limit.

2. PG_STAT (power good) bit is set.

3. VBUS_STAT[2:0] register is updated to indicate USB or

adaptor input source types.

The input current is always limited by the IINDPM[4:0] register

and the limit can be updated by the host if needed.

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

DETAILED DESCRIPTION (continued)

Boost Mode

Host Mode and Default Mode Operation

with Watchdog Timer

The SGM41518 supports Boost mode. When a load device is

connected to the USB port, the converter can operate as a

step-up synchronous converter (Boost mode) with 1.5MHz

switching frequency to supply power from the battery to that

load. Converter will be set to Boost mode if at least 30ms is

passed from enabling this mode (BST_CONFIG bit = 1) and

the following conditions are satisfied:

After a power-on reset, the device starts in default mode

(standalone) with all registers reset as if the watchdog timer is

expired. When the host is in sleep mode or there is no host,

the device stays in the default mode in which the SGM41518

operates like an autonomous charger. The battery is charged

for 11.5 hours (default value for the fast charging safety timer).

Then the charge stops while Buck converter continues to

operate to power the system load. In this mode,

WATCHDOG_FAULT bit is high.

1. V_BAT> V_{BATLOW_BST}

.

2. V_VBUS< V_BAT+ V_SLEEP(in sleep mode).

3. Acceptable voltage range at TS pin (V_BHOT< V_TS< V_BCOLD).

Most of the flexibility features of the SGM41518 become

available in the host mode when the device is controlled by a

host with I²C. By setting the WD_RST bit to 1, the charger

mode changes from default mode to host mode. In this mode,

the WATCHDOG_FAULT bit is low and all device parameters

can be programmed by the host. To prevent the device

watchdog from reset that results in going back to default

mode, the host must disable the watchdog timer by setting

WATCHDOG[1:0] = 00, or it must consistently reset the

watchdog timer before expiry by writing 1 to WD_RST to prevent

WATCHDOG_FAULT bit from being set. Every time a 1 is written

to the WD_RST, the watchdog timer will restart counting.

Therefore, it should be reset again before overflow (expiry) to

keep the device in the host mode. If the watchdog timer expires

(WATCHDOG_FAULT bit = 1), the device returns to default mode

and all registers are reset to their default values except for

EN_ICHG_MON[1:0], IINDPM[4:0], PFM_DIS, SYS_MIN[2:0],

The output voltage is set to V_PMID= 5V and is maintained as

long as V_BATis above V_{BATLOW_BST}. The VBUS_STAT[2:0]

status register bits are set to 111 in Boost mode.

To minimize the output overshoot in Boost mode, the device

starts with PFM first and then switches to PWM. As stated

before, PFM can be avoided by using PFM_DIS bit in Buck

and Boost modes.

The SGM41518 keeps the Q1 FET off in Boost mode. By

setting both the BST_CONFIG bit and the CHG_CONFIG bit

to 1 during adapter insertion or removal, the charger will

automatically transition between charging mode and Boost

mode. The device is in charge mode when the adapter is

plugged in and the conditions to start a new charge cycle are

valid. If the adapter is removed and the Boost enable

conditions are active, the device automatically transitions to

Boost mode to power accessories connected to the PMID.

MIN_BAT_SEL,

VINDPM[3:0],

Q1_FULLON,

OVP[1:0],

BOOSTV[1:0],

BATFET_DIS,

VDPM_BAT_TRACK[1:0],

BATFET_DLY, VINDPM_INT_MASK, IINDPM_INT_MASK,

REG_RST and VINDPM_OS[1:0] bits that keep their values

unchanged.

POR

Watchdog Timer Expired

Reset Registers

Start

Watchdog Timer

I²C Interface Enabled

Y

I²C Write?

N

Host Mode

Host Programs Registers

Default Mode

Reset Watchdog Timer

Reset Selective Registers

Y

WD_RST Bit = 1?

N

Y

N

I²C Write?

Y

N

Watchdog Timer

Expired?

Figure 3. Watchdog Timer Flow Chart

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

DETAILED DESCRIPTION (continued)

Charge Status Report

STAT is an open-drain output pin that reports the status of

charge and can drive an LED for indication: a low indicates

charging is in progress, a high shows charging is completed

or disabled and alternating low/high (blinking) show a

charging fault. The STAT may be disabled (keep the

open-drain switch off) by setting EN_ICHG_MON[1:0] = 11.

Battery Charging Management

The SGM41518 is designed for charging single-cell Li-Ion or

Li-poly batteries with a charge current up to 1.26A (MAX).

The battery connection switch (BATFET) is in the charge or

discharge current path features low on-resistance (10mΩ

TYP) to allow high efficiency and low voltage drop.

Charging Cycle in Autonomous Mode

Charging is enabled if CHG_CONFIG = 1 and nCE pin is

pulled low. In default mode, the SGM41518 runs a charge

cycle with the default parameters itemized in Table 2. At any

moment, the device can be controlled by changing to the host

mode.

The CHRG_STAT[1:0] status register reports the present

charging phase and status by two bits: 00 = charging disabled,

01 = in pre-charge, 10 = in fast charging (constant current mode

or constant voltage mode) and 11 = charging completed.

A negative pulse is sent on nINT pin to inform the host when a

charging cycle is completed.

Table 2. Charging Parameter Default Setting

In addition, the output status of STAT pin can be set by

STAT_SET[1:0] bits, 00 = LED off (HIZ), 01 = LED on (low),

10 = LED blinking at 1s on 1s off, 11 = LED blinking at 1s on

3s off. This two bits only take effect when

EN_ICHG_MON[1:0] = 01.

Default Mode

SGM41518

4.208V

340mA

40mA

Charging Voltage (V_REG

)

Charging Current (I_{CHG_REG}

)

Pre-Charge Current (I_PRECHG

)

Termination Current (I_TERM

Temperature Profile

Safety Timer

)

60mA

Battery Charging Profile

The SGM41518 features a full battery charging profile with

five phases. In the beginning of the cycle, the battery voltage

JEITA

11.5h

(V_BAT

) is tested and appropriate current and voltage

Start a New Charging Cycle

regulation levels are selected as shown in Table 3.

Depending on the detected status of the battery, the proper

phase is selected to start or for continuation of the charging

cycle. The phases are trickle charge (V_BAT< 2.2V),

pre-charge and fast-charge (constant current and constant

voltage).

If the converter can start switching and all the following

conditions are satisfied, a new charge cycle starts:

• NTC temperature fault is not asserted (TS pin).

• Safety timer fault is not asserted.

• BATFET is not forced off. (BATFET_DIS bit = 0).

• Charging enabled (3 conditions: CHG_CONFIG bit = 1,

ICHG[5:0] register is not 0mA and nCE pin is low).

• Battery voltage is below the programmed full charge level

(V_REG).

Table 3. Charging Current Setting Based on V_BAT

Selected

V_BAT

Voltage

Default Value

in the Register

Charging

Current

CHRG_STAT[1:0]

A new charge cycle starts automatically if battery voltage falls

< 2.2V

2.2V to 3.15V

> 3.15V

I_SHORT

I_PRECHG

I_CHG

30mA

40mA

01

10

below the recharge threshold level (V_REG- 100mV or V_REG

-

200mV configured by VRECHG bit). Also, if the charge cycle

is completed, a new charging cycle can be initiated by

toggling of the nCE pin or CHG_CONFIG bit.

340mA

Note that in the DPM or thermal regulation modes, normal

charging functions are temporarily modified: The charge

current will be less than the value in the register; termination

is disabled, and the charging safety timer is slowed down by

counting at half clock rate.

Normally a charge cycle terminates when the charge voltage

is above the recharge threshold level and the charging

current falls below the termination threshold if the device is

not in thermal regulation or Dynamic Power Management

(DPM) mode.

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

DETAILED DESCRIPTION (continued)

Regulation Voltage

VREG[4:0]

Battery Voltage

Charge Current

ICHG[5:0]

Charge Current

V_BATLOW(3.15V)

V_SHORTZ(2.2V)

IPRECHG[3:0]

ITERM[3:0]

I_SHORT

Trickle Charge Pre-charge

Fast Charge and Voltage Regulation

Top-Off Timer Safety Timer

(Optional) Expiration

Figure 4. Battery Charging Profile

Charge Termination

safety timer is suspended, the top-off timer will also be

suspended or if the safety timer is slowed down, the

termination timer will also be slowed down. The

TOPOFF_ACTIVE bit reports the active/not active status of

A charge cycle is terminated when the battery voltage is

higher than the recharge threshold and the charge current

falls below the programmed termination current. Unless there

is a high power demand for system and it needs to operate in

supplement mode, the BATFET turns off at the end of the

charge cycle. Even after termination, the Buck converter

operates continuously to supply the system.

the

top-off

timer.

The

CHRG_STAT[1:0]

and

TOPOFF_ACTIVE bits can be read to find status of the

termination.

Any of the following events resets the top-off timer:

CHRG_STAT[1:0] is set to 11 and a negative pulse is sent to

nINT pin after termination.

1. Disable to enable transition of nCE (charge enable).

2. A low to high change in the status of termination.

3. Set REG_RST bit to 1.

If the charger is regulating input current, input voltage or

junction temperature instead of charge current, termination

will be temporarily prevented. EN_TERM bit is termination

control bit and can be set to 0 to disable termination before it

happens.

The setting of the top-off timer is applied at the time of

termination detection and unless a new charge cycle is

started, modifying the top-off timer parameters after

termination has no effect. A negative pulse is sent to nINT

when top-off timer is started or ended.

At low termination currents (60mA TYP), the offset in the

internal comparator may give rise to a higher (+5mA to

+10mA) actual termination current. A delay in termination can

be added (optional) as a compensation for comparator offset

using a programmable top-off timer. During the delay,

constant voltage charge phase continues and gives the falling

charge current a chance to drop closer to the programmed

value. The top-off delay timer has the same restrictions of the

safety timer. As an example, if under some conditions the

Temperature Qualification

The charging current and voltage of the battery must be

limited when battery is cold or hot. A thermistor input for

battery temperature monitoring is included in the device that

can protect the battery based on JEITA guidelines.

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

DETAILED DESCRIPTION (continued)

Compliance with JEITA Guideline

JEITA guideline (April 20, 2007 release) is implemented in the

device for safe charging of the Li-Ion battery. JEITA highlights

the considerations and limits that should to be considered for

charging at cold or hot battery temperatures. High charge

current and voltage must be avoided outside normal

operating temperatures (typically 0 ℃ and 60 ℃ ). This

functionality can be disabled if not needed. Four temperature

levels are defined by JEITA from T1 (minimum) to T4

(maximum). Outside this range, charging should be stopped.

The corresponding voltages sensed by NTC are named V_T1to

V_T4. Due to the sensor negative resistance, a higher

temperature results in a lower voltage on TS pin. The battery

cool range is between T1 and T2, and the warm range is

between T3 and T4. Charge must be limited in the cool and

warm ranges.

the JEITA_ISET_H[1:0] bits. At cool temperatures (T1 - T2),

the current setting can be reduced down to 50% or 20% of

fast charging current selectable by the JEITA_ISET_L bit

when JEITA_ISET_L_EN = 1, and the charge voltage is set to

V_REGwhen JEITA_VSET_L = 0, the charge voltage is set to

the lower of V_REGand 4.1V when JEITA_VSET_L = 1.

Additional, the cool threshold T2 and warm threshold T3 can

be changed through JEITA_VT2 [1:0] and JEITA_VT3 [1:0],

and the charge current can be disabled by setting

JEITA_ISET_L_EN = 0.

A 103AT-2 type thermistor is recommended to use with the

SGM41518. Other thermistors may be used and bias network

(see Figure 5) can be calculated based on the following

equations:













1

R_THCOLD×R_THHOT

×

−

(1)

V_T1V_T4

R_T2

=

One of the conditions for starting a charge cycle is having the

TS voltage within V_T1to V_T4window limits. If during the

charge, battery gets too cold or too hot and TS voltage

exceeds the T1 - T4 limits, charging is suspended (zero

charge current) and the controller waits for the battery

temperature to come back within the T1 to T4 window.

















1

R_THHOT

×

−1 −R

×

−1





THCOLD

V_T4

V_T1











1

V_T1



−1



(2)



1

R_T1

=













1

+









R_T2

R_THCOLD

JEITA recommends reducing charge current to 1/2 of fast

charging current or lower at cool temperatures (T1 - T2). For

warmer temperature (within T3 - T4 range), charge voltage is

recommended to be kept below 4.1V.

where V_T1and V_T4are T_COLDand T_HOTthreshold voltage on

TS pin as percentage to V_REGN, R_THCOLDand R_THHOTare

thermistor resistances (R_TH) at desired T1 (Cold) and T4 (Hot)

temperatures. Select T_COLD= 0℃ and T_HOT= 60℃ for Li-Ion

or Li-polymer batteries. For a 103AT-2 type thermistor

R_THCOLD= 27.28kΩ and R_THHOT= 3.02kΩ, the calculation

results are: R_T1= 5.29kΩ and R_T2= 30.72kΩ. The standard

value is 5.23kΩ for R_T1and 30.9kΩ for R_T2.

The SGM41518 exceeds the JEITA requirement by its flexible

charge parameter settings. At warm temperature range (T3 -

T4), the charge voltage is set to the lower of V_REGand 4.1V

when JEITA_VSET_H = 0, the charge voltage is set to V_REG

when JEITA_VSET_H = 1, and the charge current can be

reduced down to 0%, 20% or 50% of fast charging current by

SGM41518

BAT

10µF

REGN

4.7µF

R_T1

TS

Li-Ion

Cell

NTC

R_T2

10kΩ@25℃

Figure 5. Battery Thermistor Connection and Bias Network

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

DETAILED DESCRIPTION (continued)

Boost Mode Temperature Monitoring (Battery

Discharge)

The safety timer is paused if a fault occurs and charging is

suspended. It will resume once the fault condition is removed.

If charging cycle is stopped by a restart or by toggling nCE pin

or CHG_CONFIG bit, the timer resets and restarts a new

timing.

The device is capable to monitor the battery temperature for

safety during the Boost mode. The temperature must remain

within the V_BCOLDto V_BHOTthresholds, otherwise the Boost

mode will be suspended and VBUS_STAT[2:0] bits are set to

000. Moreover, NTC_FAULT[2:0] register is updated to report

Boost mode cold or hot condition. Once the temperature

returns within the window, the Boost mode is resumed and

NTC_FAULT[2:0] register is cleared to 000 (normal).

Narrow Voltage DC (NVDC) Design in SGM41518

The SGM41518 features an NVDC design using the BATFET

that connects the system and battery. By using the linear

region of the BATFET, the charger regulates the system bus

voltage (SYS pin) above the minimum setting using Buck

converter even if the battery voltage is very low. MOSFET

linear mode allows for the large voltage difference between

SYS and BAT pins to appear as V_DSacross the switch while

conducting and charging battery. SYS_MIN[2:0] register sets

the minimum system voltage (default 3.5V). If the system is in

minimum system voltage regulation, VSYS_STAT bit is set.

V_REGN

Boost Disabled

V_BCOLD

(-20℃)

Boost Enabled

The BATFET operates in linear region when the battery

voltage is below the minimum system voltage setting. The

system voltage is regulated to 180mV (TYP) above the

minimum system voltage setting. The battery gradually gets

charged and its voltage rises above the minimum system

voltage and lets BATFET to change from linear mode to fully

turned-on switch such that the voltage difference between the

system and battery is the small V_DSof fully on BATFET.

V_BHOT

(60℃)

Boost Disabled

AGND

Figure 6. TS Pin Thermistor Temperature Window

Settings in Boost Mode

The system voltage is always regulated to 50mV (TYP) above

the battery voltage if:

Safety Timer

Abnormal battery conditions may result in prolonged charge

cycles. An internal safety timer is considered to stop charging

in such conditions. If the safety time is expired,

CHRG_FAULT[1:0] bits are set to 11 and a negative pulse is

sent to nINT pin. By default, the charge time limit is 2 hours if

the battery voltage does not rise above V_BATLOWthreshold.

And it is 11.5 hours if it goes above V_BATLOW. This feature is

optional and can be disabled by clearing EN_TIMER bit. The

11.5 hours limit can also be changed to 20 hours by clearing

CHG_TIMER bit.

1. The charging is terminated.

2. Charging is disabled and the battery voltage is above the

minimum system voltage setting.

4.5

V_VBUS= 5V, V_BAT= 2.7V to 4.3V

V_REG= 4.624V, V_{SYS_MIN}= 3.5V

PFM Disable

4.3

4.1

Charge Disable

3.9

The safety timer counts at half clock rate when charger is

running under input voltage regulation, input current

regulation, JEITA cool or thermal regulation, because in these

conditions, the actual charge current is likely to be less than

the register setting. As an example, if the safety timer is set to

11.5 hours and the charger is regulating the input current

(IINDPM_STAT bit = 1) in the whole charging cycle, the

actual safety time will be 23 hours. Clearing the TMR2X_EN

bit will disable the half clock rate feature.

3.7

Charge Enable

3.5

3.3

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

Battery Voltage (V)

Figure 7. System Voltage vs. Battery Voltage

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

DETAILED DESCRIPTION (continued)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Dynamic Power Management (DPM)

The SGM41518 has a dynamic power management (DPM)

feature. To implement DPM, the device always monitors the

input current and voltage to regulate power demand from the

source and avoid input adapter overloading or to meet the

maximum current limits specified in the USB specs.

Overloading an input source may results in either current

trying to exceed the input current limit (I_INDPM) or the voltage

tending to fall below the input voltage limit (V_INDPM). With DPM,

the device keeps the VSYS regulated to its minimum setting

by reducing the battery charge current adequately such that

the input parameter (voltage or current) does not exceed the

V_VBUS= 5V, V_{SYS_MIN}= 3.5V

I_INDPM= 500mA, V_BAT= 3.2V

Charge Enable

0

10

20

30

V_{BAT_SYS}(mV)

Figure 8. BATFET Gate Regulation V-I Curve

40

50

60

70

80

limit. In other words, charge current is reduced to satisfy I_IN

≤

I_INDPMor V_IN≥ V_INDPMwhichever occurs first. DPM can be

either an I_INtype (IINDPM) or V_INtype (VINDPM) depending

on which limit is reached.

BATFET Control for System Power Reset

and Ship Mode

Changing to the supplement mode may be required if the

charge current is decreased and reached to zero, but the

input is still overloaded. In this case, the charger reduces the

system voltage below the battery voltage to allow operation in

the supplement mode and provide a portion of system power

demand from the battery through the BATFET.

Ship Mode (BATFET Disable)

Ship mode is usually used when the system is stored or in

idle state for a long time or is in shipping. In such conditions, it

is better to completely disconnect battery and make system

voltage zero to minimize the leakage and extend the battery

life. To enter ship mode, the BATFET has to be forced off by

setting BATFET_DIS bit. The BATFET turns off immediately if

BATFET_DLY bit is 0, or turns off after a t_{SM_DLY}delay (12.5

seconds) if BATFET_DLY is set.

The IINDPM_STAT or VINDPM_STAT status bits are set

during an IINDPM or VINDPM respectively.

Battery Supplement Mode

If the system voltage drops below the battery voltage, the

BATFET gradually starts to turn on. The threshold margin is

180mV if V_{SYS_MIN}setting is less than V_BATand 45mV if

Exit Ship Mode (BATFET Enable)

To exit the ship mode and enable the BATFET, one of the

following can be applied:

V_{SYS_MIN}setting is larger than V_BAT.At low discharge currents,

the BATFET gate voltage is regulated (R_DSmodulation) such

that the BATFET V_DSstays at 25mV. At higher currents, the

BATFET will turn fully on (reaching its lowest R_DSON). From

this point, increasing the discharge current will linearly

increase the BATFET V_DS(determined by R_DSON× I_D). Use of

the MOSFET linear mode at lower currents prevents swinging

oscillation of entering and exiting the supplement mode.

With no input power (no operating VBUS):

1. Connect the adapter to the input with a valid voltage to the

VBUS input.

2. Pull nQON pin from logic high to low to enable BATFET, for

example, by shorting nQON to GND. The negative pulse

width should be at least a t_SHIPMODE(1s TYP) for deglitching.

With the chip already powered by VBUS:

BATFET gate regulation V-I characteristics is shown in Figure

8. If the battery voltage falls below its minimum depletion, the

BATFET turns off and exits supplement mode.

3. Clear BATFET_DIS bit using host and I²C.

4. Set REG_RST bit to reset all registers including BATFET_DIS

bit to default (0).

5. Apply a negative pulse to nQON pin (same as 2).

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SGM41518

DETAILED DESCRIPTION (continued)

Full System Reset with BATFET Using nQON

When the input source is not present, the BATFET can act as

a load on/off switch between the system and battery. This

feature can be used to apply a power-on reset to the system.

Host can toggle BATFET_DIS bit to cycle power off/on and

reset the system. A push-button connected to nQON pin or a

negative pulse can also be used to manually force a system

power cycle when BATFET is ON (BATFET_DIS bit = 0). For

this function, a negative logic pulse with a minimum width of

t_{QON_RST}(10s TYP) must be applied to the nQON pin that

results in a temporary BATFET turn off for t_{BATFET_RST}(320ms

TYP) that automatically turns on afterward. This functionality

can be disabled by setting BATFET_RST_EN bit to 0.

1. Enable BATFET: Applying an nQON logic high to low

transition with longer than t_SHIPMODEdeglitch time (negative

pulse) turns on BATFET to exit ship mode (Figure 9 left). HIZ is

also enabled (EN_HIZ = 1) when exiting shipping mode. After

exiting shipping mode, the host can disable HIZ (EN_HIZ = 0).

OTG cannot be enabled (BST_CONFIG = 1) until HIZ is

disabled.

2. Reset BATFET: By applying a logic low for a duration of at

least t_{QON_RST}to nQON pin while VBUS is not powered and

BATFET is allowed to turn on (BATFET_DIS bit = 0), the

BATFET turns off for t_{BATFET_RST}and then it is re-enabled

resulting in a system power-on reset. This function can be

disabled by clearing BATFET_RST_EN bit (Figure 9 right).

In summary, the nQON pin controls BATFET and system

reset in two different ways:

A typical push button circuit for nQON is given in Figure 10.

Press Push Button

nQON

t_{QON_RST}

t_SHIPMODE

t_{BATFET_RST}

BATFET

Status

BATFET off due to I²C

or system overload

BATFET on

BATFET off

Reset BATFET

Turn on BATFET

When BATFET_DIS = 1 or SLEEPZ = 1

When BATFET_DIS = 0 and SLEEPZ = 0

Figure 9. nQON Enable and Reset BATFET Timing

SYS

BATFET (Q4)

Control

BAT

V_PULL-UP

nQON

Figure 10. nQON Manual Operation Circuit

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High Input Voltage, 1.26A Single-Cell Battery Charger

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SGM41518

DETAILED DESCRIPTION (continued)

6. A DPM event (VINDPM or IINDPM) occurred (a

maskable interrupt).

Status Outputs Pins (STAT, nINT and

PMID_GD)

Once a fault happens, the INT pulse is asserted immediately

and the fault bits are updated in REG0x09. Fault status is not

reset in the register until the host reads it. A new fault will not

assert a new INT pulse until the host reads REG0x09 and all

the previous faults are cleared. Therefore, in order to read the

current time faults, the host must read REG0x09 two times

consecutively. The first read returns the history of the fault

register status (from the time of the last read or reset) and the

second one checks the current active faults. As an exception,

the NTC_FAULT bit reports the actual real-time status of TS

pin.

Power Good Indication (PG_STAT Bit)

When a good input source is connected to VBUS and input

type is detected, the PG_STAT status bit goes high. A good

input source is detected if all following conditions on V_VBUS

are satisfied and input type detection is completed:

• V_VBUSis in the operating range: V_{VAC_UVLOZ}< V_VBUS< V_{VAC_OV}

.

• Device is not in sleep mode: V_VBUS> V_BAT+ V_SLEEP

.

• Input source is not poor: V_VBUS> V_VBUSMIN(3.8V TYP) when

I_{BAD_SRC}(30mA TYP) loading is applied. (Poor source

detection.)

• Completed input source type detection.

PMID Voltage Indicator (PMID_GD)

In the SGM41518, accessory devices can be connected to

the charger PMID pin to draw power from the adapter through

Q1 direct path or battery Boost mode. An optional external

P-MOSFET can be placed between the charger PMID pin and

the accessory input to disconnect the power path during

over-current and over-voltage conditions. PMID_GD is used

to drive the external P-MOSFET through an inverter.

PMID_GD output high turns on the inverter, which pulls the

P-MOSFET gate low to turn on the P-MOSFET, while

PMID_GD output low turns off the P-MOSFET.

Charge Status (STAT Pin)

Charging state is indicated with the open-drain STAT pin as

explained in Table 4. This pin is able to drive an LED (see

Figure 1). The functionality of the STAT pin is disabled if the

EN_ICHG_MON[1:0] bits are set to 10 or 11.

Table 4. STAT Pin Function

Charging State

Charging battery (or recharge)

Charging completed

STAT Indicator

Low (LED ON)

High (LED OFF)

Charging is disabled or in sleep mode

With the adapter plugged in, when V_VBUSis above battery but

below V_ACOVand passes poor source detection, PMID_GD

goes from low to high. If the Q1 current exceeds 106% of the

IINDPM threshold or the adapter voltage rises above 6V

(V_{BST_OVP}), PMID_GD will go from high to low.

Charge is suspended due to input over-voltage,

TS fault, timer faults or system over-voltage or

Boost mode is suspended (TS fault)

EN_ICHG_MON[1:0] = 01, controlled by register

only, no matter with charging state

1Hz Blinking

STAT_SET[1:0]

nINT Interrupt Output Pin

When a new update occurs in the charger states, a 256μs

negative pulse is sent through the nINT pin to interrupt the

host. The host may not continuously monitor the charger

device and by receiving the interrupt, it can react and check

the charger situation on time.

If all conditions are valid, the high voltage adapter over

V_{BST_OVP}will continue to charge the battery. The external

P-MOSFET will remain off to protect the accessory from

over-voltage fault.

When the adapter is plug out, PMID_GD goes low before

battery Boost mode initiates.

The following events can generate an interrupt pulse:

In battery Boost mode, the device regulates the PMID voltage

between 4.85V and 5.3V as a regulated power supply for

accessory devices. PMID_GD goes from low to high when the

PMID voltage rises above 3.8V (V_VBUSMIN). Similar to the

adapter's current situation, the PMID valid voltage range is

between V_VBUSMINand V_{BST_OVP}. Once the PMID voltage is

outside this range, PMID_GD will go low to disconnect the

accessory device from the PMID. During Boost mode,

PMID_GD is driven high to low for all conditions exiting Boost

mode such as Boost mode disable in register, ACOV, TS fault,

battery drain (V_{BAT_DPL}), BATFET over-current (I_{BATFET_OCP}),

etc.

1. Faults reflected in REG0x09 register (watchdog, Boost

overload, charge faults and battery over-voltage).

2. Charging completed.

3. PSEL detection identified a connected source (USB or

adapter).

4. Input source voltage entered the "input good" range:

a) V_VBUSexceeded V_BAT(not in sleep mode).

b) V_VBUScame below V_{VAC_OV}

.

c) V_VBUSremained above V_VBUSMIN(3.8V TYP) when

I_{BAD_SRC}(30mA TYP) load current is applied.

5. Input removed or out of the "input good" range.

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SGM41518

DETAILED DESCRIPTION (continued)

maximum IC surface temperature in Buck mode and if T_J

intends to exceed this level, the device reduces the charge

current to keep maximum temperature limited to +120℃

(thermal regulation mode) and sets the THERM_STAT bit to 1.

As expected, the actual charging current is usually lower than

programmed value during thermal regulation. Therefore, the

safety timer runs at half clock rate and charge termination is

disabled during thermal regulation.

SGM41518 Protection Features

Monitoring of Voltage and Current

During the converter operation, the input and system voltages

(VBUS and VSYS) and switch currents are constantly

monitored to assure safe operation of the device in both Buck

and Boost modes, as will be explained below.

Buck Mode Voltage and Current Monitoring

1. Input Over-Voltage (ACOV)

If the junction temperature exceeds T_SHUT(+150℃), thermal

shutdown protection arises in which the converter is turned off,

CHRG_FAULT[1:0] bits are set to 10 in the fault register and

an INT pulse is sent.

Converter switching will stop as soon as VBUS voltage

exceeds V_{VAC_OV}over-voltage limit that is programmable by

OVP[1:0] in REG0x06. It is selectable between 5.5V, 6.5V,

10.5V and 14V (default) for USB or 5V, 9V or 12V adaptors

respectively.

When the device recovers and T_Jfalls below the hysteresis

band of T_{SHUT_HYS}(30℃ under T_SHUT), the converter resumes

automatically.

Each time VBUS exceeds the OVP limit, an INT pulse is

asserted. As long as the over-voltage persists, the

CHRG_FAULT[1:0] bits are set to 01 in REG0x09. Fault will

be cleared to 00 if the voltage comes back below limit (and a

hysteresis threshold) and host reads the fault register.

Charger resumes its normal operation when the voltage

Boost Mode Thermal Protections

Similar to Buck mode, T_Jis monitored in Boost mode for

thermal shutdown protection. If junction temperature exceeds

T

_SHUT(+150℃), the Boost mode will be disabled (BST_CONFIG

bit clears). If T_Jfalls below the hysteresis band of T_{SHUT_HYS}(30℃

under T_SHUT), Boost can recover again by re-enabling

BST_CONFIG bit by host.

comes back below OVP limit.

2. System Over-Voltage (SYSOVP)

During a system load transient, the device clamps the system

voltage to protect the system components from over-voltage.

The SYSOVP over-voltage limit threshold is 350mV + V_BAT, or

350mV + V_{SYS_MIN}when in SYSMIN condition (programmed

minimum system regulation voltage + 350mV). Once a SYSOVP

occurs, switching stops to clamp any overshoot and a 30mA

sink current is applied to SYS to pull the voltage down.

Battery Protections

Battery Over-Voltage Protection (BATOVP)

The over-voltage limit for the battery is 4% above the battery

regulation voltage setting. In case of a BATOVP, charging or

external direct charging stops right away, the BAT_FAULT bit

is set to 1 and an INT pulse is sent.

Boost Mode Voltage and Current Monitoring

1. Output Short Protection for PMID

Battery Over-Discharge Protection

The SGM41518 real-time monitors the battery discharge

current through the BATFET (Q4) to ensure safe operation in

Boost mode. Under an over-current condition where the

Boost input current exceeds I_{BATFET_OCP}, the device is latched

within 100µs. When an over-current condition is detected, the

BOOST_FAULT bit of fault register is set to 1, indicating a

fault in Boost operation, and an INT is asserted to notify the

host.

If battery discharges too much and V_BATfalls below the

depletion level (V_{BAT_DPL_FALL}), the device turns off BATFET to

protect battery. This protection is latched and is not recovered

until an input source is connected to the VBUS pin. In such

condition, the battery will start charging with the small I_SHORT

current (30mA TYP) first as long as V_BAT< V_SHORTZ. When

battery voltage is increased and V_SHORTZ< V_BAT< V_BATLOW

,

the charge current will increase to the pre-charge current

level programmed in the IPRECHG[3:0] register.

2. Output Over-Voltage Protection for PMID

In Boost mode, converter stops switching and PMID_GD is

pulled low if PMID voltage rises above regulation and

exceeds the V_{BST_OVP}over-voltage limit (6V TYP).

Battery Over-Current Protection for System

The BATFET will latch off, if its current limit is exceeded due to

a short or large overload on the system (I_BAT> I_{BATFET_OCP}). To

reset this latch off and enable BATFET, the "Exit Ship Mode"

procedure must be followed.

Thermal Regulation and Shutdown

Buck Mode Thermal Protections

Internal junction temperature (T_J) is always monitored to

avoid overheating. A limit of +120 ℃ is considered for

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DETAILED DESCRIPTION (continued)

I²C Serial Interface and Data Communication

Standard I²C interface is used to program SGM41518

parameters and get status reports. I²C is well known 2 wire

serial communication interface that can connect one (or more)

master device(s) to some slave devices for two-way

communication. The bus lines are named serial data (SDA)

and serial clock (SCL). The device that initiates a data

transfer is a master. A master generates the SCL signal.

Slave devices have unique addresses to identify. A master is

typically a micro controller or a digital signal processor.

SDA

SCL

S

P

START

STOP

Figure 11. I²C Bus in START and STOP Conditions

Data Bit Transmission and Validity

The data bit (high or low) must remain stable on the SDA line

during the HIGH period of the clock. The state of the SDA can

only change when the clock (SCL) is LOW. For each data bit

transmission, one clock pulse is generated by master. Bit

transfer in I²C is shown in Figure 12.

The SGM41518 operates as a slave device that address is

0x3B (3BH). It has sixteen 8-bit registers, numbered from

REG0x00 to REG0x0F. A register read beyond REG0x0F

(0x0F) returns 0xFF.

Physical Layer

The standard I²C interface of SGM41518 supports standard

mode and fast mode communication speeds. The frequency

of standard mode is up to 100kbits/s, while the fast mode is

up to 400kbits/s. Bus lines are pulled high by weak current

source or pull-up resistors and in logic high state with no

clocking when the bus is free. The SDA and SCL pins are

open-drain.

SDA

SCL

Data Line Stable Change of Data

and Data Valid

Allowed

Figure 12. I²C Bus Bit Transfer

I²C Data Communication

Byte Format

START and STOP Conditions

Data is transmitted in 8-bit packets (one byte at a time). The

number of bytes in one transaction is not limited. In each

packet, the 8 bits are sent successively with the Most

Significant Bit (MSB) first. An acknowledge (or not-acknowledge)

bit must come after the 8 data bits. This bit informs the

transmitter whether the receiver is ready to proceed for the

next byte or not. Figure 13 shows the byte transfer process

with I²C interface.

A transaction is started by taking control of the bus by master

if the bus is free. The transaction is terminated by releasing

the bus when the data transfer job is done as shown in Figure

11. All transactions begin by the master who applies a

START condition on the bus lines to take over the bus and

exchange data. At the end, the master terminates the

transaction by applying one (or more) STOP condition.

START condition is when SCL is high and a high to low

transition on the SDA is generated by master. Similarly, a

STOP is defined when SCL is high and SDA goes from low to

high. START and STOP are always generated by a master.

After a START and before a STOP the bus is considered

busy.

1

9

1

9

SCL

SDA

MSB

Acknowledgement

signal from receiver

Acknowledgement

signal from receiver

S/Sr

P/Sr

START

or Repeated

START

ACK

STOP

or Repeated

START

Figure 13. Byte Transfer Process

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DETAILED DESCRIPTION (continued)

Acknowledge (ACK) and Not Acknowledge (NCK)

After transmission of each byte by transmitter, an

acknowledge bit is replied by the receiver as ninth bit. With

the acknowledge bit, the receiver informs the transmitter that

the byte was received, and another byte is expected or can

be sent (ACK) or it is not expected (NCK = not ACK). Clock

(SCL) is always generated by the master, including for the

acknowledge clock pulse. SDA line is released for receiver

control during the acknowledge clock pulse, and the receiver

can pull the SDA line low as ACK (reply a 0 bit) or let it be

high as NCK during the SCL high pulse. After that, the master

can either STOP (P) to end the transaction or send a new

START (S) condition to start a new transfer (called repeated

start). For example, when master wants to read a register in

slave, one start is needed to send the slave address and

register address, and then, without a stop condition, another

start is sent by master to initiate the receiving transaction

from slave. Master then sends the STOP condition and

releases the bus.

(when master is asking for data). Data direction is the same

for all next bytes of the transaction. To reverse it, a new

START or repeated START condition must be sent by master

(STOP will end the transaction). Usually the second byte is a

WRITE sending the register address that is supposed to be

accesses in the next byte(s). The data transfer transaction is

shown in Figure 14.

WRITE: If the master wants to write in the register, the third

byte can be written directly as shown in Figure 15 for a single

write data transfer. After receiving the ACK, master may issue

a STOP condition to end the transaction or send the next

register data, which will be written to the next address in a

slave as multi-write. A STOP is needed after sending the last

data.

READ: If the master wants to read a single register (Figure

16), it sends a new START condition along with device

address with R/W bit = 1. After ACK is received, master reads

the SDA line to receive the content of the register. Master

replies with NCK to inform slave that no more data is needed

(single read) or it can send an ACK to request for sending the

next register content (multi-read). This can continue until a

NCK is sent by master. A STOP must be sent by master in

any case to end the transaction.

Data Direction Bit and Addressing Slaves

The first byte sent by master after the START is always the

target slave address (7 bits) and an eighth data-direction bit

(R/W). R/W bit is 0 for a WRITE transaction and 1 for READ

1

9

1

9

1

9

SCL

SDA

R/W

P

S

I²C Slave Address

Data Byte

ACK

START

STOP

Figure 14. Data Transfer Transaction

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SGM41518

DETAILED DESCRIPTION (continued)

Frame 1

Frame 2

1

9

1

9

SCL

SDA

0

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

Byte#2 Register Address Byte

ACK by

Device

START by

Master

Frame 3

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

ACK by

Device

STOP by

Master

Byte#3 Data Byte 1 to SGM41518 Register

Figure 15. A Single Write Transaction

Frame 1

Frame 2

1

0

9

1

9

SCL

SDA

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

START by

Master

Byte#2 Register Address Byte

ACK by

Device

Frame 3

Frame 4

1

0

9

1

9

SCL

(Continued)

SDA

(Continued)

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

R

START by

Master

Byte#3 I²C Slave Address Byte

Byte#4 Data Byte from Device

NCK by

Master

STOP by

Master

ACK by

Device

Figure 16. A Single Read Transaction

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SGM41518

DETAILED DESCRIPTION (continued)

Data Transactions with Multi-Read or Multi-Write

Multi-read and multi-write are supported by SGM41518 for

REG0x00 through REG0x0F registers, as explained in Figure

17 and Figure 18. In the multi-write, every new data byte sent

by master is written to the next register of the device. A STOP

is sent whenever master is done with writing into device

registers.

In a multi-read transaction, after receiving the first register

data (its address is already written to the slave), the master

replies with an ACK to ask the slave for sending the next

register data. This can continue as much as it is needed by

master. Master sends back an NCK after the last received

byte and issues a STOP condition.

Frame 1

Frame 2

1

0

9

1

9

SCL

SDA

B7

B6

B5

B4

B3

B2

B1

B0

1

0

1

W

Byte#1 I²C Slave Address Byte

Byte#2 Register Address Byte

ACK by

Device

START by

Master

ACK by

Device

Frame 3

Frame 4

1

9

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D3

D2

D1

D0

D4

Byte#3 Data Byte 1 to SGM41518 Register

ACK by

Device

Byte#4 Data Byte 2 to SGM41518 Register

ACK by

Device

Frame N

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

Byte#N Data Byte n to SGM41518 Register

ACK by

Device

STOP by

Master

Figure 17. A Multi-Write Transaction

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High Input Voltage, 1.26A Single-Cell Battery Charger

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DETAILED DESCRIPTION (continued)

Frame 1

Frame 2

1

9

1

9

SCL

SDA

0

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

START by

Master

Byte#2 Register Address Byte

ACK by

Device

Frame 3

Frame 4

1

0

9

1

9

SCL

(Continued)

SDA

(Continued)

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

R

Byte#3 I²C Slave Address Byte

Byte#4 Data Byte 1 from Device

ACK by

Master

START by

Master

ACK by

Device

Frame 5

Frame N

1

9

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D3

D2

D1

D0

D4

Byte#5 Data Byte 2 from Device

ACK by

Master

Byte#N Data Byte n from Device

NCK by

Master

STOP by

Master

Figure 18. A Multi-Read Transaction

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SGM41518

REGISTER MAPS

All registers are 8-bit and individual bits are named from D[0] (LSB) to D[7] (MSB).

I²C Register Address Map

FUNCTION

CHARGE

VREG

STAT

FLAG

MASK

THRESHOLD SETTING

─

ENABLE

0x01[4]

─

0x08[4:3]

0x09[5:4]

─

0x04[7:3]

0x0F[7:6]

0x02[5:0]

0x03[7:4]

0x03[3:0]

0x04[0]

VREG_FT

ICHG

─

0x0F[7:6]

─

IPRECHG

ITERM

─

0x05[7]

─

VRECHG

CHG_TIMER

TOPOFF_TIMER

TMR2X

─

0x09[5:4]

0x05[2]

0x05[3]

0x04[2:1]

0x07[6]

0x0A[3]

─

0x04[2:1]

─

0x06[3:0]

0x0F[1:0]

VINDPM

0x0A[6]

─

0x0A[1]

─

VDPM_BAT_TRACK

IINDPM

─

0x0A[5]

─

0x0A[0]

─

0x07[1:0]

0x00[4:0]

0x02[6]

0x07[1:0]

─

Q1_FULLON

0x08[7:5]

0x0A[7]

VBUS

─

PG

IINDET

0x08[2]

─

0x07[7]

EN_ICHG_MON

STAT

─

0x00[6:5]

0x0F[3:2]

0x01[3:1]

─

0x00[6:5]

─

0x00[6:5]

SYS_MIN

HIZ MODE

WATCHDOG

WD_RST

0x08[0]

─

0x00[7]

─

0x09[7]

0x05[5:4]

─

0x05[5:4]

─

0x01[6]

OTG

0x08[7:5]

─

0x06[5:4]

0x01[0]

0x07[3]

─

0x01[5]

MIN_BAT_SEL

BATFET

─

0x07[5]

BATFET_RST

PFM

─

0x07[2]

─

0x01[7]

JEITA

─

0x0D[0]

JEITA_VT2

JEITA_VT3

JEITA_VSET_L

JEITA_VSET_H

JEITA_ISET_L

JEITA_ISET_H

TS_STAT

TREG

─

0x0C[3:2]

0x0C[1:0]

0x0C[7]

0x07[4]

0x05[0]

0x0C[5:4]

─

0x0C[6]

─

0x09[2:0]

─

0x08[1]

─

0x05[1]

─

TSHUT

─

0x09[5:4]

0x09[3]

0x09[6]

─

BUS OVP

BAT OVP

0x0A[2]

0x06[7:6]

─

BOOST FAULT

REG_RST

─

0x0B[7]

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SGM41518

REGISTER MAPS (continued)

I²C Slave Address of SGM41518: 0x3B

Bit Types:

R:

Read only

R/W:

n:

Read/Write

Parameter code formed by the bits as an unsigned binary number.

REG0x00: Input Current Limit Register [Reset = 0x17]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Enable HIZ Mode

0 = Disable (default)

1 = Enable

In HIZ mode, the VBUS pin is effectively disconnected from internal

circuit. Some leakage current may exist.

REG_RST

or Watchdog

D[7]

EN_HIZ

0

R/W

Enable STAT Pin Function

00 = Enable following charging state (default)

01 = Enable following STAT_SET[1:0] bits

10 = Disable (float pin)

D[6:5] EN_ICHG_MON[1:0]

00

R/W

REG_RST

11 = Disable (float pin)

These bits turn on or off the function of the STAT open-drain output

pin (charge status or customer customized indicator).

IINDPM[4]

1 = 1600mA

Input Current Limit Value (n: 5 bits):

= 100 + 100n (mA)

IINDPM[3]

1 = 800mA

Offset: 100mA

Range: 100mA (00000) - 3.2A (11111)

Default: 2400mA (10111), not typical

IINDPM[2]

1 = 400mA

D[4:0]

IINDPM[4:0]

10111

R/W

REG_RST

IINDPM[1]

1 = 200mA

IINDPM changes after an input source detection.

Host can overwrite IINDPM after input source

detection is completed.

IINDPM[0]

1 = 100mA

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High Input Voltage, 1.26A Single-Cell Battery Charger

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REGISTER MAPS (continued)

REG0x01: Charger Control 1 Register [Reset = 0x1A]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Enable PFM Mode

0 = Enable (default)

1 = Disable

D[7]

PFM_DIS

0

R/W

REG_RST

Enable Pulse Frequency Modulation.

PFM is normally used to save power at light load by reducing

converter switching frequency.

I²C Watchdog Timer Reset

0 = Normal (default)

1 = Reset

REG_RST

or Watchdog

D[6]

WD_RST

0

R/W

Watchdog Timer Reset Control Bit.

Write 1 to this bit to avoid watchdog expiry. WD_RST resets to 0

after watchdog timer reset (expiry).

Enable OTG

0 = OTG disable (default)

1 = OTG enable

This bit has priority over charge enable in the CHG_CONFIG.

REG_RST

or Watchdog

D[5]

D[4]

BST_CONFIG

CHG_CONFIG

0

1

R/W

Enable Battery Charging

0 = Charge disable

1 = Charge enable (default)

Charge is enabled when CHG_CONFIG bit is 1 and nCE pin is

pulled low.

REG_RST

or Watchdog

Minimum System Voltage

000 = 2.6V

001 = 2.8V

010 = 3V

011 = 3.2V

100 = 3.4V

101 = 3.5V (default)

110 = 3.6V

D[3:1]

SYS_MIN[2:0]

101

R/W

REG_RST

111 = 3.7V

Minimum System Voltage Value.

Offset: 2.6V

Range: 2.6V (000) - 3.7V (111)

Default: 3.5V (101)

Minimum Battery Voltage for Boost Mode

0 = 3V V_BATfalling (default)

1 = 2.6V V_BATfalling

D[0]

MIN_BAT_SEL

0

R/W

REG_RST

Default:

V

_BATfalling, V_{BATLOW_BST}= 3V.

_BATrising, V_{BATLOW_BST}= 3.2V.

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

REGISTER MAPS (continued)

REG0x02: Charge Current Limit Register [Reset = 0x91]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

REG_RST

or Watchdog

D[7]

Reserved

1

R/W

Reserved

VBUS FET Switch (Q1)

0 = Use higher R_DSONif I_INDPM< 700mA (for better accuracy) (default)

1 = Use lower R_DSONalways (fully ON for better efficiency)

Used to control the on-resistance of Q1 (VBUS switch) for better

input current measurement accuracy.

D[6]

Q1_FULLON

0

R/W

REG_RST

Note that Q1 is off in Boost mode.

ICHG[5]

1 = 640mA

ICHG[4]

1 = 320mA

Fast Charge Current Value (n: 6 bits):

= 20n (mA) (n ≤ 63)

ICHG[3]

1 = 160mA

Offset: 0mA

Range: 0mA (000000) - 1260mA (111111),

Default: 340mA (010001)

REG_RST

or Watchdog

D[5:0]

ICHG[5:0]

010001

R/W

ICHG[2]

1 = 80mA

ICHG[1]

1 = 40mA

Note: Setting I_CHG= 0mA disables charge.

ICHG[0]

1 = 20mA

REG0x03: Pre-Charge and Termination Current Limit Register [Reset = 0x12]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Pre-Charge Current Limit (n: 4 bits):

= 20 + 20n (mA) (n ≤ 12)

IPRECHG[3]

1 = 160mA

0

R/W

IPRECHG[2]

1 = 80mA

Offset: 20mA

Range: 20mA (0000) - 260mA (1100)

Default: 40mA (0001)

0

1

0

1

0

R/W

REG_RST

or Watchdog

D[7:4]

IPRECHG[3:0]

IPRECHG[1]

1 = 40mA

Note:

IPRECHG[0]

1 = 20mA

Values above 12D = 1100 (260mA) are clamped

to 12D = 1100 (260mA).

ITERM[3]

1 = 160mA

Termination Current Limit (n: 4 bits):

= 20 + 20n (mA)

ITERM[2]

1 = 80mA

REG_RST

or Watchdog

D[3:0]

ITERM[3:0]

Offset: 20mA

Range: 20mA (0000) - 320mA (1111)

Default: 60mA (0010)

ITERM[1]

1 = 40mA

ITERM[0]

1 = 20mA

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

REGISTER MAPS (continued)

REG0x04: Battery Voltage Limit Register [Reset = 0x58]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VREG[4]

1 = 512mV

0

R/W

Charge Voltage Limit (n: 5 bits):

= 3856 + 32n (mV) if n ≤ 24, n ≠ 15;

VREG[3]

1 = 256mV

= 4.352V

Offset: 3.856V

Range: 3.856V (00000) - 4.624V (11000)

Default: 4.208V (01011)

Special Value: 4.352V (01111)

if n = 15

1

0

1

R/W

VREG[2]

1 = 128mV

REG_RST

or Watchdog

D[7:3]

VREG[4:0]

VREG[1]

1 = 64mV

Note:

Values above 24D = 11000 (4.624V) are clamped

to 24D = 11000 (4.624V).

VREG[0]

1 = 32mV

Top-Off Timer

00 = Disabled (default)

01 = 15 minutes

10 = 30 minutes

11 = 45 minutes

REG_RST

or Watchdog

D[2:1] TOPOFF_TIMER[1:0]

00

R/W

The charge extension time added after the termination condition is

detected.

If disabled, charging terminates as soon as termination conditions

are met.

Battery Recharge Threshold

0 = 100mV below VREG[4:0] (default)

1 = 200mV below VREG[4:0]

A recharge cycle will start if a fully charged battery voltage drops below

VREG - VRECHG settings.

REG_RST

or Watchdog

D[0]

VRECHG

0

REG0x05: Charger Control 2 Register [Reset = 0x9F]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Charging Termination Enable

0 = Disable

1 = Enable (default)

REG_RST

or Watchdog

D[7]

EN_TERM

1

R/W

REG_RST

or Watchdog

D[6]

Reserved

0

R/W

Reserved

Watchdog Timer Setting

00 = Disable watchdog timer

01 = 40s (default)

REG_RST

or Watchdog

D[5:4]

WATCHDOG[1:0]

01

10 = 80s

11 = 160s

Expiry time of the watchdog timer if it is not reset.

Charge Safety Timer Enable

0 = Disable

1 = Enable (default)

When enabled the pre-charge and fast charge periods are included

in the timing.

REG_RST

or Watchdog

D[3]

EN_TIMER

1

R/W

Charge Safety Timer Setting

0 = 20h

1 = 11.5h (default)

REG_RST

or Watchdog

D[2]

D[1]

CHG_TIMER

TREG

1

R/W

Thermal Regulation Threshold

0 = 80℃

1 = 120℃ (default)

For Buck mode.

REG_RST

or Watchdog

JEITA Charging Current

0 = 50% of I_CHG

1 = 20% of I_CHG(default)

When JEITA_ISET_L_EN = 1.

JEITA_ISET_L

(0℃ - 10℃)

REG_RST

or Watchdog

D[0]

1

R/W

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

REGISTER MAPS (continued)

REG0x06: Charger Control 3 Register [Reset = 0xD6]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VAC Pin OVP Threshold

00 = 5.5V

01 = 6.5V (5V input)

10 = 10.5V (9V input)

D[7:6]

OVP[1:0]

11

R/W

REG_RST

11 = 14V (12V input) (default)

OVP Threshold for Input Supply.

Boost Mode Voltage Regulation

00 = 4.85V

D[5:4]

BOOSTV[1:0]

01

R/W

01 = 5V (default)

10 = 5.15V

REG_RST

11 = 5.30V

VINDPM Threshold (n: 4 bits):

= Offset + 0.1n (V)

VINDPM[3]

1 = 800mV

Offset: 3.9V (VINDPM_OS = 00, default)

Range: 3.9V (0000) - 5.4V (1111)

Default: 4.5V (0110)

VINDPM[2]

1 = 400mV

D[3:0]

VINDPM[3:0]

0110

R/W

Offset: 5.9V (VINDPM_OS = 01)

Range: 5.9V (0000) - 7.4V (1111)

REG_RST

VINDPM[1]

1 =200mV

Offset: 7.5V (VINDPM_OS = 10)

Range: 7.5V (0000) - 9V (1111)

VINDPM[0]

1 =100mV

Offset: 10.5V (VINDPM_OS = 11)

Range: 10.5V (0000) - 12V (1111)

REG0x07: Charger Control 4 Register [Reset = 0x4C]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Input Current Limit Detection

0 = Not in input current limit detection (default)

1 = Force input current limit detection when VBUS is present

Reloads with 0 when input detection is completed.

REG_RST

or Watchdog

D[7]

IINDET_EN

0

R/W

Enable Half Clock Rate Safety Timer

0 = Disable

1 = Safety timer slow down during DPM, JEITA cool, or thermal

regulation (default)

REG_RST

or Watchdog

D[6]

D[5]

TMR2X_EN

1

0

R/W

Slow down by a factor of 2.

Disable BATFET

0 = Allow BATFET (Q4) to turn on (default)

1 = Turn off BATFET (Q4) after a t_{SM_DLY}delay time (REG0x07 D[3])

BATFET_DIS

REG_RST

t

_{SM_DLY}is typically 12.5 seconds.

JEITA Charging Voltage

0 = Set charge voltage to the lower of 4.1V and V_REG(default)

1 = Set charge voltage to V_REG

JEITA_VSET_H

REG_RST

or Watchdog

D[4]

D[3]

D[2]

0

1

R/W

(45℃ - 60℃)

BATFET Turn Off Delay Control

0 = Turn off BATFET immediately

1 = Turn off BATFET after t_{SM_DLY}(default)

BATFET_DIS bit is set.

BATFET_DLY

REG_RST

Enable BATFET Reset

0 = Disable BATFET reset

1 = Enable BATFET reset (default)

REG_RST

or Watchdog

BATFET_RST_EN

Dynamic VINDPM Tracking

00 = Disable (V_INDPMset by register)

01 = V_BAT+ 200mV

10 = V_BAT+ 250mV

VDPM_BAT_

TRACK[1:0]

D[1:0]

00

R/W

REG_RST

11 = V_BAT+ 300mV

Set V_INDPMto track V_BATvoltage. Actual V_INDPMis the larger of

VINDPM[3:0] and this register value.

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

REGISTER MAPS (continued)

REG0x08: Charger Status 1 Register [Reset = 0xXX]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VBUS Status Register

000 = No input

001 = USB host SDP (500mA) → PSEL HIGH

011 = Adapter 2.4A → PSEL LOW

111 = OTG

D[7:5]

VBUS_STAT[2:0]

xxx

R

N/A

Other values are reserved.

Current limit value is reported in IINDPM[4:0] register.

Charging Status

00 = Charge disable

D[4:3]

CHRG_STAT[1:0]

xx

R

01 = Pre-charge (V_BAT< V_BATLOW

)

N/A

10 = Fast charging (constant current or voltage)

11 = Charging terminated

Input Power Status (VBUS in good voltage range and not poor)

0 = Input power source is not good

1 = Input power source is good

D[2]

D[1]

D[0]

PG_STAT

THERM_STAT

VSYS_STAT

x

R

N/A

Thermal Regulation Status

0 = Not in thermal regulation

1 = In thermal regulation

System Voltage Regulation Status

0 = Not in VSYSMIN regulation (V_BAT> V_{SYS_MIN}

)

1 = In VSYSMIN regulation (V_BAT< V_{SYS_MIN}

)

REG0x09: Fault Register [Reset = 0xXX]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Watchdog Fault Status

0 = Normal (no fault)

1 = Watchdog timer expired

D[7] WATCHDOG_FAULT

x

R

N/A

Boost Mode Fault Status

0 = Normal

1 = PMID overloaded in OTG or battery voltage too low (any

condition that prevents Boost starting)

D[6]

BOOST_FAULT

x

R

Charging Fault Status

00 = Normal

D[5:4] CHRG_FAULT[1:0]

xx

x

R

01 = Input fault (VAC OVP or V_BAT< V_VBUS< 3.8V)

10 = Thermal shutdown

11 = Charge safety timer expired

N/A

Battery Fault Status

0 = Normal

D[3]

BAT_FAULT

1 = Battery over-voltage (BATOVP)

JEITA Condition Based on Battery NTC Temperature Measurement

000 = Normal

010 = Warm (Buck mode only)

011 = Cool (Buck mode only)

101 = Cold

D[2:0]

NTC_FAULT[2:0]

xxx

R

N/A

110 = Hot

NTC fault bits are updated in real-time and does not need a read to

reset.

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

REGISTER MAPS (continued)

REG0x0A: Charger Status2 Register [Reset = 0xXX]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

N/A

Good Input Source Detected

0 = A good VBUS is not attached

1 = A good VBUS attached

D[7]

VBUS_GD

x

R

Input Voltage Regulation (Dynamic Power Management)

0 = Not in VINDPM

D[6]

VINDPM_STAT

x

R

N/A

1 = In VINDPM

Input Current Regulation (Dynamic Power Management)

0 = Not in IINDPM

1 = In IINDPM

D[5]

D[4]

D[3]

IINDPM_STAT

Reserved

x

R

N/A

Reserved

Active Top-Off Timer Counting Status

0 = Top-off timer not counting

1 = Top-off timer counting

TOPOFF_ACTIVE

Input Over-Voltage Status (AC adaptor is the input source)

0 = No over-voltage (no ACOV)

1 = Over-voltage detected (ACOV)

D[2]

ACOV_STAT

x

0

R

N/A

VINDPM Event Detection Interrupt Mask

0 = Allow VINDPM INT pulse

1 = Mask VINDPM INT pulse

D[1] VINDPM_INT_MASK

R/W

REG_RST

IINDPM Event Detection Mask

0 = Allow IINDPM to send INT pulse

1 = Mask IINDPM INT pulse

D[0]

IINDPM_INT_MASK

REG0x0B: Part Information Register [Reset = 0x6X]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Register Reset

0 = No effect (keep current register settings) (default)

1 = Reset R/W bits of all registers to the default and reset safety

timer (it also resets itself to 0 after register reset is completed.)

D[7]

REG_RST

0

R/W

REG_RST

1

Part ID

1100 = SGM41518

D[6:3]

PN[3:0]

R

N/A

0

x

D[2]

SGMPART

1

R

N/A

D[1:0]

DEV_REV[1:0]

xx

Revision

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

REGISTER MAPS (continued)

REG0x0C: Charger Control 5 Register [Reset = 0x75]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

JEITA Charging Voltage

0 = Set charge voltage to V_REG(default)

1 = Set charge voltage to the lower of 4.1V and V_REG

JEITA_VSET_L

(0℃ - 10℃)

REG_RST

or Watchdog

D[7]

0

R/W

Charge Enable during Cool Temperature

0 = Disable

1 = Enable (default)

JEITA_ISET_L_EN

REG_RST

or Watchdog

D[6]

1

R/W

(0℃ - 10℃)

Charge Current Setting during Warm Temperature

00 = 0% of I_CHG

01 = 20% of I_CHG

10 = 50% of I_CHG

11 = 100% of I_CHG(default)

JEITA_ISET_H[1:0]

REG_RST

or Watchdog

D[5:4]

11

(45℃ - 60℃)

In warm condition, the safety timer does not become 2X.

JEITA Cool Threshold Setting

00 = V_T2= 70.75% (5.5℃)

01 = V_T2= 68.25% (10℃) (default)

10 = V_T2= 65.25% (15℃)

REG_RST

or Watchdog

D[3:2]

D[1:0]

JEITA_VT2[1:0]

JEITA_VT3[1:0]

01

R/W

11 = V_T2= 62.25% (20℃)

JEITA Warm Threshold Setting

00 = V_T3= 48.25% (40℃)

01 = V_T3= 44.75% (45℃) (default)

10 = V_T3= 40.75% (50.5℃)

11 = V_T3= 37.75% (54.5℃)

REG_RST

or Watchdog

REG0x0D: Charger Control 6 Register [Reset = 0x01]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

REG_RST

or Watchdog

D[7:1]

0000000

R/W

Reserved

JEITA Enable

0 = Disable

1 = Enable (default)

REG_RST

or Watchdog

D[0]

1

R/W

JEITA_EN

REG0x0E: Reserved [Reset = 0xXX]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

D[7:0]

xxxxxxxx

R

Reserved

N/A

Reserved

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

REGISTER MAPS (continued)

REG0x0F: Charger Control 7 Register [Reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VREG Fine Tuning

00 = Disable (default)

01 = V_REG+ 8mV

10 = V_REG- 8mV

REG_RST

or Watchdog

D[7:6]

00

R/W

VREG_FT

11 = V_REG- 16mV

REG_RST

or Watchdog

D[5:4]

D[3:2]

00

R/W

Reserved

STAT Pin Output Setting

00 = LED off (HIZ) (default)

01 = LED on (Low)

10 = LED blinking 1s on 1s off

11 = LED blinking 1s on 3s off

This bits only takes effect when EN_ICHG_MON[1:0] = 01.

REG_RST

or Watchdog

STAT_SET[1:0]

VINDPM Offset

00 = 3.9V (default)

01 = 5.9V

D[1:0]

00

R/W

REG_RST

VINDPM_OS[1:0]

10 = 7.5V

11 = 10.5V

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

APPLICATION INFORMATION

The SGM41518 is typically used as a charger with power

path management in smart phones, tablets and other portable

devices. In the design, it comes along with a host controller (a

processor with I²C interface) and a single-cell Li-Ion or

Li-polymer battery.

current in the worst case is around the I_CHG/2 when D ≈ 0.5. If

the converter does not operate at D ≈ 50%, the worst case

capacitor RMS current can be estimated from (5) in which D

is the closest operating duty cycle to 0.5.

I_CIN= I_CHG× D× 1−D

(

)

(5)

Detailed Design Procedure

For SGM41518, place C_INacross PMID and GND pins close

to the chip. Voltage rating of the capacitor must be at least 25%

higher than the normal input voltage to minimize voltage

derating. For a 13.5V input voltage, the preferred rating is

25V or higher.

Inductor Design

Small energy storage elements (inductor and capacitor) can

be used due to the high frequency (1.5MHz) switching

converter used in the SGM41518. Inductor should tolerate

currents higher than the maximum charge current (I_CHG) plus

half the inductor peak to peak ripple current (∆I) without

saturation:

A C_IN= 22μF is suggested.

Output Capacitor Design

The output capacitance (on the system) must have enough

RMS (ripple) current rating to carry the inductor switching

ripple and provide enough energy for system transient current

demands. I_COUT(C_OUTRMS current) can be calculated by:

∆I

2

(3)

I_SAT> I_CHG

+

The inductor ripple current is determined by the input voltage

(V_VBUS), duty cycle (D = V_BAT/V_VBUS), switching frequency (f_S=

1.5MHz) and the inductance (L). In CCM:

I_RIPPLE

I_COUT

=

≈ 0.29×I_RIPPLE

V_VBUS×D× 1−D

(

)

2×

3

(4)

(6)

(7)

∆I =

f_S×L

And the output voltage ripple can be calculated by:

Inductor ripple current is maximum when D ≈ 0.5. If the input

voltage range (V_VBUS) is limited higher, D values can be

considered.



₂









V_OUT

∆V_O

=

1−

8LC_OUTf_S

V_VBUS

Increasing L or C_OUT(the LC filter) can reduce the ripple.

In the practical designs, inductor peak to peak current ripple

is selected in a range between 20% to 40% of the maximum

DC current ∆I = (0.2 ~ 0.4) × I_CHGfor a good trade-off between

inductor size and efficiency. Selecting higher ripple allows

choosing of smaller inductance.

The internal loop compensation of the device is optimized for >

22μF ceramic output capacitor. 10V, X7R (or X5R) ceramic

capacitors are recommended for the output.

Input Power Supply Considerations

To power the system from the SGM41518, either an input

power source with a voltage between 3.9V to 13.5V and at

least 100mA current rating should power VBUS, or a

single-cell Li-Ion battery with voltage higher than V_{BAT_UVLOZ}

should be connected to BAT pin of the device. The input

source must have enough current rating to allow maximum

power delivery through charger (Buck converter) to the

system.

For each application, V_VBUSand I_CHGare known, so L can be

calculated from (4) and current rating of the inductor can be

selected from (3). Choose an inductor that has small DCR

and core losses at 1.5MHz to have high efficiency and cool

operation at full load.

Input Capacitor Design

Select low ESR ceramic input capacitor (X7R or X5R) with

sufficient voltage and RMS ripple current rating for decoupling

of the input switching ripple current (I_CIN). The RMS ripple

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High Input Voltage, 1.26A Single-Cell Battery Charger

with NVDC Power Path Management

SGM41518

APPLICATION INFORMATION (continued)

Layout Guidelines

It is better to avoid using vias for these connections and keep

the high frequency current paths short enough and on the

same layer. A GND copper layer under the component layer

helps to reduce noise emissions. Pay attention to the DC

current and AC current paths in the layout and keep them

short and decoupled as much as possible.

The switching node (SW) creates very high frequency noises,

which are several times higher than f_SW(1.5MHz) due to

sharp rise and fall of the voltage and current in the switches.

To reduce the ringing issues and noise generation, it is

important to design a proper layout for minimizing the current

path impedance and loop area. A graphical guideline for the

current loops and their frequency content is provided in

Figure 19. The following considerations can help to make a

better layout.

4. For analog signals, it is better to use a separate analog

ground (AGND) branched only at one point from GND pin. To

avoid high current flow through the AGND path, it should be

connected to GND only at one point (preferably the GND pin).

1. Place the input capacitor between PMID and GND pins as

close as possible to the chip with shortest copper connections

(avoid vias). Choose the smallest capacitor size.

5. Place decoupling capacitors close to the IC pins with the

shortest copper connections.

6. Solder the exposed thermal pad of the package to the PCB

ground planes. Ensure that there are enough thermal vias

directly under the IC, connecting to the ground plane on the

other layers for better heat dissipation and cooling of the

device.

2. Connect one pin of the inductor as close as possible to the

SW pin of the device and minimize the copper area

connected to the SW node to reduce capacitive coupling from

SW area to nearby signal traces. This decreases the noise

induced through parasitic stray capacitances and

displacement currents to other conductors. SW connection

should be wide enough to carry the charging current. Keep

other signals and traces away from SW if possible.

7. Select proper sizes for the vias and ensure enough copper

is available to carry the current for a given current path. Vias

usually have some considerable parasitic inductance and

resistance.

3. Place output capacitor GND pin as close as possible to the

GND pin of the device and the GND pin of input capacitor C_IN.

DC Current

DC Current Path

(I_AC≈ 0)

SYS

SW

(Boost Mode

Direction)

Switching Frequency

and Its Low Order

Very High

Frequency

(Current Path)

SYS

Harmonics

(Current Path)

Load

Transient

Current Path

C_IN

C_OUT

Figure 19. The Paths and Loops Carrying High Frequency, DC Currents and Very High Frequency

(for Layout Design Consideration)

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (SEPTEMBER 2022) to REV.A

Page

Changed from product preview to production data.............................................................................................................................................All

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PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

WLCSP-2.0×2.4-30B

D

0.22

0.20

0.4

30 × Φ

A1 CORNER

E

0.4

TOP VIEW

RECOMMENDED LAND PATTERN (Unit: mm)

30 × Φd

5

4

3

2

1

A

B

C

D

E

F

A

e

A1

e

SIDE VIEW

BOTTOM VIEW

Dimensions In Millimeters

Symbol

MIN

MOD

0.575

MAX

0.625

0.220

2.030

2.430

0.290

A

A1

D

E

0.525

0.180

1.970

2.370

0.230

0.200

2.000

2.400

d

0.260

e

0.400 BSC

NOTE: This drawing is subject to change without notice.

SG Micro Corp

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PACKAGE INFORMATION

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

P2

P0

W

Q2

Q4

Q2

Q4

Q2

Q4

Q1

Q3

Q1

Q3

Q1

Q3

B0

Reel Diameter

P1

A0

K0

Reel Width (W1)

DIRECTION OF FEED

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL

Reel Width

Reel

Diameter

A0

B0

K0

P0

P1

P2

W

Pin1

Package Type

W1

(mm)

(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant

WLCSP-2.0×2.4-30B

7″

9.0

2.15

2.55

0.75

4.0

2.0

8.0

Q1

SG Micro Corp

TX10000.000

www.sg-micro.com

PACKAGE INFORMATION

CARTON BOX DIMENSIONS

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF CARTON BOX

Length

(mm)

Width

(mm)

Height

(mm)

Reel Type

Pizza/Carton

7″ (Option)

7″

368

442

227

410

224

8

18

SG Micro Corp

www.sg-micro.com

TX20000.000


型号：	SGM41518
厂家：	Shengbang Microelectronics Co, Ltd
描述：	High Input Voltage, 1.26A Single-Cell Battery Charger with NVDC Power Path Management 电池
文件：	总47页 (文件大小：1444K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SGM41518 [SGMICRO]

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