XE1202AI027TRLF [SEMTECH]
433 MHz / 868 MHz / 915 MHz Low-Power, Integrated UHF Transceiver; 的433 MHz / 868 MHz的/ 915 MHz的低功耗，集成的UHF收发器
| 型号： | XE1202AI027TRLF |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 433 MHz / 868 MHz / 915 MHz Low-Power, Integrated UHF Transceiver |
| 文件： | 总32页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XE1202A TrueRF™
IAmp
QAmp
SCAN
I
Limiter
Limiter
BPF
BPF
AMP
AMP
AMP
AMP
DCLK
RFA
RFB
FSK
Demod.
Bit
Sync.
LNA
DATAOUT
Q
Pattern
Recognition
PATTERN
LO
Buff.
Phase
Shifter
FEI
RSSI
MODE 0
MODE 1
MODE 2
SI
Prog.
Control
Logic
divider
SO
modulator
/n Synthesizer
SCK
PFD
RFOUT
PA
VCO
EN
POR
I Ref
/n
Clock Out
Oscillator
DATAIN
XE1202A TrueRF™
433 MHz / 868 MHz / 915 MHz
Low-Power, Integrated UHF Transceiver
GENERAL DESCRIPTION
KEY PRODUCT FEATURES
The XE1202A TrueRF™ is a single chip transceiver
operating in the 433, 868 and 915 MHz license free
ISM (Industry Scientific and Medical) frequency
bands. Its highly integrated architecture allows for
minimum external components while maintaining
design flexibility. All major RF communication
parameters are programmable and most of them can
be dynamically set. The XE1202A TrueRF™ offers a
wide range of channel bandwidths, without the need
to modify the number or parameters of the external
components. The XE1202A TrueRF™ is optimized for
low power consumption whilst offering high RF output
power and channelized operation suitable for both the
European (ETSI-300-220) and the North American
(FCC part 15) regulatory standards.
Programmable RF output power: up to +15 dBm
High reception sensitivity: down to –116 dBm
Low power consumption: RX
TX = 62mA @15 dBm output power
Supply voltage down to 2.4 V
=
14 mA;
Data rates from 4.8 kbits/s to 76.8 kbits/s, NRZ
coding
Channel filter bandwidths from 20 kHz to 400 kHz
On-chip frequency synthesizer with minimum
frequency resolution of 500 Hz
Continuous phase 2-level FSK modulation
Incoming data pattern recognition
Built-in Bit-Synchronizer for incoming data and clock
synchronization and recovery
RSSI (Received Signal Strength Indicator) and FEI
(Frequency Error Indicator)
ORDERING INFORMATION
APPLICATIONS
Security systems
Voice and data over an RF link
Process and building control
Access control
Part number
Temperature range
-40 °C to +85 °C
Package
LQFP44
XE1202AI027TRLF
Home automation
Home appliances interconnection
Rev 1 January 2006
www.semtech.com
XE1202A TrueRF™
TABLE OF CONTENTS
1
2
3
3.1
3.2
Functional Block Diagram....................................................................................................................... 4
Pin description......................................................................................................................................... 5
Electrical Characteristics........................................................................................................................ 6
Absolute Maximum Operating Ranges.................................................................................................. 6
Specifications........................................................................................................................................ 6
3.2.1 Operating Range ....................................................................................................................................... 6
3.2.2 Electrical Specifications ............................................................................................................................. 6
4
Description............................................................................................................................................... 9
4.1
Detailed description .................................................................................................................................. 9
4.1.1 Receiver .................................................................................................................................................... 9
4.1.2 Receiver LNA modes .............................................................................................................................. 10
4.1.3 RSSI ........................................................................................................................................................ 11
4.1.4 Frequency Error Indicator - FEI................................................................................................................ 11
4.1.5 Transmitter............................................................................................................................................... 14
4.1.6 Pattern recognition................................................................................................................................... 15
4.1.7 Frequency synthesizer............................................................................................................................. 15
5
Serial Interface Definition, Principles of Operation............................................................................. 16
5.1
Serial Control Interface ............................................................................................................................ 16
5.1.1 General description.................................................................................................................................. 16
5.1.2 Write sequence........................................................................................................................................ 16
5.1.3 Read sequence........................................................................................................................................ 16
5.2
Configuration and Status registers ........................................................................................................... 17
5.2.1 RTParam configuration register ............................................................................................................... 17
5.2.2 FSParam configuration register ............................................................................................................... 19
5.2.3 DataOut register ...................................................................................................................................... 20
5.2.4 ADParam configuration register............................................................................................................... 20
5.2.5 Pattern register ........................................................................................................................................ 21
5.3
5.4
5.5
5.6
5.7
5.8
6
6.1
6.2
6.3
6.4
6.5
7
Operating Modes ................................................................................................................................ 23
Transmitted Data Interface ................................................................................................................. 25
Received Data Interface ..................................................................................................................... 25
Pattern Recognition Interface.............................................................................................................. 26
Clock Output Interface ........................................................................................................................ 26
Default settings at power-up ............................................................................................................... 26
Application Information......................................................................................................................... 27
Receiver matching network................................................................................................................. 27
Transmitter matching network ............................................................................................................ 27
VCO tank............................................................................................................................................ 29
Loop filter of the frequency synthesizer............................................................................................... 30
Reference crystal for the frequency synthesizer ................................................................................. 30
Packaging information .......................................................................................................................... 32
© Semtech 2006
www.semtech.com
3
XE1202A TrueRF™
The XE1202A TrueRF™ UHF Transceiver IC provides a single chip solution intended for use as a low cost FSK
transceiver to establish a frequency-agile, half-duplex, bi-directional RF link, with non-return to zero data coding.
The device is available in an LQFP44 package and is designed to provide a fully functional multi-channel FSK
transceiver. It is intended for applications in the 433 and 868 MHz European bands and the North American 902-
928 MHz ISM band. The single chip transceiver operates down to 2.4 V and provides low power consumption
solutions for battery-operated and power sensitive applications. Thanks to the low external components count, the
XE1202A is ideal for small size, low-cost UHF links. Its reference board has no tunable components, which
facilitates high volume cost sensitive production.
The XE1202A TrueRF™ can easily be interfaced to a controller such as the XEMICS’ XE8000 Series of ultra low-
power microcontrollers. The XE1202A TrueRF™ serial control registers are programmed by the MCU and the MCU
manages the communication protocol.
1 Functional Block Diagram
IAmp
QAmp
SCAN
I
Limiter
BPF
BPF
AMP
AMP
AMP
AMP
DCLK
RFA
RFB
FSK
Demod.
Bit
Sync.
LNA
DATAOUT
Limiter
Q
Pattern
Recognition
PATTERN
LO
Buff.
Phase
Shifter
FEI
RSSI
MODE 0
MODE 1
MODE 2
SI
Prog.
Control
Logic
divider
SO
modulator
/n Synthesizer
SCK
PFD
RFOUT
PA
VCO
EN
POR
I Ref
/n
Clock Out
Oscillator
DATAIN
Figure 1: XE1202A TrueRF™ block diagram
© Semtech 2006
www.semtech.com
4
XE1202A TrueRF™
2 Pin Description
PIN
1
2
NAME
MODE(1)
MODE(0)
/EN
DESCRIPTION
In
In
In
Transmit/Receive/Standby/Sleep Mode Select
Transmit/Receive/Standby/Sleep Mode Select
Chip Enable
3
4
5
VSSF
RFA
RF Analog Ground
RF Input
In
6
RFB
In
RF Input
7
8
9
VSSP
VSSP
RFOUT
VDDP
VSSP
VDD
TKA
TKB
VSSF
LFB
VDDD
VSSD
TSUPP
SCAN
OPT
TMOD[0]
TMOD[1]
VSSA
XTA
VSSA
XTB
VDDA
QAMP
IAMP
TMOD[2]
TMOD[3]
TIBIAS
VDD
SO
SI
In
In
Out
Power Amplifier Ground
Power Amplifier Ground
RF Output
Power Amplifier Supply Voltage
Power Amplifier Ground
RF Analog Supply Voltage
VCO Tank
VCO Tank
RF Analog Ground
PLL Loop Filter
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I/O
I/O
RF Digital Supply Voltage
RF Digital Ground
Test Circuit Supply Voltage (connected to VSS in normal operation)
Scan Test Input (connected to VSS in normal operation)
(connected to VSS in normal operation)
(connected to VSS in normal operation)
(connected to VSS in normal operation)
Analog Ground
Ref Xtal / Input of external clock
Analog Ground
Reference Xtal
In
I/O
I/O
Analog Supply Voltage
Buffered Q Output
Buffered I Output
Out
Out
(connected to VSS in normal operation)
(connected to VSS in normal operation)
(connected to VSS in normal operation)
Digital Supply Voltage
Configuration Register Serial Output
Configuration Register Serial Input
Configuration Register Serial Clock
Output clock at reference frequency divided by 4, 8, 16 or 32
Digital Ground
Recovered Received Data Clock
Received Data
Transmit Data
Output of the pattern recognition block
Transmit/Receive/Standby/Sleep Mode Select
Out
In
In
SCK
CLKOUT
VSS
DCLK
DATAOUT
DATAIN
PATTERN
MODE(2)
Out
Out
Out
In
Out
In
Table 1: Pin Description
© Semtech 2006
www.semtech.com
5
XE1202A TrueRF™
3 Electrical Characteristics
3.1 Absolute Maximum Operating Ranges
Stresses above those values listed below may cause permanent device failure. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Symbol
VDDmax
ML
Description
Min.
-0.4
Max.
3.9
Unit
Supply voltage
V
Receiver input level
Storage temperature
-5
dBm
°C
Tmax
-55
125
Table 2: Absolute Maximum Operating Ranges
The device is ESD sensitive and should be handled with precaution.
3.2 Specifications
3.2.1
Operating Range
Symbol
Description
Min.
2.4 (*)
Max.
Unit
VDD
T
Supply voltage
3.6
85
25
V
Temperature
-40
-
°C
pF
CLop
Load capacitance on digital ports
Table 3: Operating Range
(*) For narrow-band configurations (base-band filter bandwidths of 10, 20 and 40 kHz), the minimum operating
supply voltage is 2.4 V. For 200 kHz base-band filter bandwidth setting the minimum operating supply voltage is 2.7
V.
3.2.2
Electrical Specifications
The table below gives the electrical specifications of the transceiver under the following conditions:
Supply Voltage = 3.3 V, temperature = 25 °C, 2-level FSK without pre-filtering, fC = 434, 869 and 915 MHz,
∆f = 5 kHz, Bit rate = 4.8 kbits/s, BWSSB = 10 kHz, BER = 1 % (measured at the output of the bit synchronizer), LNA
input and PA output matched to 50 Ω, environment as defined in section 6, unless otherwise specified.
Symbol
IDDSL
IDDST
Description
Supply current in sleep mode
Supply current in standby Crystal oscillator (39 MHz)
Conditions
Min
-
-
Typ
0.2
0.85
Max
1
1.10
Unit
µA
mA
mode
enabled
IDDR
IDDT
Supply current in receive
mode
Supply current in transmitter RFOP = 5 dBm
-
14
16.5
mA
-
-
33
62
40
75
mA
mA
mode
RFOP = 15 dBm
RFS
RF sensitivity 869 / 915 MHz A-mode
B-mode
-
-116
-103
dBm
dBm
-113
-100
RF sensitivity 434 MHz
A-mode
B-mode
-
-114
-100
dBm
dBm
-111
-98
FDA
Frequency deviation
-
-
5
-
kHz
kHz
Programmable
10
-
-
-
20
40
-
kHz
kHz
kHz
dBc
-
-
100
-10
-
CCR
Co-channel rejection
-13
-
© Semtech 2006
www.semtech.com
6
XE1202A TrueRF™
Symbol
IIP3
Description
Conditions
fLO
Min
Typ
Max
Unit
Input intercept point (from f1
=
+
1
MHz,
LNA input to base-band filter f2 = fLO + 1.995 MHz
output)
A-mode
-33
-18
-
-
dBm
dBm
B-mode
-36
-21
BW
Base band filter bandwidth
Programmable
-
-
10
-
kHz
kHz
20
-
-
-
40
-
-
kHz
kHz
dBc
200
ACR
BR
Adjacent channel rejection funw = fLO + 65 kHz
869 / 915 MHz Pw=-107 dBm, A-mode
Adjacent channel rejection funw = fLO + 65 kHz
45
48
-
42
45
dBc
-
434 MHz
Pw=-102 dBm, A-mode
-
-
-
-
-
4.8
9.6
19.2
38.4
-
-
-
-
-
kbits/
s
kbits/
s
kbits/
s
Bit rate
Programmable
76.8
kbits/
s
kbits/
s
RFOP
FR
RF output power
Programmable
RFOP1
RFOP2
RFOP3
RFOP4
-3
+2
+7
+12
0
+5
+10
+15
-
-
-
-
-
-
-
dBm
dBm
dBm
dBm
MHz
MHz
MHz
Synthesizer frequency range Programmable
433
435
870
928
Each range with its own 868
external components
902
TS_BBR Receiver baseband wake-up
time (first step)
-
200
100
200
500
250
150
250
600
µs
µs
µs
µs
Crystal oscillator enabled
TS_TR
TS_FS
TS_BB2
Transmitter wake-up time
Frequency
enabled
synthesizer
-
-
-
Frequency synthesizer wake- Crystal oscillator enabled
up time
Frequency
enabled
synthesizer
Receiver
RF
Front-End
wake-up time
RTParam_WBB=0
TS_FSW
TS_RS
Between 2 channels at 1
MHz channel spacing
100
-
150
1.0
µs
Frequency
switching time
synthesizer
RSSI
enabled
during
-
-
ms
RSSI wake-up time (receiver
operation in mode 100)
mode 010 0.5 ms before
switching to mode 100
(see figure 8)
RSSI
enabled
during
-
1.5
ms
mode 100
TS_RSM
TS_OS
-
-
0.5
0.3
-
ms
ms
RSSI measurement time
0.5
Crystal oscillator wake-up
time
© Semtech 2006
www.semtech.com
7
XE1202A TrueRF™
Symbol
Description
Conditions
Min
Typ
Max
Unit
TS_FE
FEI
wake-up
time Receiver enabled
-
-
-
-
20/BR
4/BR
(RTParam_Fsel = 1)
RTParam_Fsel = 1
RTParam_Fsel = 0
ms
ms
FEI
counting
duration
(RTParam_Fsel = 0)
FXTAL
FSTEP
Crystal oscillator frequency
Frequency synthesizer step
-
-
39
-
-
MHz
Hz
500
Exact step is XTAL
77824
/
VTHR
Equivalent
thresholds
RSSI
input A-mode,low range:VTHR1
-
-105
-
dBm
VTHR2
VTHR3
A-mode,high range:VTHR1
VTHR2
VTHR3
-
-
-
-
-
-100
-95
-90
-85
-80
-
-
-
-
-
dBm
dBm
dBm
dBm
dBm
-
FERR
SPR
FEI error threshold
Pw=-100 dBm, A-mode
RTParam_Fsel = 1
-
0.5
-
Spurious emission in receiver (1)
mode
-
-65
-
dBm
VIH
VIL
% VDD
75
-
-
-
-
-
%
%
%
%
Digital input level high
Digital input level low
-
% VDD
25
VOH
VOL
Digital output level high
Digital output level low
% VDD
75
-
-
% VDD
25
Table 4: Electrical Specifications
SPR strongly depends on the design of the application board and the choice of the external components. Values
down to -70 dBm can be achieved with careful design.
© Semtech 2006
www.semtech.com
8
XE1202A TrueRF™
4 Description
The XE1202A TrueRF™ is a direct conversion (Zero-IF) half-duplex data transceiver. It includes a receiver, a
transmitter, a frequency synthesizer and some service blocks. The circuit operates in the 3 ISM frequency bands
(433 MHz, 868 MHz, 915 MHz) and uses 2-level FSK modulation/demodulation to provide a complete transmission
link.
In a typical application, the XE1202A TrueRF™ is programmed by a microcontroller via the 3-wire serial bus, SI,
SO, SCK to write to and read from the configuration registers.
The circuit consists of 5 main functional blocks:
The Receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver is
composed of a low-noise amplifier, down-conversion mixers, baseband filters, baseband amplifiers, limiters,
demodulator and the bit synchronizer. The bit synchronizer transforms the data output of the demodulator into a
glitch-free bit stream DATAOUT and generates a synchronized clock, DCLK, which can be used to sample
DATAOUT without requiring external signal processing. In addition, the receiver includes a Received Signal
Strength Indicator (RSSI) function, a Frequency Error Indicator (FEI) function that provides an indication of local
oscillator frequency error, and pattern recognition function to detect programmable reference words in the received
bit stream. The bandwidth of the base-band filters, the frequency deviation of the expected incoming FSK signal as
well as the bit rate of the received data are all programmable.
The Transmitter performs the modulation of the carrier by an input bit stream and the transmission of the
modulated signal. Carrier modulation is achieved directly through the frequency synthesizer via a Sigma-Delta
modulator. The frequency deviation and bit rate of the modulated carrier are programmable. An on-chip power
amplifier then amplifies the signal. The output power can be programmed to one of 4 possible settings.
The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver section as well as the
continuous phase FSK (CPFSK) modulated signal for the transmitter section. The core of the synthesizer is
implemented with a PLL structure. The frequency is programmable with a step size of 500 Hz in the 3 ISM
frequency bands at 433, 868 and 915 MHz. This frequency synthesizer includes a crystal oscillator which provides
the reference for the PLL. This reference frequency can be divided by 4, 8, 16 or 32 and available as CLKOUT to
provide a clock signal for an external processor.
The Digital Interface provides internal control signals for the whole circuit according to the configuration register
settings.
The Service Block provides the internal voltage and current sources and provides all the necessary functions for
the circuit to work properly.
4.1 Detailed description
4.1.1
Receiver
The outputs of the receiver are the two signals DATAOUT and DCLK. When “RTParam_Bits” is set to “1” (see the
Configuration register section below), the bit synchronizer is enabled, and the two output signals are the output
NRZ demodulated data and the sampling clock, respectively. The function of the bit synchronizer is to remove the
glitches from DATAOUT and to provide the output clock DCLK to sample the data. The value of DATAOUT is valid
at the rising edge of DCLK.
To ensure correct operation of the bit synchronizer, the following three conditions must be satisfied:
the received data must start with a preamble of 24 bits for synchronization; this preamble must be a sequence of
alternating “0” and “1”,
the received data must have at least one transition from “0” to “1” or from “1” to “0” every 8 bits,
the accuracy of the bit rate must be within ± 5 % of that programmed (assuming the reference Xtal oscillator is 39
MHz).
© Semtech 2006
www.semtech.com
9
XE1202A TrueRF™
When “RTParam_Bits” is set to “0”, the bit synchronizer is turned off, and DATAOUT is the output of the
demodulator. In this case DCLK is not used and its value is set “low”.
For guaranteed operation of the demodulator, the modulation index, β, of the modulated carrier should meet the
2⋅∆f
following condition:
β =
≥ 2,
BR
where ∆f is the frequency deviation, and BR the bit rate.
Table 5 details typical sensitivity figures for different bit rates, frequency deviations and baseband filter bandwidths:
Bit rate
[kbits/s
]
BW
[kHz]
Sensitivity for 1 % BER
[dBm]
∆f
[kHz]
mode A
-116
mode B
-103
4.8
5
10
20
10
20
20
40
40
100
100
40
20
40
40
200
200
200
200
-117
-115
-115.5
-112.5
-109
-107
-109
-106.5
-104
-101
9.6
-102.5
-99.5
-97.5
-95
-97.5
-95
19.2
38.4
76.8
Table 5: Sensitivity for 1 % BER
Figure 2 illustrates the typical BER curve under narrowband conditions:
RX in mode A
-2
10
-3
10
BER
-4
10
-5
10
-6
10
-116 -115 -114 -113 -112 -111 -110 -109
Pin [dBm]
Figure 2: BER versus Rx input power with BR=4.8 kbits/s, ∆f=5 kHz, BW=10 kHz
4.1.2
Receiver LNA modes
The receiver can be operated in two different modes that provide the highest sensitivity (for reception of weak
signals) or the highest linearity (in areas of strong signals). The receiver mode is determined by the programming of
the “RTParam_Rmode” register (see the Configuration register section below).
A-mode: high sensitivity mode (see RFS parameter)
B-mode: high linearity mode (see IIP3 parameter)
© Semtech 2006
www.semtech.com
10
XE1202A TrueRF™
4.1.3
RSSI
When enabled, this function provides an RSSI (Received Signal Strength Indication) based on the signal at the
output of the base-band filter. To enable the RSSI function, the bit “RTParam_RSSI” should be set to “1” (see the
Configuration register section below). When enabled, the status of the RSSI is a 2-bit word stored in register
“DataOut_RSSI”, which can be read via the serial control interface. The contents of the register are defined in
Table 6 below, where VRFFIL is the differential amplitude of the equivalent input RF signal when the receiver is
operated in A-mode. The thresholds VTHRi are the thresholds at the output of the base-band filter divided by the
gain between the input of the receiver and this output.
DataOut_RSSI
Description
VRFFIL ≤ VTHR1
0 0
VTHR1 < VRFFIL ≤ VTHR2
VTHR2 < VRFFIL ≤ VTHR3
VTHR3 < VRFFIL
0 1
1 0
1 1
Table 6: RSSI status description
Two ranges, each of three VTHRi thresholds are defined and selected via the setting of the register
“RTParam_RSSR”, to provide an overall RSSI range of typically 25 dB.
The timing diagram of an RSSI measurement is illustrated by Figure 3 below. When the RSSI function has been
activated the signal strength is periodically measured and the result is stored in the register “DataOut_RSSI” at
each rising edge of DATAIN. TS_RS is the wake-up time required after the function has been enabled to ensure
that a valid reading of RSSI is obtained. For a proper operation, the pulse length on DATAIN has to be higher than
8µs.
RTParam_RSSI
/en
TS_RS
TS_RSM
RSSI_out
val1
val2
val3
val4
0
xxx
(internal signal)
datain
DtaOut_RSSI
xxx
val1
val4
Figure 3: RSSI measurement timing diagram
For applications where a valid RSSI reading is required within as short a time frame as possible, enabling the RSSI
during receiver mode 010 instead of 100 (see the definition of TS_RS in Table 4) allows a valid RSSI within 1 ms of
valid data being received.
4.1.4
Frequency Error Indicator - FEI
When enabled, this function provides an indication of the frequency error of the local oscillator compared with the
received carrier frequency. For guaranteed operation of the FEI function, the following two conditions should be
satisfied.
© Semtech 2006
www.semtech.com
11
XE1202A TrueRF™
The modulation index, b, of the modulated carrier should meet the following condition:
2⋅∆f
BR
β =
≥ 2,
where ∆f is the frequency deviation and BR is the bit rate.
The bandwidth of the baseband filter (BBW) must be greater than the sum of the frequency offset and the received
signal bandwith, as defined below:
BBW > fOFFSET + BWSIGNAL
where BBW is the baseband filter bandwidth defined by the RTParam_BW parameter (see the Configuration
Registers section below), fOFFSET is the difference between the carrier frequency and the LO frequency, and
BR
⎛
⎞
BWSIGNALis equal to
+ ∆f
.
⎜
⎟
2
⎝
⎠
The FEI function has two modes of operation, defined by the value set in the register “RTParam_Fsel” (see the
Configuration register section below).
4.1.4.1
“RTParam_Fsel” = 1
With the “RTParam_FEI” bit set to “1” and the “RTParam_Fsel” bit set to “1”, the FEI uses frequency correlation to
provide a 2-bit status word, which is stored in the register “DataOut_FEI”. The contents of this register are defined
below in Table 7. The status of this register is provided in the following table, where fLO is the internal local oscillator
frequency, and fRF is the carrier frequency of the received signal.
DataOut_FEI
Meaning
⏐fLO-fRF⏐ ≤ fERR
0 0
-
0 1
1 0
1 1
(fLO-fRF) > fERR
(fLO-fRF) < -fERR
Table 7: FEI status description
The value fERR = FERR * BR, where BR is the bit rate and FERR is a ratio given in the electrical specifications. As
an example, for a bit rate of 4.8kbits/s and with FERR = 0.5, fERR is 2.4 kHz.
The FEI-Correlator function works properly only if the input signal is the preamble sequence defined under the
Receiver section above, and if the frequency error to be detected is lower than 20 kHz.
The time diagram of an FEI measurement is similar to that of an RSSI measurement, and is illustrated in Figure 4
below. When the FEI is enabled, the frequency error is periodically measured and the result is stored in the register
“DataOut_FEI” at each rising edge of DATAIN. TS_FE is the wake-up time required after the function has been
enabled to obtain a valid result. For a proper operation, the pulse length on DATAIN has to be higher than 8µs.
© Semtech 2006
www.semtech.com
12
XE1202A TrueRF™
RTParam_FEI
en
fei_out
XX
VAL1
VAL2
VAL3
VAL4
XX
datain
DataOut_FEI
XX
VAL2
VAL4
TS_FE
Figure 4: FEI measurement timing diagram when “RTParam_Fsel” = 1
4.1.4.2 “RTParam_Fsel” = 0
With the “RTParam_FEI” bit set to “1” and the RTParam_Fsel” bit set to “0”, the FEI function uses over sampling of
the signal at the output of the demodulator. When activated by the rising edge of DATAIN, this function provides an
8-bit word equivalent to the duty cycle of the demodulated preamble, stored in register “DataOut_FEI”.
Each sample is used to control an up/down counter, when the sample is "1" the content of the counter is
incremented, when the sample is "0" the content of the counter is decremented. As a consequence, the final 8-bit
value of the counter stored in “DataOut_FEI” gives an indication of the duty cycle of the demodulated signal. The
range of stored values is from -128 and +127. The further from 0 the value of DataOut_FEI, the higher the error on
the LO frequency. If the stored value in “DataOut_FEI” is typically zero, then the duty cycle of the preamble is about
50 %, and the LO frequency is nominally correct.
Since this FEI uses the signal before the bit synchronizer, its value can vary from one measurement to another,
due to the presence of jitter and glitches in the signal. If possible, it is advised to make 4-5 measurements and take
the average value.
The timing diagram for this FEI measurement is illustrated in Figure 5 below. The FEI function is activated at the
rising edge of the /EN signal when the RTParam_FEI bit is set to “1”. Then, the internal FEI counter is activated at
the rising edge of DATAIN. After a period TS_FE equal to the duration of 4 bits (see Electrical Specifications), the
counter is stopped and the contents are stored in the register DataOut_FEI. For a proper operation, the pulse
length on DATAIN has to be higher than 8µs.
The maximum delay between the rising edge of DATAIN and the first clock on the internal FEI counter is 1/(16*BR),
where BR is the bit rate.
© Semtech 2006
www.semtech.com
13
XE1202A TrueRF™
RTParam_FEI
en
Demodulated
BIT B0 BIT B0+1 BIT B0+2 BIT B0+3 BIT B0+4
data
datain
counter_out
0
N
DataOut_FEI
X
N
TS_FE
Figure 5: Timing diagram of an FEI measurement when “RTParam_Fsel” = 0
(the number of transitions on “counter_out” is for illustration only)
4.1.5
Transmitter
The output power of the power amplifier is programmable on four values with the register “RTParam_Tpow” (see
the Configuration register section below), as shown in the table below, where RFOP values are given in Electrical
Specifications section.
RTParam_Tpow
Output power
RFOP1
0 0
RFOP2
RFOP3
RFOP4
0 1
1 0
1 1
Table 8: output power settings
The degree of filtering of the baseband data prior to the modulation of the LO carrier frequency is programmable
via the RTParam_Filter register:
-
the input bit stream is directly applied to the frequency synthesizer without any pre-filtering
(RTParam_Filter=0)
-
the input bit stream is pre-filtered before being applied to the frequency synthesizer; with this filtering, each
edge of the bit stream is linearly smoothed with a staircase transition (RTParam_Filter=1)
This is illustrated in Figure 6, where DATAIN is the input bit stream to be transmitted:
© Semtech 2006
www.semtech.com
14
XE1202A TrueRF™
t
bit
datain
no filtering
IN
freq_synth
t
rise
staircase filtering
IN
freq_synth
Figure 6: Modulation without and with pre-filtering
The characteristic of the smoothing filter is the ratio trise/tbit. The value of this ratio is programmable with the register
“RTParam_Stair”, as illustrated in Table 9:
FSParam_Stair
trise/tbit
10 %
0
20 %
1
Table 9: Smoothing filter
4.1.6
Pattern recognition
XE1202A TrueRF™ includes a pattern recognition function. When “ADParam_Pattern” (see the Configuration
register section below) is set to “1” pattern recognition is enabled, providing that the bit synchronizer is also
enabled. With the pattern recognition function enabled, the demodulated data is compared with a pattern stored in
the “Pattern” register. The length of this pattern can be 8, 16, 24, or 32 bits, as defined by “ADParam_Psize”. When
comparing the streams 0, 1, 2, or 3 errors, as defined by “ADParam_Psize” can be allowed to detect a match. The
PATTERN output is driven by the output of this comparator. It is “high” when a match is detected, otherwise “low”.
When the feature is disabled, the PATTERN output is set to “low”.
4.1.7
Frequency synthesizer
The exact frequency step of the frequency synthesizer can be obtained from the following equation:
FSTEP = FXTAL / 77 824.
As an example, if FXTAL is exactly 39 MHz, FSTEP = 501.13 Hz.
© Semtech 2006
www.semtech.com
15
XE1202A TrueRF™
When the “RTParam_Clkout” bit is set high, FXTAL is frequency divided by 4, 8, 16, or 32, depending on the value
of register “ADParam_Clkfreq” (see the Configuration register section below), and made available as CLKOUT, for
use as clock signal for an MCU or external circuitry. If the reference frequency is 39 MHz, the available output
frequency of CLKOUT is 1.22, 2.44, 4.87, or 9.75 MHz, respectively. When the XE1202A TrueRF™ is in Sleep
Mode (MODE[2:0] = 000), CLKOUT is disabled.
5 Serial Interface Definition, Principles of Operation
5.1 Serial Control Interface
5.1.1
General description
A 3-wire bi-directional bus (SCK, SI, SO) is used to program the XE1202A TrueRF™ and read data from it. SCK
and SI are input signals, for example generated by a microcontroller. SO is an output signal controlled by the
XE1202A TrueRF™. In write mode, at the falling edge of the SCK signal, the logic data on the SI line is written into
an internal shift register. In read mode, at the rising edge of the SCK signal, the data on the SO line becomes valid
and should be sampled at the next falling edge of SCK.
The signal /EN must be low during the complete write and read sequences. In write mode the actual content of the
configuration register is updated at the rising edge of the /EN signal. Before this, the new data is stored in
temporary registers whose content does not affect the transceiver settings.
5.1.2
Write sequence
The time diagram of a write sequence is illustrated in Figure 7 below. This sequence is initiated when a Start
condition is detected, defined by the SI signal being set to “0” during a period of SCK. The next bit is a read/write
(R/W) bit which should be “0” to indicate a write operation. The next 5 bits are the address of the control register
A[4:0] to be accessed, MSB first. Then the next 8 bits contain the data to be written in the register. The sequence
ends with 2 stop bits set to “1”. The data on SI should change at the rising edges of SCK, and is sampled at the
falling edge of SCK. After the 2 stop bits, the data transfer is terminated, even if the SI line stays at “1”. After this
the SI line should be at “1” for at least one clock cycle on SCK before a new write or read sequence can start. This
mode of operation allows data to be written to multiple registers without the need to alter the status of EN.
The maximum frequency of SCK is 1 MHz. The minimum clock pulse width is 0.5us. Set-up and hold time for SI on
the falling edge of SCK is 200 ns, over the operating supply and temperature range.
SCK
STOP STOP
START R/W
A(4)
A(1)
A(0)
D(7)
D(6)
D(3)
D(2)
D(1)
D(0)
SI
SO
/EN
Figure 7: Write sequence into configuration register
5.1.3
Read sequence
The time diagram of a read sequence is illustrated in Figure 8. The sequence is initiated when a Start condition is
detected, defined by the SI signal being set to “0” during a period of SCK. The next bit is a read/write (R/W) bit
which should be “1” to indicate a read operation. The next 5 bits are the address of the control register A[4:0] to be
accessed, MSB first. The data from the register is then output on the SO pin.
The data becomes valid at the rising edges of SCK and should be sampled at the falling edge of SCK. After this the
data transfer is terminated. The SI line must stay high for at least one clock cycle on SCK to start a new write or
read sequence. The maximum current drive on SO is 2 mA for a supply voltage of 2.7 V, and the maximum load is
CLop, as defined in the Electrical Specifications.
© Semtech 2006
www.semtech.com
16
XE1202A TrueRF™
SCK
SI
START R/W
A(4)
A(0)
D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
SO
/EN
Figure 8: Read sequence into configuration register
When the serial interface is not used for read or write operations, both SCK and SI should be set to “1”.
Note that except in read mode, SO is set to “0” and cannot be configured in a high-impedance mode.
5.2 Configuration and Status registers
XE1202A TrueRF™ has a series of configuration registers programmable through the serial control interface
described above. Their details are listed in Table 10 below. The size of these registers is 1, 2, 3, or 4 bytes. Their
byte address is a 5 bit address, A[4:0]. In addition, there is one register, DataOut, from which users can read
various transceiver status information.
Size
2 x 8 bit
Description
Name
Byte Address
RTParam
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
Receiver
parameters registers
Frequency parameters
and
transmitter
FSParam
3 x 8 bit
DataOut
ADParam
1 x 8 bit
2 x 8 bit
Transceiver data register
Additional parameters
Pattern
Reference pattern for the “pattern
recognition” function
4 x 8 bit
Table 10: Configuration registers
All the bits that are referred to as “reserved” in this section should be set to “0” during write operations.
5.2.1
RTParam configuration register
Bits
Byte Address
Description
Name
7
00000
RTParam_Rmode
Receiver modes:
0 -> A-mode (high sensitivity)
1 -> B-mode (high linearity)
RTParam_Bits
6
00000
Bit synchronizer on/off:
0 -> off; 1 -> on
RSSI on/off:
0 -> off; 1 -> on
RTParam_RSSI
RTParam_FEI
5
4
00000
00000
FEI on/off:
0 -> off; 1 -> on
© Semtech 2006
www.semtech.com
17
XE1202A TrueRF™
Bits
Byte Address
Description
Name
RTParam_BW
3-2
00000
Bandwidth of the BB filter:
0 0 -> 10 kHz
0 1 -> 20 kHz
1 0 -> 40 kHz
1 1 -> 200 kHz
RTParam_Tpow
1-0
00000
Transmitter output power:
0 0 -> 0 dBm
0 1 -> 5 dBm
1 0 -> 10 dBm
1 1 -> 15 dBm
RTParam_Osc
RTParam_WBB
RTParam_Filter
7
6
5
4
00001
00001
00001
00001
Source for the reference frequency:
0 -> on-chip crystal oscillator
1 -> external signal
Receiver wake-up type selection
0 -> “Boost” power up sequence
1 -> Standard power-up sequence
Pre-filtering of bit stream in
transmitter mode:
0 -> no filtering; 1 -> filtering
RTParam_Fsel
RTParam_Stair
FEI mode:
0 -> FEI_Demodulator
1 -> FEI_Correlator
3
2
00001
00001
Rise
and
fall
time
when
RTParam_Filter = 1:
0 -> 10 % of bit duration
1 -> 20 % of bit duration
RTParam_Modul
Modulation switch:
0 -> modulation enabled;
1 -> modulation disabled
1
0
00001
00001
RTParam_RSSR
RTParam_Clkout
RSSI range:
0 -> low range; 1 -> high range
CLKOUT enable:
0 -> CLKOUT disabled
1 -> CLKOUT enabled (equal to
FXTAL divided by 4, 8, 16 or 32)
Table 11: RTParam configuration register
© Semtech 2006
www.semtech.com
18
XE1202A TrueRF™
5.2.2
FSParam configuration register
Name
FSParam_Band
Bits
7-6
Byte Address
00010
Description
Frequency band:
0 0 -> not valid
0 1 -> 433 – 435 MHz
1 0 -> 868 – 870 MHz
1 1 -> 902 – 928 MHz
5-3
2-0
00010
00010
FSParam_Dev
FSParam_BR
Frequency deviation:
0 0 0 -> 5 kHz
0 0 1 -> 10 kHz
0 1 0 -> 20 kHz
0 1 1 -> 40 kHz
1 0 0 -> 100 kHz
Bit rate:
0 0 0 -> 4.8 kbits/s
0 0 1 -> 9.6 kbits/s
0 1 0 -> 19.2 kbits/s
0 1 1 -> 38.4 kbits/s
1 0 0 -> 76.8 kbits/s
others -> not valid
7-0
00011
00100
FSParam_Freq
LO frequency in 2’s-complement
representation:
7-0
00…0 -> fLO = middle of the range
0X…X -> fLO = higher than the
middle of the range
1X…X -> fLO = lower than the
middle of the range
MSB = bit 7 of byte at pos. 00011
LSB = bit 0 of byte at pos. 00100
See example below
Table 12: FSParam configuration register
Table 13 below provide an example of LO frequency setting in FSParam_Freq:
Byte
00011
Bit 7
Address
Bit 0
Byte Address
00100
LO frequency
Note: FXTAL = 39.0 MHz
Bit 7
Bit 0
F0, where F0 depends on the selected
frequency band (see FSParam_Band
)
00000000
F0 = 434.0 MHz for the 433-435 MHz band
F0 = 869.0 MHz for the 868-870 MHz band
F0 = 915.0 MHz for the 902-928 MHz band
F0 + 500 Hz
00000000
00000001
00000010
11111111
11111110
00000000
00000000
11111111
11111111
F0 + 2 * 500 Hz
F0 – 500 Hz
F0 – 2 * 500 Hz
Table 13: LO Frequency setting
© Semtech 2006
www.semtech.com
19
XE1202A TrueRF™
5.2.3
DataOut register
Name
Bits
Byte Address
Description
7-6
RSSI output:
DataOut_RSSI
00101
0 0 -> lowest level
0 1 -> 2nd level
1 0 -> 3rd level
1 1 -> highest level
7-0
5-4
00101
00101
FEI output:
Output of the up/down counter in
2’s-complement representation
DataOut_FEI
When
RTParam_Fsel = 0
MSB = bit 7
FEI output:
DataOut_FEI
0 0 -> frequency OK
1 0 -> frequency too low
When
RTParam_Fsel = 1
1 1 -> frequency too high
Table 14: DataOut register
5.2.4
ADParam configuration register
Bits
Byte Address
Name
Description
7
00110
Pattern recognition enable:
0 -> Disabled
ADParam_Pattern
1 -> Enabled
6-5
00110
Size of reference pattern recognition
word:
ADParam_Psize
0 0 -> 8 bits
0 1 -> 16 bits
1 0 -> 24 bits
1 1 -> 32 bits
4-3
00110
Number of tolerated errors for the
pattern recognition:
ADParam_Ptol
0 0 -> 0 error
0 1 -> 1 error
1 0 -> 2 errors
1 1 -> 3 errors
2-1
00110
00110
ADParam_Clkfreq
Frequency of CLKOUT:
0 0 -> 1.22 MHz (div. ratio: 32)
0 1 -> 2.44 MHz (div. ratio: 16)
1 0 -> 4.87 MHz (div. ratio: 8)
1 1 -> 9.75 MHz (div. ratio: 4)
0
IQ amplifiers enable:
0 -> Disabled
ADParam_IQA
1 -> Enabled
7
00111
00111
ADParam_Res1
Reserved. Should be set to “0”
6
Inversion of the Rx output data:
0 -> non-inverted data
1 -> inverted data
ADParam_Invert
© Semtech 2006
www.semtech.com
20
XE1202A TrueRF™
Bits
Byte Address
Name
Description
5
00111
Baseband
regulation:
filter
bandwidth
ADParam_RegBW
0 -> Enabled
1 -> Disabled
4
3
00111
00111
Periodicity of baseband filter
bandwidth regulation:
0 -> only at start-up of the receiver
ADParam_Regfreq
ADParam_Regcond
1
-> every 60 seconds whilst
receiver enabled
Regulation process of the baseband
filter bandwidth according to the
selected bandwidth:
0 -> regulation restarted each time
the bandwidth is changed
1
-> no regulation when
bandwidth is changed
2
00111
Boosting process of the baseband
filter according to the selected
bandwidth:
ADParam_WBBcond
0 -> boosting restarted each time
the bandwidth is changed
1
->
no
boosting
when
bandwidth is changed
1
0
00111
00111
Selection of the XOSC load
capacitance mode:
0 -> CLop + C0 = 15 pF
1 -> CLop + C0 = 11 pF (low-current
mode)
ADParam_Xsel
RESERVED
RESERVED
Table 15: ADParam configuration register
5.2.5
Pattern register
The pattern register may be used to automatically detect the reception of a user-defined pattern and asserts the
PATTERN signal for one bit duration. In this register, a reference pattern length of 8, 16, 24, or 32 bits (see
ADParam_Psize parameter) may be defined. The first byte of the pattern is always stored at byte address A[4:0] (=
01000). If defined, the second and subsequent byte(s) are stored at address A[4:0] = 01001, and so on.
The MSB of the reference pattern is always bit 7 of the address 01000 and the LSB is bit 0 of address 01000,
01001, 01010, or 01011 if the pattern length is 8, 16, 24, or 32 bits, respectively.
Comparing the demodulated data, the first bit received of the last word (or second, third or fourth from last word,
depending upon the value stored in the ADParam_Psize register) is compared with bit 7 (the MSB) of byte address
01000. The last bit received is compared with bit 0 (the LSB) in the Pattern register.
Name
Bits
Byte Address
01000
01001
01010
01011
Description
7-0
Pattern
1st byte of the reference pattern
2
nd byte
3rd byte
4th byte
Table 16: Pattern register addresses
© Semtech 2006
www.semtech.com
21
XE1202A TrueRF™
Table 17 below shows an example of pattern recognition with a 32-bit pattern:
Byte
01000
Bit 7
Address
Bit 0
Byte Address
01001
Byte Address
01010
Byte Address
01011
Bit 7
Bit 0
Bit 7
Bit 0
Bit 7
Bit 0
10101010
10101010
10010011
10010011
10010011
101 10010011
10101010
10101010
previous bits from
demodulator
last bit received
Table 17: Pattern recognition example (32-bit)
Table 18 below shows an example of pattern recognition with an 8-bit pattern.
Byte
01000
Bit 7
Address
Bit 0
Byte Address
01001
Byte Address
01010
Byte Address
01011
Bit 7
Bit 0
Bit 7
Bit 0
Bit 7
Bit 0
xxxxxxxx
xxxxxxxx
10010011
xxxxxxxx
101 10010011
previous bits from
demodulator
last bit received
Table 18: Pattern recognition example (8-bit)
© Semtech 2006
www.semtech.com
22
XE1202A TrueRF™
5.2.6
Supplementary configuration
Configuration settings to optimize device performance under certain operation conditions are described in Table 19
below:
Bits
Byte Address
Name
Description
2
10011
Bandwidth decoding map:
TParam_BW
Baseband filter bandwidth
(RTParam_BW):
0 -> default values:
RTParam_BW(1:0) = 00 => 10 kHz
RTParam_BW(1:0) = 01 => 20 kHz
RTParam_BW(1:0) = 10 => 40 kHz
RTParam_BW(1:0) = 11 => 200 kHz
1 -> new values:
RTParam_BW(1:0) = 00 => 14.3 kHz
RTParam_BW(1:0) = 01 => 28.5 kHz
RTParam_BW(1:0) = 10 => 66.7 kHz
RTParam_BW(1:0) = 11 => 100 kHz
5-3
10110
Cut-off frequency of the HPF stages
allowing to cancel the DC and low-
frequency offsets in the baseband
circuit:
TParam_HPF
0 0 0 -> 660 Hz (default value)
0 0 1 -> 1.48 kHz
0 1 0 -> 1.75 kHz
0 1 1 -> 1.96 kHz
1 0 0 -> 2.55 kHz
1 0 1 -> 3.34 kHz
1 1 0 -> 5.11 kHz
1 1 1 -> 10.2 kHz
Table 19: Supplementary configuration
Using TParam_BW allows intermediate bandwidths to be accessed; these additional bandwidths can be selected to
optimize the sensitivity and the selectivity of the applications for which the signal bandwidth is different from the 4
default filter bandwidths.
The wake-up time of the receiver may be reduced by increasing the cut-off frequency of the HPF stages. This is
accomplished by changing the value of TParam_HPF.
Note that the selected cut-off frequency should be less than (∆f – (BR/2)) to avoid sensitivity degradation.
5.3 Operating Modes
The XE1202A TrueRF™ has 4 main operating modes as set by the MODE[2:0] inputs as illustrated in Table 20
below. Switching between modes is only possible when the /EN signal is low. The actual change will be applied to
the transceiver upon the rising edge of the /EN signal.
Over the operating supply and temperature range, set-up and hold time for MODE[2:0] on the rising edge of /EN is
200 ns, while the negative pulse duration on /EN is 2 µs minimum. Please refer to Figure 9:
© Semtech 2006
www.semtech.com
23
XE1202A TrueRF™
MODE[2:0]
EN
XXX
YXY
Transceiver in Mode XXX
Transceiver in Mode YXY
Figure 9: Switching mode sequence
Name
MODE(2:0) Description
0 0 0
0 0 1
1 0 0
1 1 1
-
Sleep mode
Xtal oscillator enabled
Standby mode
Receiver mode
Transmitter mode
Xtal oscillator, Frequency synthesizer, Receiver enabled
Xtal oscillator, Frequency synthesizer, Transmitter enabled
Table 20: XE1202A Main operating modes
Three additional operating modes are defined and should be used when the transceiver is switched from the
standby mode to the receiver or transmitter mode. These additional operating modes are illustrated in Table 21
below.
Name
Receiver mode
MODE(2:0) Description
0 1 0
0 1 1
Xtal oscillator, Baseband enabled (first step)
Xtal oscillator, Frequency synthesizer, Baseband enabled
(first step)
1 1 0
Xtal oscillator, Frequency synthesizer enabled
Transmitter mode
Table 21: XE1202A Additional operating modes
The power up sequence from sleep to receiver mode is selected by setting the RTParam_WBB parameter to “0”. The
sequence is described in Table 22 below:
Received data valid
Mode = 000 Mode = 001 Mode = 010
Mode = 011
Mode = 100
Mode=001
Xtal
oscillator
enabled
- Sleep
-
Xtal - Baseband
- Xtal
-
Frequency - RF Front End
-
oscillator
synthesizer
- Baseband
- Frequency synthesizer
- Baseband
enenabled
oscillator
enabled
-
Xtal
oscillator
-
Xtal
oscillator
enabled
enabled
≥TS_OS
≥TS_BBR
≥TS_FS
≥TS_BB2
Table 22: Power up sequence from Standby to Receive Mode
© Semtech 2006
www.semtech.com
24
XE1202A TrueRF™
The typical current consumption values during the power-up sequence from Standby to Receive Mode are shown
in Table 23 as follows:
14.0 mA
11.5 mA
3.0 mA
0.85 mA
<1 uA
Mode= 000 Mode= 001
Mode=010
Mode =011
Mode = 100
≥TS_OS
≥TS_BBR
≥TS_FS
≥TS_BB2
Table 23: Typical current consumption profile during the power up sequence from Standby to Receive Mode
The power up sequence from sleep to transmit mode is described in Table 24:
Transmission
Mode = 000 Mode = 001 Mode = 110
Mode =111
Mode=001
Xtal
- Sleep
- Xtal
oscillator
-
Frequency - Power Amplifier
-
synthesizer - Frequency synthesizer
oscillator
enabled
-
Xtal
-
Xtal
oscillator enabled
oscillator
enabled
enabled
≥TS_OS
≥TS_FS
≥TS_TR
Table 24: Standard power up sequence from Standby to Transmit Mode
5.4 Transmitted Data Interface
When in transmit mode (MODE[2:0] = 111), the DATAIN signal is used as input for the on-chip modulator. DATAIN
is not sampled, so the bit duration should match the bit rate setting of the receiver. Whenever XE1202A TrueRF™
are used on both sides of the communication link, the bit rate should be one of those defined in Table 4 (BR). In
this case the bit rate error should be less than 5 % compared to the specified value.
DATAIN
(NRZ)
BIT N+1
BIT N
1/BR
Figure 10: DATAIN timing
5.5 Received Data Interface
The outputs of the receiver are the two signals DATAOUT and DCLK. When the bit “RTParam_Bits” is “1”, the bit
synchronizer is turned on, and the two output signals are respectively the output NRZ bit stream and the sampling
clock. The value of DATAOUT is valid at the rising edge of DCLK (see Figure 11 on next page):
© Semtech 2006
www.semtech.com
25
XE1202A TrueRF™
DATAOUT
(NRZ)
BIT N+1
BIT N
DCLK
Figure 11: DATAOUT timing
When “RTParam_Bits” is “0”, the bit synchronizer is turned off, and the signal DATAOUT is the output of the
demodulator. In this case DCLK is not used and its value is set to “low”. The maximum current drive on DATAOUT
and DCLK is 2 mA @ 2.7 V, the maximum load is CLop.
5.6 Pattern Recognition Interface
When this feature is enabled, the incoming NRZ bit stream is compared with a pattern stored in the “Pattern”
register. The PATTERN output (active-low) is driven by the output of this comparator and is synchronized by DCK.
It is asserted when a match is detected, otherwise negated (please see Figure 12, below). Changes occur at the
rising edge of DCK.
DATAOUT
(NRZ)
BIT N=PATTERN[0]
BIT N-1=PATTERN[1]
BIT N-x=PATTERN[x]
DCLK
PATTERN
Figure 12: Pattern Recognition timing
When the feature is disabled, the PATTERN output is always negated. The maximum current drive on PATTERN is
2 mA @ 2.7 V, the maximum load is CLop.
5.7 Clock Output Interface
CLKOUT is a clock signal at 1.22, 2.44, 4.87, or 9.75 MHz, depending on user-programming. When the XE1202A
TrueRF™ is in Sleep Mode (MODE[2:0] = 000) or when “RTParam_Clkout” is low, this clock is disabled.
5.8 Default settings at power-up
Upon power-up all RTParam, FSParam, ADParam and Pattern registers are set to 00H.
At power-up, the XE1202A TrueRF™ is in Standby mode, which means that the Xtal oscillator is enabled;
additionally a clock signal at 1.22 MHz (reference frequency divided by 32) is present at CLKOUT. However,
internally, RTParam_Clkout is low, which means that if the configuration register remains unaltered, the clock
signal at CLKOUT will be disabled on the first rising edge of /EN; in addition, at the first rising edge of /EN, the
circuit will be put in the mode corresponding to the status of the signals at MODE(2:0) inputs. Thus, to keep the
circuit in Standby mode and the clock signal present on CLKOUT, RTParam_Clkout has to be set high during the
first communication through the 3-wire bus, and the MODE(0) has to be set high before the first rising edge of /EN.
© Semtech 2006
www.semtech.com
26
XE1202A TrueRF™
6 Application Information
This section provides details of the recommended component values for the frequency dependant blocks of the
XE1202A TrueRF™. Note that these values are dependent upon circuit layout and PCB structure, and that
decoupling components have been omitted for clarity.
6.1 Receiver matching network
The schematic of the matching network at the input of the receiver is given Figure 13 below (for a source
impedance of 50 Ω).
CR1
RFA
SOURCE
XE1202A
TrueRF™
LR1
CR3
RFB
CR2
VSS
Figure 13: Receiver matching network
The typical recommended values for the external components are given in Table 25:
Name
CR1
CR2
CR3
LR1
434 MHz
1.5 pF ± 5 %
1.5 pF ± 5 %
NC
868 MHz
1.2 pF ± 5 %
1.5 pF ± 5 %
NC
915 MHz
0.82 pF ± 5 %
0.82 pF ± 5 %
NC
100 nH ± 5 %
27 nH ± 5 %
27 nH ± 5 %
Table 25: External Matching Components
6.2 Transmitter matching network
The optimum load impedances for 15 dBm output power at the three main frequencies are given in Table 26:
434 MHz
66 – 5j
868 MHz
66 + 14j
915 MHz
64 + 13j
PA optimum load
Table 26: Optimum load impedance versus frequency
© Semtech 2006
www.semtech.com
27
XE1202A TrueRF™
The Smith charts in Figure 14 and Figure 15 below show curves of output power versus load impedance when the
highest output level is selected (15 dBm mode):
15 dB m 869M Hz
1
0 .9
1. 2
0 .8
1.4
1.6
1. 8
0 .5
2
0 .4
2 .4
3
0 .3
4
0 .2
5
0 .1
10
15 dBm
2 0
50
2 .4
50
2 0
10
0 .1
14 dBm
12 dBm
5
0 .2
4
0 .3
3
0 .4
2
0 .5
0 .6
1.8
1.6
1.4
1.2
0 .8
0 .9
1
Figure 14: Output power versus load impedance at 868 MHz
1 5 d B m 9 1 5 M H z
1
0.9
1.2
0 .8
1.4
1.6
1.8
0 .5
2
0 .4
2 .4
3
0.3
4
0 .2
5
0 .1
10
15 dBm
2 0
50
2 .4
50
2 0
10
14dBm
0 .1
5
0 .2
12 dBm
4
0 .3
3
0.4
2
0.5
0 .6
1.8
1.6
1. 4
1.2
0 .8
0.9
1
Figure 15: Output power versus load impedance at 915 MHz
© Semtech 2006
www.semtech.com
28
XE1202A TrueRF™
The schematic of the recommended matching network at the output of the transmitter is given in Figure 16 below.
The two Π-sections are used to provide harmonic filtering for passing FCC and ETSI regulations:
VDD
CT2
XE1202A
TrueRF™
CT3
LT3
LT2
...
Figure 16: Transmitter output network
The typical component values of this matching circuit are given Table 27 below:
Name
Typical Value Typical Value
Typical Value
for 915 MHz
Tolerance
for 434 MHz
6.8 pF
1.0 pF
22 pF
for 869 MHz
CT1
CT2
CT3
CT4
CT5
LT1
LT2
LT3
1.5 pF
1.8 pF
NC
± 5 %
± 5 %
± 5 %
± 5 %
± 5 %
± 5 %
± 5 %
± 5 %
0.56 pF
15 pF
33 pF
3.3 pF
2.2 pF
47 nH
10 nH
8.2 nH
6.8 pF
4.7 pF
33 nH
3.3 pF
2.2 pF
39 nH
22 nH
10 nH
22 nH
8.2 nH
Table 27: Matching circuit component values
6.3 VCO tank
The tank of the VCO is implemented with an inductor in parallel with an (optional) capacitor. The recommended
values for these components are given in Table 28 below:
Name
LR1
434 MHz
39 nH ± 2 %
NC
869 MHz
6.8 nH ± 2 %
NC
915 MHz
5.6 nH ± 2 %
NC
CR1
Table 28: VCO tank component values
In order to optimize the tuning range of the VCO, the value of the inductance should be as high as possible and
external capacitance must be avoided if possible. It is recommended that the PCB layout includes two ‘footprints’ in
order to place two inductances in parallel; this enables the tank of the VCO to be centered more precisely.
© Semtech 2006
www.semtech.com
29
XE1202A TrueRF™
6.4 Loop filter of the frequency synthesizer
The loop filter of the frequency synthesizer is shown in Figure 17 below:
LFB
RL1
CL2
XE1202A
TrueRF™
CL1
VSS
Figure 17: Loop filter of the frequency synthesizer
The recommended values for the external components are given in the following table:
Name
CL1
434 MHz
22 nF ± 10 %
1 nF ± 5 %
869 MHz
22 nF ± 10 %
1 nF ± 5 %
915 MHz
22 nF ± 10 %
1 nF ± 5 %
CL2
RL1
0.56 kΩ ± 5 %
0.47 kΩ ± 5 %
0.47 kΩ ± 5 %
Table 29: loop filter component values
6.5 Reference crystal for the frequency synthesizer
For narrow band applications, (lowest frequency deviation and the narrowest baseband filter), the crystal for
reference oscillator of the frequency synthesizer should have characteristics as shown in Table 30:
Name
Description
Min. value
Typ. Value
Max. value
Fs
Nominal frequency
-
39.0 MHz
-
(fundamental)
CL
Rm
Cm
C0
∆fs(0)
∆fs(∆T)
Load capacitance for fs (on-chip)
Motional resistance
Motional capacitance
-
-
-
-
-
-
8 pF (*)
-
-
-
-
-
-
40 Ω
30 fF
7 pF (*)
10 ppm
10 ppm
Shunt capacitance
Calibration tolerance at 25 °C
Stability over temperature range
(-40 °C to 85 °C)
Aging tolerance in first 5 years
-
-
5 ppm
∆fs(∆t)
Table 30: Recommended crystal characteristics
(*) The on-chip oscillator is implemented in two selectable versions: the first for CL = 8 pF and C0 = 7 pF, and the
second for CL = 8 pF and C0 = 3 pF; the latter will allow larger amplitude for the internal signal with slightly lower
power consumption.
The electrical specifications given in Section 3.2.2 are valid provided the crystal satisfies the specifications given in
Table 30.
For less demanding applications (wider signal bandwidth and/or reduced temperature range), it is possible to use a
crystal with larger values for ∆fs(0), ∆fs(∆T), and/or ∆fs(∆t). In this case fOFFSET + BWssb should be lower than
BBW, where fOFFSET is the offset (error) from the carrier frequency (the sum of ∆fs(0), ∆fs(∆T), and/or ∆fs(∆t)),
© Semtech 2006
www.semtech.com
30
XE1202A TrueRF™
BWssb is the single side-band bandwidth of the signal, and BBW is the single side-band bandwidth of the base-
band filter.
The XE1202A TrueRF™ can be used with a 3rd overtone reference crystal operating on its 3rd harmonic at 39.00
MHz. Note however that:
•
•
the oscillator start-up time is higher than in fundamental mode,
an extra 1.5 k – 16 kΩ resistor has to be placed in parallel with the crystal. In this case, the crystal should
have CL = 8 to 10 pF, Rm < 60 Ω, C0 < 7 pF.
© Semtech 2006
www.semtech.com
31
XE1202A TrueRF™
7 Packaging information
XE1202A TrueRF™ is assembled in a 44-lead LQFP package as shown in Figure 18
VSS
MODE(1)
VSS
MODE(0)
VSS
IAMP
QAMP
EN
VSSF
RFA
VDDA
XE1202A
RFB
XTB
VSSP
VSSA
VSSP
XTA
RFOUT
VSSA
VDDP
VSS
VSSP
Figure 18: Package pinning and dimensions
© Semtech 2006
www.semtech.com
32
XE1202A TrueRF™
© Semtech 2005
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no
responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation,
repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond
the specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH
PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK.
Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and
hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and
attorney fees which could arise.
Contact Information
Semtech Corporation
Wireless and Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone (805) 498-2111 Fax : (805) 498-3804
© Semtech 2006
www.semtech.com
33
相关型号：
©2020 ICPDF网 联系我们和版权申明