SX1255IWLTRT [SEMTECH]
Low Power Digital I and Q RF Multi-PHY Mode Transceiver;
| 型号： | SX1255IWLTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Low Power Digital I and Q RF Multi-PHY Mode Transceiver 电信 电信集成电路 |
| 文件： | 总43页 (文件大小：1169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SX1255
WIRELESS & SENSING PRODUCTS
SX1255 RF Front-End Transceiver
DATASHEET
Low Power Digital I and Q RF Multi-PHY Mode Transceiver
VBAT1
VBAT2 VR_ANA1 VR_ANA2 VR_DIG
0 to −30dB with 2dB steps
0 to −48dB with 6dB steps
CT ΣΔ
Rx pre−filter
Power Distribution System
1b
RFIN
Rx pre−filter
CT ΣΔ
I_RX
1b
RX
PLL
I_OUT
Q_OUT
I_IN
DIV 4
DIV 4
2
2
N
32
32
2
Fractional frequency
synthesizer
Q_RX
Digital Bridge
ΣΔ
I2S
N
32
32
TX
Q_IN
PLL
2
ATT
Fractional frequency
synthesizer
Gain DAC
DIO(2)
DIO(3)
DIO(1)
DIO(0)
5b
1b
RFOUT_P
RFOUT_M
Tx Filter
FIR−DAC
I_TX
Driver
1b
Tx Filter
FIR−DAC
Q_TX
balun
Registers and interface
XOSC
CLK select
XTA XTB
CLK IN CLK OUT
NSS MOSI MISO SCK RESET
GENERAL DESCRIPTION
KEY PRODUCT FEATURES
The SX1255 is a highly integrated RF front-end to digital I
and Q modulator/demodulator Multi-PHY mode transceiver
capable of supporting multiple constant and non-constant
envelope modulation schemes. It is designed to operate
over the 400 - 510 MHz worldwide licensed and unlicensed
frequency bands. Its highly integrated architecture allows
for a minimum of external components whilst maintaining
maximum design flexibility. All major RF communication
parameters are programmable and most of them can be
dynamically set. The SX1255 offers support for both
narrow-band and wide-band communication modes without
the need to modify external components. The SX1255 is
Fully flexible I and Q modulator and demodulator
Half or full-duplex operation
Bullet proof RX LNA
Analog TX and RX pre-filtering
2
Decimated I&Q signal under I S industry format
Programmable tap TX FIR-DAC filter
Linear TX amplifier for both constant and non-constant
envelope modulation schemes
optimized for low power consumption while offering the ORDERING INFORMATION
provision for high RF output power and channelized
operation. TrueRF™ technology enables
external component count whilst still satisfying ETSI, FCC
and ARIB and other regulations.
a low-cost
Part Number
SX1255IWLTRT
SX1255WS
Temperature Range
-40; +85 C
Qty. per Reel
3000
Package
MLPQW-32
-
-40; +85 C
1 Wafer
APPLICATIONS
Pb-free, Halogen Free
RoHS / WEEE compliant product
IEEE 802.15.4g SUN Multi-PHY Mode Smartgrid
Cognitive / Software Defined Radio (SDR)
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
TABLE OF CONTENT
DATASHEET
1.
General Description ................................................................................................................................................ 6
1.1.
Simplified Block Diagram ............................................................................................................................... 6
Pin and Marking Diagram................................................................................................................................ 7
Pin Description................................................................................................................................................ 8
1.2.
1.3.
2.
Electrical Characteristics......................................................................................................................................... 9
2.1.
ESD Notice...................................................................................................................................................... 9
Absolute Maximum Ratings ............................................................................................................................ 9
Operating Range............................................................................................................................................. 9
Electrical Specifications ................................................................................................................................ 10
2.2.
2.3.
2.4.
2.4.1. Power Consumption............................................................................................................................... 10
2.4.2. Frequency Synthesis.............................................................................................................................. 10
2.4.3. Transmitter Front-End............................................................................................................................ 11
2.4.4. Receiver Front-End................................................................................................................................ 11
2.4.5. SPI Bus Digital Specification.................................................................................................................. 12
Chip Description.................................................................................................................................................... 13
3.
3.1.
Power Supply Strategy.................................................................................................................................. 13
Low Battery Detector..................................................................................................................................... 13
Frequency Synthesizer ................................................................................................................................. 13
3.2.
3.3.
3.3.1. Reference Oscillator............................................................................................................................... 13
3.3.2. CLK_OUT Output................................................................................................................................... 14
3.3.3. PLL Architecture..................................................................................................................................... 14
3.3.3.1. VCO................................................................................................................................................... 14
3.3.3.2. PLL Bandwidth .................................................................................................................................. 14
3.3.3.3. Carrier Frequency and Resolution .................................................................................................... 14
3.3.3.4. PLL Lock Time .................................................................................................................................. 15
3.3.3.5. Lock Detect Indicator......................................................................................................................... 15
3.4.
Transmitter Analog Front-End Description.................................................................................................... 15
3.4.1. Architectural Description ........................................................................................................................ 15
3.4.2. TX I / Q Channel Filters.......................................................................................................................... 15
3.4.3. TX I / Q Up-Conversion Mixers .............................................................................................................. 16
3.4.4. RF Amplifier ........................................................................................................................................... 16
3.5.
Transmitter Digital Baseband Description..................................................................................................... 17
3.5.1. Digital-to-Analog Converters.................................................................................................................. 17
3.6. Receiver Analog Front-End Description ............................................................................................................19
3.6.1. Architectural Description ........................................................................................................................ 19
3.6.2. LNA and Single to Differential Buffer ..................................................................................................... 19
3.6.3. I /Q Downconversion Quadrature Mixer................................................................................................. 19
3.6.4. Baseband Analog Filters and Amplifiers ................................................................................................ 19
3.7.
Receiver Digital Baseband............................................................................................................................ 20
3.7.1. Architectural Block Diagram................................................................................................................... 20
3.7.2. Analog-to-Digital Converters.................................................................................................................. 20
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
DATASHEET
3.7.3. Temperature Sensor .............................................................................................................................. 20
3.8.
Loop-Back.................................................................................................................................................... 21
3.8.1. Digital Loop-Back................................................................................................................................... 21
3.8.2. RF Loop Back ............................................................................................................................................22
Digital Interface..................................................................................................................................................... 23
4.
4.1.
General overview .......................................................................................................................................... 23
Definition and operation of the SPI interface................................................................................................. 23
Digital IO Pin Mapping .................................................................................................................................. 24
I and Q interface............................................................................................................................................ 24
4.2.
4.3.
4.4.
4.4.1. General description................................................................................................................................ 24
4.4.2. Mode A................................................................................................................................................... 25
4.4.3. Mode B................................................................................................................................................... 26
4.4.3.1. Introduction........................................................................................................................................ 26
4.4.3.2. Parameters........................................................................................................................................ 29
Configuration and Status Registers ...................................................................................................................... 33
5.
6.
5.1.
General Description ...................................................................................................................................... 33
Application Information ......................................................................................................................................... 37
6.1.
6.2.
Crystal Resonator Specification.................................................................................................................... 37
Reset of the Chip .......................................................................................................................................... 37
6.2.1. POR ....................................................................................................................................................... 37
6.2.2. Manual Reset......................................................................................................................................... 38
6.3.
6.4.
TX Noise Shaper........................................................................................................................................... 38
Reference Design ......................................................................................................................................... 39
7.
8.
Packaging Information .......................................................................................................................................... 40
7.1.
Package Outline Drawing.............................................................................................................................. 40
Recommended Land Pattern ........................................................................................................................ 40
Thermal Impedance ...................................................................................................................................... 41
Tape and Reel Specification ......................................................................................................................... 41
7.2.
7.3.
7.4.
Revision History.................................................................................................................................................... 42
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
FIGURES
DATASHEET
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Block Diagram ..................................................................................................................................... 6
Pin Diagram ......................................................................................................................................... 7
Marking Diagram ................................................................................................................................. 7
TCXO Connection .............................................................................................................................. 13
SX1255 Transmitter Analog Front-End Block Diagram ..................................................................... 15
FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 32 ....................................... 17
FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 64 ....................................... 18
SX1255 Receiver Analog Front-End Block Diagram ......................................................................... 19
SX1255 Digital Receiver Baseband Block Diagram .......................................................................... 20
Temperature Sensor Response ........................................................................................................ 21
Digital and RF Loop-Back Paths ....................................................................................................... 22
SPI Timing Diagram (single access) .................................................................................................. 23
Tx timing diagram of I and Q interface in mode A (SX1255 master) ................................................. 25
Tx timing diagram of I and Q interface in mode A (SX1255 slave) .................................................... 26
The I2S interface block in its context (mux cells are included in PAD_CTL block) ........................... 27
Timing diagram of I and Q interfaces in mode B1 ............................................................................. 28
Timing diagram of I and Q interfaces in mode B2 ............................................................................. 29
POR Timing Diagram ......................................................................................................................... 37
Manual Reset Timing Diagram .......................................................................................................... 38
Example Digital Modulator Implementation ....................................................................................... 38
SX1255 Application Schematic .......................................................................................................... 39
Package Outline Drawing .................................................................................................................. 40
Recommended Land Pattern ............................................................................................................ 40
Tape and Reel Specification .............................................................................................................. 41
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
TABLES
DATASHEET
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
SX1255 Pinout ..................................................................................................................................... 8
Absolute Maximum Ratings ................................................................................................................. 9
Operating Ranges ............................................................................................................................... 9
Power Consumption Specification ..................................................................................................... 10
Frequency Synthesizer Specification ................................................................................................ 10
TX Front-End Specifications .............................................................................................................. 11
RX Front-End Specification ............................................................................................................... 11
SPI Digital Specification .................................................................................................................... 12
TX Analog Filter Single Sideband Bandwidth .................................................................................... 16
TX DAC Single Sideband Bandwidth ................................................................................................ 17
DIO Mapping ..................................................................................................................................... 24
Mapping of IO pins related to the I and Q transfer ............................................................................. 25
Sampling rates 1st set ....................................................................................................................... 30
Sampling rates 2nd set ...................................................................................................................... 30
Number of bits per sample for the 1st set and B1 mode ................................................................... 30
Number of bits per sample for the 2nd set and B1 mode .................................................................. 31
Number of bits per sample for the 2nd set and B2 mode .................................................................. 32
Number of bits per sample for the 1st set and B2 mode ................................................................... 32
Crystal Resonator Specification ........................................................................................................ 37
Datasheet Revision History ............................................................................................................... 42
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
1. General Description
DATASHEET
The SX1255 is a single-chip Zero-IF RF-to-digital front-end transceiver integrated circuit ideally suited for today's high
performance multi-PHY mode or SDR ISM band RF applications. The SX1255 has a maximum signal bandwidth of 500
kHz in both transmission and reception and is intended as a high performance, low-cost RF-to-digital converter and
provides a generic RF front-end that allows several constant and non-constant envelope modulation schemes to be
handled, such as the MR-FSK, MR-OFDM and MR-O-QPSK applications in the 400 - 510 MHz licensed and unlicensed
frequency bands.
The SX1255's advanced features set greatly simplifies system design whilst the high level of integration reduces the
external BOM to an optional RF power amplifier, and a handful of passive decoupling and matching components. A simple
4-wire 1-bit digital serial or I2S like interface are provided for the baseband I and Q data streams to the baseband
processor.
The SX1255 can operate in both half and full-duplex mode and is compliant with ETSI, FCC and ARIB regulatory
requirements. It is available in a MLPQ-W 5 x 5 mm 32 lead package.
1.1. Simplified Block Diagram
VBAT1
VBAT2 VR_ANA1 VR_ANA2 VR_DIG
Power Distribution System
0 to −30dB with 2dB steps
0 to −48dB with 6dB steps
CT ΣΔ
CT ΣΔ
Rx pre−filter
Rx pre−filter
1b
RFIN
I_RX
1b
RX
PLL
I_OUT
Q_OUT
I_IN
DIV 4
DIV 4
2
N
32
32
2
Fractional frequency
synthesizer
Q_RX
Digital Bridge
I2S
ΣΔ
N
32
32
2
TX
Q_IN
PLL
2
ATT
Fractional frequency
synthesizer
Gain DAC
DIO(2)
DIO(3)
DIO(1)
DIO(0)
5b
1b
RFOUT_P
RFOUT_M
Tx Filter
FIR−DAC
I_TX
Driver
1b
Tx Filter
FIR−DAC
Q_TX
balun
Registers and interface
XOSC
CLK select
XTA XTB
CLK IN CLK OUT
NSS MOSI MISO SCK RESET
Figure 1. Block Diagram
SX1255 - Rev. 3.0
October 2013 ©2013 Semtech Corporation
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SX1255
WIRELESS & SENSING PRODUCTS
1.2. Pin and Marking Diagram
DATASHEET
The following diagrams illustrate the pin arrangement of the MLPQ-W package (top view) and the IC marking description.
Figure 2. Pin Diagram
Figure 3. Marking Diagram
Note: yyww refers to the date code xxxxxx refers to the lot number
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
1.3. Pin Description
DATASHEET
Table 1
SX1255 Pinout
Number
Name
Ground
VR_PA
VBAT1
VR_ANA1
GND
Type
Description
0
1
2
3
4
5
6
7
8
9
-
-
Exposed ground pad
Regulated supply for TX amplifier
VBAT Supply voltage
Regulated supply for analog TX circuit
Ground
-
-
-
VR_DIG
XTA
-
Regulated supply for digital circuit
Crystal pad
I/O
-
GND
Ground
XTB
I/O
I/O
O
I
Crystal pad / input for external clock
Reset
Reset
CLK_OUT
CLK_IN
Q_IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
36 MHz digital clock output
36 MHz digital clock input (SX1255 used in slave TX mode)
Digital baseband data input for I (inphase) channel DAC
Digital baseband data input for Q (quadrature) channel DAC
Digital baseband data output from I (inphase) channel ADC
Digital baseband data output from Q (quadrature) channel ADC
VBAT supply voltage
I
I_IN
I
Q_OUT
I_OUT
VBAT2
SCK
O
O
-
I
SPI clock
MISO
O
I
Master In Slave Output SPI output
Master Out Slave Input SPI input
SPI chip select
MOSI
NSS
I
DIO0
O
O
O
O
-
Digital I/O, software configured
Digital I/O, software configured
Digital I/O, software configured
Digital I/O, software configured
Regulated supply for analog RX circuit
Ground
DIO1
DIO2
DIO3
VR_ANA2
GND
-
RF_IN
GND
I
RX LNA input
-
Ground
RF_ON
RF_OP
GND
O
O
-
Differential TX Output, negative node
Differential TX Output, positive node
Ground
VBAT3
-
VBAT supply for TX amplifier
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
2. Electrical Characteristics
DATASHEET
2.1. ESD Notice
The SX1255 is a high performance radio frequency device.
Class 2 of the JEDEC standard JESD22-A114-C (Human Body Model) on all pins
Class III of the JEDEC standard JESD22-C101-C (Charged Device Model) on all pins
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 2
Absolute Maximum Ratings
Symbol
Description
Maximum Supply Voltage
Maximum Temperature
Min
-0.5
-55
-
Max
3.9
Units
V
VDDmr
Tmr
Tj
115
125
+6
°C
Maximum Junction Temperature
Maximum RF Input Level
°C
Pmr
-
dBm
2.3. Operating Range
Operating ranges define the limits for functional operation and parametric characteristics of the device as described in this
section. Functionality outside these limits is not implied.
Table 3
Operating Ranges
Symbol
Description
Min
2.7
-40
-
Max
3.6
+85
25
Units
V
VDDop
Top
Operational Supply Voltage
Operational Temperature
Load Capacitance on Digital Ports
RF Input Level
°C
Clop
ML
pF
-
0
dBm
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
DATASHEET
2.4. Electrical Specifications
The table below gives the electrical specifications of the transceiver under the following conditions:
supply Voltage = 3.3 V, temperature = 25 °C, f
= 36 MHz, f = 434 MHz, Output power = -5 dBm (100 ohm differential
RF
XOSC
transmission), TXBWANA = 250 kHz, RXBWANA = 250 kHz, mode A, external baseband RX filter = 150 kHz, unless
otherwise specified.
Note: RF performance depends on assembly. Electrical specifications listed below are obtained with the QFN package
described in section 7 “Packaging Information”.
2.4.1. Power Consumption
Table 4
Power Consumption Specification
Symbol
Description
Conditions
Min
Typ
0.2
1.15
18
Max
1
Units
uA
IDDSL
Supply Current in Sleep Mode
-
-
-
-
IDDST
IDDRX
IDDTX
Supply Current in Standby Mode
Supply Current in Receive Mode
Supply Current in Transmit Mode
Crystal oscillator enabled
1.5
25
mA
mA
RFOutput Power = -5 dBm
60
90
mA
2.4.2. Frequency Synthesis
Table 5
Frequency Synthesizer Specification
Symbol
Description
Conditions
Min
400
32
-
Typ
-
Max
510
Units
MHz
MHz
us
FR
Synthesizer Frequency Range
Programmable
FXOSC
TS_OS
TS_FS
Crystal Oscillator Frequency
See Section 5
36
36.864
500
Crystal Oscillator Wake-up Time
From sleep mode
Crystal Oscillator Enabled
300
50
RX Frequency Synthesizer
Wake-up Time
-
150
us
FSTEP = FXOSC / 220
FSTEP
Frequency Synthesizer Step Size
30.5
34.3
35.16
Hz
TS_HOP_RX
RX Frequency Synthesizer Hop Time
(to within 10 kHz of target frequency)
200 kHz step
-
-
-
-
20
20
30
50
-
-
-
-
us
us
us
us
400 kHz step
1.2 MHz step
25 MHz step
RX Frequency Synthesizer Hop Time
(to within 10 kHz of target frequency)
TS_HOP_TX
200 kHz step
400 kHz step
1.2 MHz step
25 MHz step
-
-
-
-
20
20
30
50
-
-
-
-
us
us
us
us
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
DATASHEET
2.4.3. Transmitter Front-End
Table 6
TX Front-End Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
FCLK_IN
External Clock Frequency for TX
Synthesizer or DAC input clock
SX1255 slave mode
32
-
36.864
MHz
TS_TR
TXPmax
TXP1dB
TXOIP3
PHN
Transmitter Wake-up Time
TX Maximum Output Power
TX 1 dB Compression Point
TX Output IP3
Frequency synthesizer enabled
Saturated Power
-
120
+7
-
-
-
-
us
+4
+2
+13
dBm
dBm
dBm
Peak Value
+5
-5 dBm average output power
+16
Transmitter Phase Noise
10 kHz offset from carrier
100 kHz offset from carrier
1 MHz offset from carrier
-
-
-
-110
-108
-128
-
-
-
dBc/Hz
dBc/Hz
dBc/Hz
PHNF
Transmitter Output Noise Floor
10 MHz offset from carrier
-128
-
-135
0.2
-
dBc/Hz
°RMS
PHNID
Transmitter Integrated DSB Phase
Noise
Integrated bandwidth from
500 Hz to 125 kHz
1.5
TXGM
Transmitter IQ Gain Mismatch
Transmitter IQ Phase Mismatch
-
-
0.5
1
3
dB
°
TXPM
1
-
TXBWANA
Transmitter Analog Prefilter BW (DSB) Programmable in 31 steps
420
-30
1700
+30
kHz
%
TXBWANAPrc Transmitter Analog Prefilter BW
precision
-
TXBWDIFG
TXLO
Transmitter FIR-DAC Taps
Programmable
24
-
-
64
-
-
TX LO Leakage (Before DC offset
Calibration)
ADC rms input: -10 dBFS
-8
dBc
TXEVM
Transmitter Error Vector Magnitude
tbd
dB
2.4.4. Receiver Front-End
Table 7
RX Front-End Specification
Symbol
FCLK_IN
CLK_INJ
RXNF
Description
Conditions
Min
32
-
Typ
Max
36.864
0.01
Units
MHz
%
External Clock Frequency for RX ADC SX1255 slave mode
-
-
External Clock Jitter Specification
Receiver Noise Figure
External clock. White noise
Maximum LNA Gain
Maximum LNA Gain -6dB
Minimum LNA Gain
-
-
-
4.5
6.5
38
7
9
40
dB
RXGR
IIP3
RX Gain Range
Adjustable in 2 dB steps
-
70
-
dB
rd Order Input Intercept Point
Maximum LNA Gain
Maximum LNA Gain -6dB
Minimum LNA Gain
-28
-21
+10
-23
-16
+20
-
-
-
3
dBm
Unwanted tones are 2 MHz and 3.8
MHz above the LO
SX1255 - Rev. 3.0
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WIRELESS & SENSING PRODUCTS
DATASHEET
Table 7
RX Front-End Specification
Symbol
RXGM
Description
Conditions
Min
Typ
0.5
0.5
-
Max
Units
dB
Receiver IQ Gain Mismatch
Receiver IQ Phase Mismatch
Receiver Analog Prefilter BW (SSB)
Receiver Wake-up Time
-
1
RXPM
-
500
-
3
1500
-
°
RXBWANA
TS_RE
Programmable
kHz
ms
Frequency synthesizer enabled
tbd
2.4.5. SPI Bus Digital Specification
Table 8
SPI Digital Specification
Symbol
VIH
Description
Conditions
Min
0.8
-
Typ
Max
Units
VDD
VDD
VDD
VDD
MHz
ns
Digital Input High Level
Digital Input Low Level
Digital Output High Level
Digital Output Low Level
SCK Frequency
-
-
-
VIL
0.2
VOH
VOL
FSCK
tch
Imax = 1 mA
Imax = -1 mA
0.9
-
-
-
0.1
10
-
-
-
-
SCK High Time
50
50
-
-
tcl
SCK Low Time
-
-
ns
trise
SCK Rise Time
5
5
-
-
ns
tfall
SCK Fall Time
-
-
ns
tsetup
MOSI Set-up Time
From MOSI change to SCK
rising edge
30
-
ns
thold
MOSI Hold Time
NSS Set-up Time
NSS Hold Time
From SCK rising edge to MOSI
change
60
30
-
-
-
-
-
-
ns
ns
ns
tnsetup
From NSS falling edge to SCK
rising edge
tnhold
From SCK falling edge to NSS
rising edge
100
tnhigh
tdata
NSS High Time Between SPI Access
Data Hold and Set-up Time
20
-
-
-
-
ns
ns
250
SX1255 - Rev. 3.0
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DATASHEET
3. Chip Description
This section describes the architecture of the SX1255 Multi-PHY mode transceiver.
3.1. Power Supply Strategy
The SX1255 employs an advanced power distribution scheme (PDS), which provides stable operating characteristics over
the full temperature and voltage range of operation.
The SX1255 can be powered from any low-noise voltage source via pins VBAT1, VBAT2 and VBAT3. Decoupling
capacitors should be connected, as suggested in the reference design, on VR_PA, VR_DIG, VR_ANA1 and VR_ANA2 pins
to ensure a correct operation of the built-in voltage regulators.
3.2. Low Battery Detector
A low battery detector is also included allowing the generation of an interrupt signal in response to passing a
programmable threshold adjustable through the register RegLowBat. The interrupt signal can be mapped to the DIO0 pin,
through the programmation of RegDioMapping.
3.3. Frequency Synthesizer
The SX1255 incorporates two separate state of the art fractional-N PLLs for the TX and RX circuit blocks
3.3.1. Reference Oscillator
The crystal oscillator is the main timing reference of the SX1255. It provides the reference source for the transmit and
receive frequency synthesizers and as a clock for digital processing.
The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the built-
in sequencer, the SX1255 optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To
manually control the startup time, the user should monitor the signal CLK_OUT which will only be made available on the
output buffer when a stable XO oscillation is achieved.
An external crystal controlled source, such as a clipped-sinewave TCXO, clock can be used to replace the crystal
oscillator, This external source should be provided on XTB (pin 8) and XTA (pin 6) should be left open, as illustrated in
Figure 4, below.
XTA
GND
XTB
VCC
OP
VCC
GND
CD
Figure 4. TCXO Connection
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The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an
appropriate value of decoupling capacitor, CD. Due to the low jitter requirements required by the receiver digital block it is
recommended that only a crystal controlled external frequency source is used.
3.3.2. CLK_OUT Output
For master mode operation the SX1255 provides a system clock output made available at pin CLK_OUT.
3.3.3. PLL Architecture
The SX1255 incorporates two fourth-order type fractional-N sigma-delta PLLs. The PLLs include integrated VCO and
programmable bandwidth loop filter, removing the need for any external components. The PLLs are autocalibrating and are
capable of fast switching and settling times.
3.3.3.1. VCO
Both TX and RX VCOs operate at twice the RF frequency, with the oscillators centered at 1.9 GHz. This reduces any LO
leakage in receive mode, to improve the quadrature precision of the receiver, and to reduce the pulling effects on the VCO
during transmission.
The VCO calibration is fully automated, calibration times are fully transparent to the end-user as the processing time is
included in the TS_TR and TS_RE specifications.
3.3.3.2. PLL Bandwidth
The bandwidth of the PLL loop filters are independently configurable via the configuration registers TxPllBw and RxPllBw
for the modulation schemes supported, as well as fast channel switching and lock times to support FHSS and frequency
agile applications, such as AFA.
3.3.3.3. Carrier Frequency and Resolution
Both the TX and RX embed a 20-bit sigma-delta modulator and the frequency resolution, constant over the entire
frequency range, is calculated using the following formula:
FXOSC
----------------
220
FSTEP
=
The RX and RX carrier frequencies are programmed through registers RegFrfRx and RegFrfTx, split across register
addresses 0x01 to 0x03 and 0x04 to 0x06, respectively, and are calculated by:
FRF = FSTEP × Frfxx(23, 0)
where: Frfxx is the integer value of the RegFrfRx or RegFrfTx as defined above.
Note: As stated above, the Frfxx settings are split across 3 bytes for both the transmitter and receiver frequency
synthesizers. A change in the center frequency will only be taken into account when the least significant byte FrfxxLsb in
RegFrfxxLsb is written and when exiting SLEEP mode
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3.3.3.4. PLL Lock Time
RX and TX PLL lock times are a function of a number of technical factors, such as synthesized frequency, frequency step,
etc. The SX1255 includes an auto-sequencer that manages the start-up sequence of the PLL.
3.3.3.5. Lock Detect Indicator
A lock indication signal for both RX and TX PLLs can be accessed via DIO pins, and is toggled high when the PLL reaches
its locking range. Please refer to Figure 11 to map this interrupt to the desired DIO pins.
3.4. Transmitter Analog Front-End Description
The analog front-end of the SX1255 transmitter stage comprises the TX frequency synthesizer, I and Q channel filters, the
I / Q mixer and RF amplifier blocks.
3.4.1. Architectural Description
The block diagram of the transmitter front-end block is illustrated below.
TX Fractional-N
Frequency Synthesizer
RF Loop-Back
(To RX)
Div by 4
Differential
I-Channel Filter
I-Channel
DAC
RF_OP
Differential
Driver
I / Q
Mixer
RF_ON
Q-Channel
DAC
Differential
Q-Channel Filter
Figure 5. SX1255 Transmitter Analog Front-End Block Diagram
3.4.2. TX I / Q Channel Filters
Differential analog I and Q signals input to the TX Front-End from the TX FIR DAC are filtered by I and Q channel filters.
These filters smooth the reconstructed analog waveforms and remove quantization noise generated by the I and Q
channel TX FIR DACs. The filters are unity gain third-order low pass Butterworth types with programmable bandwidth
configured via TxAnaBw.
The 3 dB BW of the analog TX filter BW can be calculated from:
17.15
------------------------------------------------------------------
=
BW3dB
(41 – RegTxBwAna(4, 0))
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The analog filter bandwidth should be set to greater than the signal bandwidth so as to reduce any group delay variations.
The range of programmable TX analog filter bandwidths is tabulated below in Table 9.
Table 9 TX Analog Filter Single Sideband Bandwidth
TxAnaBw
(Dec)
TxAnaBw
(Bin)
SSB Filter
BW
TxAnaBw
(Dec)
TxAnaBw
(Bin)
SSB Filter
BW
(kHz)
(kHz)
0
1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
209
214
220
226
232
238
245
252
260
268
277
286
296
306
318
330
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
343
357
373
390
408
429
451
476
504
536
572
613
660
715
780
858
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3.4.3. TX I / Q Up-Conversion Mixers
The TX I / Q mixer block mixes the baseband analog I and Q signals with that from the PLL frequency synthesizer and up
converts to the RF carrier frequency. The mixer block includes a highly linear I/ Q mixer stage with programmable gain
configurable via configuration register RegTxGain. The modulated RF signal is input to the TX RF amplifier stage.
3.4.4. RF Amplifier
The TX amplifier receives the input signal from the TX mixer and provides two differential outputs. The first output provides
the RF_OP and RF_ON signals in TX mode. The second output is used to provide an internal differential signal to the
receiver during RX gain calibration. The amplifier provides good linear performance required to meet the peak to average
power level variation of OFDM.
The peak output power is +5 dBm, which allows for an average output power of greater than -5 dBm with 10 dB back-off.
The Output signal is intended to be amplified through a suitable external RF power amplifier to the maximum permissible
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level allowed by relevant regulatory standards. The optimum load impedance presented RF amplifier is 100 ohms
differential.
3.5. Transmitter Digital Baseband Description
The transmitter digital baseband section contains separate I and Q channel digital-to-analog convertors.
3.5.1. Digital-to-Analog Converters
The TX DAC is the first block of the SX1255 transmitter. It accepts the 1-bit I and Q noise shaped 32 to 36 Msample/
second or I2S datastream from the baseand processor and converts into two analog differential signals. Each TX DAC
provides 8-bits of resolution in a 500 kHz bandwidth which corresponds to maximum RF transmitted double sideband
bandwidth of 1 MHz.
A programmable Finite Impulse Response (FIR) filter allows the removal of the digital modulator noise from the external
baseband processor. The number of taps implemented by the FIR-DAC and subsequent single-side DAC bandwidth is
controlled by the parameter TxDacBw.
Table 10 TX DAC Single Sideband Bandwidth
TxDacBw (Dec) TxDacBw (Bin)
No. DAC-FIR Taps
SSB Filter BW (kHz)
0
1
2
3
4
5
000
001
010
011
100
101
24
32
40
48
56
64
450
290
Examples of the FIR DAC normalized magnitude response are illustrated below.
Figure 6. FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 32
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Figure 7. FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 64
The DAC 3dB bandwidth is proportional to the sampling frequency fs and inversely proportional to the number of taps N. In
the case where f = 32MHz with N = 32 the 3 dB bandwidth is typically 450 kHz. Reducing the bandwidth may be useful to
S
reduce the quantisation noise contribution when the signal bandwidth request is lower, as is illustrated in the case where N
= 64, resulting in a 3 dB bandwidth of approximately 290 kHz.
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3.6. Receiver Analog Front-End Description
The SX1255 Receiver Front-End is based upon a Zero-IF architecture, ideally suited to handle multiple complex
modulation schemes. The RX chain incorporates a programmable gain LNA and single to differential buffer, I / Q mixer,
separate I and Q channel analog low-pass filters and programmable baseband amplifiers. The amplified differential analog
I and Q outputs are input to two 5th order continuous-time Sigma-Delta Analog to Digital Converters (ADC) for further
signal processing in the digital domain.
3.6.1. Architectural Description
The block diagram of the receiver front-end block is illustrated below.
I-Channel
Baseband
Amplifier
I-Channel
Pre-Filter
Singleto
Differential
Balun
LNA
I-Channel
CT ΣΔ
ADC
RF_IN
Differential
I / Q
Mixer
Q-Channel
CT ΣΔ
ADC
Q-Channel
Pre-Filter
Q-Channel
Baseband
Amplifier
RFLoop-
Back
(From TX)
Divby4
TXFractional-N
FrequencySynthesizer
Figure 8. SX1255 Receiver Analog Front-End Block Diagram
3.6.2. LNA and Single to Differential Buffer
The LNA uses a common-gate topology, which allows for a flat characteristic over the whole frequency range. It is
designed to have an input impedance of 50 Ohms or 200 Ohms (as selected with bit LnaZin in RegRxAnaGain). A single to
differential buffer is implemented to improve the second order linearity of the receiver.
The LNA gain, including the single-to-differential buffer, is programmable over a 48 dB dynamic range, and gain control can
be enabled via an external AGC function.
3.6.3. I /Q Downconversion Quadrature Mixer
The mixer is inserted between output of the RF buffer stage and the input of the I and Q channel analog low-pass filter
stages.This block is designed to downconvert the spectrum of the input RF signal to base-band and offers both high IIP2
and IIP3 responses.
3.6.4. Baseband Analog Filters and Amplifiers
The differential I and Q baseband mixer signals are pre-filtered by a programmable 1st order low-pass pre-filter and input
to programmable linear baseband amplifiers. The single sideband 3 dB bandwidth of the pre-filters can be programmed
between 500 kHz and 1500 kHz. This additional pre-filtering improves the selectivity of the receiver for complex modulation
schemes, such as OFDM.
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The amplifier stage gain offers 32 dB of programmable gain, in 2 dB steps, from -24 dB to +6 dB via configuration register
RegRxAnaGain while the analog filter bandwidth is programmed via the two least significant bits of configuration register
RegRxBw.
3.7. Receiver Digital Baseband
The receiver digital baseband section contains separate I and Q channel continuous time Sigma-Delta analog-to-digital
converters to digitize and filter the analog bit stream.
3.7.1. Architectural Block Diagram
The block diagram of the receiver digital baseband is illustrated below.
I-Channel
Baseband
Amplifier
I(t) 1-bit
serial stream
I-Channel
CT ΣΔ
ADC
Q(t) 1-bit
serial stream
Q-Channel
CT ΣΔ
ADC
SX1255
LOGIC
DSP
Q-Channel
Baseband
Amplifier
CLK_IN
or
CLK_OUT
DSP
INTERFACE
Figure 9. SX1255 Digital Receiver Baseband Block Diagram
3.7.2. Analog-to-Digital Converters
The receiver digital baseband consists of separate I and Q channel 5th order continuous-time sigma-delta modulator
analog -to-digital converters which sample and digitize the analog baseband I and Q signals output at the analog baseband
amplifiers.
The ADC output allows for 13-bits of resolution after decimation and filtering by the external baseband processor within a
500 kHz maximum bandwidth, corresponding to a maximum RF received double sideband bandwidth of 1 MHz.
The ADC output is one bit per channel quadrature bit stream at 32 to 36 MSamples/s or I2S data-stream.
3.7.3. Temperature Sensor
The receiver ADC can be used to perform a temperature measurement by digitizing the sensor response. The response of
the sensor is -1C / Lsb. Since a CMOS temperature sensor is not accurate by nature, the sensor should be calibrated at
ambient temperature for a precise reading.
It takes less than 100 us for the SX1255 to evaluate the temperature (from setting RxAdcTemp = “1”). The AdcTemp value
can be read at Q_OUT. Since there is no on-chip decimation or averaging it is recommended that data on Q_OUT is
externally processed, for example using a simple FFT.
The temperature measurement should be performed with the SX1255 in StandbyEnable Mode (RegMode = 0x01).
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RxAdcTemp
-1°C/Lsb
RxAdcTemp(t)
RxAdcTemp(t-1)
Returns 150d (typ.)
Needs calibration
t t+1
Ambient
-40°C
+85°C
Figure 10. Temperature Sensor Response
3.8. Loop-Back
The SX1255 provides mechanisms to both monitor and externally calibrate both the RF transmission path and the I and Q
bit streams generated by the external baseband processor.
3.8.1. Digital Loop-Back
The digital loop-back enables the connection of the input and output I and Q baseband bit streams prior to processing by
the SX1255.
This loop back path enables the validation of the transmitter and receiver baseband processing paths.
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3.8.2. RF Loop Back
The RF loop-back path connects the balanced RF output signal of the transmitter driver stage to the output of the
differential mixer of the receiver. This path provides a mechanism for the external baseband processor to implement a
calibration for the following:
- Receiver I, Q gain mismatch
- Receiver I and Q phase imbalance
- Transmitter I, Q gain mismatch
- Transmitter I and Q phase imbalance
- Transmitter DC offset
Figure 11. Digital and RF Loop-Back Paths
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4. Digital Interface
4.1. General overview
The SX1255 has several operating modes, configuration parameters and internal status indicators. All these operating
modes, configuration parameters and status information are stored in internal registers that may be accessed by the
external micro-controller via the serial SPI interface.
4.2. Definition and operation of the SPI interface
The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL
= 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented.
Three access modes to the registers are provided:
SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and
a read byte is received for the read access. The NSS pin goes low at the begin of the frame and goes high after the data
byte.
BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally
between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the
beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.
Figure 12 below shows a typical SPI single access to a register.
Figure 12. SPI Timing Diagram (single access)
MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the
rising edge of SCK. MISO is generated by the slave on the falling edge of SCK.
A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high.
The first byte is the address byte. It is made of:
wnr bit, which is 1 for write access and 0 for read access
7 bits of address, MSB first
The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on
MISO in case of read access. The data byte is transmitted MSB first.
Succeeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without rising NSS and
re-sending the address. The address is then automatically incremented at each new byte received (BURST mode).
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The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is
actually a special case of BURST mode with only 1 data byte transferred.
During the write accesses, the byte transferred from the slave to the master on the MISO line is the value of the written
register before the write operation.
4.3. Digital IO Pin Mapping
Four general purpose IO pins are available on the SX1255 and their configuration is controlled through the
RegDioMapping configuration register.
Mode
Diox
DIO3
DIO2
DIO1
DIO0
Mapping
Sleep
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Standby
-
xosc_ready
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RX
pll_lock_rx
-
pll_lock_rx
-
-
pll_lock_rx
-
-
pll_lock_rx
-
-
Low Bat
TX
pll_lock_tx
pll_lock_tx
-
-
-
-
-
-
-
-
-
-
Table 11 DIO Mapping
4.4. I and Q interface
4.4.1. General description
There are two main ways of transferring the I and Q signals between the SX1255 and the external digital circuit.
In mode A, the I and Q signals are directly the outputs of the sigma-delta modulator in Rx, and the inputs of the FIR-DAC in
Tx. This mode is the one which is implemented in the SX1255 circuit.
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In mode B, the I and Q signals are pre- and post-processed by the internal digital bridge. In Rx the I and Q signals are
decimated inside the chip and in Tx the I and Q signals are interpolated and ΣΔ modulated internally. In this mode the
signals are transferred via an I2S-like protocol working in two possible configurations.
The table below gives the mapping of the pins as a function of the selected mode.
Pins
10) CLK_OUT
11) CLK_IN
12) Q_IN
Mode A
CLK_OUT
Mode B1
CLK_OUT
Mode B2
CLK_OUT
CLK_IN
Q_IN
Not used
Q_IN
Not used
Not used
IQ_IN
13) I_IN
I_IN
I_IN
14) Q_OUT
15) I_OUT
23) DIO2
Q_OUT
I_OUT
Not used
Q_OUT
I_OUT
WS
Not used
IQ_OUT
WS
Table 12 . Mapping of IO pins related to the I and Q transfer
4.4.2. Mode A
The convention of the I and Q interface for the Rx link in mode A is that the data is delivered on a rising edge of the internal
clock, available on CLK_OUT.
For the Tx link, the Tx DACs can be used either with the internal clock, available on CLK_OUT for data synchronization
(SX1255 master) or with an input clock CLK_IN (SX1255 slave).
The figure below provides the timing diagram for the Tx link in mode A, in the case SX1255 is master:
CLK_OUT
tsetup
thold
data stable
I/Q
data stable
Figure 13. Tx timing diagram of I and Q interface in mode A (SX1255 master)
To relax the constraints on the setup and hold time, when SX1255 is used as master, it is recommended to use the falling
edge of the clock (CLK_OUT) to provide the I&Q bitstreems to the chip. The circuit will sample the data on the next falling
edge of the clock.
tsetup_min = 14 ns
thold_min = 0 ns
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The figure below provides the timing diagram for the Tx link in mode A, in the case SX1255 is slave:
thold
CLK_IN
tsetup
I/Q
data stable
data stable
Figure 14. Tx timing diagram of I and Q interface in mode A (SX1255 slave)
In the case SX1255 is slave, CLK_IN is provided externally. The I/Q bitstreems should be provided on the rising edge of
the CLK_IN clock and the circuit will sample the data on the falling edge of the clock.
tsetup_min = 0 ns
thold_min = 6 ns
4.4.3. Mode B
4.4.3.1. Introduction
In mode B, the I and Q signals are pre- and post-processed by the internal digital bridge. An I2S based interface provides
an easy way to transfer parallel I/Q data between the SX1255 and an external baseband chip.
In Rx mode, the serial I/Q data coming from the RF front-end (I_RX/Q_RX) is decimated in the digital bridge to generate
parallel I/Q signals at a sampling rate depending on the programmed decimator factor. The I2S interface block is able then
to convert this parallel I/Q data (buses i_in_bridge[31:0] / q_in_bridge[31:0]) into one or two I2S serial bitstream(s) and
send it to an external baseband signal along with the other I2S signals as defined by the standard.
Similarly, in Tx mode the FIR-DACs are fed by two serial I/Q bitstreems coming from the digital bridge (I_TX/Q_TX). The
I2S interface is able to convert the I2S serial data coming from an external baseband chip into parallel I/Q signals (buses
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i_out_bridge[31:0]/q_out_bridge[31:0]). Then these parallels signals are interpolated and ΣΔ modulated before being fed to
the FIR_DACs. The figure below shows the I2S interface in its context in mode B:
I_OUT
I_RX
i_in_bridge[31:0]
q_in_bridge[31:0]
iism_sd_i_out
iism_sd_q_out
ADC
ADC
N
Q_OUT
DIO2
Q_RX
N
EXTERNAL
BASEBAND
CHIP
RX BRIDGE
in_rdy
iism_ws
I2S INTERFACE
iism_sd_i_in
CLK_XTAL
I_TX
out_rdy
TX BRIDGE
I_IN
DAC
i_out_bridge[31:0]
ΣΔ
ΣΔ
N
N
Q_TX
Q_IN
q_out_bridge[31:0]
iism_sd_q_in
iism_sck_out
DAC
CLK_XTAL
CLK_OUT
CLK_IN
XTAL
Figure 15. The I2S interface block in its context (mux cells are included in PAD_CTL block)
In B mode, the I2S interface is master of the I2S bus. The block generates the usual I2S signal, the clock CLK_OUT, the
word select WS (available on DIO2 pin) and one or two serial data. It also samples the serial data coming from the external
chip.
Mode B1 is an extension of the I2S format, where the I and Q serial data are not multiplexed on the same line but put or
accepted on 2 pins I_OUT/Q_OUT or I_IN/Q_IN respectively in I2S transmitter mode or in I2S receiver mode. In mode B1,
the WS frequency corresponds to half of the sampling rate of the parallel I/Q signals.
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The figure below shows the timing diagram in B1 mode for samples of 8 bits wide, as an example, actually the number of
bits is variable, as explained later on in this document.
CLK_OUT
WS
I_OUT or
I_IN
In[7]
In-1[1]
In[1]
In[6]
In[0]
In+1[7]
In+1[6]
In-1[0]
Nth sample of I
Q_OUT or
Q_IN
Qn[7]
Qn-1[1]
Qn[1]
Qn[6]
Qn[0]
Qn+1[7]
Qn+1[6]
Qn-1[0]
Nth sample of Q
Figure 16. Timing diagram of I and Q interfaces in mode B1
Mode B2 is purely I2S compatible and the I/Q serial data is multiplexed on the I_OUT pin (Tx mode) or pin I_IN (Rx mode).
Serial data with WS polarity set to “0” corresponds to I signal while WS polarity set to “1” corresponds to Q signal.
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The figure below shows an example of timing diagram in B2 mode:
CLK_OUT
WS
IQ_OUT or
IQ_IN
In[7]
Qn-1[1]
In[1]
In[6]
In[0]
Qn[7]
Qn[6]
Qn-1[0]
Nth sample of I
Figure 17. Timing diagram of I and Q interfaces in mode B2
In B mode the WS is one CLK_OUT clock period ahead of time.
The digital bridge and the I2S interface are automatically started in Tx and Rx mode as soon as the corresponding modes
are activated. Disabled control bits are available in test mode.
The full duplex run is possible, but the user must be aware that in this case input and output I2S frames have the same
format, hence the decimator and interpolation factors must be identical.
4.4.3.2. Parameters
Two main parameters are programmable:
- the decimation/interpolation factor
- the frequency of the output clock CLK_OUT.
The decimation/interpolation factor is programmable on 2 sets of 14 values.The ratios are defined as follows:
R = MANT ⋅ 3m ⋅ 2n
where MANT is 8 for the 1st set and 9 for the 2nd set, m can be 0 or 1, and n is an integer between 0 and 6.
SX1255 - Rev. 3.0
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The ratios available and the corresponding sampling rates are given in the tables below for 32MHz, 36.864MHz and
Sampling Rates vs
Decimation /
8
16
24
32
48
64
96
128
192
256
384
512
768
1536
Interpolation factor
[MS/s]
4
2
1.333
1.536
1
0.667
0.768
0.5
0.333
0.384
0.25
0.167
0.192
0.125
0.144
0.083
0.096
0.063
0.072
0.042
0.048
0.021
0.024
32MHz xtal
4.608
2.304
1.152
0.576
0.288
36.864MHz xtal
Table 13 Sampling rates 1st set
36MHz crystals.
Sampling Rates
vs Decimation /
Interpolation factor
[MS/s]
9
18
27
36
54
72
108
144
216
288
432
576
864
1728
4
2
1.333
1
0.667
0.5
0.333
0.25
0.167
0.125
0.083
0.063
0.042
0.021
36MHz xtal
Table 14 Sampling rates 2nd set
Other frequencies between 32 and 36.9 MHz can be used with any decimation factor.
The frequency of the output clock CLK_OUT is equal to the crystal frequency divided by a ratio programmable on several
values which are 1, 2, 4, 8, 12, 16, 24, 32 and 48. In IISM test mode, any integer between 1 and 64 can be selected.
The number of bits per sample depends on the decimation/interpolation factor (2 sets of 14 values) as well as the
frequency of the CLK_OUT clock (9 possibilities) and the type of B mode. The allowed number of bits is between 8 and 32.
In IISM test mode, any number of bits between 4 and 32 can be selected. Less than 4 bits is not possible for
implementation reason
In B2 mode, there is a new I/Q sample every period of WS. In B1 mode, there are two I/Q samples every WS period, and
the WS frequency is reduced by a factor of 2. This mode allows to allocate twice more bits per I/Q sample.
Only a limited number of parameters combination generate valid I2S frames. Therefore the valid combination are clearly
documented and the other ones aborts the I2S interface. The tables below illustrate this statement. Depending on the
XTAL/CLK_OUT divider and the decimation/interpolation factor, the number of bits per samples are computed for the 2
predefined sets. Combination with a number of bits higher than 32 and lower than 8 are disabled in functional mode (“NA”)
and an error bit is set.
CLK_OUT/XTAL
1
2
4
8
12
16
24
32
48
Decimation/
interpolation factor
8
8
NA
8
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
16
16
Table 15 Number of bits per sample for the 1st set and B1 mode
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48
WIRELESS & SENSING PRODUCTS
CLK_OUT/XTAL
1
2
4
8
12
16
24
32
Decimation/
interpolation factor
24
32
24
32
12
16
NA
8
NA
NA
NA
8
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
NA
8
48
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
24
12
64
32
16
96
NA
NA
NA
NA
NA
NA
NA
NA
24
12
128
192
256
384
512
768
1536
32
16
NA
16
NA
NA
NA
NA
NA
NA
24
12
32
NA
32
16
NA
16
NA
NA
NA
NA
24
12
NA
NA
NA
32
NA
32
16
NA
16
NA
NA
24
NA
NA
32
Table 15 Number of bits per sample for the 1st set and B1 mode
CLK_OUT/XTAL
1
2
4
8
12
16
24
32
48
Decimation/
interpolation factor
9
18
9
NA
9
NA
NA
NA
9
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
9
18
27
27
NA
18
36
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
54
27
NA
18
72
NA
NA
NA
NA
NA
NA
NA
NA
NA
108
144
216
288
432
576
864
1728
27
NA
18
NA
NA
NA
NA
NA
NA
NA
12
27
18
NA
18
NA
NA
NA
NA
NA
24
12
NA
NA
NA
NA
27
18
NA
18
NA
NA
NA
24
12
NA
NA
27
18
NA
NA
Table 16 Number of bits per sample for the 2nd set and B1 mode
SX1255 - Rev. 3.0
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48
WIRELESS & SENSING PRODUCTS
CLK_OUT/XTAL
1
2
4
8
12
16
24
32
Decimation/
interpolation factor
8
16
NA
8
NA
NA
NA
8
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
8
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
8
24
12
32
16
48
24
12
64
32
16
96
NA
NA
NA
NA
NA
NA
NA
NA
24
12
128
192
256
384
512
768
1536
32
16
NA
NA
NA
NA
NA
NA
24
12
32
16
NA
16
NA
NA
NA
NA
24
12
32
NA
32
16
NA
16
NA
NA
24
12
NA
NA
32
24
16
Table 17 Number of bits per sample for the 1st set and B2 mode
CLK_OUT/XTAL
1
2
4
8
12
16
24
32
48
Decimation/
interpolation factor
9
18
NA
9
NA
NA
NA
9
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
9
27
NA
18
36
54
27
NA
18
72
NA
NA
NA
NA
NA
NA
NA
NA
NA
108
144
216
288
432
576
864
1728
27
NA
18
NA
NA
NA
NA
NA
NA
NA
27
NA
18
NA
NA
NA
NA
NA
12
27
18
NA
18
NA
NA
NA
24
12
NA
NA
27
18
NA
27
NA
NA
18
Table 18 Number of bits per sample for the 2nd set and B2 mode
The parallel I/Q data bus is expected to be 32-bits wide. Hence, if the number of bits per frame is lower, the I/Q data is
truncated, either MSBs or the LSBs are taken, according to a configuration bit, iism_trunc_mode.
SX1255 - Rev. 3.0
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5. Configuration and Status Registers
5.1. General Description
Notes - Reset values are automatically refreshed at Power on Reset
- DEFAULT values are the Semtech recommended register values, optimizing the device operation
- Registers for which the DEFAULT value differs from the RESET values are denoted by a * in the tables of this
section
Address
Bits
Name
Mode Reset
Description
General registers
MODE
(0x00)
7-4
3
-
r
0x00 unused
driver_enable
tx enable
rw
rw
rw
rw
rw
0x00 enables the PA driver
2
0x00 enables the complete TX part of the frontend (except the PA)
0x00 enables the complete RX part of the frontend
0x01 enables the PDS & XOSC
1
rx_enable
0
ref_enable
freq_rf_rx(23:16)
FRFH_RX
(0x01)
7-0
0xC0 MSB of RF RX carrier frequency
FRFM_RX
(0x02)
7-0
7-0
freq_rf_rx(15:8)
freq_rf_rx(7:0)
rw
rw
0xE3 MSB of RF RX carrier frequency
FRFL_RX
(0x03)
0x8E LSB of RF RX carrier frequency
F(XOSC) ⋅ freq_rf_rx
-----------------------------------------------------
220
fRF_RX
=
Resolution is 34.3323 Hz if F(XOSC) = 36 MHz. Default value
is 0xC0E38E = 434 MHz. The RX RF frequency is taken into
account internally only when:
- FRFL_RX is written
- leaving SLEEP mode (ref_enable 0 1 transition)
FRFH_TX
(0x04)
7-0
7-0
7-0
freq_rf_tx(23:16)
freq_rf_tx(15:8)
freq_rf_tx(7:0)
rw
rw
rw
0xC0 MSB of RF TX carrier frequency
FRFM_TX
(0x05)
0xE3 MSB of RF TX carrier frequency
FRFL_TX
(0x06)
0x8E LSB of RF TX carrier frequency
F(XOSC) ⋅ freq_rf_tx
-----------------------------------------------------
220
fRF_TX
=
Resolution is 34.3323 Hz if F(XOSC) = 36 MHz. Default value
is 0xC0E38E = 434 MHz. The TX RF frequency is taken into
account internally only when:
- FRFL_TX is written
- leaving SLEEP mode (ref_enable 0 1 transition)
VERSION
(0x07)
7-0
chip_version(7:0)
r
0x11 Version code of the chip. Bits 7-4 give the fill revision number,
bits 3-0 give the metal mask revision number.
Current value is V1A
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Address
Bits
Name
Mode Reset
Description
Transmitter registers
TXFE1
(0x08)
7
unused
r
0x00
6-4
tx_dac_gain(2:0)
rw
0x02 DAC gain, steps of 3 dB:
000 => Max gain - 9 dB
001 => Max gain - 6 dB
010 => Max gain - 3 dB
011 => Max gain, 0 dBFS -> rail-to-rail signal
100 and higher: test modes not recommended:
100 => Max gain - 9 dB with test Vref voltage
101 => Max gain - 6 dB with test Vref voltage
110 => Max gain - 3 dB with test Vref voltage
111 => Max gain, 0 dBFS with test Vref voltage
3-0
tx_mixer_gain(3:0)
rw
0x0E Mixer gain, steps of about 2 dB:
*
Actual gain ≅ -37.5 dB + 2.tx_mixer_gain(3:0)
TXFE2
(0x09)
7-6
5-3
-
r
0x00 unused
tx_mixer_tank_cap(2:0)
rw
0x04 Capacitance in parallel with the mixer tank:
Cap = 128 * tx_mixer_tank_cap(2:0) [fF]
2-0
tx_mixer_tank_res(2:0)
rw
0x04 Resistance in parallel with the mixer tank:
*
000 -> 0.95 kΩ
001 -> 1.11 kΩ
010 -> 1.32 kΩ
011 -> 1.65 kΩ
100 -> 2.18 kΩ
101 -> 3.24 kΩ
110 -> 6.00 kΩ
111 -> none => about 64 kΩ
TXFE3
(0x0A)
7
-
r
0x00 unused
6-5
tx_pll_bw
rw
0x03 Tx PLL bandwidth
PLL BW = (rx_pll_bw + 1)*75 KHz
4-0
tx_filter_bw(4:0)
rw
0x00 Tx analog filter bandwidth DSB:
BW3dB = 17.15 / (41 - tx_filter_bw(4:0)) MHz
TXFE4
(0x0B)
7-3
2-0
-
rw
rw
0x00 unused
tx_dac_bw(2:0)
0x02 Number of taps of FIR-DAC:
Actual number of taps = 24 + 8.tx_dac_bw(2:0) (max = 64)
Receiver registers
RXFE1
(0x0C)
7-5
rx_lna_gain(2:0)
rw
0x01 LNA gain setting:
000 not used
001 G1 = highest gain low power – 0 dB
010 G2 = highest gain low power – 6 dB
011 G3 = highest gain low power – 12 dB
100 G4 = highest gain low power – 24 dB
101 G5 = highest gain low power – 36 dB
110 G6 = highest gain low power – 48 dB
111 not used
4-1
0
rx_pga_gain(3:0)
rx_zin_200
rw
rw
0x0F PGA gain setting:
Gain=lowest gain + 2dB * rx_pga_gain
0x01 change of input impedance
0: 50 ohm
1: 200 ohm
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DATASHEET
Address
Bits
7:5
Name
Mode Reset
rw 0x07
Description
RXFE2
(0x0D)
rx_adc_bw(2:0)
RX ΣΔ ADC bandwidth configuration
For BW>400kHz SSB use 0x07
For 200kHz< BW<400kHz SSB use 0x05
For 100kHz<BW<400kHz SSB use 0x02
use 0x01 instead
4:2
1-0
rx_adc_trim(2:0)
rx_pga_bw(1:0)
rw 0x05*
Rx ΣΔ ADC Trimming for 36MHz crystal
rw
0x01 Rx analog filter bandwidth DSB:
00 Fc = 1500 kHz
01 Fc =1000 kHz
10 Fc = 750 kHz
11 Fc = 500 kHz
RXFE3
(0x0E)
7:3
2:1
unused
r
0x00
rx_pll_bw(1:0)
Rx PLL bandwidth
rw
0x03
PLL BW = (rx_pll_bw + 1)*75 KHz
0
rx_adc_temp
iomap0(1:0)
rw
0x00 Sets the Rx ADC into temperature measurement mode.
IRQ and pin mapping registers
IO_MAP
(0x0F)
7-6
rw
0x00 Mapping of DIO(0)
00: pll_lock_rx
01 :pll_lock_rx
10: pll_lock_rx
11: eol
5-4
3-2
1-0
iomap1(1:0)
iomap2(1:0)
iomap3(1:0)
rw
rw
rw
0x00 Mapping of DIO(1)
00: pll_lock_tx
0x00 Mapping of DIO(2)
00: xosc_ready
0x00 Mapping of DIO(3)
00: pll_lock_rx in Rx mode &
pll_lock_tx in all other modes
Misc registers
CK_SEL
(0x10)
7-4
3
-
r
0x00 Unused
dig_loopback_en
rf_loopback_en
ckout_enable
rw
rw
rw
0x00 Enables the digital loop back mode of the frontend
0x00 Enables the RF loop back mode of the frontend
2
1
0x01 0: output clock disabled on pad CLK_OUT
1: output clock enabled on pad CLK_OUT
0
ck_select_tx_dac
rw
0x00 0: internal clock (CLK_XTAL) used for Tx DAC
1: external clock (CLK_IN) used for Tx DAC
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DATASHEET
Address
Bits
7-3
3
Name
Mode Reset
Description
STAT
(0x11)
-
r
r
0x00 Not used
0x00 EOL output signal
eol
0 VBAT > EOL threshold
1 VBAT < EOL threshold (battery low)
0x00 Goes high when the XOSC is ready
0x00 Asserted when the Rx PLL is locked
0x00 Asserted when the Tx PLL is locked
0x00 disable IISM Rx (during TX mode)
0x00 disable IISM Tx (during RX mode)
2
1
xosc_ready
pll_lock_rx
r
r
0
pll_lock_tx
r
IISM
(0x12)
7
iism_rx_disable
iism_tx_disable
iism_mode[1:0]
rw
rw
rw
6
5-4
0x00 00 -> mode A
01 -> mode B1
10 -> mode B2
11 -> not used
3-0
iism_clk_div[3:0]
rw
0x00 XTAL/CLK_OUT division factor
0000 -> 1
0010 -> 4
0100 -> 12
0110 -> 24
0001 -> 2
0011 -> 8
0101 -> 16
0111 -> 32
1000 -> 48 higher values not used
DIG_BRIDGE
(0x13)
7
int_dec_mantisse
rw
0x00 interpolation/decimation factor = mant * 3^m * 2^n
0 -> 1st set; mant=8
1 -> 2nd set; mant=9
6
5-3
2
int_dec_m_parameter
int_dec_n_parameter
IISM_truncation
rw
rw
rw
0x00 interpolation/decimation factor = mant * 3^m * 2^n
m value
0x00 interpolation/decimation factor = mant * 3^m * 2^n
n value (accepted values 0 to 6)
0x00 IISM truncation mode in Rx and Tx
0 -> MSB is truncated, alignement on LSB
1 -> LSB is truncated, alignement on MSB
1
0
IISM_status_flag
unused
r
r
0x00 IISM error status bit when selected factors force IISM off
0 -> no error
1 -> error, IISM off
0x00
SX1255 - Rev. 3.0
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SX1255
WIRELESS & SENSING PRODUCTS
DATASHEET
6. Application Information
6.1. Crystal Resonator Specification
The specification for the crystal resonator of the reference oscillator circuit block is tabulated below in Table 19.
Table 19 Crystal Resonator Specification
Symbol
FXOSC
RS
Description
Conditions
Min
Typ
-
Max
36.864
140
7
Units
MHz
Ω
XTAL Frequency
32
-
XTAL Series Resistance
XTAL Shunt Capacitance
External Foot Capacitance
30
2.8
16
C0
-
pF
CLOAD
On each pin XTA and XTB
8
22
pF
Notes - The initial frequency tolerance, temperature stability and aging performance should be chosen in accordance
with the target operating temperature range and the receiver bandwidth selected
- The loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL
6.2. Reset of the Chip
A power-on reset of the SX1255 is automatically triggered at power up. Additionally, a manual reset can be issued by
controlling the RESET pin (pin 9).
6.2.1. POR
If the application requires the disconnection of VDD from the SX1255, despite the extremely low Sleep Mode current, the
user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 9
(RESET) should be left floating during the POR sequence.
VDD
Pin 9
Undefined
(Output)
SX1255is ready from
Wait for 10 ms
this point on
Figure 18. POR Timing Diagram
Please note that xosc_ready on DIO2 can be used to detect that the chip is ready.
SX1255 - Rev. 3.0
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SX1255
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DATASHEET
6.2.2. Manual Reset
A manual reset of the SX1255 is possible even for applications in which VDD cannot be physically disconnected. Pin 9
should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the
chip.
VDD
Pin 9
(Input)
High-Z
“1”
High-Z
SX1255
this point on
Sis ready from
> 100 us Wait for 5 ms
Figure 19. Manual Reset Timing Diagram
Please note that whilst pin 9 is driven high, an over current consumption of 10 mA may be observed on VDD
6.3. TX Noise Shaper
In order to generate a single TX bit-stream, th 8-bit I and Q signal should be processed by an external third order sigma-
delta modulator (implemented within the baseband processor). The noise shaper should be stable for input signals lower
than -3dBFS and compatible with SX1255 noise requirements. It is advised that the integrator outputs are saturated to
avoid any wraparound of the 2’s-complement digital word.
A representative block diagram of a single-bit feed-forward modulator is illustrated below.
Figure 20. Example Digital Modulator Implementation
SX1255 - Rev. 3.0
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WIRELESS & SENSING PRODUCTS
6.4. Reference Design
DATASHEET
Please contact your Semtech representative for evaluation tools, reference designs and design assistance. Note that all
schematics shown in this section are full schematics, listing ALL required components, including those required for power
supply decoupling.
Figure 21. SX1255 Application Schematic
SX1255 - Rev. 3.0
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SX1255
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DATASHEET
7. Packaging Information
7.1. Package Outline Drawing
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
A
D
B
E
DIM
A
.028 .030 .031 0.70
0.80
0.05
-
0.75
-
.002 0.00
-
A1 .000
-
(.008)
-
-
(0.20)
A2
b
.008 .010 .012 0.18 0.25 0.30
PIN 1
INDICATOR
(LASER MARK)
D
.193 .197 .201 4.90 5.00 5.10
D1 .118 .122 .126 3.00 3.10 3.20
E
.193 .197 .201 4.90 5.00 5.10
3.10 3.20
E1 .118 .122 .126
3.00
0.50 BSC
e
L
N
aaa
bbb
.020 BSC
.012 .016 .020 0.30 0.40 0.50
32
32
A2
.003
.004
0.08
0.10
A
SEATING
PLANE
aaa
C
C
A1
D1
LxN
E/2
E1
2
1
N
bxN
e
bbb
C A B
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Figure 22. Package Outline Drawing
7.2. Recommended Land Pattern
H
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.193)
.161
.130
.130
.020
.012
.031
.224
(4.90)
4.10
3.30
3.30
0.50
0.30
0.80
5.70
C
G
H
K
P
X
Y
Z
Z
(C)
K
G
Y
X
P
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
Figure 23. Recommended Land Pattern
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WIRELESS & SENSING PRODUCTS
7.3. Thermal Impedance
DATASHEET
The thermal impedance of this package is: Theta ja = 23.8° C/W typ., calculated from a package in still air, on a 4-layer
FR4 PCB, as per the Jedec standard.
7.4. Tape and Reel Specification
Figure 24. Tape and Reel Specification
Carrier Tape (mm)
Reel (mm)
TapeWidth
(W)
Pocket
Pitch
(P)
A / B
K
O
Reel Size Reel Width Min.Trailer
Min.
QTY per
Reel
O
O
Length
(mm)
Leader
Length
(mm)
12 +/- 0.30 8 +/- 0.20
5.25
1.10
330.2
12.4
400
400
3000
+/- 0.20
+/- 0.10
Note Single sprocket holes
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SX1255
WIRELESS & SENSING PRODUCTS
DATASHEET
8. Revision History
Table 20 Datasheet Revision History
Revision
1.0
Date
Comment
February 2013 First Datasheet revision
2.0
May 2013
Updated specifications after part characterization
Add wafer sale part number
3.0
October 2013
SX1255 - Rev. 3.0
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October 2013 ©2013 Semtech Corporation
SX1255
WIRELESS & SENSING PRODUCTS
DATASHEET
© Semtech 2013
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and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes
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SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
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Contact information
Semtech Corporation
Wireless & Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
E-mail: sales@semtech.com
support_rf@semtech.com
Internet: http://www.semtech.com
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