SK2200LF [SEMTECH]
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32;
| 型号： | SK2200LF |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总7页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SK2200
LVPECL/HSTL to HSTL
1:9 Bus Clock Driver
TEST AND MEASUREMENT PRODUCTS
Features
Description
HSTL and LVPECL Inputs
The SK2200 is a high performance bus clock driver with 9
differential HSTL (High Speed Transceiver Logic) outputs.
It can receive either HSTL or LVPECL type signals at its
inputs; this feature makes this device ideal for applications
where clock distribution, low output-to-output and within
device skew are of utmost importance.
500 MHz Maximum Clock Frequency
35 ps Output-to-Output Skew
1:9 Fanout Buffer
Low Voltage HSTL Output Buffer (VOH = 1.2V)
Stop Clock Function
9 Differential HSTL (Low Voltage Swing) Output Pairs
50Ω to GND Termination with no offset voltage
Low Part-to-Part Skew (200 ps MAX.)
New Differential Input Common Mode Range
ESD Protection of >4000V
The input is multiplexed from either HSTL or LVPECL
by the CLK_SEL. The STOP_CLK input is synchronous
so that the outputs will only be enabled/disabled when
they are already in the low state. This feature prevents
generating any runt clocks. The HSTL outputs can be
terminated using 50Ω resistor to ground without offset
voltage.
Temperature Range: 0oC to +70oC
32 Pin LQFP Package (7mm x 7mm x 1.4mm)
Functional Block Diagram
CLK_SEL
HSTL_IN
0
HSTLB_IN
9
HCLK0 - HCLK8
9
HCLKB0 - HCLKB8
PCLK_IN
1
PCLKB_IN
LEN
Q
D
STOP_CLK
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SK2200
TEST AND MEASUREMENT PRODUCTS
Pin Description
Pin
HSTL_IN, HSTLB_IN
PCLK_IN, PCLKB_IN
CLK_SEL
Function
Differential HSTL Inputs
Differential LVPECL Inputs
Input Clock Select LVTTL
Stop Clock Input LVTTL
32 31 30 29 28 27 26 25
24
VCC
HS TL_IN
HS TLB_IN
CLK_S E L
PCLK_IN
PCLKB_IN
GND
1
2
3
4
5
6
7
8
VCCQ
23
22
21
20
19
18
17
HCLK3
HCLKB3
HCLK4
HCLKB4
HCLK5
HCLKB5
VCCQ
STOP_CLK
SK2200
HCLK0 - HCLK8,
HCLKB0 - HCLKB8
Diff HSTL Outputs
GND
VCC
Ground
S TOP_CLK
Power Supply
Power Supply
9
10
11 12 13 14 15 16
VCCQ
Pin Names
Pinout
STOP_CLK
CLK_SEL
HCLK[0:8]
LOW
HCLKB[0:8]
HIGH
0
0
1
1
0
1
0
1
LOW
HIGH
HSTL_IN
PCLK_IN
HSTLB_IN
PCLKB_IN
Truth Table
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SK2200
TEST AND MEASUREMENT PRODUCTS
Package Information
4 X
A, B
NOTES:
1.
0.20 (0.008) AB T - U
Z
Dimensioning and tolerancing per ANSI Y14.5M,
1982.
Controlling Dimension: Millimeter
Datum Plane –AB– is located at bottom of lead and
A1,
B1
32
25
2.
3.
1
24
is coincident with the lead
where the lead exits
- T,U,Z -
the plastic body at the bottom of the parting line.
Datums –T–, –U–, and –Z– to be determined at
Datum Plane –AB–.
Dimensions S and V to be determined at Seating
Plane –AC–.
Dimensions A and B do not include mold
protrusion. Allowable protrusion is 0.250 (0.010)
per side. Dimensions A and B do not include mold
mismatch and are determined at Datum Plane –AB–.
Dimension D does not include Dambar protrusion.
Dambar protrusion shall not cause the D dimension
to exceed 0.520 (0.020).
4.
5.
6.
S, V
S1,V1
8
17
9
16
SEE DETAIL "Y"
7.
SEE DETAIL "AD"
G
- AB -
- AC -
8.
9.
Minimum solder plate thickness shall be
0.0075 (0.0003).
Exact shape of each corner may vary
from depiction.
0.10 (0.004) AC
MILLIMETERS
MIN MAX
INCHES
MIN MAX
˚
8x M
R
DIM
A
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
0.276 BSC
A1
B
0.138 BSC
C
E
0.276 BSC
B1
C
0.138 BSC
W
1.400
0.300
1.350
0.300
1.600
0.055 0.063
0.012 0.018
0.053 0.057
0.012 0.016
0.031 BSC
K
X
˚
H
Q
0.250 (0.010)
GAUGE PLANE
D
0.450
1.450
0.400
Detail AD
E
F
G
0.800 BSC
–T–, –Ü–, –Z–
H
0.050
0.090
0.500
0.150
0.002 0.006
0.004 0.008
0.020 0.028
J
0.200
0.700
AE
AE
K
P
o
o
M
N
12 REF
12 REF
Base Metal
0.090 0.160
0.004 0.006
0.016 BSC
N
P
0.400 BSC
o
o
o
o
5
Q
1
5
1
Detail Y
R
0.150
0.250
0.006 0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
D
F
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
S1
V
N
V1
W
X
0.20 (0.008)
M AC T –U Z
Detail AE
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SK2200
TEST AND MEASUREMENT PRODUCTS
Absolute Maximum Ratings*
Symbol
Parameter
Value
Unit
V
V
V
V
V
Output Power Supply
-0.5 to 4.0
-0.5 to 4.0
CCQ
CC
Power Supply (3.3V Supply Voltage)
3.3V LVTTL Input High Voltage
3.3V LVTTL Input Low Voltage
Ambient Temperature Range
Thermal Resistance (Junction-to-Ambient) at still air
Thermal Resistance (Junction-to-Case) at still air
Storage Temperature Range
V
3
-0.5 to V
-0.5
V
IH
CC
3
V
IL
o
T
θ
θ
T
0 to +70
59.5
C
A
o
C/W
for LQFP
JA
JC
o
14.5
C/W
for LQFP
o
-65 to +150
C
STORE
* Maximum Ratings are those values beyond which damage to the device may occur.
DC Electrical Characteristics
Power Supply (Note 4)
o
TA = 0 C
o
TA = +25 C
o
TA = +70 C
Symbol
Characteristic
Core Supply Voltage
Output Supply Voltage
Output Supply Current
Core Supply Current
Min
3.135
1.6
Typ
Max
3.465
2.0
Min
3.135
1.6
Typ
Max
3.465
2.0
Min
3.135
1.6
Typ
Max
3.465
2.0
Unit
V
V
CC
V
I
V
CCQ
275
88
275
88
275
88
mA
mA
CCQ
I
50
68
50
68
50
68
CC
SK2200 HSTL I/O DC Electrical Characteristics
(V = 3.3V ± 5%; V
CC
= 1.8 ± 0.2V; GND = 0V; Outputs loaded with 50 Ω to GND)
CCQ
o
TA = 0 C
o
TA = +25 C
o
TA = +70 C
Min
1.0
Typ
Max
1.2
Min
1.0
Typ
Max
1.2
Min
1.0
Typ
Max
1.2
Symbol Characteristic
Unit
V
1
V
V
V
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Crossover Voltage
Input HIGH Current
Input LOW Current
OH
OL
IH
IL
1
0
0.4
0
0.4
0
0.4
V
Vx + 0.1
-0.3
1.6
Vx + 0.1
-0.3
1.6
Vx + 0.1
-0.3
1.6
V
Vx - 0.1
0.9
Vx - 0.1
0.9
Vx - 0.1
0.9
V
0.68
0.68
0.68
V
X
I
I
-400
0
-400
0
-400
0
mA
mA
IH
-600
-600
-600
IL
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SK2200
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
SK2200 LVPECL Input DC Electrical Characteristics
(V = 3.3V ± 5%; V
CC
= 1.8 ± 0.2V; GND = 0V )
CCQ
o
TA = 0 C
o
TA = +25 C
o
TA = + 70 C
Symbol Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
2
V
V
I
Input HIGH Voltage
2.135
2.42
2.135
1.49
-150
200
2.42
2.135
2.42
V
IH
IL
2
Input LOW Voltage
Input Current
1.49
-150
200
1.825
150
1.825
150
1.49
-150
200
1.825
150
V
mA
mV
IN
V
V
Minimum Input Swing
600
1000
600 1000
600
1000
PP
GND
GND
GND
7
Common Mode Range
V
V
V
V
CMR
CC
CC
CC
+ 1.5V
+ 1.5V
+ 1.5V
SK2200 LVTTL Input DC Characteristics (Note 2)
(VCC=3.3V + 5%; VCCQ = 1.8 + 0.2V; GND = 0V)
o
o
o
TA = 0 C
TA = +25 C
TA = +70 C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
V
Input HIGH Voltage
2.0
2.0
2.0
V
IH
IL
Input LOW Voltage
Input HIGH Current
0.8
40
0.8
40
0.8
40
V
I
IH
- 40
-80
- 40
-80
- 40
-80
µA
I
IL
Input LOW Current
0
0
0
µA
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SK2200
TEST AND MEASUREMENT PRODUCTS
AC Characteristics
SK2200 AC Electrical Characteristics
(V = 3.3V ± 5%; V
CC
= 1.8 ± 0.2V; GND = 0V )
CCQ
o
TA = 0 C
o
TA = +25 C
o
TA = +70 C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
F
MAX
Maximum Toggle Frequency
500
500
500
MHz
3
T
PLH
PHL
Input-to-Output Delay
860
930
1000
880
940
1000
930
1040
1100
ps
T
Output-to-Output Skew (Diff)
Part-to-Part Skew
35
35
35
ps
ps
5
T
SKEW
200
200
200
Output Rise/Fall Times
(20% to 80%)
t , t
r
410
570
420
560
430
550
ps
f
8
ts
STOP_CLK Setup Time
STOP_CLK HOLD Time
Output Duty Cycle Distortion
1000
500
48
1000
500
48
1000
500
48
ps
ps
%
t
H
9
DCD
52
52
52
NOTES:
1. Parametric values are specified at V
2. Parametric values are specified at V
= 1.8V.
CCQ
= 3.3V.
CC
3. Measured from the differential input crossing point to differential output crossing point.
4. No power sequencing allowed in the system.
5. Measured from output differential crossing point to output differential crossing point.
6. For part ordering description, see TMD Part Ordering Information Data Sheet.
7. CMR range is referenced to the most positive side of the differential LVPECL input signal. Normal
operation is obtained if the high level falls within the specified range and the peak-to-peak voltage
lies between VPP
and 1V. The lower end of the CMR range varies 1:1 with GND and is equal
(min)
to GND + 1.5V. VCMR is referenced to VCC (LVPECL input supply).
8. Setup time measuring point is defined at 1.5V of the STOP_CLK and the crossing point of the
differential input clock. The setup is measured between the edge rate of the STOP_CLK and the
next rising edge of the true output of the differential input clock.
9. Measured with duty cycle of input clock ([PCLK_IN, PCLKB_IN] or [HCLK_IN, HCLKB_IN]) at 50%.
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SK2200
TEST AND MEASUREMENT PRODUCTS
Ordering Information6
Ordering Code
SK2200LF
Package ID
32-LQFP
SK2200LFT
32-LQFP
Application Notes
AN1003 - Termination Techniques for ECL/LVECL/PECL/LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL/LVECL/PECL/LVPECL
AN1008 - Interfacing With CML
Contact Information
Semtech Corporation
Test and Measurement Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858) 695-1808 FAX: (858) 695-2633
Revision 3 / April 8, 2003
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