SC1176ATSTR [SEMTECH]
Dual Synchronous Voltage Mode Controller with Current Sharing Circuitry; 双同步电压模式控制器均流电路
| 型号： | SC1176ATSTR |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Dual Synchronous Voltage Mode Controller with Current Sharing Circuitry |
| 文件： | 总23页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1176/SC1176A
Dual Synchronous Voltage Mode
Controller with Current Sharing Circuitry
POWER MANAGEMENT
Features
Description
The SC1176 is a versatile 2 phase, synchronous, volt-
age mode PWM controller that may be used in two dis-
tinct ways. First, the SC1176 is ideal for applications
where point of use output power exceeds any single in-
put power budget. Alternatively, the SC1176 can be used
as a dual switcher. The SC1176 features a temperature
compensated voltage reference, over current protection
with 50% fold-back and internal level-shifted, high-side
drive circuitry.
300kHz fixed frequency operation
Soft Start and Enable function
Power Good output provided
Over current protection with 50% fold-back
Phase-shifted switchers minimize ripple
High efficiency operation, >90%
Programmable output(s) as low as .9V
Industrial temperature range
SOIC-20 or TSSOP-20 pin Lead free package. This
product is fully WEEE and RoHS compliant
In current sharing configuration, the SC1176 can pro-
duce a single output voltage from two separate voltage Two Phase, Current Sharing Controller
sources (which can be different voltage levels) while
maintaining current sharing between the channels. Cur-
rent sharing is programmable to allow loading each input
supply as required by the application.
Flexible, same or separate VIN
Programmable current sharing
Combined current limit with fold-back
2 phases operating opposed for ripple reduction
Thermal distribution via multi-phase output
In dual switcher configuration, two feedback paths are
provided for independent control of the separate out-
puts. The device will provide a regulated output from
flexibly configured inputs (3.3V, 5V, 12V), provided 5V is
present for VCC. The two switchers are 180° out of phase
to minimize input and output ripple.
Two Independent PWM Controllers
Flexible, same or separate VIN
Independent control for each channel
Independent and separate current limit
2 phases operating opposed for ripple reduction (if
same VIN used)
The SC1176A has the phases of the Master and the Slave
inverted.
Applications
Graphics cards
DDR Memory
It offers a different pattern for ripple cancellation and
prevents phase fold back during current limit.
Peripheral add-in card
The two chips are pin compatible.
SSTL Termination
Dual-Phase power supply
Power supplies requiring two outputs
Revision: June 29, 2006
1
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SC1176/SC1176A
POWER MANAGEMENT
Typical Application Circuit
2 Channels with Current Sharing
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2
SC1176/SC1176A
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Limits
Units
VCC to GND
VIN
-0.3 to 15
± 1
V
V
V
PGND to GND
BST to GND
-0.3 to 26
Thermal Resistance Junction to Case
SOIC
24
27
°C/W
°C/W
θJC
TSSOP
Thermal Resistance Junction to Ambient
SOIC
65
85
θJA
TSSOP
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
TA
TJ
0 to 70
0 to 125
-65 to +150
300
°C
°C
°C
°C
TSTG
TLEAD
Lead Temperature (Soldering) 10 sec
Electrical Characteristics
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, 0mV < (CS(+) - (CS(-)) < 60mV , TJ = 25°C
Parameter
Conditions
IO = 2A(1), VOUT set to 2.75V
VCC
Min
2.65
4.2
Typ
Max
Units
V
Output Voltage
2.75
2.85
15
Supply Voltage
V
Supply Current
VCC = 5.0
15
mA
V
Reference Voltage
Reference Voltage Line Regulation
Reference Voltage Load Regulation
Output Line Regulation
Output Load Regulation
Gain (AOL)
IREF = 0µA
0.89
0.9
0.91
0.5
5V < VCC < 15V
%
I
REF = 0µA to 30µA
5V < VIN < 15V
IO = 0.3A to 15A (1)
-12
0.5
mV
%
1
35
%
VOSENSE to VO
dB
mV
kHz
%
Current Limit Voltage
Oscillator Frequency
Oscillator Max Duty Cycle
DH Sink Current
60
270
90
70
80
300
95
330
DH - PGND = 3.0V
DH - PGND = 2.0V
BSTH - DH = 3.5V
BSTH - DH = 2.5V
1.3
A
DH Sink Current
0.85
1.3
A
DH Source Current
DH Source Current
A
0.85
A
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SC1176/SC1176A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, 0mV < (CS(+) - (CS(-)) < 60mV , TJ = 25°C
PARAMETER
CONDITIONS
DL - PGNG = 3.0V
DL - PGND = 2.0V
BSTL - DL = 3.5V
BSTL - DL = 2.5V
Note 5
MIN
1.3
TYP
MAX
UNITS
A
DL Sink Current
DL Sink Current
0.85
1.3
A
DL Source Current
DL Source Current
Dead Time
Soft Start Charge Current (2)
Soft Start Enable
Soft Start End
Soft Start Transition(2)
Power Good Window(3)
Fold Back Current
Fold Back Voltage Knee
Input Bias Current
BSTH to DH Leakage
DH to PGND Leakage
BSTL to DL Leakage
DL to PGND
A
0.85
50
A
100
25
150
ns
µA
V
0% duty cycle
100% duty cycle
Synchronous mode
1.4
2.5
V
3.3
V
+10
50%
%VOUT
I LIM
V
VOUT = 0V
I = ILIM
0.9
VOUT
1
-IN1, +IN2, -IN2
BSTH - DH = 5V
DH - PGND = 5V
BSTL - DL = 5V
DL - PGND = 5V
µA
µA
µA
µA
µA
10
10
10
10
Notes:
(1) Specification refers to application circuit.
(2) The soft start pin sources 25µA to an external capacitor. The converter operates in synchronous mode above the soft
start transition threshold and in asynchronous mode below it.
(3) Power good is an open collector pulled low when the output voltage is outside the ±10% window.
(4) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(5) 200ns maximum at 75°.
Marking Information
(TSSOP-20)
(SOIC-20)
6
TOP
nnnn = Part Number (Example: 1471)
yyww = Date Code (Example: 0012)
yyww = Date Code (Example: 9908)
xxxx = Semtech Lot # (Example: 90101)
xxxxxx = Semtech Lot # (Example: P94A01)
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SC1176/SC1176A
POWER MANAGEMENT
Ordering Information
Pin Configuration
Device(1)
Package(2)
Top View
SC1176CSWTR
SC1176CSWTRT
SC1176ASWTR
SC1176ASWTRT
SC1176TSTR
SOIC-20
TSSOP-20
SC1176TSTRT
SC1176ATSTR
SC1176EVB-1
Current Share Version Evaluation
Board
SC1176-2EVB-2
Dual Channel Version Evaluation
Notes:
(1) Only available in tape and reel packaging. A reel
contains 1000 (SOIC) or 2500 (TSSOP) devices.
(SOIC-20 and TSSOP-20 Pin)
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
Pin Descriptions
EXPANDED PIN DESCRIPTION
Pin 1: (VREF)
Internal .9V reference
Connected to the + input of the master channel error
amplifier.
Pin 8, 13: (DH2, DH1)
DH signal (Drive High).
Pin 2: (+IN2)
Gate drive for top MOSFETs.
Requires a small serie resistor.
Pin 9, 12: (DL2, DL1)
+ Input of slave channel error amplifier.
Connected to .9V reference (Pin 1) for
2 independent channel configuration.
Pin 3, 18: (-IN2, -IN1)
DL signal (Drive Low).
Gate drive for bottom MOSFETs.
Requires a small serie resistor.
Pin 10: (PGND)
- Inputs of close loop error amplifiers.
Works as a feedback inputs (For both modes).
Pin 4: (VCC)
Power GND. Return of gate drive currents.
Pin 11: (BSTC)
VCC chip supply voltage.
15V maximum, 15mA typical.
Supply for bottom MOSFETs gate drive.
Pin 17: (SS/ENA)
Needs a 1µF ceramic multilayer decoupling capacitor
to GND (Pin 20).
Soft start pin. Internal current source connected to
external capacitor.
Pin 5, 6,15, 16: (CL2-, CL2+, CL1+, CL1-)
Pins (-) and (+) of the current limit amplifiers for both
channels.
Inhibits he chip if pulled down.
Pin 19: (PWRGD)
Connected to output current sense resistors. Com-
pares that sense voltage to internal 75mV reference.
Needs RC filter for noise rejection.
Pin 7, 14: (BST2, BST1)
Power good signal.
Open collector signal .
Turns to 0 if output voltage is outside the power good
window.
BST signal. Supply for high side driver.
Can be connected to a high enough voltage source.
Usually connected to bootstrap circuit.
Pin 20: (GND)
Analog GND.
Return of analog signals and bias of chip.
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SC1176/SC1176A
POWER MANAGEMENT
Block Diagram
NOTES
(1) Block 1 (top) is the Master and Block 2 (bottom) is the Slave in current sharing configuration.
(2) For independent operation there is no Master or Slave.
Applications Information - Theory of Operation
Main Loop(s)
their own voltage feedback path from their own
output. In this mode, the positive input of error
amplifier 2 is connected externally to Vref. If the
application uses a common input voltage, the
sawtooth phase shift between the channels
provides some measure of input ripple current
cancellation.
The SC1176 is a dual, voltage mode synchronous
Buck controller, the two separate channels are identi-
cal and share only IC supply pins (Vcc and GND),
output driver ground (PGND) and pre-driver supply
voltage (BSTC). They also share a common oscillator
generating a sawtooth waveform for channel 1 and an
inverted sawtooth for channel 2. Each channel has its
own current limit comparator. Channel 1 has the
positive input of the error amplifier internally connected
to Vref. Channel 2 has both inputs of the error ampli-
fier uncommitted and available externally. This allows
the SC1176 to operate in two distinct modes.
b) Two channels operating in current sharing
mode with common output voltage and either
common input voltage or different input voltages.
In this mode, channel 1 operates as a voltage
mode Buck controller, as before, but error amp 2
monitors and amplifies the difference in voltage
across the output current sense resistors of
channel 1 and channel 2 (Master and Slave) and
adjusts the Slave duty cycle to match output
currents. Because of finite gain and offsets in the
loop, the resistor ratio for perfect current match-
a) Two independent channels with either com-
mon or different input voltages and different
output voltages. The two channels each have
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6
SC1176/SC1176A
POWER MANAGEMENT
Applications Information - Theory of Operation
ing is not 1:1. The Master and Slave channels still
have their own current limits, identical to the
independent channel case.
The formula is:
5 − VOUT
Rpull−up (KΩ) = 2.1 X
VOUT + .1
Power Good
.5 −
VSLAVE
The controller provides a power good signal. This is an
open collector output, which is pulled low if the output
voltage is outside of the power good window.
100Ω being the value of the resistors connecting the
pins 2 and 3 to the two output sense resistors.
Soft Start/Enable
.1 V is an estimated voltage drop across the
MOSFETs.
The Soft Start/Enable (SS/ENA) pin serves several func-
tions. If held below the Soft Start Enable threshold, both
channels are inhibited. DH1 and DH2 will be low, turning
off the top FETs. Between the Soft Start Enable thresh-
old and the Soft Start End threshold, the duty cycle is
allowed to increase. At the Soft Start End threshold,
maximum duty cycle is reached. In practical applications
the error amplifier will be controlling the duty cycle be-
fore the Soft Start End threshold is reached. To avoid
boost problems during startup in current share mode,
both channels start up in asynchronous mode, and the
bottom FET body diode is used for recirculating current
during the FET off time. When the SS/ENA pin reaches
the Soft Start Transition threshold, the channels begin
operating in synchronous mode for improved efficiency.
The soft start pin sources approximately 25uA and soft
start timing can be set by selection of an appropriate
soft start capacitor value.
Positive values go to pin 3, negative to pin 2.
A +20K will be a 20K on pin 3.
A -20K will be a 20K on pin 2.
Now that the offset resistor has been fixed, we need to
set up the maximum current for each channel.
Selection of RSENSE 1 for the master channel: (in m
ohm)
RSENSE 1 = 72mV / I max master
Selection of RSENSE 2 for the slave channel: (in m ohm)
RSENSE 2 = 72mV / I max slave
SENSE RESISTOR SELECTION
Current Sharing Mode
The errors will be minimized if the power components
have been sized proportionately to the maximum
currents.
Calculation of the three programming resistors to achieve
sharing.
Independent Channels
Three resistors will determine the current sharing load
line.
Calculation of the two current limiting resistors.
There is no need for an offset resistor in the indepen-
dent channels mode, only the two sense resistors are
used:
First the offset resistor will ensure that the load line
crosses the origin (0 Amp on each channel) for sharing
at light current. A pull up resistor from the 5V bias (VCC of
the chip) will be used. For low duty cycle on the slave
channel (below 50%), the pull up will be on pin 3. For
high duty cycle on the slave channel (above 50%), the
pull up will be on pin 2.
Selection of RSENSE 1 for the channel 1: (in m ohm)
RSENSE 1 = 72mV / I max ch 1
Selection of RSENSE 2 for the channel 2: (in m ohm)
RSENSE 1 = 72mV / I max ch 2
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SC1176/SC1176A
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing
Figure 1: VOUT vs IIN(5V) and IIN(12V) with VCC applied and 4A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (1A/Div)
Ch4: IIN(12V) (1A/Div)
OUT: 4.004 Amps
I
Figure 2: VOUT vs IIN(5V) and IIN(12V) with VCC removed and 4A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (1A/Div)
Ch4: IIN(12V) (1A/Div)
IOUT: 4.004 Amps
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SC1176/SC1176A
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing (Cont.)
Figure 3: VOUT vs IIN(5V) and IIN(12V) with VCC applied and 12A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (2A/Div)
Ch4: IIN(12V) (2A/Div)
OUT: 12 Amps
I
Figure 4: VOUT vs IIN(5V) and IIN(12V) with VCC removed and 12A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (2A/Div)
Ch4: IIN(12V) (2A/Div)
IOUT: 12 Amps
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SC1176/SC1176A
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing (Cont.)
Figure 5: Efficiency data - current sharing mode.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
VIN(MASTER) = 12V
0.2
0.1
0.0
V
IN(SLAVE) = 5V
OUT = 2.75V
V
0
2
4
6
8
10
12
14
Current (A)
The Current Sharing Evaluation Board is not intended for a specific application. The power components are not
optimized for minimum cost and size. This evaluation board should be used to understand the operation of the
SC1176. To design with SC1176 for specific current sharing applications. Please refer to: Application note AN00-3.
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2006 Semtech Corp.
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SC1176/SC1176A
POWER MANAGEMENT
Evaluation Board Schematic - 2 Channel with Current Sharing
SC1176
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SC1176/SC1176A
POWER MANAGEMENT
Evaluation Board Bill of Materials - 2 Channels with Current Sharing
Item
1
Quantity
Reference
Part
2
3
3
1
3
6
2
1
1
2
2
1
7
2
1
1
1
1
C1,C7
.22uF, 50V
1uF, 50V
2
C2,C3,C4
C5,C15,C16
C8
3
10nF, 50V
1nF, 50V
4
5
C9,C10,C14
100uF, 6V
150uF, 16V
DL4148
6
C11,C12,C13,C17,C18,C19
7
D1,D2
8
L1
7.5uH, 8A
4.7uH, 8A
9
L2
10
11
12
13
14
15
16
17
18
M1,M3
IRF7809 or FDB7030
M2,M4
IRF7811 or FDB7030
R1
124
R2,R3,R4,R5,R6,R7,R8
2.2
R9,R10
R12
100
150
R13
.006
.003
SC1176
R14
U1
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SC1176/SC1176A
POWER MANAGEMENT
Evaluation Board Gerber Plots - 2 Channels with Current Sharing
Top Side Traces
Bottom Side Traces
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SC1176/SC1176A
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels
Output Current
Input Voltage = 12V @ 5Amps. 2A/DIV.
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SC1176/SC1176A
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels (Cont.)
Peak - Peak Output Ripple @ 5A
Input Voltage = 12V.
Output Voltage = 2.0V
Phase Node 12V Input @ 5A (without snubber and RC network.
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SC1176/SC1176A
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels (Cont.)
Start-up Power On
Chan. 1 = Output Current. 2A/DIV.
Chan. 2 = 5V Bias Voltage
Power Off
Chan. 1 = Output Current. 2A/DIV.
Chan. 2 = 5V Bias Voltage
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SC1176/SC1176A
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels Efficiency Test
100
95
Vin = 12V Vout =
90
85
80
75
70
2.0V
Vin = 5V Vout =
1.25V
0
1
2
3
4
5
6
OUTPUT CURRENT
The Independent Channels Evaluation Board is not intended for a specific application. The power components are
not optimized for minimum cost and size. This evaluation board should be used to understand the operation of the
SC1176. To design with the SC1176 for specific independent channels applications. Please refer to: Application
note AN00-4.
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2006 Semtech Corp.
17
SC1176/SC1176A
POWER MANAGEMENT
Evaluation Board Schematic - 2 Independent Channels
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2006 Semtech Corp.
18
SC1176/SC1176A
POWER MANAGEMENT
Evaluation Board Bill of Materials - 2 Independent Channels
Item
1
Quantity
Reference
Part
1uF, 50V
.22uF, 50V
1nF, 50V
10nF, 50V
150uF, 6V
100uF, 16V
DL4148
3
3
1
4
9
3
2
1
1
2
2
7
3
1
1
1
2
1
C1,C2,C3
C4,C6,C11
C5
2
3
4
C7,C8,C9,C10
5
C12,C13,C14,C15,C16,C17,C18,C19,C20
6
C21,C22,C23
7
D1,D2
8
L1
7.5uH, 8A
4.7uH, 8A
IRF7809 or FDB7030
IRF7811 or FDB7030
2.2
9
L2
10
11
12
13
14
15
16
17
18
M1,M3
M2,M4
R1,R2,R3,R4,R5,R6,R7
R8,R9,R13
R10
100
.006
R11
220
R12
.003
R14,R15
U1
124
SC1176
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19
SC1176/SC1176A
POWER MANAGEMENT
Evaluation Board Gerber Plots - 2 Independent Channels
Top Side Traces
Bottom Side Traces
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SC1176/SC1176A
POWER MANAGEMENT
Layout Guidelines
should be returned to the bottom MOSFET source to pro-
vide the best gate current return path. Analog ground
(GND) should be returned to the ground side of the out-
put capacitors so that the analog circuitry in the control-
ler has an electrically quiet reference and to provide the
greatest feedback accuracy. The problem is that the dif-
ferential voltage capability of the two IC grounds is lim-
ited to about 1V for proper operation and so the physical
separation between the two grounds must also be mini-
mized. If the grounds are too far apart, fast current tran-
sitions in the connection can generate voltage spikes
exceeding the 1V capability, resulting in unstable and er-
ratic behavior.
Power and signal traces must be kept separated for noise
considerations. Feedback, current sense traces and ana-
log ground should not cross any traces or planes carrying
high switching currents, such as the input loop or the
phase node.
The input loop, consisting of the input capacitors and
both MOSFETs must be kept as small as possible. All of
the high switching currents occur in this loop. The en-
closed loop area must be kept small to minimize induc-
tance and radiated and conducted emissions. Designing
for minimum trace length is not always the best approach,
often a more optimum layout can be achieved by keep-
ing loop area constraints in mind.
The feedback divider must be close to the IC and be
returned to analog ground. Current sense traces must
be run parallel and close to each other and to analog
ground.
It is important to keep gate lengths short, the IC must be
close to the power switches. This is more difficult in a
dual channel device than a single and requires that the
two power paths run on either side of a centrally located
controller.
The IC must have a ceramic decoupling capacitor across
its supply pins, mounted as close to the device as pos-
sible. The small ceramic, noise-filtering capacitors on the
current sense lines should also be placed as close to the
IC as possible.
Grounding requirements are always conflicting in a buck
converter, especially at high power, and the trick is to
achieve the best compromise. Power ground (PGND)
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SC1176/SC1176A
POWER MANAGEMENT
Outline Drawing - SOIC-20
DIMENSIONS
INCHES MILLIMETERS
A
D
E
e
DIM
A
N
MIN NOM MAX MIN NOM MAX
-
-
-
-
-
-
-
-
-
-
.093
.104 2.35
.012 0.10
.100 2.05
.020 0.31
.013 0.20
2.65
0.30
2.55
0.51
0.33
A1 .004
A2 .081
2X E/2
b
.012
.008
c
D
.500 .504 .508 12.70 12.80 12.90
E1 .291 .295 .299 7.40 7.50 7.60
E1
E
e
.406 BSC
10.30 BSC
1.27 BSC
.050 BSC
-
-
-
-
h
L
.010
.016
.030 0.25
.041 0.40
0.75
1.04
(.041)
(1.04)
L1
N
20
20
-
-
01
aaa
0°
8°
0°
8°
1
2
3
ccc
C
.004
.010
.013
0.10
0.25
0.33
2X N/2 TIPS
bbb
ccc
e/2
B
D
h
aaa C
A2
A
h
SEATING
H
PLANE
bxN
bbb
A1
C
C
A-B D
c
GAGE
PLANE
0.25
L
(L1)
01
SEE DETAIL
A
DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE-H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-013, VARIATION AC.
Land Pattern - SOIC-20
X
DIMENSIONS
DIM
INCHES
(.362)
.276
MILLIMETERS
(9.20)
7.00
C
G
P
X
Y
Z
(C)
G
Y
Z
.050
1.27
.024
0.60
.087
2.20
.449
11.40
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2.
REFERENCE IPC-SM-782A, RLP NO. 307A.
www.semtech.com
2006 Semtech Corp.
22
SC1176/SC1176A
POWER MANAGEMENT
Outline Drawing - TSSOP-20
DIMENSIONS
INCHES MILLIMETERS
A
DIM
A
D
E
MIN NOM MAX MIN NOM MAX
e
-
-
-
-
-
-
-
-
-
-
-
-
.047
1.20
0.15
1.05
0.30
0.20
N
A1 .002
A2 .031
.006 0.05
.042 0.80
.012 0.19
.007 0.09
2X E/2
b
c
D
.007
.003
.251 .255 .259 6.40 6.50 6.60
E1
E1 .169 .173 .177 4.30 4.40 4.50
PIN 1
E
e
.252 BSC
.026 BSC
6.40 BSC
0.65 BSC
INDICATOR
L
L1
N
.018 .024 .030 0.45 0.60 0.75
(.039)
(1.0)
ccc
1 2 3
C
e/2
20
20
2X N/2 TIPS
-
-
01
0
8
0
8
B
aaa
.004
.004
.008
0.10
0.10
0.20
bbb
ccc
D
aaa C
A2
A
SEATING
PLANE
H
C
A1
bxN
c
bbb
C A-B D
GAGE
PLANE
0.25
L
(L1)
01
DETAIL A
SEE DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE-H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
REFERENCE JEDEC STD MO-153, VARIATION AC.
4.
Land Pattern - TSSOP-20
X
DIMENSIONS
DIM
INCHES
(.222)
.161
MILLIMETERS
(5.65)
4.10
0.65
0.40
1.55
7.20
C
G
P
X
Y
Z
(C)
G
Y
Z
.026
.016
.061
.283
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2006 Semtech Corp.
23
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