SC1175 [SEMTECH]
Low Power Dual Synchronous DC/DC Controller With Current Sharing Circuitry; 低功耗双同步DC / DC控制器均流电路
| 型号： | SC1175 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Low Power Dual Synchronous DC/DC Controller With Current Sharing Circuitry |
| 文件： | 总20页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1175
Low Power Dual Synchronous DC/DC
Controller With Current Sharing Circuitry
POWER MANAGEMENT
Features
Description
The SC1175 is a versatile 2 phase, synchronous, voltage mode
PWM controller that may be used in two distinct ways. First, the
SC1175 is ideal for applications where point of use output power
exceeds any single input power budget. Alternatively, the SC1175
can be used as a dual switcher. The SC1175 features a tempera-
ture compensated voltage reference, over current protection with
50% fold-back and internal level-shifted, high-side drive circuitry.
u 300kHz fixed frequency operation
u Soft Start and Enable function
u Power Good output provided
u Over current protection with 50% fold-back
u Phase-shifted switchers minimize ripple
u High efficiency operation, >90%
u Programmable output(s) as low as 1.25V
u Industrial temperature range
In current sharing configuration, the SC1175 can produce a single
output voltage from two separate voltage sources (which can be
different voltage levels) while maintaining current sharing between
the channels. Current sharing is programmable to allow loading
each input supply as required by the application.
u SOIC 20 pin package
Two Phase, Current Sharing Controller
In dual switcher configuration, two feedback paths are provided
for independent control of the separate outputs. The device will
provide a regulated output from flexibly configured inputs (3.3V,
5V, 12V), provided 5V is present for VCC. The two switchers are
180° out of phase to minimize input and output ripple.
u Flexible, same or separate VIN
u Programmable current sharing
u Combined current limit with fold-back
u 2 phases operating opposed for ripple reduction
u Thermal distribution via multi-phase output
Applications
Two Independent PWM Controllers
u Graphics cards
u DDR Memory
u Peripheral add-in card
u SSTL Termination
u Dual-Phase power supply
u Power supplies requiring two outputs
u Flexible, same or separate VIN
u Independent control for each channel
u Independent and separate current limit
u 2 phases operating opposed for ripple reduction (if same
VIN used)
Typical Application Circuit
2 Channels with Current Sharing
1
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Revision 7/31/2000
SC1175
POWER MANAGEMENT
Absolute Maximum Rating
Parameter
VCC to GND
Symbol
Limits
-0.3 to 15
± 1
Units
V
VIN
PGND to GND
V
BST to GND
-0.3 to 26
30
V
q
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering) 10 sec
°C/W
JC
q
90
°C/W
°C
JA
TA
TJ
0 to 85
0 to 125
-65 to +150
300
°C
TSTG
TLEAD
°C
°C
Electrical Characteristics
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, 0mV < (CS(+) - CS(-)) < 60mV , TJ = 25°C
PARAMETER
CONDITIONS
MIN
TYP MAX UNITS
Output Voltage
Supply Voltage
Supply Current
IO = 2A(1), VOUT set to 2.75V
VCC
2.65
4.2
2.75
2.85
15
V
V
V
CC = 5.0
10
1.25
1
mA
1.2375-
± 1
1.2625-
± 1
Reference
V
Load Regulation
IO = 0.3A to 15A (1)
5V < VCC < 15V
5V < VIN < 15V
VOSENSE to VO
%
%
Reference Line Regulation
Output Line Regulation
Gain (AOL)
.5
.5
%
35
70
dB
mV
kHz
%
Current Limit Voltage
Oscillator Frequency
Oscillator Max Duty Cycle
DH Sink Current
60
270
90
1
80
300
95
330
DH - PGND = 3.5V
DH - PGND = 1.75V
BSTH - DH = 5.0V
BSTH - DH = 2.5V
A
DH Sink Current
.5
A
DH Source Current
DH Source Current
1
A
.5
A
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SC1175
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, 0mV < (CS(+) - CS(-)) < 60mV , TJ = 25°C
PARAMETER
CONDITIONS
MIN
TYP MAX UNITS
DL Sink Current
DL - PGND = 3.5V
DL - PGND = 1.75V
BSTL - DL = 5V
1
.5
1
A
A
A
A
DL Sink Current
DL Source Current
DL Source Current
Dead Time
BSTL - DL = 2.5V
.5
50
100
25
ns
µA
V
Soft Start Charge Current(2)
Soft Start Enable
0% duty cycle
100% duty cycle
Synchronous mode
1.4
Soft Start End
2.5
V
Soft Start Transition(2)
Power Good Window(3)
Fold Back Current
Fold Back Voltage Knee
Input Bias Current
3.3
V
+10
50%
%VOUT
ILIM
V
VOUT = 0V
I = ILIM
1.25
VOUT
1
-IN1, +IN2, -IN2
µA
NOTES:
(1) Specification refers to application circuit.
(2) The soft start pin sources 25µAto an external capacitor. The converter operates in synchronous mode above the soft
start transition threshold and in asynchronous mode below it.
(3) Power good is an open collector pulled low when the output voltage is outside the ±10% window.
(4) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1175
POWER MANAGEMENT
Pin Configuration
Ordering Information
DEVICE(1)
PACKAGE
SC1175CSW.TR
SO-20
CURRENT SHARE
VERSION EVALUATION
BOARD
SC1175EVB-1
DUAL CHANNEL
VERSION EVALUATION
BOARD
SC1175EVB-2
Notes:
(1) Only available in tape and reel packaging. A reel
contains 1000 devices
Marking Information
Pin Descriptions
EXPANDED PIN DESCRIPTION
Pin 1: (VREF)
Internal 1.25V reference
Connected to the + input of the master channel error
amplifier.
Pin 2: (+IN)
TOP
+ Input of slave channel error amplifier.
Connected to 1.25V reference (Pin 1) for the two
independent channel configuration.
Pin 3, 18: (-IN2, -IN1)
yyww = Datecode (Example: 9908)
xxxx = Semtech Lot # (Example: 90101)
- Inputs of close loop error amplifiers.
Works as a feedback inputs (For both modes).
Pin 4: (VCC)
VCC chip supply voltage.
15V maximum, 10mA typical.
Pin 9, 12: (DL2, DL1)
DL signal (Drive Low).
Gate drive for bottom MOSFETs.
Requires a small series resistor.
Pin 10: (PGND)
Power GND. Return of gate drive currents.
Pin 11: (BSTC)
Supply for bottom MOSFETs gate drive.
Pin 17: (SS/ENA)
Soft start pin. Internal current source connected to
external capacitor.
Inhibits the chip if pulled down.
Pin 19: (PWRGD)
Power good signal.
Open collector signal .
Turns to 0 if output voltage is outside the power good
window.
Pin 20: (GND)
Analog GND.
Return of analog signals and bias of chip.
Needs a 1µF ceramic multilayer decoupling capaci-
tor to GND (Pin 20).
Pin 5, 6,15, 16: (CL2-, CL2+, CL1+, CL1-)
Pins (-) and (+) of the current limit amplifiers for both
channels.
Connected to output current sense resistors. Com-
pares that sense voltage to internal 75mV reference.
Needs RC filter for noise rejection.
Pin 7, 14: (BST2, BST1)
BST signal. Supply for high side driver.
Can be connected to a high enough voltage source.
Usually connected to bootstrap circuit.
Pin 8, 13: (DH2, DH1)
DH signal (Drive High).
Gate drive for top MOSFETs.
Requires a small series resistor.
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SC1175
POWER MANAGEMENT
Block Diagram
NOTES
(1) Block 1 (top) is the Master and Block 2 (bottom) is the Slave in current sharing configuration.
(2) For independant operation there is no Master or Slave.
Applications Information
Theory of Operation
Main Loop(s)
output. In this mode, the positive input of error
amplifier 2 is connected externally to Vref. If the
application uses a common input voltage, the
sawtooth phase shift between the channels
provides some measure of input ripple current
cancellation.
The SC1175 is a dual, voltage mode synchronous
Buck controller, the two separate channels are
identical and share only IC supply pins (Vcc and
GND), output driver ground (PGND) and pre-driver
supply voltage (BSTC). They also share a common
oscillator generating a sawtooth waveform for chan-
nel 1 and an inverted sawtooth for channel 2. Each
channel has its own current limit comparator. Chan-
nel 1 has the positive input of the error amplifier
internally connected to Vref. Channel 2 has both
inputs of the error amplifier uncommitted and avail-
able externally. This allows the SC1175 to operate in
two distinct modes.
b) Two channels operating in current sharing
mode with common output voltage and either
common input voltage or different input voltages.
In this mode, channel 1 operates as a voltage
mode Buck controller, as before, but error amp 2
monitors and amplifies the difference in voltage
across the output current sense resistors of
channel 1 and channel 2 (Master and Slave) and
adjusts the Slave duty cycle to match output
currents. Because of finite gain and offsets in the
loop, the resistor ratio for perfect current match-
a) Two independent channels with either com-
mon or different input voltages and different
output voltages. The two channels each have
their own voltage feedback path from their own
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SC1175
POWER MANAGEMENT
Theory of Operation (Cont.)
The formula is:
ing is not 1:1. The Master and Slave channels still
have their own current limits, identical to the
independent channel case.
VOUT + .1
R (pull − up) = 100 Ω X 762 X .5 −
VSLAVE IN
Power Good
The controller provides a power good signal. This is
an open collector output, which is pulled low if the
output voltage is outside of the power good window.
100W being the value of the resistors connecting the
pins 2 and 3 to the two output sense resistors.
The estimated voltage drop across the MOSFETs is
0.1V.
Positive values go to pin 3, negative to pin 2.
If R (pull-up) = +20KW then place a 20WK resistor on
pin 3.
If R (pull-up) = -20KW then place a 20KW on pin 2.
Now that the offset resistor has been fixed, we need
to set up the maximum current for each channel.
Selection of RSENSE 1 for the master channel:
(mohms)
RSENSE 1 = 72mV / I max master
Selection of RSENSE 2 for the slave channel: (mohms)
RSENSE 1 = 48mV / I max master
The errors will be minimized if the power compo-
nents have been sized proportionately to the maxi-
mum currents.
Soft Start/Enable
The Soft Start/Enable (SS/ENA) pin serves several
functions. If held below the Soft Start Enable thresh-
old, both channels are inhibited. DH1 and DH2 will be
low, turning off the top FETs. Between the Soft Start
Enable threshold and the Soft Start End threshold,
the duty cycle is allowed to increase. At the Soft Start
End threshold, maximum duty cycle is reached. In
practical applications the error amplifier will be
controlling the duty cycle before the Soft Start End
threshold is reached. To avoid boost problems during
startup in current share mode, both channels start
up in asynchronous mode, and the bottom FET body
diode is used for recirculating current during the FET
off time. When the SS/ENA pin reaches the Soft Start
Transition threshold, the channels begin operating in
synchronous mode for improved efficiency. The soft
start pin sources approximately 25uA and soft start
timing can be set by selection of an appropriate soft
start capacitor value.
Independent Channels
Calculation of the two current limiting resistors.
There is no need for an offset resistor in the indepen-
dent channels mode, only the two sense resistors
are used:
Selection of RSENSE 1 for the channel 1: (mohms)
RSENSE 1 = 72mV / I max ch 1
SENSE RESISTOR SELECTION
Selection of RSENSE 2 for the channel 2: (mohms)
Current Sharing Mode
R
SENSE 1 = 72mV / I max ch 2
Calculation of the three programming resistors to
achieve sharing.
Three resistors will determine the current sharing
load line.
First the offset resistor will ensure that the load line
crosses the origin (0 Amp on each channel) for
sharing at light current. A pull up resistor from the 5V
bias (VCC of the chip) will be used. For low duty cycle
on the slave channel (below 50%), the pull up will be
on pin 3. For high duty cycle on the slave channel
(above 50%), the pull up will be on pin 2.
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing
Figure 1: VOUT vs IIN(5V) and IIN(12V) with VCC applied and 4A load. Soft start capacitor = 10nF.
PIN D
Ch1: VOUT
Ch2: IIN(5V) (1A/Div)
Ch4: IIN(12V) (1A/Div)
IOUT: 4.004 Amps
Figure 2: VOUT vs IIN(5V) and IIN(12V) with VCC removed and 4A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (1A/Div)
Ch4: IIN(12V) (1A/Div)
IOUT: 4.004Amps
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing (Cont.)
Figure 3: VOUT vs IIN(5V) and IIN(12V) with VCC applied and 12A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (2A/Div)
Ch4: IIN(12V) (2A/Div)
IOUT: 12Amps
Figure 4: VOUT vs IIN(5V) and IIN(12V) with VCC removed and 12A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (2A/Div)
Ch4: IIN(12V) (2A/Div)
IOUT: 12Amps
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing (Cont.)
Figure 5: Efficiency data - current sharing mode.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
VIN(MASTER) = 12V
VIN(SLAVE) = 5V
VOUT = 2.75V
0.2
0.1
0.0
0
2
4
6
8
10
12
14
Current (A)
The Current Sharing Evaluation Board is not intended for a specific application. The power components are not
optimized for minimum cost and size. This evaluation board should be used to understand the operation of the
SC1175.
To design with the SC1175 for specific current sharing applications. Please refer to: Application note AN00-3.
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SC1175
POWER MANAGEMENT
Evaluation Board Schematic - 2 Channel with Current Sharing
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SC1175
POWER MANAGEMENT
Evaluation Board Bill of Materials - 2 Channels with Current Sharing
Item
1
Quantity
Reference
Part
2
3
3
1
3
6
2
1
1
2
2
1
7
2
1
1
1
1
C1,C7
.22uF, 50V
1uF, 50V
2
C2,C3,C4
C5,C15,C16
C8
3
10nF, 50V
4
1nF, 50V
100uF, 6V
150uF, 16V
DL4148
5
C9,C10,C14
6
C11,C12,C13,C17,C18,C19
7
D1,D2
8
L1
7.5uH, 8A
4.7uH, 8A
9
L2
10
11
12
13
14
15
16
17
18
M1,M3
IRF7809 or FDB7030
M2,M4
IRF7811 or FDB7030
R1
124
R2,R3,R4,R5,R6,R7,R8
2.2
R9,R10
R12
100
150
R13
.006
.003
SC1175
R14
U1
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SC1175
POWER MANAGEMENT
Evaluation Board Gerber Plots - 2 Channels with Current Sharing
Top Side Traces
Bottom Side Traces
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels
Figure 6:
Figure 7: Output Current
Input Voltage = 12V @ 5Amps. 2A/DIV.
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels (Cont.)
Figure 8: Peak - Peak Output Ripple @ 5A
Input Voltage = 12V.
Output Voltage = 2.0V
Figure 9: Phase Node 12V Input @ 5A (without
snubber and RC network.
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels (Cont.)
Figure 10: Start-up Power On
Chan. 1 = Output Current. 2A/DIV.
Chan. 2 = 5V Bias Voltage
Figure 11: Power Off
Chan. 1 = Output Current. 2A/DIV.
Chan. 2 = 5V Bias Voltage
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels Efficiency Test
Figure 12:
100
95
Vin = 12V Vout =
2.0V
90
85
80
75
70
Vin = 5V Vout =
1.25V
0
1
2
3
4
5
6
OUTPUT CURRENT
The Independent Channels Evaluation Board is not intended for a specific application. The power components
are not optimized for minimum cost and size. This evaluation board should be used to understand the opera-
tion of the SC1175.
To design with the SC1175 for specific independent channels applications. Please refer to: Application note
AN00-4.
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SC1175
POWER MANAGEMENT
Evaluation Board Schematic - 2 Independent Channels
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SC1175
POWER MANAGEMENT
Evaluation Board Bill of Materials - 2 Independent Channels
Item
1
Quantity
Reference
Part
3
3
1
4
9
3
2
1
1
2
2
7
3
1
1
1
2
1
C1,C2,C3
C4,C6,C11
C5
1uF, 50V
.22uF, 50V
1nF, 50V
10nF, 50V
2
3
4
C7,C8,C9,C10
5
C12,C13,C14,C15,C16,C17,C18,C19,C20 150uF, 6V
6
C21,C22,C23
100uF, 16V
DL4148
7
D1,D2
8
L1
7.5uH, 8A
4.7uH, 8A
9
L2
10
11
12
13
14
15
16
17
18
M1,M3
IRF7809 or FDB7030
M2,M4
IRF7811 or FDB7030
R1,R2,R3,R4,R5,R6,R7
2.2
R8,R9,R13
R10
100
.006
220
R11
R12
.003
124
R14,R15
U1
SC1175
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SC1175
POWER MANAGEMENT
Evaluation Board Gerber Plots - 2 Independent Channels
Top Side Traces
Bottom Side Traces
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SC1175
POWER MANAGEMENT
PCB Layout
Analog ground (GND) should be returned to the
Power and signal traces must be kept separated for
noise considerations. Feedback, current sense traces
and analog ground should not cross any traces or
planes carrying high switching currents, such as the
input loop or the phase node.
ground side of the output capacitors so that the analog
circuitry in the controller has an electrically quiet
reference and to provide the greatest feedback accu-
racy. The problem is that the differential voltage
capability of the two IC grounds is limited to about 1V
for proper operation and so the physical separation
between the two grounds must also be minimized. If
the grounds are too far apart, fast current transitions in
the connection can generate voltage spikes exceeding
the 1V capability, resulting in unstable and erratic
behavior.
The feedback divider must be close to the IC and be
returned to analog ground. Current sense traces must
be run parallel and close to each other and to analog
ground.
The IC must have a ceramic decoupling capacitor
across its supply pins, mounted as close to the device
as possible. The small ceramic, noise-filtering capaci-
tors on the current sense lines should also be placed
as close to the IC as possible.
The input loop, consisting of the input capacitors and
both MOSFETs must be kept as small as possible. All
of the high switching currents occur in this loop. The
enclosed loop area must be kept small to minimize
inductance and radiated and conducted emissions.
Designing for minimum trace length is not always the
best approach, often a more optimum layout can be
achieved by keeping loop area constraints in mind.
It is important to keep gate lengths short, the IC must
be close to the power switches. This is more difficult
in a dual channel device than a single and requires
that the two power paths run on either side of a cen-
trally located controller.
Grounding requirements are always conflicting in a
buck converter, especially at high power, and the trick
is to achieve the best compromise. Power ground
(PGND) should be returned to the bottom MOSFET
source to provide the best gate current return path.
Outline Drawing - SO-20
Contact Information
Ref. MS-013AC
Contact Information
Semtech Corporation
Power Management Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
ECN00-1204
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