SC1153CSW [SEMTECH]

PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS; 可编程同步DC / DC控制器的先进的处理器


型号：	SC1153CSW
厂家：	SEMTECH CORPORATION
描述：	PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS 可编程同步DC / DC控制器的先进的处理器控制器
文件：	总7页 (文件大小：81K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

DESCRIPTION

FEATURES

The SC1153 is a low-cost, full featured, synchronous

voltage-mode controller designed for use in single

ended power supply applications where efficiency is of

primary concern. Synchronous operation allows for the

elimination of heat sinks in many applications. The

SC1153 is ideal for implementing DC/DC converters

needed to power advanced microprocessors, such as

Pentium^®lll, in both single and multiple processor con-

figurations. Internal level-shift, high-side drive circuitry,

and preset shoot-thru control, allows for use of inex-

pensive n-channel power switches.

•= ^{Low cost / full featured}

•= Synchronous operation

•= 5 Bit VID programmable output

•= On-chip power good and OVP functions

•= Designed to meet Intel VRM 8.4 (Pentium^®IlI)

•= 1.3V to 3.5V Range, 1% tolerance

APPLICATIONS

•= Pentium^®IlI Core Supply

•= Multiple Microprocessor Supplies

•= Voltage Regulator Modules (VRM)

•= Programmable Power Supplies

•= High Efficiency DC/DC Conversion

SC1153 features include an integrated 5-bit VID DAC,

temperature compensated voltage reference, triangle

wave oscillator, current limit comparator, frequency

shift over-current protection, and an accessible, inter-

nally compensated error amplifier. Power good signal-

ing, logic compatible shutdown, and over voltage pro-

tection are also provided.

ORDERING INFORMATION

DEVICE⁽¹⁾

PACKAGE TEMP. RANGE (T_J)

SO-20 0 - 125°C

SC1153CSW.TR

The SC1153 operates at a fixed 200KHz, providing an

optimum compromise between efficiency, external

component size, and cost.

Note:

(1) Only available in tape and reel packaging. A reel

contains 1000 devices.

PIN CONFIGURATION

BLOCK DIAGRAM

Top View

VCC CS-

CS+

SHUTDOWN

BSTH

CURRENT LIMIT

1.25V REF

UPPER FET

LEVEL SHIFT

AND DRIVE

70mV

VID4

D/A

VID3

VID2

PGNDH

OSCILLATOR

VID1

VID0

200kHz

VOSENSE

SHOOT-THRU

CONTROL

OPEN COLLECTORS

VCC

PWRGOOD

BSTL

ERROR

AMP

SYNCHRONOUS

FET DRIVE

(20-Pin SOIC)

OVP

PGNDL

GND

Pentium is a registered trademark of Intel Corporation

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Maximum

Units

V_CCto GND

PGND to GND

BST to GND

V_IN

-0.3 to 7

± 1

-0.3 to 15

Thermal Resistance

Junction to Case

°C/W

°C

θ_JC

θ_JA

Thermal Resistance

Junction to Ambient

Operating

Temperature Range

T_A

0 to 70

-65 to +150

300

Storage

Temperature Range

T_STG

T_LEAD

°C

Lead Temperature

(Soldering) 10 sec

°C

ELECTRICAL CHARACTERISTICS

Unless specified: V_CC= 4.75V to 5.25V; GND = PGND = 0V; FB = V_O; 0mV < (CS(+) - CS(-)) < 60mV; T_J= 25^oC

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Voltage

I_O= 2A⁽¹⁾

V_CC

See Output Voltage Table.

Supply Voltage

4.2

Supply Current

_CC= 5.0

Load Regulation

I_O= 0.3A to 15A⁽¹⁾

All VID codes⁽¹⁾

V_OSENSEto V_O

Line Regulation

0.5

200

Gain (A_OL)

kHz

Current Limit Voltage

Oscillator Frequency

Oscillator Max Duty Cycle

DH Sink/Source Current

DL Sink/Source Current

OVP Threshold Voltage

OVP Source Current

180

220

BST_H- DH = 4.5V, DH - PGND_H= 2V

BST_L- DL = 4.5V, DL - PGND_L= 2V

120

100

V_OVP= 3V

Power Good Threshold

Voltage

110

Dead Time

NOTE:

(1) Specification refers to application circuit (Figure 1.).

(2) This part is ESD sensitive. Use of standard ESD handling precautions is required.

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

PIN DESCRIPTION

Pin #

Pin Name

GND

Pin Function

Small Signal Analog and Digital Ground

Chip Supply Voltage

VCC

OVP

PWRGOOD⁽¹⁾

High Signal Out if V_O> Setpoint + 20%

Open collector logic output, high if V_Owithin 10% of setpoint

Current Sense Input (negative)

Current Sense Input (positive)

Power Ground for High Side Switch

High Side Driver Output

CS(-)

CS(+)

PGNDH

Not Connected

PGNDL

Power Ground for Low Side Switch

Low Side Driver Output

BSTL

Vcc for Low Side Driver (Boost)

Vcc for High Side Driver (Boost)

Logic Low shuts down the converter

Top end of internal feedback chain

Programming Input (MSB)

BSTH

SHUTDOWN⁽¹⁾

VOSENSE

VID4⁽¹⁾

VID3⁽¹⁾

VID2⁽¹⁾

VID1⁽¹⁾

VID0⁽¹⁾

Programming Input

Programming Input (LSB)

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

PIN CONFIGURATION

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

APPLICATION CIRCUIT

5mOhm

1000uF

C10

1000uF

5V IN

VCCP

4 uH

10k

1000uF

0.1uF

1N5817

1000uF

C12

0.1uF

1000uF

12V IN

R3 2.32k

C11

R4 1.00k

VCC

CS+

CS-

0.1uF

OVP

VID0

VID1

VID2

VID3

VID4

OVP

VOSENSE

VID0

VID1

PWRGOOD

VID4

VID2

VID3

BSTH

SHUTDOWN

GND

PGNDH

PGNDL

C13

0.1uF

BSTL

SC1153CS

SHUTDOWN

PWRGOOD

Pentium^®ll Power Supply

Figure 1.

MATERIALS LIST

Quantity Reference Part/Description

Vendor

Various

SANYO

Various

Notes

C1,C11-C13 0.1µF Ceramic

C2-C10

1000µF/6.3V

1N5817

MV-GX or equiv. Low ESR

4µH

8 Turns 16AWG on MICROMETALS T50-52D core

Q1, Q2

See notes

FET selection requires trade-off between efficiency

and cost. Absolute maximum R_DS(ON)= 22 mΩ

IRC

OAR-1 Series

5mΩ

Various

SEMTECH

10kΩ, 5%, 1/8W

2.32kΩ, 1%, 1/8W

1kΩ, 1%, 1/8W

10Ω, 5%, 1/8W

SC1153CS

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

OUTPUT VOLTAGE TABLE

Unless specified: V_CC= 5.00V; GND = PGND = 0V; FB = V_O; 0mV < (CS(+) - CS(-)) < 60mV; T_J= 25°C

PARAMETER

CONDITIONS

VID

MIN

TYP

MAX

UNITS

43210

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

11111

11110

11101

11100

11011

11010

11001

11000

10111

10110

10101

10100

10011

10010

10001

10000

Output Voltage

I_O= 2A in Application Circuit

(Figure 1)

1.287

1.336

1.386

1.435

1.485

1.534

1.584

1.633

1.683

1.732

1.782

1.832

1.881

1.931

1.980

2.030

1.980

2.079

2.178

2.277

2.376

2.475

2.574

2.673

2.772

2.871

2.970

3.069

3.168

3.267

3.366

3.465

1.300

1.350

1.400

1.450

1.500

1.550

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.000

2.100

2.200

2.300

2.400

2.500

2.600

2.700

2.800

2.900

3.000

3.100

3.200

3.300

3.400

3.500

1.313

1.364

1.414

1.465

1.515

1.566

1.616

1.667

1.717

1.768

1.818

1.868

1.919

1.969

2.020

2.070

2.020

2.121

2.222

2.323

2.424

2.525

2.626

2.727

2.828

2.929

3.030

3.131

3.232

3.333

3.434

3.535

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

CHARACTERISTIC CURVES

SC1153 Efficiency in Application Circuit (Figure 1).

100%

95%

90%

85%

80%

75%

70%

Vo=3.5V

3.0V

2.5V

1.8V

2.0V

Output Current (Amps)

SC1153 Regulation in Application Circuit (Figure 1).

-5

-10

-15

-20

-25

Output Current (Amps)

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

OUTLINE DRAWING SO-20

Ref. MS-013AC

THEORY OF OPERATION

The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting

input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by

the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the

triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal

oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200kHz.

The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive

signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals

are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has

turned off, and visa-versa.

The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an

overcurrent condition. The latch is reset at the start of each oscillator period.

The PWRGOOD and OVP signals are derived from the voltage at the VOSENSE pin by comparators fed from the

internal feedback chain.

ECN00-1346

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1153CSW [SEMTECH]

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