ACS8595 [SEMTECH]

Line Card Protection Switch for SONET/SDH AdvancedTCA Systems; 线路卡保护开关，用于SONET / SDH的AdvancedTCA系统


型号：	ACS8595
厂家：	SEMTECH CORPORATION
描述：	Line Card Protection Switch for SONET/SDH AdvancedTCA Systems 线路卡保护开关，用于SONET / SDH的AdvancedTCA系统开关
文件：	总12页 (文件大小：160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ACS8595 ATCA

Line Card Protection Switch for

SONET/SDH AdvancedTCA Systems

ADVANCED COMMUNICATIONS

Description

FINAL

Features

PRODUCT BRIEF

The ACS8595 ATCA is a highly integrated, single-chip

solution for “Hit-less” protection switching of SEC

(SDH/SONET Equipment Clock) + Sync clock “Groups”,

from Master and Slave SETS clock cards and a third

(Stand-by) source, for line cards/blades in a SONET or

SDH ATCA (Advanced Telecommuncications Computing

Architecture) Network Element. The ACS8595 has fast

activity monitors on the SEC clock inputs and will

implement automatic system protection switching against

the Master clock failure. The selection of the

Master/Slave input can be forced by a Force Fast Switch

pin. If both the Master and Slave input clocks fail, the

Stand-by “Group” is selected or, if no Stand-by is

available, the device enters Digital Holdover mode.

SONET/SDH applications up to OC-3/STM-1 bit rates

Switches between grouped inputs (SEC/Sync pairs)

Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz

multiples up to 155.52 MHz), plus Frame Sync/Multi-

Frame Sync

Outputs: Six SEC clocks at any of several spot frequen-

cies from 2 kHz up to 77.76 MHz via the TTL/CMOS

port and up to 311.04 MHz via the PECL/LVDS port

Modes for E3/DS3 and multiple E1/DS1 rate output

clocks

Generates 8 kHz Frame Sync and 2 kHz Multi-Frame

Sync output clocks with programmable pulse width

and polarity

Frequency translation of SEC input clock to different

The ACS8595 can perform frequency translation,

converting, for example, an 8 kHz SEC input clock from

the ATCA backplane into a range of spot frequencies from

2 kHz up to 311.04 MHz (up to 77.76 MHz on the

TTL/CMOS ports). The output frequency is independently

programmable on each of the six SEC output ports, so the

ACS8595 ATCA has the potential to supply simultanously

up to six different SEC frequencies, for example, to meet

the individual requirements of several Advanced

Mezzanine Cards (AMCs).

local line card clocks

Robust activity monitoring on all clock inputs

Supports Free-run, Locked and Digital Holdover

modes of operation

Automatic “Hit-less” source switchover on loss of

input

External force fast switch between SEC1/SEC2 inputs

Phase Build-out for output clock phase continuity dur-

ing input switchover

PLL “Locked” and “Acquisition” bandwidths individu-

The ACS8595 has one PECL/LVDS output port and five

TTL/CMOS ports. It also provides an 8 kHz Frame Sync

and a 2 kHz Multi-Frame Sync TTL/CMOS signal output

with programmable pulse width and polarity.

ally selectable from 18, 35 or 70 Hz

Serial interface for device set-up

IEEE 1149.1 JTAG Boundary Scan is supported.

Single 3.3 V operation, 5 V I/O compatible

Operating temperature (ambient) of -40 to +85°C

Available in 100-pin LQFP package

The ACS8595 includes a Serial Port, which can be SPI

compatible, providing access to the configuration and

status registers for device setup.

Lead (Pb)-free version (ACS8595T), RoHS and WEEE

Block Diagram

compliant

Figure 1 Block Diagram of the ACS8595 ATCA

3 x SEC/Sync Input Groups

SEC1 & SEC2:

SEC Outputs:

TTL/PECL/LVDS,

O1 (PECL/LVDS)

SEC3 and all Syncs

TTL only

O2 (TTL)

O3 (TTL)

O4 (TTL)

O5 (TTL)

O6 (TTL)

DPLL1

DPLL2

SEC1

Master

MUX

Input

SEC Port

Monitors

and

Input

Selection

Control

APLL2

APLL 1

SYNC1

Output

Port

Frequency

Selection

SEC2

Digital Feedback

APLL3

Slave

Selector

SYNC2

Sync Outputs:

E1/DS1

Synthesis

MFrSync 2 kHz (TTL)

FrSync 8 kHz (TTL)

SEC3

MUX

Stand-by

SYNC3

01 TO O6:

8 kHz

1.544/2.048 MHz

3.088/4.096 MHz

6.176/8.192 MHz

12.352/16.384 MHz

6.48 MHz (not O1)

19.44 MHz

25.92 MHz

34.368 MHz

38.88 MHz

44.736 MHz

SEC Inputs:

Programmable

Frequencies

2 kHz, 4 kHz,

N x 8 kHz

TCK

TDI

TMS

TRST

TDO

Chip

Clock

Generator

IEEE

1149.1

JTAG

Priority

Table

Serial Interface

Port

1.544/2.048 MHz

6.48 MHz

19.44 MHz

25.92 MHz

38.88 MHz

51.84 MHz

77.76 MHz

155.52 MHz (only O1)

TCXO or

311.04 MHz (only O1)

155.52 MHz

F8595_001BlockDia_01

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

Pin Diagram

FINAL

PRODUCT BRIEF

Table 1 Power Pins (cont...)

Pin No.

Symbol

I/O

Type

Description

Figure 2 ACS8595 Pin Diagram

20,

AGND3,

AGND4

Supply Ground: Analog ground for output

PLLs APLL2 and APPL1.

11,

15,

DGND1,

DGND2,

DGND3

Supply Ground: Digital ground for

components in PLLs.

49,

62,

84,

DGND4,

DGND5,

DGND6,

DGND7

Supply Ground: Digital ground for logic.

AGND1

NC1

NC26

PORB

SCLK

VDD5

VDD4

CSB

SDI

CLKE

TMS

NC25

NC24

NC23

NC22

DGND5

VDD3

NC21

TRST

VDD2

NC20

NC19

NC18

SYNC3

NC17

SEC3

SYNC2

IC1

NC2

AGND2

VA1+

NC3

32,

GND_DIFFa,

GND_DIFFb

Supply Ground: Digital ground for

differential ports.

INTREQ

NC4

REFCLK

DGND1

VD1+

VD3+

DGND3

DGND2

VD2+

NC5

SRCSW

VA2+

AGND3

NC6

Note...I = Input, O = Output, P = Power, TTL^U= TTL input with pull-up

resistor, TTL_D= TTL input with pull-down resistor.

ACS8595 ATCA

SONET/SDH LC/P

Table 2 Internally Connected and Not Connected Pins

Pin No.

Symbol

I/O

Type

Description

IC2

NC7

NC8

NC9

3, 22, IC1, IC2,

96,97, IC3, IC4,

98, 99 IC5, IC6,

Internally Connected: Leave to float.

2,4,

7,9,

NC1, NC2,

NC3,NC4,

Not Connected: Leave to float.

17,21, NC5,NC6,

23,24, NC7, NC8,

F8595LPB_002PINDIAG_02

25,26, NC9, NC10,

27,28, NC11, NC12,

29,36, NC13,NC14,

37,48, NC15, NC16,

53,55, NC17, NC18,

56,57, NC19, NC20,

60,63, NC21, NC22,

64,65, NC23, NC24,

66,75, NC25, NC26,

79,80, NC27, NC28,

81, 82, NC29, NC30,

Pin Description

Table 1 Power Pins

NC31

Pin No.

Symbol

I/O

Type

Description

12,16, VD1+, VD2+,

Supply Voltage: Digital supply to gates in

analog section, +3.3 Volts ±10%.

13,

VD3+

33,

VDD_DIFFa,

VDD_DIFFb

Supply Voltage: Digital supply for

differential output pins 19 and 20,

+3.3 Volts ±10%.

Table 3 Other Pins

Pin No.

Symbol

INTREQ

I/O

Type

Description

VDD5V

Digital Supply for +5 Volts Tolerance to

Input Pins. Connect to +5 Volts (±10%) for

clamping to +5 Volts. Connect to VDD for

clamping to +3.3 Volts. Leave floating for

no clamping. Input pins tolerant up to

+5.5 Volts.

TTL/CMOS Interrupt Request: Active High/Low

software Interrupt output.

REFCLK

SRCSW

TTL

Reference Clock: 12.800 MHz.

50, 58, VDD1, VDD2,

61, 71 VDD3, VDD4

72, 85, VDD5, VDD6,

Supply Voltage: Digital supply to logic,

+3.3 Volts ±10%.

Source Switching: Force Fast Source

Switching on SEC1 and SEC2.

VDD7

FrSync

TTL/CMOS Output Reference: 8 kHz Frame Sync

output.

VA1+

Supply Voltage: Analog supply to clock

multiplying PLL,

+3.3 Volts ±10%.

MFrSync

TTL/CMOS Output Reference: 2 kHz Multi-Frame Sync

output.

19, 91 VA2+, VA3+

Supply Voltage: Analog supply to output

PLLs APLL2 and APPL1, +3.3 Volts ±10%.

34,

O1POS,

O1NEG

LVDS/PECL Output Reference: Programmable, default

38.88 MHz, LVDS.

AGND1,

AGND2

Supply Ground: Analog grounds.

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

Table 3 Other Pins (cont...)

FINAL

PRODUCT BRIEF

Table 3 Other Pins (cont...)

Pin No.

Symbol

I/O

Type

Description

Pin No.

Symbol

SDO

I/O

Type

TTL

Description

40,

SEC1_POS,

SEC1_NEG

PECL/LVDS Input Reference: Programmable, default

19.44 MHz, PECL.

100

Interface Address: SPI compatible Serial

Data Output.

42,

SEC2_POS,

SEC2_NEG

PECL/LVDS Input Reference: Programmable, default

19.44 MHz PECL.

TTL/CMOS Output Reference: Programmable, disabled

by default.

SYNC1

TTL

(Master) Multi-Frame Sync 2 kHz Input:

Connect to 2 or 8 kHz Multi-Frame Sync

output of Master SETS.

TTL/CMOS Output Reference: Programmable, disabled

by default.

TTL/CMOS Output Reference: Programmable, default

19.44 MHz.

SEC1

SEC2

SYNC2

TTL

(Master) Input Reference: Programmable,

default 8 kHz.

TTL/CMOS Output Reference: Programmable, disabled

by default.

(Slave) Input Reference: Programmable,

default 8 kHz.

TTL/CMOS Output Reference: Programmable, disabled

by default.

(Slave) Multi-Frame Sync 2 kHz: Connect to

2 or 8 kHz Multi-Frame Sync output of Slave

SETS.

SONSDHB

TTL

SONET or SDH Frequency Select: Sets the

initial power-up state (or state after a

PORB) of the SONET/SDH frequency

selection registers, Reg. 34, Bit 2 and

Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4.

When set Low, SDH rates are selected

(2.048 MHz etc.) and when set High,

SONET rates are selected (1.544 MHz etc.)

The register states can be changed after

power-up by software.

SEC3

SYNC3

TRST

TTL

(Stand-by) Input Reference: External stand-

by reference clock source, programmable,

default 19.44 MHz.

(Stand-by) Input Reference: External stand-

by 2 or 8 kHz Multi-Frame Sync clock

source.

JTAG Control Reset Input: TRST = 1 to

enable JTAG Boundary Scan mode. TRST =

0 is Boundary Scan stand-by mode, still

allowing normal device operation (JTAG

logic transparent). NC if not used.

Introduction

The ACS8595 ATCA is a Line Card Protection device

designed to complement the Semtech SETS devices

which maintain the SETS functions in both SONET and

SDH Network Elements. The ACS8595 ATCA extends this

functionality on to the Line Card, for which it has been

specifically designed. The ACS8595 ATCA uses “Hit-less”

group switching between Master and Slave inputs or a

third (Stand-by) input group, to generate and maintain

accurate and stable SEC and frame synchronization pulse

outputs for distribution on the Line Card, typically for

Advanced Mezzaninie Cards (AMCs) on AdvancedTCA

equipment.

TMS

TTL

JTAG Test Mode Select: Boundary Scan

enable. Sampled on rising edge of TCK. NC

if not used.

CLKE

SCLK Edge Select: SCLK active edge select,

CLKE = 1, selects falling edge of SCLK to be

active.

SDI

TTL

Serial Interface Address: Serial Data Input.

CSB

Chip Select (Active Low): This pin is

asserted Low by the microprocessor to

enable the microprocessor interface.

SCLK

PORB

TTL

Serial Data Clock. When this pin goes High

data is latched from SDI pin.

Power-On Reset: Master reset. If PORB is

forced Low, all internal states are reset

back to default values.

The ACS8595 provides a simple, compact, yet flexible

solution, which can be easily tailored for use with a range

of transmission formats and rates, via software

configuration.

TCK

TDO

TTL

JTAG Clock: Boundary Scan clock input.

TTL/CMOS JTAG Output: Serial test data output.

Updated on falling edge of TCK.

The ACS8595 employs various mechanisms to maintain

the integrity of its output clocks when its input clocks fail

or fall below the required specification levels. By

TDI

TTL

JTAG Input: Serial test data Input. Sampled

on rising edge of TCK.

smoothing out the effects of these input anomalies, the

ACS8595 improves the overall stability and reliability of

Revision 2.00/October 2005 © Semtech Corp.

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

the downstream system synchronization, which

translates to improved quality of service.

FINAL

PRODUCT BRIEF

Input frequencies supported range from 2, 4, 8 kHz (and

n x 8 kHz) up to 155.52 MHz. Common E1, DS1,

OC-3/STM-1 and sub-divisions are supported as spot

frequencies to which the DPLLs will directly lock. Any input

frequency, up to 100 MHz, that is a multiple of 8 kHz can

also be locked to via a built-in programmable divider.

Refer to Table 4 for details of each input port.

The key architectural advantage that the ACS8595 has

over traditional solutions is in the use of Digital Phase

Locked Loop (DPLL) technology for precise and

repeatable performance over temperature or voltage

variations and between parts.

Input Locking Frequency Modes

Semtech can provide an Evaluation Board so that

designers can rapidly appraise the ACS8595 ATCA device

and see for themselves the benefits that a Semtech ATCA

solution can bring to their designs.

Each input port has to be configured to receive the

expected input frequency. To achieve this, three Input

Locking Frequency Modes are provided: Direct Lock,

Lock8K and DivN.

General Description

SEC Activity Monitors

A monitoring function constantly appraises the activity of

each input SEC, and reports anomalous behavior. Each of

the input monitors is individually configurable, allowing

flags or interrupts to be raised which can influence both

the operating state of the device, and which inputs are

available for selection by the PLL circuitry. Any Input SEC

which suffers a loss-of-activity will be declared as

unavailable.

Inputs

The ACS8595 SETS device has input ports for clock

groups from three sources, typically Master, Slave and

Stand-by, where each clock group comprises one SEC and

optionally one Sync signal. This means that when any SEC

input changeover is made, the corresponding Sync signal

changeover is also made. Master and Slave SEC inputs to

the device support TTL/CMOS and PECL/LVDS. The

Stand-by SEC and three Sync inputs are TTL/CMOS only.

Anomalies detected by the Activity Monitor are integrated

in a Leaky Bucket Accumulator. Occasional anomalies do

All the TTL/CMOS ports are 3 V and 5 V compatible (with not cause the accumulator to cross the alarm setting

clamping if required by connecting the VDD5V pin).

threshold, so the selected reference source is retained.

Table 4 Input Reference Source Selection and Priority Table

Port Name

SEC1 TTL

Channel Number

Input Port Technology

TTL/CMOS

Frequencies Supported

DefaultPriority

0011

Up to 100 MHz (see Note (i))

Default (SONET): 8 kHz Default (SDH): 8 kHz

SEC2 TTL

SEC1 DIFF

SEC2 DIFF

0100

0101

0110

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 8 kHz Default (SDH): 8 kHz

PECL/LVDS

PECL default

Up to 155.52 MHz (see Note (ii))

Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz

PECL/LVDS

Up to 155.52 MHz (see Note (ii))

PECL default

Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz

SYNC1

SYNC2

SEC3

0111

1000

1001

TTL/CMOS

2/4/8 kHz auto-sensing

n/a

Up to 100 MHz (see Note (i))

Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz

SYNC3

1010

TTL/CMOS

2/4/8 kHz auto-sensing

n/a

Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being

77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,

19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 bit 2, ip_sonsdhb).

(ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz (and 311.04 MHz for Output O1 only).

(iii) SEC1 TTL and SEC2 TTL ports are on pins SEC1 and SEC2. SEC1 DIFF (Differential) port uses pins SEC1POS and SEC1NEG, similarly

SEC2DIFF uses pins SEC2POS and SEC2NEG.

Revision 2.00/October 2005 © Semtech Corp.

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

FINAL

PRODUCT BRIEF

Persistent anomalies cause the alarm setting threshold to the Register Descriptions in the datasheet for advanced

be crossed and result in the selected SEC (and Sync)

being rejected.

features and more information.

DPLL1 Main Features

There is one Leaky Bucket Accumulator per SEC input.

Each Leaky Bucket Accumulator can be programmed with

a Bucket ID (0 to 3) which assigns to the Leaky Bucket the

corresponding Leaky Bucket Configuration (from four

available Configurations). Each Leaky Bucket

Configuration comprises the following programmable

parameters:

z Multiple E1 and DS1 outputs supported

z Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs

z Multiple phase loss and multiple phase detectors

z Direct PLL locking to common SONET/SDH input

frequencies or any multiple of 8 kHz

z Automatic mode switching between Free-run, Locked

z Bucket size

and Digital Holdover modes (states)

z Alarm trigger (set threshold)

z Alarm clear (reset threshold)

z Leak rate (decay rate

z Fast detection on input failure and entry into Digital

Holdover mode (holds at the last good frequency

value)

z Frequency translation between input and output rates

via direct digital synthesis

Phase Locked Loops (PLLs)

z High accuracy digital architecture for stable PLL

dynamics combined with an APLL for low jitter final

output clocks

Figure 1 shows the PLL circuitry which comprises two

Digital PLLs (DPLL1 and DPLL2), two output multiplying

and filtering Analog PLLs (APLL1 and APLL2), output

frequency dividers in an Output Port Frequency Selection

block, a Synthesis block, multiplexers MUX1 and MUX2,

and a feedback Analog PLL (APLL3). These functional

blocks and their interconnections are highly configurable,

via register control, providing a range of output

z Non-revertive mode

z Frame Sync pulse alignment

z Selectable automatic DPLL bandwidth control (auto

selects either Locked bandwidth, or Acquisition

bandwidth), or Locked DPLL bandwidth

frequencies and a choice of levels of jitter performance.

z Two programmable bandwidth controls:

• Locked bandwidth: 18, 35 or 70 Hz

• Acquisition bandwidth: 18, 35 or 70 Hz

The DPLLs give a stable and consistent level of

performance that can be easily programmed for different

dynamic behavior or operating range. They are not

affected by operating conditions or silicon process

variations. Digital Synthesis is used to generate all

required SONET/SDH output frequencies. The digital logic

operates at 204.8 MHz that is multiplied up from the

external 12.800 MHz oscillator module. Hence the best

resolution of the output signals from the DPLLs is one

204.8 MHz cycle or 4.9 ns.

z Programmable damping factor, (For optional faster

locking and peaking control) Factors = 1.2, 2.5, 5, 10

or 20

z Programmable DPLL pull-in frequency range

z Phase Build-out on source switching (hit-less source

switching), on/off

z Freeze Phase Build-out, on/off

Both of the DPLLs’ outputs can be connected to

multiplying and filtering APLLs. The outputs of these

APLLs are divided making a number of frequencies

simultaneously available for selection at the output clock

ports. The various combinations of DPLL, APLL,

Multiplexer and divider configurations allow for

generation of a comprehensive set of frequencies, as

listed in Table 5 and Table 6.

DPLL2 Main Features

The main features of DPLL2 are:

z Always locked to DPLL1

z Single programmable bandwidth control: 18, 35 or

70 Hz

z Programmable damping factor, (For optional faster

locking and peaking control) Factors = 1.2, 2.5, 5, 10

or 20.

DPLLs

z Digital feedback, on/off

DPLL1 is the more feature rich of the two DPLLs. The main

features of the two DPLLs are summarized here. Refer to z Output frequency selection

Revision 2.00/October 2005 © Semtech Corp.

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

FINAL

PRODUCT BRIEF

z DS3/E3 support (44.736 MHz / 34.368 MHz)

individually selectable. Output 01 is a differential port

(pins O1POS and O1NEG), and can be selected PECL or

LVDS. All other outputs are TTL/CMOS.

independent of rates from DPLL1

• Low jitter E1/DS1 options independent of rates

from DPLL1

Table 5 Output Port Frequencies and Technologies

• Frequencies of n x E1/DS1 including 16 and 12 x

E1, and 16 and 24 x DS1 supported

Output Port

Port Name

Frequencies Supported

Frequencies as per Table 6

Technology

LVDS/PECL

(LVDS default)

• Squelched (clock off)

O2, O3, O4, TTL/CMOS

O5 and O6

z Can provide the source for the 2 kHz and 8 kHz

outputs available at Outputs 01 to 06

FrSync

TTL/CMOS

FrSync, 8 kHz programmable pulse width and

polarity, see Reg. 7C.

z Can use its phase detector to measure the input

MFrSync

TTL/CMOS

MFrSync, 2 kHz programmable pulse width and

polarity, see Reg. 7C.

phase difference between two inputs

z Selectable digital feedback, on/off

Table 6 Output Frequencies/Lowest Jitter Configuration

(Typical Conditions)

Either the software or an internal state machine controls

the operation of DPLL1. The state machine for DPLL2 is

very simple and cannot be manually/externally controlled.

One additional feature of DPLL2 is the ability to measure

a phase difference between two inputs.

Jitter Level (typ)

Frequency (MHz)

rms (ps)

p-p (ns)

0.6

2 kHz

8 kHz

0.6

1.5

1.0

1.2

1.0

0.75

1.2

1.0

0.75

1.0

1.536

(not O5/O6)

250

150

220

150

110

220

110

3800

120

DPLL1 always produces an output at 77.76 MHz to feed

the APLL, regardless of the frequency selected at the

output pins or the locking frequency (frequency at the

input of the Phase and Frequency Detector — PFD).

1.544

2.048

2.0586667

2.316

(not O5/O6)

2.7306667

2.796

DPLL2 can be operated at a number of frequencies. This

is to enable the generation of extra output frequencies,

which cannot be easily related to 77.76 MHz. If DPLL2 is

enabled, it locks to the 8 kHz from DPLL1. This is because

all of the frequencies of operation of DPLL2 can be

divided to 8 kHz and this will ensure synchronization of

frequencies, from 8 kHz upwards, within the two DPLLs.

3.088

3.728

4.096

via Digital1 or Digital2 (not O1)

(not O5/O6)

4.296

1.0

0.6

1.0

1.5

1.0

0.6

1.2

2.6

0.75

1.6

1.0

1.5

0.75

1.2

2.6

1.0

0.75

0.6

1.6

1.0

1.5

0.75

0.6

1.2

1.0

0.75

4.86

(not O5/O6)

5.728

120

250

150

6.144

6.176

APLLs

6.48

8.192

220

760

110

250

110

250

110

220

760

120

110

There are three APLLs. APLL1 and APLL2 provide a lower

final output jitter reducing the 4.9 ns p-p jitter from the

digital down to 500 ps p-p and 60 ps rms as typical final

outputs measured broadband (from 10 Hz to 1 GHz). The

feedback APLL (APLL3) is selected by default; it provides

improved performance over the digital feedback.

8.2346667

9.264

10.922667

11.184

12.288

12.352

16.384

16.46933

17.184

18.528

19.44

Each APLL has its own divider. Each divider

simultaneously outputs a series of fixed ratios of its APLL

input. These divided outputs are available on Output Ports

O1 to O6.

21.84533

22.368

24.576

24.704

25.92

250

110

250

110

Outputs

The ACS8595 delivers eight output signals on the

following ports: Six clocks, one each on ports O1 to O6;

and two Sync signals, on ports FrSync and MFrSync.

Outputs O1 to O6 are independent of each other and are

32.768

34.368

37.056

220

120

110

Revision 2.00/October 2005 © Semtech Corp.

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

FINAL

PRODUCT BRIEF

Table 6 Output Frequencies/Lowest Jitter Configuration replacement source is available. Digital Holdover

(Typical Conditions) (cont...)

operates instantaneously, which means the DPLL freezes

at the frequency it was operating at the time of entering

Digital Holdover mode.

Jitter Level (typ)

rms (ps) p-p (ns)

0.6

Frequency (MHz)

38.88

44.736

110

250

900

150

760

1.0

1.5

4.5

1.0

2.6

0.6

1.2

1.0

0.75

0.6

1.0

4.5

2.6

1.6

1.0

0.75

0.6

Input Selection Priorities

49.152

49.408

51.84

(O5/O6 only)

(O1 only)

Each input SEC can be programmed with a priority

number (see Table 4) allowing references to be chosen

according to the highest priority valid input. Under normal

operation, the input SECs are selected automatically,

according to availability and in order of priority. For special

circumstances, such as chip or board testing, the

selection may be forced by configuration.

(O5/O6 only)

(O1 only)

65.536

68.736

74.112

77.76

(O5/O6 only)

(O1 only)

220

120

110

(O5/O6 only)

(O1 only)

The priority table is initially defined by the default

configuration and can be changed via the Serial interface

by the Network Manager. In this way, when all the defined

sources are active and valid, the source with the highest

programmed priority is selected but, if this source fails,

the next-highest source is selected, and so on.

89.472

98.304

98.816

131.072

137.472

148.224

155.52

311.04

(O5/O6 only)

(O1 only)

110

900

760

250

120

110

(O1 only)

(O5/O6 only)

(O1 only)

Table 4 gives details of the input reference ports. Specific

frequencies and priorities are set by configuration.

(O1 only)

Modes of Operation

Ultra Fast Switching

The device has three principle modes of operation:

SEC inputs are monitored using a leaky bucket approach

to allow source qualification criterion to be monitored. A

reference source is normally disqualified after the leaky

bucket monitor thresholds have been crossed. An option

for a faster disqualification has been implemented so that

a loss of activity of just a few reference clock cycles will

raise an alarm and cause a reference switch.

z Free-run

z Locked

z Digital Holdover

The Free-run mode is typically used following a power-on-

reset or a device reset before network synchronization

has been achieved. In the Free-run mode, the timing and

synchronization signals generated from the ACS8595 are

based on the 12.800 MHz clock frequency provided from

the external oscillator and are not synchronized to an

input SEC. The accuracy can be enhanced via software

calibration to within ±0.0196229 ppm.

External Forced Fast Protection Switching

External Forced Fast Protection Switching mode, for fast

switching between inputs SEC1 or SEC2, can be triggered

directly from the dedicated pin SRCSW.

Restoration

The Locked mode is used when an input SEC has been

selected and the PLL has had time to lock. When the

Locked mode is achieved, the output signal is in phase

and is locked to the selected input SEC. The priority table

determines which input SEC is selected. When the

ACS8595 is in Locked mode, the output frequency and

phase follows that of the selected input SEC.

Restoration of repaired reference sources is handled

carefully to avoid inadvertent disturbance of the output

clock. For this, the ACS8595 has two modes of operation;

Revertive and Non-revertive.

Sync Reference Sources

In Digital Holdover mode, the ACS8595 provides the

timing signals to maintain the Line Card when its currently The ACS8595 provides the facility to have a Sync

selected input source becomes invalid, and no other valid reference source associated with each SEC.

Revision 2.00/October 2005 © Semtech Corp.

Page7

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

The Sync inputs (SYNC1, SYNC2 and SYNC3) are used for

Frame Sync output alignment and can be 2, 4 or 8 kHz

(automatically detected frequency).

FINAL

PRODUCT BRIEF

Performance Benefits from DPLL/APLL Technology

The use of Digital Phase Locked Loop technology ensures

precise and repeatable performance over temperature or

voltage variations, and between parts. The overall PLL

bandwidth, loop damping, pull-in range and frequency

accuracy are all determined by digital parameters that

provide a consistent level of performance. An Analog PLL

takes the signal from the DPLL output and provides a

lower jitter output. The APLL bandwidth is set four orders

of magnitude higher than the DPLL bandwidth. This

ensures that the overall system performance still

maintains the advantage of consistent behavior provided

by the digital approach.

As in all the Semtech ACS85xx series of parts supporting

such a mechanism, the Sync is treated as an additional

part of the SEC clock. The failure of a Sync input will never

cause a source disqualification. The Sync input is used to

internally align the generation of the output 2 kHz and

8 kHz Sync pulses.

Serial Interface

The ACS8595 device has an SPI compatible serial

interface, providing access to the configuration and

status registers for device set-up and monitoring.

The DPLLs are clocked by the external oscillator module

therefore the Free-run or Digital Holdover frequency

stability is only determined by the stability of the external

oscillator module. This key advantage confines all

temperature critical components to one well defined and

pre-calibrated module, whose performance can be

chosen to match the application.

Performance

Conformance

All performance parameters of the DPLLs are

programmable without the need to understand detailed

PLL equations. Bandwidth, damping factor and lock

range, for example, can all be set directly.

The ACS8595 is designed for use in Line Cards in Network

Elements which must meet the requirements of the

following specifications:

ITU: G. 736, G.742, G.812, G.813, G.824, K.41.

A high level of phase and frequency accuracy is made

Telcordia: GR-253-CORE, GR-499-CORE, GR-1244-CORE. possible in the ACS8595 by an internal resolution of up to

ANSI: T1.101-1999.

ETSI: ETSI 300 462-3, ETSI 300 462-5.

54 bits and internal Holdover accuracy of up to

7.5 x 10^-14ppb (instantaneous).

Typical Application

Figure 3 Semtech’s Product Family Solution for a Typical SONET/SDH Architecture

Multiple Line cards

Line Card (0C-12, OC-48)

Recovered Clock

Master Clock

Master Sync

Slave Clock

Frame Sync

ACS8515

ACS8525

ACS8526

FRAMER

SERDES

Multi Frame Sync

Slave Sync

ACS8527

E1/DS1

To/from

SONET/SDH/PDH

Network

ACS8595 ATCA

Stand-by Clock

Stand-by Sync

LINE

Clock

Distribution

ACS8942A

JAM PLL

CARD

PROTECTION

Low Jitter/Low Skew

Low Jitter up to 622 MHz

Backplane

Slave Sync Card

Master Sync Card

Input CLK Sources

Config.

ACS8510

ACS8520

ACS8522

ACS8530

SETS

Priorities

TCLK

mP/Serial Bus

SSM

Priorities

Output

CLKs

CLK

Primary Ref.

Input/

output

SSM Handling

Function

Line

I/F

Unit

DATA

Clock

Distribution

DATA

SEC

SetsLinecardGenApp_08

Page8

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

FINAL

PRODUCT BRIEF

Table 7 Register Map

RO = Read Only

R/W = Read/Write

Data Bit

)

7 (MSB)

0 (LSB)

chip_id (RO)

00 4D

01 21

02 00

chip_id[7:0], 8 LSBs of Chip ID

chip_id[15:8], 8 MSBs of Chip ID

chip_revision[7:0]

chip_revision (RO)

test_register1 (R/W)

03 14 Phase_alarm

Disable_180

Resync_

analog

Set to 0

8K Edge

Polarity

Set to 0

test_register2 (R/W)

sts_interrupts (R/W)

04 12

05 FF

Do not use

status_SEC2_ status_SEC1_ status_SEC2_ status_SEC1_

DIFF

TTL

06 3F operating_

mode

DPLL1_main_

ref_failed

status_SEC3

sts_current_DPLL_frequency,

see OC/OD

07 00

Bits [18:16] of sts_current_DPLL_frequency

DPLL1_operating_mode

sts_interrupts (R/W)

08 10 Sync_alarm_

int

sts_operating_mode (RO)

sts_priority_table (RO)

09 01 Sync_alarm

DPLL2_Lock

DPLL1_freq_

soft_alarm

DPLL2_freq_

soft_alarm

0A 00

0B 00

Highest priority validated source

Currently selected source

3rd highest priority validated source

2nd highest priority validated source

sts_current_DPLL_frequency[7:0] 0C 00

Bits [7:0] of sts_current_DPLL_frequency

Bits [15:8] of sts_current_DPLL_frequencyy

(RO)

[15:8] 0D 00

[18:16] 07 00

0E 00

Bits [18:16] of sts_current_DPLL_frequency

SEC1 TTL

sts_sources_valid (RO)

SEC2 DIFF

SEC1 DIFF

SEC2 TTL

0F 00

SEC3

sts_reference_sources (RO)

Alarm Status on inputs:

No Activity

SEC2 TTL

Phase Lock

SEC2 TTL

No Activity

SEC1 TTL

Phase Lock

SEC1 TTL

SEC1 & SEC2 TTL 11 22

SEC1 & SEC2 DIFF 12 22

No Activity

SEC2 DIFF

Phase Lock

SEC2 DIFF

No Activity

SEC1 DIFF

Phase Lock

SEC1 DIFF

SEC3 14 22

No Activity

SEC3

Phase Lock

SEC3

cnfg_ref_selection_priority (R/W) 19 32

SEC1 & SEC2 TTL

programmed_priority_SEC2_TTL

programmed_priority_SEC2_DIFF

programmed_priority_SEC1_TTL

SEC1 & SEC2 DIFF 1A 00

SEC3 1C 04

programmed_priority_SEC1_DIFF

programmed_priority_SEC3

cnfg_ref_source_frequency_

<input> (R/W), where <input> =

SEC1 TTL 22 00 divn_SEC1 TTL lock8k_SEC1

Bucket_id_SEC1 TTL

Bucket_id_SEC2 TTL

Bucket_id_SEC1 DIFF

Bucket_id_SEC2 DIFF

Bucket_id_SEC3

reference_source_frequency_SEC1 TTL

reference_source_frequency_SEC2 TTL

reference_source_frequency_SEC1 DIFF

reference_source_frequency_SEC2 DIFF

TTL

SEC2 TTL 23 00 divn_SEC2 TTL lock8k_SEC2

TTL

SEC1 DIFF 24 03 divn_SEC1

DIFF

lock8k_SEC1

DIFF

SEC2 DIFF 25 03 divn_SEC2

DIFF

lock8k_SEC2

DIFF

SEC3 28 03 divn_SEC3

lock8k_SEC3

reference_source_frequency_SEC3

DPLL1_operating_mode

cnfg_operating_mode (R/W)

32 00

33 0F

force_select_reference_source

(R/W)

forced_select_SEC_input

cnfg_input_mode (R/W)

cnfg_DPLL2_path (R/W)

cnfg_differential_inputs (R/W)

34 CA auto_extsync_ phalarm_

XO_ edge

extsync_en

ip_sonsdhb

reversion_

mode

timeout

35 A0

36 03

DPLL2_dig_

feedback

SEC2_DIFF_

PECL

SEC1_DIFF_

PECL

cnfg_dig_outputs_sonsdh (R/W)

cnfg_digtial_frequencies (R/W)

cnfg_differential_output (R/W)

cnfg_auto_bw_sel

38 04

39 08

3A C2

dig2_sonsdh

dig1_sonsdh

digital1_frequency

digital2_frequency

Output O1 _LVDS_PECL

3B 98 auto_BW_sel

DPLL1_lim_int

Page9

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

Table 7 Register Map (cont...)

FINAL

PRODUCT BRIEF

RO = Read Only

R/W = Read/Write

cnfg_nominal_frequency

(R/W)

Data Bit

)

7 (MSB)

0 (LSB)

[7:0] 3C 99

[15:8] 3D 99

Bits[7:0] of cnfg_nominal_frequency

Bits[15:8] of cnfg_nominal_frequency

Bits[7:0] of cnfg_DPLL_freq_limit

cnfg_DPLL_freq_limit (R/W) [7:0] 41 76

cnfg_DPLL_freq_limit (R/W) [9:8] 42 00

Bits[9:8] of

cnfg_DPLL_freq_limit

cnfg_interrupt_mask (R/W) [7:0] 43 00 Set to 0

Set to 0

SEC2 DIFF

SEC1 DIFF

SEC2 TTL

SEC1 TTL

Set to 0

[15:8] 44 00 operating_

mode

main_ref_

failed

SEC3

[23:16] 45 00 Sync_ip_alarm

cnfg_freq_divn (R/W)

cnfg_monitors (R/W)

[7:0]. 46 FF

[13:8] 47 3F

48 04

divn_value [7:0] (divide Input frequency by n)

divn_value [13:8] (divide Input frequency by n)

los_flag_on_

TDO

ultra_fast_

switch

ext_switch

PBO_freeze

PBO_en

cnfg_registers_source_select

(R/W)

4B 00

DPLL1_DPLL2

_select

cnfg_freq_lim_ph_loss

freq_lim_ph_

loss

cnfg_upper_threshold_0 (R/W)

cnfg_lower_threshold_0 (R/W)

cnfg_bucket_size_0 (R/W)

cnfg_decay_rate_0 (R/W)

50 06

51 04

52 08

53 01

upper_threshold_0_value (Activity alarm, Config. 0, Leaky Bucket - set threshold)

lower_threshold_0_value (Activity alarm, Config. 0, Leaky Bucket - reset threshold)

Bucket_size_0_value (Activity alarm, Config. 0, Leaky Bucket - size)

decay_rate_0_value (Activity

alarm, Config. 0, Leaky Bucket -

leak rate)

cnfg_upper_threshold_1 (R/W)

cnfg_lower_threshold_1 (R/W)

cnfg_bucket_size_1 (R/W)

cnfg_decay_rate_1 (R/W)

54 06

55 04

56 08

57 01

upper_threshold_1_value (Activity alarm, Config. 1, Leaky Bucket - set threshold)

lower_threshold_1_value (Activity alarm, Config. 1, Leaky Bucket - reset threshold)

Bucket_size_1_value (Activity alarm, Config. 1, Leaky Bucket - size)

decay_rate_1_value (Activity

alarm, Config. 1, Leaky Bucket -

leak rate)

cnfg_upper_threshold_2 (R/W)

cnfg_lower_threshold_2 (R/W)

cnfg_bucket_size_2 (R/W)

cnfg_decay_rate_2 (R/W)

58 06

59 04

5A 08

5B 01

upper_threshold_2_value (Activity alarm, Config. 2, Leaky Bucket - set threshold)

lower_threshold_2_value (Activity alarm, Config. 2, Leaky Bucket - reset threshold)

Bucket_size_2_value (Activity alarm, Config. 2, Leaky Bucket - size)

decay_rate_2_value (Activity

alarm, Config. 2, Leaky Bucket -

leak rate)

cnfg_upper_threshold_3 (R/W)

cnfg_lower_threshold_3 (R/W)

cnfg_bucket_size_3 (R/W)

cnfg_decay_rate_3 (R/W)

5C 06

5D 04

5E 08

5F 01

upper_threshold_3_value (Activity alarm, Config. 3, Leaky Bucket - set threshold)

lower_threshold_3_value (Activity alarm, Config. 3, Leaky Bucket - reset threshold)

Bucket_size_3_value (Activity alarm, Config. 3, Leaky Bucket - size)

decay_rate_3_value (Activity

alarm, Config. 3, Leaky Bucket -

leak rate)

cnfg_output_frequency (R/W)

Outputs O4 & 03

60 00

output_freq_O4

output_freq_O3

OutputsO5 & O2 61 06

OutputsO1 & 06 62 80

output_freq_O5

output_freq_O1

output_freq_O2

output_freq_O6

(MFrSync/FrSync) 63 C0 MFrSync_en

cnfg_DPLL2_frequency (R/W) 64 00

65 01 DPLL2_meas_ APLL2_for_

FrSync_en

DPLL2_frequency

DPLL1_frequency

cnfg_DPLL1_frequency (R/W)

DPLL1_freq_to_APLL2

DPLL1_ph

DPLL1_E1/DS

cnfg_DPLL2_bw (R/W)

66 00

67 10

69 11

6A 13

6B 13

DPLL2_bandwidth

cnfg_DPLL1_locked_bw (R/W)

cnfg_DPLL1_acq_bw (R/W)

cnfg_DPLL2_damping (R/W)

cnfg_DPLL1_damping (R/W)

cnfg_DPLL2_PD2_gain (R/W)

DPLL1_locked_bandwidth

DPLL1_acquisition_bandwidth

DPLL2_damping

DPLL2_PD2_gain_alog_8k

DPLL1_PD2_gain_alog_8k

DPLL2_PD2_gain_alog

DPLL1_damping

6C C2 DPLL2_PD2_

gain_enable

DPLL2_PD2_gain_digital

cnfg_DPLL1_PD2_gain (R/W)

6D C2 DPLL1_PD2_

gain_enable

DPLL1_PD2_gain_alog

DPLL1_PD2_gain_digital

Page10

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

Table 7 Register Map (cont...)

FINAL

PRODUCT BRIEF

RO = Read Only

R/W = Read/Write

Data Bit

)

7 (MSB)

0 (LSB)

cnfg_phase_offset (R/W)

[7:0] 70 00

[15:8] 71 00

phase_offset_value [7:0]

phase_offset_value[15:8]

cnfg_PBO_phase_offset (R/W)

72 00

PBO_phase_offset

cnfg_phase_loss_fine_limit (R/W) 73 A2 fine_limit_en

noact_ph_loss narrow_en

wide_range_ multi_ph_resp

phaseloss_en en

phase_loss_fine_limit

cnfg_phase_loss_coarse_limit

(R/W)

74 85 coarse_lim_

phase_loss_coarse_limit

cnfg_ip_noise_window (R/W)

76 06 ip_noise_

window_en

sts_current_phase (RO)

[7:0] 77 00

[15:8] 78 00

current_phase[7:0]

current_phase[15:8]

cnfg_phase_alarm_timeout

(R/W)

79 32

timeout_value (in two-second intervals)

cnfg_sync_pulses (R/W)

cnfg_sync_phase (R/W)

cnfg_sync_monitor (R/W)

cnfg_interrupt (R/W)

7A 00 2k_8k_from_

DPLL2

8k_invert

8k_pulse

2k_invert

2k_pulse

7B 00 Indep_FrSync/ Sync_OC-N_

Sync_phase_SYNC3

Sync_monitor_limit

Sync_phase_SYNC2

Sync_phase_SYNC1

MFrSync

rates

7C 2B ph_offset_

ramp

7D 02

Interrupt

GPO_en

Interrupt

tristate_en

Interrupt

int_polarity

cnfg_protection(R/W)

7E 85

protection_value

Page11

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ACS8595 ATCA

ADVANCED COMMUNICATIONS

FINAL

PRODUCT BRIEF

Ordering Information

Table 8 Parts List

Part Number

Description

ACS8595

ATCA Line Card Protection Switch for SONET/SDH AdvancedTCA Systems

Lead (Pb)-free package version of ACS8595; RoHs and WEEE compliant

Evaluation Board and Software

ACS8595T

ACS8595 EVB

Disclaimers

Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical

applications. This product is not authorized or warranted by Semtech for such use.

Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised

to obtain the latest version of the relevant information before placing orders.

Compliance to relevant standards- Operation of this device is subject to the User’s implementation and design practices. It is the

responsibility of the User to ensure equipment using this device is compliant to any relevant standards.

Contacts

For Additional Information, contact the following:

Semtech Corporation Advanced Communications Products

E-mail:

Internet:

USA:

sales@semtech.com

acsupport@semtech.com

http://www.semtech.com

200 Flynn Road, Camarillo, CA 93012-8790

Tel: +1 805 498 2111, Fax: +1 805 498 3804

FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C.

Tel: +886 2 2748 3380 Fax: +886 2 2748 3390

EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way,

Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN

Tel: +44 (0)1794 527 600

Fax: +44 (0)1794 527 601

ISO9001

CERTIFIED

Page12

www.semtech.com

ACS8595 [SEMTECH]

相关型号：

ACS8595EVB

ACS8595T

ACS86D

ACS86D/SAMPLE

ACS86D/SAMPLE-02

ACS86DMSR

ACS86DMSR-02

ACS86HMSR

ACS86HMSR-02

ACS86K

ACS86K/SAMPLE

ACS86K/SAMPLE-02