S1C05250 [SEIKO]
TELEPHONE CALLING NO IDENT CKT, PDSO24, PLASTIC, SOP1-24;
| 型号： | S1C05250 |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | TELEPHONE CALLING NO IDENT CKT, PDSO24, PLASTIC, SOP1-24 电信 光电二极管 电信集成电路 |
| 文件： | 总36页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MF1220-02
CMOS CALLING NUMBER IDENTIFICATION RECEIVER IC
S1C05250
Technical Manual
S1C05250 Technical Hardware
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
All the product names mentioned herein are trademarks and/or registered trademarks of their respective owners.
© SEIKO EPSON CORPORATION 2001 All rights reserved.
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
Devices
S1
C
63158
F
0A01
00
00
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 63000 A1
C
1
Packing specification
2
Version (1: Version 1
)
1
)
Tool type (A1: Assembler Package
Corresponding model number
(63000: common to S1C63 Family)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
2: Actual versions are not written in the manuals.
Comparison table between new and previous number
S1C63 Family processors
S1C63 Family peripheral products
Previous No.
E0C63158
E0C63256
E0C63358
New No.
S1C63158
S1C63256
S1C63358
Previous No.
E0C63467
E0C63557
E0C63558
E0C63567
New No.
Previous No.
E0C5250
E0C5251
New No.
S1C05250
S1C05251
S1C63467
S1C63557
S1C63558
S1C63567
E0C63P366 S1C6P366
E0C63404
E0C63406
E0C63408
S1C63404
S1C63406
S1C63408
E0C63F567 S1C6F567
E0C63658
E0C63666
S1C63658
S1C63666
E0C63F408 S1C6F408
E0C63F666 S1C6F666
E0C63454
E0C63455
E0C63458
E0C63466
S1C63454
S1C63455
S1C63458
S1C63466
E0C63A08
E0C63B07
E0C63B08
E0C63B58
S1C63A08
S1C63B07
S1C63B08
S1C63B58
E0C63P466 S1C6P466
Comparison table between new and previous number of development tools
Development tools for the S1C63 Family
Development tools for the S1C63/88 Family
Previous No.
ADP63366
ADP63466
ASM63
New No.
Previous No.
New No.
S5U1C63366X
S5U1C63466X
S5U1C63000A
ADS00002
S5U1C88000X1
GWH00002 S5U1C88000W2
URM00002 S5U1C88000W1
GAM63001 S5U1C63000G
ICE63 S5U1C63000H1
PRC63001 S5U1C63001P
PRC63002 S5U1C63002P
PRC63004 S5U1C63004P
PRC63005 S5U1C63005P
PRC63006 S5U1C63006P
PRC63007 S5U1C63007P
URS63366 S5U1C63366Y
CONTENTS
CONTENTS
1 Overview.......................................................................................................................1
1.1 Features......................................................................................................................................................................1
1.2 Block Diagram...........................................................................................................................................................2
1.3 Pin Assignment.........................................................................................................................................................2
1.4 Pin Description..........................................................................................................................................................3
2 Power Supply Block and Initial Reset ...........................................................................5
2.1 Power Supply............................................................................................................................................................5
2.2 Initial Reset.................................................................................................................................................................5
3 Functional Description..................................................................................................6
3.1 Register Description................................................................................................................................................6
3.2 Input Amp Circuit...................................................................................................................................................11
3.3 Ring/Line Reversal Signal Detection.............................................................................................................12
3.4 FSK Demodulation...............................................................................................................................................12
3.5 Dual-Tone Detection............................................................................................................................................13
4 Precautions on Mounting............................................................................................14
5 Electrical Characteristics ............................................................................................16
5.1 Absolute Maximum Ratings..............................................................................................................................16
5.2 Recommended Operating Conditions...........................................................................................................16
5.3 DC Characteristics................................................................................................................................................16
5.4 Current Consumption...........................................................................................................................................16
5.5 Crystal Oscillation Characteristics...................................................................................................................17
5.6 FSK Demodulation Circuit Characteristics...................................................................................................17
5.6.1 FSK AC Characteristics...................................................................................................................17
5.6.2 FSK Switching Characteristics.......................................................................................................17
5.7 Dual-Tone (CAS) Detection Circuit Characteristics.................................................................................18
5.7.1 CAS AC Characteristics...................................................................................................................18
5.7.2 CAS Switching Characteristics......................................................................................................18
5.8 Call Progress Mode (CPM) Detection Circuit Characteristics..............................................................19
5.8.1 CPM AC Characteristics...................................................................................................................19
5.8.2 CPM Switching Characteristics......................................................................................................19
5.9 Serial Interface Circuit Characteristics..........................................................................................................20
5.9.1 Serial Interface AC Characteristics..............................................................................................20
5.9.2 FSK Demodulated Data Read Mode..........................................................................................21
5.9.3 CAS Detection Circuit Control-Register Write Mode.............................................................21
5.10 S1C05250 Timing Chart...................................................................................................................................22
5.10.1 Bellcore On-Hook Data Transfer................................................................................................22
5.10.2 Bellcore Off-Hook Data Transfer................................................................................................22
5.10.3 BT Idle State CLI Service.............................................................................................................23
5.10.4 BT Loop State CLI Service..........................................................................................................23
5.11 External Wiring Diagram (Example)............................................................................................................24
5.11.1 Example of Bellcore-Compatible Telephone Circuit............................................................24
5.11.2 Example of Bellcore-Compatible Auxiliary Circuit................................................................25
S1C05250 TECHNICAL MANUAL
EPSON
i
CONTENTS
6 Package...................................................................................................................... 26
7 Pad Layout.................................................................................................................. 27
7.1 Pad Layout Diagram............................................................................................................................................27
7.2 Pad Coordinates...................................................................................................................................................27
ii
EPSON
S1C05250 TECHNICAL MANUAL
1
OVERVIEW
1 Overview
The S1C05250 (CAS + FSK IC) is a CMOS IC for calling number identification with a Call Waiting function.
It provides an interface to various call information delivery services based on Bellcore GR-30-CORE, such as CND
(Calling Number Delivery), CNAM (Calling Name Delivery), and CIDCW (Calling Identity on Call Waiting), as
well as British Telecom’s CLIP (Calling Line Identification Service)andCableCommunications Association’s CDS
(Caller Display Service).
The S1C05250 incorporates power-down, ring detection, and carrier detection circuits, a synchronous receive data
output function, and a clock-synchronized serial interface. All these features make itsuitablefor various applications
such as those listed below.
• Calling number delivery service with a Call Waiting function
• Telephone sets and similar auxiliary equipment
• Telephone answering equipment
• Multifunction telephones
• Facsimiles
• Computer peripheral circuits
1.1 Features
• Conforms to Bellcore GR-30-CORE and SR-TSV-002476
• Conforms to British Telecom SIN227 and SIN242
• Can detect Bellcore CPE alert signal (CAS) and British Telecom idle-tone alert signal using a programmable
band-pass filter
• FSK demodulation circuit based on ITU-T V.23 and BELL202
• Filter bypass mode to detect call progress mode (CPM) signal
• Programmable alert-signal detection level
• Carrier/ring detection output
• Supports 3.57945 MHz crystal oscillator or external clock input
• Serial-receive data output
• Serial host interface
• Power-down mode
• Power supply voltage:
• Operating temperature range: -20°C to 70°C
• Current consumption: 3 mA when operating
1 µA during power-down
• Shipping form: SOP1-24pin package (plastic) or chip
2.7 V to 5.5 V
S1C05250 TECHNICAL MANUAL
EPSON
1
1
OVERVIEW
1.2 Block Diagram
BPOUT
CDIN
Data/timing
recovery
circuit
–
INN
INP
FB
Band-pass
filter
FSK
demodulator
SDO
Amp
+
CAS tone
filter
Identification
circuit
Detection
circuit
#DET
VREF
#RDET
#RDRC
RDIN
VDD/2
#PQUAL
#IRQ
VDD
Interrupt
control circuit
To other blocks
VDD
VSS
SDI
Timing
generator
Control circuit
#SCLK
OSC3 OSC4
PDWN #RESET MODE
Figure 1.2.1 Block diagram
1.3 Pin Assignment
SOP1-24pin
1
24
S1C05250
12
13
No.
1
Pin name
INP
No.
Pin name
No.
13
14
15
16
17
18
Pin name
OSC3
OSC4
N.C.
No.
19
20
21
22
23
24
Pin name
#SCLK
SDI
7
8
#RDET
PDWN
#RESET
N.C.
2
INN
3
FB
9
SDO
4
VREF
10
11
12
#PQUAL
#DET
CDIN
5
RDIN
#RDRC
MODE
VSS
BPOUT
VDD
6
#IRQ
Figure 1.3.1 Pin assignment
2
EPSON
S1C05250 TECHNICAL MANUAL
1
OVERVIEW
1.4 Pin Description
Note: The signal and pin names prefixed by # in this manual are those of active-low signals and pins.
Table 1.4.1 Pin description
Power-down
Pin name Pin No.
Type
Description
state
Off
INP
INN
FB
1
2
3
4
Input
Analog
Positive input: Non-inverted amp input
Connect this pin to the RING side of the twisted-pair telephone line
through an input-gain setting resistor and DC-decoupling capacitor. In
power-down mode, this pin is disconnected from the internal circuit.
Negative input: Inverted amp input
Input
Analog
Off
Connect this pin to the TIP side of the twisted-pair telephone line
through an input-gain setting resistor and DC-decoupling capacitor. In
power-down mode, this pin is disconnected from the internal circuit.
Amp output
Output
Analog
High-Z
Connect a feedback resistor to set the gain between this pin and the
INN pin. In power-down mode, this pin goes to a high-impedance
state.
VREF
Output
Analog
VDD level Reference voltage output
This pin outputs a voltage that is 1/2 of VDD. Connect this pin to VSS
via a 0.1-µF capacitor. In power-down mode, this pin outputsa voltage
equal to VDD.
RDIN
5
6
Schmitt
trigger input
Active
Active
Ring detection input
For ring detection, attenuate the ring signal before inputting it to this
pin. This input circuit remains active even in power-down mode.
Ring detection RC pin
Connect an RC network to this pin and set the delay time for ring
signal detection. This output circuit remains active even in power-
down mode.
#RDRC
Open-drain
output
Schmitt
trigger input
Output
#RDET
PDWN
7
8
Active
Active
Ring detection output
This pin outputs the #RDRC signal after it is passed through a
Schmitt trigger buffer. Upon detection of the ring signal, this pin
changes to Low level.
Input
Power-down input
This pin must be held at Low level during normal operation. When the
pin is set to High level, the S1C05250 is placed in power-down mode.
During power-down mode, each pin on the S1C05250 is placed in the
state shown in this table.
#RESET
MODE
9
Input
Input
Active
Active
Reset input
All of the internal registers are reset to the default state when the pin
is set to Low level. Before any data can be written to the internal
registers, this pin must be set to High level.
11
Mode selection input: Selects CAS mode or FSK/CPM mode
CAS mode is selected by setting this input to High level, so that CAS
detection is enabled while FSK function/CPM detection is disabled.
Also, in this state, data can be written from the host device to the
internal registers using the SDI and #SCLK pins. Note that before
writing data to the internal registers, the serial interface must be
synchronized to the data write sequence by temporarily setting this
pin to Low level.
FSK/CPM mode is selected by setting this input to Low level, in which
case CAS detection is disabled and FSK function/CPM detection is
enabled. In this state, the host device can read out receive data from
the SDO pin.
VSS
12
13
Power supply
Negative power-supply pin
Connect this pin to the ground line of the system.
Crystal oscillator input/external clock input
(-)
OSC3
Input
Off
Connect a crystal resonator between this pin and the OSC4 pin and an
appropriate capacitance between this pin and the VSS pin. This pin
can also be used for external clock input. In power-down mode, this
pin is disconnected from the internal circuit.
S1C05250 TECHNICAL MANUAL
EPSON
3
1
OVERVIEW
Power-down
Pin name Pin No.
Type
Description
state
OSC4
14
Output
High level Crystal oscillator output
Connect a crystal resonator between this pin and the OSC3 pin and an
appropriate capacitance between this pin and the VSS pin. When
connecting external clock input to the OSC3 pin, leave this pin open.
During power-down mode, this pin changes to High level.
#PQUAL
#DET
16
17
Output
Output
High level Prequalify output
The prequalify status of the CAS tone can be monitored from this pin
in CAS mode. This pin returns to High level when the CAS tone is not
detected.
Active
Detection output
During power-down mode, this pin changes to Low level when a ring
signal is input or pulled to Low level by the Line Reversal signal.
During normal operation in FSK mode, this pin goes toLowlevel when
an FSK signal is input. During normal operation in CPM mode,this pin
outputs the input signal in pulse form at the amplitude level of VDD
and VSS. By measuring the frequency of the pulse from the host side,
the CPM (dial) tone can be identified. During normal operation in CAS
mode, this pin goes to Low level when a CAS tone signal is input.
Interrupt request output
In power-down mode, this pin changes to Low level when a ring signal
is input or pulled to Low level by the Line Reversal signal. During
normal operation in FSK mode, this pin changes to Low level when
receive data is latched into the internal register and is ready to be
read by the host. Then, when the host reads the first bit of the receive
data, this pin returns to High level. During normal operation in CPM
mode, this pin changes to Low level when a signal with a frequency of
200 Hz or above, such as the dial tone, is input. During normal
operation in CAS mode, this pin changes to Low level when the CAS
tone is detected. This pin is held at Low level while the CAS tone is
being input.
#IRQ
18
Open-drain
output
Active
#SCLK
19
Input
Active
Active
Serial clock input
When the host writes to the internal register or reads receive data, a
clock signal is fed from the host into this pin. The receive data read
out by the host is sequentially shifted at falling edges of the clock
signal fed to this pin.
SDI
20
21
Input
Serial data input
When the host writes to the internal register, the write data is input
from this pin.
SDO
Output
High level Serial data output
This pin outputs the receive data read out by the host. When
asynchronous mode is selected, data in asynchronous mode is
output. When synchronous mode is selected, data is output
synchronously with the clock signal fed to the #SCLK pin by the host.
In power-down, CPM, or CAS mode, this pin is held at High level.
Capacitor connecting pin
BPOUT
CDIN
22
23
Input
Analog
VREF
Connect a 0.1-µF capacitor between this pin and the CDIN pin.
Capacitor connecting pin
Output
High-Z
Analog
Connect a 0.1-µF capacitor between this pin and the BPOUT pin.
Positive power supply
VDD
24
Power supply
Open
N.C.
10,15
Unconnected
4
EPSON
S1C05250 TECHNICAL MANUAL
2
POWER SUPPLY BLOCK AND INITIAL RESET
2 Power Supply Block and Initial Reset
2.1 Power Supply
The following shows the operating power supply voltage of the S1C05250.
Power supply voltage: 2.7 V to 5.5 V
The S1C05250 is operated in the above voltage range by a single power supply that is connected between VDD and
VSS. The voltage required for internal operation (VREF = 1/2 VDD) is generated by the IC itself.
VDD
R
External
power
supply
+
–
+
VREF
VSS
–
R
Figure 2.1.1 Power supply block
2.2 Initial Reset
The S1C05250 contains control registers that can be accessed by the external CPU through a serial interface. The
control registers are initialized by an initial reset which is applied from the #RESET pin.
Control register
R
Write control circuit
R
#RESET
MODE
Figure 2.2.1 Initial reset circuit
Specifically, the control registers are reset by pulling the #RESET pin to Low level (VSS) from outside of the IC.
Then, the reset state is eliminated by releasing the #RESET pin back to High level (VDD). Also, the write control
circuit for the control register is reset when the #RESET pin or MODE pin isat Low level. Before datacan be written
to the control register, both #RESET and MODE must be at High level.
S1C05250 TECHNICAL MANUAL
EPSON
5
3
FUNCTIONAL DESCRIPTION
3 Functional Description
3.1 Register Description
The S1C05250 contains eight 4-bit registers that can be accessed by the CPU.
The CPU can access these CPU interface registers through the serial interface pins (SDI, #SCLK, and MODE) and
control the mode of the S1C05250. The CPU uses the first four bits of transmit data to specify the address A[3:0] of
the internal register to be accessed. The data is transmitted beginning with the LSB (A0). The four bits that follow
the LSB are data bits D[3:0] which are the data to be written to the specified register. This data is also transmitted
beginning with the LSB (D0).
Table 3.1.1 shows registers and control bit assignments.
Table 3.1.1 Register structure
Register
name
MDR
GLR
Address
A[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Data bit
Initial value
D3
TEST
GL3
GH3
TL3
X
D2
D1
D0
0000
0100
0100
0110
XXX1
X011
0001
0001
FSK/CPM
GL2
Bellcore/BT ASYNC/SYNC
GL1
GH1
TL1
X
GL0
GH0
TL0
GHR
TLR
GH2
TL2
THR
X
TH0
AV0
WL0
WH0
AVR
X
AV2
AV1
WL1
WH1
WLR
WHR
WL3
WH3
WL2
WH2
6
EPSON
S1C05250 TECHNICAL MANUAL
3
FUNCTIONAL DESCRIPTION
Each register is detailed below.
MDR: Mode Register (Address = 0h)
Table 3.1.2 MDR register
Description
Initial
value
0
Bit
D0
Bit name
ASYNC/SYNC
Asynchronous/synchronous mode selection
This bit is used to select asynchronous or synchronous mode.
ASYNC/SYNC bit
Mode
0
1
Selects asynchronous mode
Selects synchronous mode
Asynchronous mode is selected by setting this bit to 0, in which case the 8-bit
serial data output from the SDO pin is forwarded in asynchronous mode.
Synchronous mode is selected by setting this bit to 1. When the FSK signal is
received in FSK mode, serial data is output from the SDO pin and read by the
CPU synchronously with the clock signal fed from the CPU to the #SCLK pin.
Also, in synchronous mode, when the receive data is ready for output, the #IRQ
pin changes to Low level, indicating that the CPU can read the data.
Bellcore/BT selection
D1
Bellcore/BT
0
This bit is used to select Bellcore or BT (British Telecom) mode.
Bellcore/BT bit
Mode
0
1
Selects Bellcore mode
Selects BT mode
When this bit is set to 0, the gain in the dual-tone filter is set directly by the GLR
and GHR registers.
When this bit is set to 1, the value set by the GLR and GHR registers plus 6 dB is
set as the gain in the dual-tone filter.
D2
FSK/CPM
0
CPM mode selection
This bit is used to select FSK or CPM mode when the MODE pin is low.
FSK/CPM bit
Mode
0
1
Selects FSK mode
Selects CPM mode
If this bit is set to 1 when the MODE pin is held at Low level (FSK/CPMmode),the
receive filter is bypassed, and when the CPM tone is input to the INP/INN pin, the
#IRQ pin goes to Low level. Also, since the pulse generated from the CPM tone
signal is output from the #DET pin, the CPM (dial) tone can be identified by
measuring the frequency of the pulse.
If this bit is set to 0 when the MODE pin is held at Low level (FSK/CPMmode),the
FSK function is enabled.
When the MODE pin is high (CAS mode), settings on this pin do not affect the
device operation.
D3
TEST
0
Test mode selection
This bit is used to test the IC. This bit normally must be fixed to 0.
S1C05250 TECHNICAL MANUAL
EPSON
7
3
FUNCTIONAL DESCRIPTION
GLR: Low-Tone Gain Setting Register (Address = 1h)
Table 3.1.3 GLR register
Initial
value
Bit
Bit name
Description
D0
D1
D2
D3
GL0
GL1
GL2
GL3
0100 Low-tone filter gain selection
These bits control gain in the 2,130-Hz tone filter.
GL3 GL2 Gain (dB) GL1 GL0 Gain (dB)
0
0
1
1
0
1
0
1
0
-4
-8
0
0
1
1
0
1
0
1
0
-1
-2
-3
-12
GL1 and GL0 change the gain in increments of 1 dB, whereas GL3 and GL2
change the gain in increments of 4 dB. The alert-tone detection level is attenuated
(sensitivity is lowered) by an amount equal to the total gain set here.
GHR: High-Tone Gain Setting Register (Address = 2h)
Table 3.1.4 GHR register
Initial
value
Bit
Bit name
Description
D0
D1
D2
D3
GH0
GH1
GH2
GH3
0100 High-tone filter gain selection
These bits control gain in the 2,750-Hz tone filter.
GH3 GH2 Gain (dB) GH1 GH0 Gain (dB)
0
0
1
1
0
1
0
1
0
-4
-8
0
0
1
1
0
1
0
1
0
-1
-2
-3
-12
GH1 and GH0 change the gain in increments of 1 dB, whereas GH3 and GH2
change the gain in increments of 4 dB. The alert-tone detection level is attenuated
(sensitivity is lowered) by an amount equal to the total gain set here.
8
EPSON
S1C05250 TECHNICAL MANUAL
3
FUNCTIONAL DESCRIPTION
TLR, THR: Detection Threshold Setting Registers (Address = 3h, 4h)
Table 3.1.5 TLR and THR registers
Initial
value
Bit
Bit name
Description
D0
D1
D2
D3
D0
D1
D2
D3
TL0
TL1
TL2
TL3
TH0
X
0110 CAS detection threshold selection
These bits control the minimum duration of tone with which the CAS tone is
identified. TH0 (THR register bit 0) is the MSB of the threshold set.
TH0 TL3 TL2 TL1 TL0 Threshold value (msec)
XXX1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
9
12
16
19
21
23
26
29
32
34
36
39
43
46
48
50
53
56
59
61
64
67
70
73
76
78
81
84
87
90
X
X
Invalid (Cannot be set)
The bit setting 10110 corresponds to Bellcore and British Telecom Loop State
service; the bit setting 11001 corresponds to British Telecom Idle State service.
AVR: Average Divide-Ratio Select Register (Address = 5h)
Table 3.1.6 AVR register
Initial
value
Bit
Bit name
Description
D0
D1
D2
D3
AV0
AV1
AV2
X
X011 Average counter divide-ratio selection
These bits control the frequency divide ratio of the internal average counter.
Setting to 011 is recommended.
AV2 AV1 AV0
Divide ratio
1/1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1/2
1/4
1/8
1/16
1/32
1/64
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FUNCTIONAL DESCRIPTION
WLR: Low-Tone Record Window Select Register (Address = 6h)
Table 3.1.7 WLR register
Initial
value
Bit
Bit name
Description
D0
D1
D2
D3
WL0
WL1
WL2
WL3
0001 Low-tone window width selection
These bits are used the low-tone record window width of the identification block.A
tone can be identified when one cycle of it is within the specified range.
WL3 WL2 WL1 WL0
Window width (%)
0.51, -0.50
0.57, -0.56
0.63, -0.62
0.69, -0.68
0.75, -0.74
0.81, -0.80
0.87, -0.85
0.93, -0.91
0.99, -0.97
1.06, -1.03
1.12, -1.09
1.18, -1.15
1.24, -1.20
1.30, -1.26
1.36, -1.32
1.42, -1.38
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit setting 0001 is Bellcore’s default value. Bit setting 0010 corresponds to British
Telecom Loop State service and setting 1100 corresponds to British Telecom Idle
State service.
WHR: High-Tone Record Window Select Register (Address = 7h)
Table 3.1.8 WHR register
Initial
value
Bit
Bit name
Description
D0
D1
D2
D3
WH0
WH1
WH2
WH3
0001 High-tone window width selection
These bits are used to select the high-tone record window width of the
identification block. A tone can be identified when one cycle of it is within the
specified range.
WH3 WH2 WH1 WH0
Window width (%)
0.51, -0.49
0.59, -0.56
0.67, -0.64
0.75, -0.71
0.83, -0.79
0.90, -0.86
0.98, -0.94
1.06, -1.02
1.14, -1.09
1.22, -1.17
1.30, -1.24
1.37, -1.32
1.45, -1.39
1.53, -1.46
1.61, -1.54
1.69, -1.61
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit setting 0001 is Bellcore’s default value. Bit setting 0010 corresponds to British
Telecom Loop State service and setting 1001 corresponds to British Telecom Idle
State service.
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FUNCTIONAL DESCRIPTION
3.2 Input Amp Circuit
The amp at the input stage must have its circuit configured to allow gain to be set correctly. For this reason, it
requires five to six external resistors.
FB
VREF
R4
R6
R5
INN
INP
R2
R1
–
TIP
To filter
Amp
+
RING
R3
VREF
VREF
Figure 3.2.1 Input amp circuit
The gain in the input amp can be set depending on values R1 to R6 as shown below. Note that R3 and R5 may be
replaced by one resistor.
R 5
R 1
R 6
R 2
G A MP =
=
[times]
(W hen R 1 = R 2, R 3 = R 4, R 5 = R 6)
To set the FSK and CAS tone signal-detection levels, determine each resistance value with respect to VDD as shown
below.
R 5
R 1
R 6
R 2
VD D
5
G A MP =
=
=
× 0.562 [times]
VDD is the power supply voltage fed to the VDD pin of the S1C05250. For R3 and R4, Seiko Epson recommends
using a resistance of about 100 kΩ for noise prevention.
Tables 3.2.1 and 3.2.2 show typical resistance values and amp gain for the case where VDD = 5 V and VDD = 3 V,
respectively.
Table 3.2.1 Resistance values and gain (VDD = 5 V)
Value
Parameter
Condition
Bellcore
499 kΩ
BT
499 kΩ
R1, R2
R3, R4
R5, R6
1%
1%
1%
100 kΩ
100 kΩ
281 kΩ
281 kΩ
Input amp gain
0.562 times (-5dB)
-42.9 dBm
-44.9 dBm
-35.8 dBm
0.562 times (-5dB)
-45.1 dBV
-47.1 dBV
-44.0 dBV
FSK/CPM - CD ON level (Typ.)
FSK/CPM - CD OFF level (Typ.)
CAS - CD ON level (Typ.)
Tone filter gain = -4dB
Condition
Table 3.2.2 Resistance values and gain (VDD = 3 V)
Value
Parameter
Bellcore
499 kΩ
100 kΩ
168 kΩ
BT
R1, R2
R3, R4
R5, R6
499 kΩ
100 kΩ
168 kΩ
1%
1%
1%
Input amp gain
0.3372 times (-9.4dB) 0.3372 times (-9.4dB)
FSK/CPM - CD ON level (Typ.)
FSK/CPM - CD OFF level (Typ.)
CAS - CD ON level (Typ.)
-42.9 dBm
-44.9 dBm
-35.8 dBm
-45.1 dBV
-47.1 dBV
-44.0 dBV
Tone filter gain = -4dB
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FUNCTIONAL DESCRIPTION
3.3 Ring/Line Reversal Signal Detection
Figure 3.3.1 shows a typical circuit used to detect the Bellcore ring signal andBritish Telecom Line Reversal signal.
When the S1C05250 is in power-down mode, this circuit detects the ring signal or Line Reversal signal. The Line
Reversal or ring signal causes the voltage on the RDIN pin to rise, which drives the Schmitt rigger outputhigh. This
causes the Nch transistor to turn on and the #RDRC pin to change to Low level. Since the RDIN pin is normally at
the VSS level, the #RDRC pin is at the High level. When the ring signal is input or the Line Reversal signal is
generated, the capacitor of the #RDRC pin discharges, causing the #RDRC pin to change state from High to Low.
The #RDET pin operates in the same way, except that in any mode other than power-down mode, the #RDET pin
always responds to input on the RDIN pin.
0.2 µF
TIP
470 kΩ
RDIN
VDD
33 kΩ
270 kΩ
VDD
RING
#RDRC
0.2 µF
0.2 µF
#RDET
VDD
#IRQ
#DET
Figure 3.3.1 Ring/Line Reversal signal detection circuit
3.4 FSK Demodulation
The received FSK-modulated signal, after being processed by the band-pass filter, is demodulated by the FSK
demodulation circuit. If the FSK signal is input when the PDWN pin is set to Low level and FSK mode has been
selected by the host CPU, the #DET pin changes to Low level. The received data is read out from the SDO pin by
the host CPU. Also, the #IRQ pin is driven Low each time one byte is received. This demodulation circuit supports
a FSK-modulated signal that conforms to ITU-T V.23 or Bell202.
Table 3.4.1 FSK data characteristics
Parameter
Mark frequency
Bellcore
1200 Hz ±1%
2200 Hz ±1%
BT
1300 Hz ±1.5%
2100 Hz ±1.5%
Space frequency
Receive signal level
Mark: -32 dBm to -12 dBm Mark: -40 dBV to -14 dBV
Space: -36 dBm to -12 dBm Space: -36 dBV to -8 dBV
Signal distortion
Transfer rate
≥ 25 dB
≥ 20 dB
1200 baud ±1%
1200 baud ±1%
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FUNCTIONAL DESCRIPTION
3.5 Dual-Tone Detection
Dual tones (Bellcore CPE alert signal (CAS), British Telecom tone alert signal) are detected using two tone filters
and digital identification circuits. If dual tones are received when the PDWN pin is set low and CAS mode has been
selected by the host CPU, the #DET pin and the #IRQ pin changes to Low level.
Table 3.5.1 Dual-tone characteristics
Bellcore
BT (tone alert signal)
Line disconnected Line connected
2130 Hz ±1.1% 2130 Hz ±0.6%
Parameter
(CPE alert signal)
Low tone frequency
High tone frequency
Receive signal level
2130 Hz ±0.5%
2750 Hz ±0.5%
-32 dBm to -14 dBm/tone,
off-hook
2750 Hz ±1.1%
-40 dBV to -2 dBV/tone,
on-hook
2750 Hz ±0.6%
-40 dBV to -8 dBV/tone,
off-hook
Rejection signal level
Receive tone twist
Tone output time
Simultaneous voice
reception
≤ -45 dBm
≤ -46 dBV
0 to 6 dB
0 to 7 dB
0 to 7 dB
75 msec to 85 msec
Yes
88 msec to 110 msec
No
80 msec to 85 msec
Yes
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PRECAUTIONS ON MOUNTING
4 Precautions on Mounting
<Oscillation Circuit>
● Oscillation characteristics change depending on conditions (board pattern, components used, etc.).
In particular, when a crystal oscillator is used, use the oscillator manufacturer's recommended values for
constants such as capacitance.
● Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to
prevent this:
(1) Components which are connected to the OSC3, OSC4 terminals, such as oscillators and capacitors, should
be connected in the shortest line.
(2) As shown in the right hand figure, make a VSS pattern as large as possible at circumscription of the OSC3,
OSC4 terminals and the components connected to these terminals.
Furthermore, do not use this VSS pattern for any purpose other than the oscillation system.
Sample VSS pattern
OSC4
OSC3
VSS
(3) When supplying an external clock to the OSC3 terminal, the clock source should be connected to the OSC3
terminal in the shortest line.
Furthermore, do not connect anything else to the OSC4 terminal.
● In order to prevent unstable operation of the oscillation circuit due to current leak between OSC3 and VDD,
please keep enough distance between OSC3 and VDD or other signals on the board pattern.
<Power Supply Circuit>
● Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent
this:
(1) The power supply should be connected to the VDD, VSS and VREF terminals with patterns as short and large
as possible.
(2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be
connected as short as possible.
Bypass capacitor connection example
VDD
VSS
VDD
VSS
14
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PRECAUTIONS ON MOUNTING
<Arrangement of Signal Lines>
● In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a
large current signal line near the circuits that are sensitive to noise such as the oscillation unit.
● When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may
generated by mutual interference between the signals and it may cause a malfunction.
Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation
unit.
Prohibited pattern
OSC4
OSC3
VSS
Large current signal line
High-speed signal line
<Precautions for Visible Radiation (when bare chip is mounted)>
● Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to
malfunction. When developing products which use this IC, consider the following precautions to prevent
malfunctions caused by visible radiations.
(1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual
use.
(2) The inspection process of the product needs an environment that shields the IC from visible radiation.
(3) As well as the face of the IC, shield the back and side too.
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5
ELECTRICAL CHARACTERISTICS
5 Electrical Characteristics
5.1 Absolute Maximum Ratings
Table 5.1.1 Absolute maximum ratings
Parameter
Power supply voltage
Input voltage
Symbol
Rated value
Unit
V
VDD
VI
-0.5 to 7
-0.3 to VDD+0.3
V
Total output current
Power dissipation
Storage temperature
Solder temperature
Soldering time
ΣIVDD
PD
±10
mA
mW
°C
250
TSTG
TSOL
tSOL
TOPR
-65 to 150
255
°C
10
Sec
°C
Operating temperature
-20 to 70
Electrostatic withstand voltage VE
EIAJ test (C=200pF): 150V or more
MIL test (C=100pF, R=1.5kΩ): 1200V or more
V
The voltages are referenced to the VSS pin as the ground level.
5.2 Recommended Operating Conditions
Table 5.2.1 Recommended operating conditions
Parameter
Symbol
VDD
Condition
2.7 to 5.5
3.579545
±0.01
Unit
V
Power supply voltage
Crystal/clock frequency
Crystal/clock frequency error
fCLK
MHz
%
fERR
The voltages are referenced to the VSS pin as the ground level.
5.3 DC Characteristics
Table 5.3.1 DC characteristics
Unless otherwise noted: VDD=2.7V to 5.5V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
High level input voltage (1) VIH1
OSC3, MODE, #SCLK, SDI,
PDWN, #RESET
0.8VDD
VDD
V
High level input voltage (2) VIH2
Low level input voltage (1) VIL1
RDIN, #RDRC
0.7VDD
0
VDD
V
V
OSC3, MODE, #SCLK, SDI,
PDWN, #RESET
0.2VDD
Low level input voltage (2) VIL2
RDIN, #RDRC
0
0
0.3VDD
0.5
V
High level input current
IIH
IIL
VIH=VDD
VIL=VSS
RDIN, OSC3, MODE, #SCLK, SDI,
PDWN, #RESET, #IRQ
#RDRC (RDIN = Low)
µA
Low level input current
RDIN, OSC3, MODE, #SCLK, SDI, -0.5
PDWN, #RESET, #RDRC, #IRQ
0
µA
High level output current
Low level output current
IOH
IOL
VOH=0.9VDD SDO, #DET, #RDET, #PQUAL
VOL=0.1VDD SDO, #DET, #RDET, #PQUAL,
#IRQ, #RDRC
-1.5 mA
mA
2.5
VREF output voltage
Input impedance
VREF
RIN
VDD/2
200
V
MΩ
INP, INN
CDIN
10
RCDIN
140
260 kΩ
5.4 Current Consumption
Table 5.4.1 Current consumption
Unless otherwise noted: VDD=2.7V to 5.5V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C
Parameter
Symbol
IOP
Condition
During power-down (PDWN = High)
When operating (no signal input) VDD=5V
VDD=3V
Min.
Typ.
Max. Unit
Current consumption
1.0
µA
mA
mA
3.0
1.8
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ELECTRICAL CHARACTERISTICS
5.5 Crystal Oscillation Characteristics
Table 5.5.1 Crystal oscillation characteristics
Unless otherwise noted: VDD=2.7V to 5.5V, VSS=0V, CG=CD=18pF, Ta=25°C
Parameter
Oscillation start time
Symbol
tsta
Condition
Min.
Typ.
Max.
20
Unit
3.579545MHz oscillator
msec
5.6 FSK Demodulation Circuit Characteristics
5.6.1 FSK AC Characteristics
Table 5.6.1 FSK AC characteristics
Unless otherwise noted: VDD=5.0/3.0V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Transfer rate
TRATE
1188 1200 1212 Baud
Bell 202 mark (logic 1) frequency
Bell 202 space (logic 0) frequency
ITU-T V.23 mark (logic 1) frequency
fB1
fB0
fV1
1188 1200 1212
2178 2200 2222
1280 1300 1320
2068 2100 2132
Hz
Hz
Hz
Hz
dB
ITU-T V.23 space (logic 0) frequency fV2
SN ratio
SNR
20
–
–
Carrier-detect ON sensitivity
(input level at TPI/RING)
1
CDONFSK VDD=5V
-44.9 -42.9 -40.9 dBm
-47.1 -45.1 -43.1 dBV
-44.9 -42.9 -40.9 dBm
-47.1 -45.1 -43.1 dBV
-46.9 -44.9 -42.9 dBm
-49.1 -47.1 -45.1 dBV
-46.9 -44.9 -42.9 dBm
-49.1 -47.1 -45.1 dBV
Input amp gain (GAMP)=-5dB
VDD=3V
Input amp gain (GAMP)=-9.4dB
Carrier-detect OFF sensitivity
1
CDOFFFSK VDD=5V
Input amp gain (GAMP)=-5dB
VDD=3V
Input amp gain (GAMP)=-9.4dB
1 When the gain in the input amp is set to GAMP (dB), the CDONFSK and CDOFFFSK values (Typ.) can be calculated
from the equation below.
CDONFSK [dBm] = -GAMP - 47.9 + 20log(VDD) [dBm], CDONFSK [dBV] = -GAMP - 50.1 + 20log(VDD) [dBV]
5
5
CDOFFFSK [dBm] = -GAMP - 49.9 + 20log(VDD) [dBm], CDOFFFSK [dBV] = -GAMP - 52.1 + 20log(VDD) [dBV]
5
5
5.6.2 FSK Switching Characteristics
Table 5.6.2 FSK switching characteristics
Unless otherwise noted: VDD=5.0/3.0V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C, CL=50pF
Parameter
PDWN fall → FSK
Symbol
Condition
Min.
Typ.
Max.
20
Unit
msec
msec
msec
msec
msec
tSUPD
Carrier detect start time
Data end → #DET rise
tCDON
tCDOFF
tDOCH
5
5
10
10
7
15
15
PDWN rise → Oscillation start
VDD=5V
VDD=3V
12
10
15
1st RING
2nd RING
Input
101010... 1 DATA
V
V
IH2
#RDRC
#RDET
PDWN
#DET
IL2
t
SUPD
t
CDON
t
CDOFF
SDO
101010... 1 DATA
t
DOCH
OSC4
Figure 5.6.1 FSK switching characteristics
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ELECTRICAL CHARACTERISTICS
5.7 Dual-Tone (CAS) Detection Circuit Characteristics
5.7.1 CAS AC Characteristics
Table 5.7.1 CAS AC characteristics
Unless otherwise noted: VDD=5.0/3.0V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C
Parameter
Symbol
Condition
VDD=5V, Bellcore mode
Input amp gain (GAMP)=-5dB
Tone filter gain=-4dB
Min.
Typ.
Max.
-35.1
Unit
Carrier-detect sensitivity
(input level at TPI/RING)
1
CDONTONE
-39.8
-35.8
dBm
VDD=5V, BT mode 2
nput amp gain (GAMP)=-5dB
Tone filter gain=-4dB
-48.0
-39.8
-48.0
-44.0
-35.8
-44.0
-40.0
-35.1
-40.0
dBV
dBm
dBV
VDD=3V, BT mode 2
nput amp gain (GAMP)=-9.4dB
Tone filter gain=-4dB
VDD=3V, BT mode 2
nput amp gain (GAMP)=-9.4dB
Tone filter gain=-4dB
Low tone frequency
High tone frequency
fLTONE
fHTONE
Bellcore (±0.5%)
2119.35 2130
2110 2130
2140.65
2150
Hz
Hz
Hz
Hz
Hz
Hz
BT line disconnected
BT line connected (±0.6%)
Bellcore (±0.5%)
2117.22 2130
2736.25 2750
2142.78
2763.75
2780
BT line disconnected
2720
2750
BT line connected (±0.6%)
2733.50 2750
2766.50
1 When the gain in the input amp is set to GAMP (dB), the CDONTONE value (Typ.) can be calculated from the
equation below.
(When the internal tone filter gain = –4 dB)
CDONTONE [dBm] = -GAMP - 40.8 + 20log(VDD) [dBm], CDONTONE [dBV] = -GAMP - 49 + 20log(VDD) [dBV]
5
5
2 BT mode is selected by setting the mode register (address = 0h) bit 2 to 1. By this setting, the gain in each dual-
tone filter is raised +6 dB for adjustment to the British Telecom CD level.
5.7.2 CAS Switching Characteristics
Table 5.7.2 CAS switching characteristics
Unless otherwise noted: VDD=5.0/3.0V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C, CL=50pF
Parameter
CAS detect capture time
CAS end →#DET rise
CAS width
Symbol
tCASAQ
tCASDH
tCASW
Min.
Typ.
2.8×(N+2)+16.9
2.8×(31-N)+13.1
80
Max.
85
Unit
msec
msec
msec
75
N = TH0 × 16 + TL3 × 8 + TL2 × 4 + TL1 × 2 + TL0
tCASW
CAS
#DET
tCASAQ
tCASDH
Figure 5.7.1 CAS switching characteristics
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ELECTRICAL CHARACTERISTICS
5.8 Call Progress Mode (CPM) Detection Circuit Characteristics
5.8.1 CPM AC Characteristics
Table 5.8.1 CPM AC characteristics
Unless otherwise noted: VDD=5.0/3.0V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C
Parameter
Carrier-detect ON sensitivity
(input level at TPI/RING)
Symbol
Condition
Min.
-44.9
-47.1
-44.9
-47.1
-46.9
-49.1
-46.9
-49.1
Typ.
-42.9
-45.1
-42.9
-45.1
-44.9
-47.1
-44.9
-47.1
Max.
Unit
1
CDONCPM VDD=5V
-40.9 dBm
-43.1 dBV
-40.9 dBm
-43.1 dBV
-42.9 dBm
-45.1 dBV
-42.9 dBm
-45.1 dBV
Input amp gain (GAMP)=-5dB
VDD=3V
Input amp gain (GAMP)=-9.4dB
Carrier-detect OFF sensitivity
1
CDOFFCPM VDD=5V
Input amp gain (GAMP)=-5dB
VDD=3V
Input amp gain (GAMP)=-9.4dB
1 When the gain in the input amp is set to GAMP (dB), the CDONCPM and CDOFFCPM values (Typ.) can be calculated
from the equation below.
CDONCPM [dBm] = -GAMP - 47.9 + 20log(VDD) [dBm], CDONCPM [dBV] = -GAMP - 50.1 + 20log(VDD) [dBV]
5
5
CDOFFCPM [dBm] = -GAMP - 49.9 + 20log(VDD) [dBm], CDOFFCPM [dBV] = -GAMP - 52.1 + 20log(VDD) [dBV]
5
5
5.8.2 CPM Switching Characteristics
Table 5.8.2 CPM switching characteristics
Unless otherwise noted: VDD=5.0/3.0V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C, CL=50pF
Parameter
Symbol
tCPMAQ
tCPMIH
Min.
Typ.
25
Max.
Unit
CPM tone-detect capture time
CPM tone end → #IRQ rise
msec
msec
30
CPM
#IRQ
#DET
tCPMAQ
tCPMIH
Figure 5.8.1 CPM switching characteristics
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ELECTRICAL CHARACTERISTICS
5.9 Serial Interface Circuit Characteristics
5.9.1 Serial Interface AC Characteristics
Table 5.9.1 Serial interface AC characteristics
Unless otherwise noted: VDD=5.0/3.0V, VSS=0V, fCLK=3.579545MHz, Ta=-20 to 70°C, CL=50pF
Parameter
#SCLK frequency
Symbol
Min.
Typ.
Max.
1
Unit
MHz
nsec
nsec
nsec
nsec
µsec
µsec
µsec
µsec
µsec
fSCLK
#SCLK pulse width
SDI setup time
tWSCLK
tSSDI
tHSDI
tDSDO
tSMH
tHMH
tSML
400
250
500
SDI hold time
SDO delay time
250
MODE High setup time
MODE High hold time
MODE Low setup time
MODE Low hold time
MODE Low pulse width
1
1
1
1
1
tHML
tMDW
SDI
tSSDI
tHSDI
fSCLK
#SCLK
tHMH
tMDW
tSMH
MODE
tWSCLK
tWSCLK
Figure 5.9.1 Serial interface input timing
SDO
tDSDO
tDSDO
#SCLK
MODE
tHML
tSML
Figure 5.9.2 Serial interface output timing
20
EPSON
S1C05250 TECHNICAL MANUAL
5
ELECTRICAL CHARACTERISTICS
5.9.2 FSK Demodulated Data Read Mode
The FSK signal fed to the INP and INN pins is demodulated into 8-bit asynchronous (start-stop) data. The
demodulated data is then sampled by the internal 8-bit shift register. When the data has been stored in the shift
register, the #IRQ pin changes to Low level, indicating that the data can be read by the host CPU.
If the MODE pin is set to Low level and synchronoµs mode has been selected (MDR[0] = 1), the host CPU reads
out the 8-bit data synchronously with the clock signal fed from the host CPU to the #SCLK pin. Figure 5.9.3 shows
the timing at which this data is read. Each bit of the 8-bit data is output from the SDO pin synchronously with
falling edges of the #SCLK clock signal, beginning with bit 0. The host CPU latches each bit into the internal logic
at rising edges of the #SCLK clock signal.
If the MODE pin is set to Low level and asynchronous mode has been set (MDR[0] = 0), the data is output from the
SDO pin at a transfer rate of 1,200 baud. The clock signal from the host CPU is unnecessary. The host CPU latches
the data synchronously with the start bit.
417 µsec
Receive data
SDO
Stop bit
High on rising edge of stop bit
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
#SCLK
#IRQ
#IRQ changes to High level on the first rise of #SCLK.
CAS/write mode
#IRQ→Low
FSK/read mode
MODE
Figure 5.9.3 Data read timing in synchronous mode
SDO
#SCLK
#IRQ
start
stop
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
CAS/write mode
FSK/read mode
MODE
Figure 5.9.4 Data read timing in asynchronous mode
5.9.3 CAS Detection Circuit Control-Register Write Mode
The host CPU can write 4-bit data to the internal registers through the SDI pin in order to set each control bit. The
host CPU must temporarily pull the MODE pin to Low level to initialize the write control circuit before it can write
data. Then, after releasing the MODE pin back to High level, the host CPU must be held at High level whilewriting
data to the internal register. The data input to the SDI pin is sampled at rising edges of the clock signal fed from the
host CPU to the #SCLK pin. The first four bits of data sent from the host CPU are the address A[3:0] of the internal
register to be accessed. The subsequent four bits are the data bits D[3:0] to be written to the specified register. The
data is input beginning with the LSB.
First data
Second data
n’th data
SDI
#SCLK
MODE
A0 A1 A2 A3 D0 D1 D2 D3 A0 A1 A2
D3
Low level
FSK/read mode
CAS/write mode
Figure 5.9.5 Data write timing
S1C05250 TECHNICAL MANUAL
EPSON
21
5
ELECTRICAL CHARACTERISTICS
5.10 S1C05250 Timing Chart
5.10.1 Bellcore On-Hook Data Transfer
INP/INN
#RDRC
#IRQ
1st RING
FSK data transfer
2nd RING
Power-down due to timeout
Power-down
PDWN
MODE
#DET
SDI
after receiving last data
FSK/read mode
Ring detection
Ring detection
No carrier
Carrier detection
Receive data
Serial clock
SDO
#SCLK
OSC4
Figure 5.10.1 Bellcore on-hook data transfer timing chart
5.10.2 Bellcore Off-Hook Data Transfer
CPE→Off-Hook
CPE→Receiver muted
CPE→Receiver muting released
INP/INN
SAS
CAS
ACK
FSK data transfer
#RDRC
#IRQ
DTMF D transmitted from CPE
Placed in CAS mode
after receiving last data
Power-on state maintained when receiver
is off-hook to detect CAS tone
PDWN
MODE
#DET
SDI
CAS/write mode
FSK/read mode
FSK mode must be set to prevent failure in carrier detection after sending ACK
CAS tone detection
Carrier detection
Control data bits written
Receive data
SDO
Serial clock
Serial clock
#SCLK
OSC4
Figure 5.10.2 Bellcore off-hook data transfer timing chart
22
EPSON
S1C05250 TECHNICAL MANUAL
5
ELECTRICAL CHARACTERISTICS
5.10.3 BT Idle State CLI Service
Line Reversal
INP/INN
#RDRC
#IRQ
Alert signal
FSK data transfer
1st RING
Power-down due to timeout
Ring detection
Power-down after receiving last data
PDWN
MODE
CAS/write mode
FSK/read mode
Carrier detection
Line Reversal detection CAS tone detection
#DET
SDI
Control data bits written
Receive data
SDO
Serial clock
Serial clock
#SCLK
OSC4
Figure 5.10.3 BT Idle State CLI service timing chart
5.10.4 BT Loop State CLI Service
TE→Off-hook
TE→Receiver muted
TE→Receiver muting released
INP/INN
Alert signal
ACK
FSK data transfer
#RDRC
#IRQ
DTMF D transmitted from TE
Placed in CAS mode
after receiving last data
Power-on state maintained when
receiver is off-hook to detect CAS tone
PDWN
MODE
#DET
SDI
CAS/write mode
FSK/read mode
FSK mode must be set to prevent failure in carrier detection after sending ACK
CAS tone detection
Carrier detection
Control data bits written
Receive data
SDO
Serial clock
Serial clock
#SCLK
OSC4
Figure 5.10.4 BT Loop State CLI service timing chart
S1C05250 TECHNICAL MANUAL
EPSON
23
5
ELECTRICAL CHARACTERISTICS
5.11 External Wiring Diagram (Example)
5.11.1 Example of Bellcore-Compatible Telephone Circuit
TIP
Protective
network
RING
R3
R5
S1C05250
VDD
500 pF
500 pF
R
1
2
INP
INN
FB
VDD
1 µF
R
BPOUT
CDIN
SDO
0.1 µF
R6
Hook
switch
270 kΩ
R4
VREF
0.2 µF 0.2 µF
RDIN
#RDRC
#RDET
PDWN
#RESET
NC
SDI
#SCLK
#IRQ
470 kΩ
Communication
network
33 kΩ
0.2 µF 0.1 µF
#DET
#PQUAL
NC
Receiver
18 pF
MODE
OSC4
OSC3
VSS
18 pF
Mute control
DTMF tone
3.579545 MHz
Figure 5.11.1 Example of Bellcore-compatible telephone circuit
Note: The above circuit diagram is merely an example, and does not guarantee the operation of the
circuit.
See Section 3.2, "Input Amp Circuit", for the R1 to R6 values.
24
EPSON
S1C05250 TECHNICAL MANUAL
5
ELECTRICAL CHARACTERISTICS
5.11.2 Example of Bellcore-Compatible Auxiliary Circuit
TIP
Protective
network
RING
R3
R5
S1C05250
VDD
500 pF
500 pF
R
1
2
INP
INN
FB
VDD
To telephone
1 µF
R
BPOUT
CDIN
SDO
0.1 µF
R6
Hook
switch
270 kΩ
R4
VREF
0.2 µF 0.2 µF
RDIN
#RDRC
#RDET
PDWN
#RESET
NC
SDI
#SCLK
#IRQ
470 kΩ
DTMF
interface
33 kΩ
0.2 µF 0.1 µF
#DET
#PQUAL
NC
18 pF
MODE
OSC4
VSS
OSC3
18 pF
3.579545 MHz
Mute control
DTMF tone
Figure 5.11.2 Example of Bellcore-compatible auxiliary circuit
Note: The above circuit diagram is merely an example, and does not guarantee the operation of the
circuit.
See Section 3.2, "Input Amp Circuit", for the R1 to R6 values.
S1C05250 TECHNICAL MANUAL
EPSON
25
6
PACKAGE
6 Package
SOP1-24pin Plastic Package
15.47max
Unit: mm (inch)
(0.609max
)
15.17±0.1
0.597
+0.004
–0.003
(
)
24
13
0°
10°
1
12
±0.05
0.15
+0.001
–0.002
(
0.006
)
±0.3
0.5
0.02
±0.1
0.4
+0.011
1.27
0.05
+0.003
–0.012
(
)
–0.004
(
)
(
0.016
)
1.3
(
0.051)
26
EPSON
S1C05250 TECHNICAL MANUAL
7
PAD LAYOUT
7 Pad Layout
7.1 Pad Layout Diagram
Die No.
6
5
4
3
2
1
7
8
9
22
21
20
19
Y
X
10
(0, 0)
11
12
18
17
13
14 15
16
2.12 mm
Chip thickness: 400 µm
Pad opening: 100 µm
7.2 Pad Coordinates
(Unit: µm)
Pad No.
Pad name X coordinate Y coordinate
Pad No.
12
Pad name X coordinate Y coordinate
1
2
CDIN
BPOUT
VDD
650
330
946
946
946
946
946
946
778
548
317
-17
#RESET
MODE
VSS
-872
-666
-234
-60
-607
-946
-946
-946
-946
-734
-433
-99
13
3
80
14
4
INP
-162
-410
-657
-872
-872
-872
-872
-872
15
OSC3
OSC4
#PQUAL
#DET
#IRQ
5
INN
16
637
872
872
872
872
872
872
6
FB
17
7
VREF
18
8
RDIN
#RDRC
#RDET
PDWN
19
9
20
#SCLK
SDI
190
10
11
21
479
-318
22
SDO
778
S1C05250 TECHNICAL MANUAL
EPSON
27
International Sales Operations
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In pursuit of “Saving”Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
S1C05250
Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
First issue October, 1999
M
Printed March, 2001 in Japan
A
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