SDC4565JTR-G1 [SDC]
Current Mode PWM Controller;型号: | SDC4565JTR-G1 |
厂家: | Shaoxing Devechip Microelectronics Co., Ltd |
描述: | Current Mode PWM Controller |
文件: | 总11页 (文件大小:398K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
General Description
Features
SDC4565 is a highly integrated current mode PWM control
IC optimized for high performance, low standby power
and cost effective offline flyback converter applications in
sub 60W range.
Frequency shuffling technology for improved EMC
performance
Audio noise free operation
Extended burst mode control for improved efficiency
and minimum standby power design
External programmable PWM switching
Internal synchronized slope compensation
Low VDD startup current and low operating current
Leading edge blanking on current sense input
Good protecverage with auto self-recovery
(UVLOOCP/OLP)
The internal slope compensation improves system large
signal stability and reduces the possible subharmonic
oscillation at high PWM duty cycle output. Leading-edge
blanking on current sense(CS) input removes the signal
glitch due to snubber circuit diode reverse recovery and
thus greatly reduces the external component count and
system cost in the design.
Package: T-23-6
SDC4565 offers complete protection coverage with
automatic self-recovery feature including cycle-by-cycle
current limiting (OCP), over load protection (OLP), VDD
over voltage clamp and under voltage lockout (UVLO). The
gate drive output is clamped to maximum 12V to protect
the power MOSFET.
Applications
Battery charger
Power adapter
Set-top box power supplies
SOT-23-6
Figure 1. Package Type
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Datasheet
Pin Configuration
Package: SOT-23-6
1
2
3
6
GND
GATE
VDD
FB
RI
5
4
SENSE
Figure 2. Pin Configuration
Pin Number
Pin Name
Function
Ground
1
GND
Feedback input pin. The PWM duty cycle is determined by voltage level into this pin
and SENSE pin input
2
3
FB
RI
Internal Oscillator frequency setting pin. A resistor connected between RI and GND
set the PWM frequency
Csense input pin. Connected to MOSFET current sensing resistor node
4
5
6
SENSE
VDD
Chip DC power supply pin
Totem-pole gate drive output for the power MOSFET
GATE
Table 1. Pin Description
December, 2013 Rev. 1.1
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Datasheet
Functional Block Diagram
RI
Current
Reference
Soft
GATE
Drive
SET
CLR
S
Q
Q
Shuffling
OSC
VDD
POR
UVLO
VDD
R
Burst
Mode controller
Clamping
VTH_OC
Leading
Edge
SENSE
FB
Blanking
Internal
Supply
Regulator
OVP
ope
ensation
OLP
GND
Figure 3. Functional Block Diagram
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Datasheet
Ordering Information
-
X
SDC4565 X
X
E1: Pb-free
G1: Halogen-free
Circuit Type
Package
SOT-23-6: J
TR: Tape Reel
Part Number
Pb-free Halogen-free
SDC4565JTR-E1 SDC4565JT1
Marking ID
Temperature
Package
Packing Type
Range
Pb-free
4565
Halogen-free
SOT-23-6
4565G
Tape Reel
-40℃~85℃
December, 2013 Rev. 1.1
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Datasheet
Absolute Maximum Ratings (NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device.)
Parameter
VDD DC supply voltage
Symbol
VDD
Value
-0.3~30
32
Unit
V
VDD clamp voltage
VDD_CLAMP
ICLAMP
VFB
V
VDD DC clamp current
10
mA
V
VFB input voltage
-0.3~7
-0.3~7
-0.3~7
150
SENSE input voltage
VSENSE
VRI
V
VRI input voltage
V
Operating junction temperature TJ
Storage temperature TSTG
Latch-up test per JEDEC 78
ESD,HBM model per Mil-Std-883H,Method 3015
ESD,MM model per JEDEC EIA/JESD22-A115
TJ
°C
°C
mA
V
TSTG
~150
200
-
HBM
MM
2000
200
V
Table 2. Absolute Maximum Ratings
Recommended Operating Conditions
Parameter
Symbol
VDD
Min
10
Max
30
Unit
V
VDD DC supply voltage
Oscillation frequency
fOSC
60
70
kHz
°C
Operating Temperature Range
TOP
-40
85
Table 3. Recommended Operating Conditions
December, 2013 Rev. 1.1
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Datasheet
Electrical Characteristics (Ta=25°C, unless otherwise specified)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Supply Voltage (VDD)
VDD =12.5V, RI=100k,
Measure Leakage current into VDD
VDD=16V,
VDD start up current
Operation current
ISTARTUP
IDD
-
-
3
20
-
uA
mA
V
1.4
8.2
RI=100k, VFB=3V
VDD under voltage lockout
enter
VUVLO(ON)
-
-
7.2
9.2
VDD under voltage lockout
exit (recovery)
VUVLO(OFF)
VDD_CLAMP
13.5
30
14.5
32
15.5
34
V
V
VDD zener clamp voltage
IVDD=10mA
Feedback Input Section(FB Pin)
FB open loop voltage
VFB_OPEN
IFB_SHORT
-
-
-
4.8
0.8
-
-
V
Short FB pin to GND and Measure
Current
FB pin short circuit current
mA
Zero duty cycle fb threshold
voltage zero
VTH_0D
VDD=16V, RI=100k
-
-
0.85
V
Power limiting FB threshold
voltage
VTH_PL
tD_PL
-
-
-
-
3.7
35
80
-
-
V
ms
%
Power limiting debounce time
VDD=16V, RI=100k,
FB=3V, CS=0
Maximum duty cycle
DCMAX
70
90
Current Sense Input(Sense Pin)
Leading edge blanking time
tBLANKING
tD_OC
RI=100k
-
-
300
75
-
-
ns
ns
Over current detection and
coelay
VDD=16V,
CS>VTH_OC, FB=3.3V
Over rrent threshold
voltage at zero duty cycle
VTH_OC
FB=3.3V, RI=100k
0.70
0.75
0.81
V
Oscillator
Normal oscillation frequency
fOSC
RI=100k
60
-
65
5
70
-
kHz
%
Frequency temperature
stability
VDD =16V,RI=100k,
ΔfTEMP
ΔfVDD
Ta=-20°C~100°C
Frequency voltage stability
VDD= 12V~25V,RI=100k
-
5
-
%
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Datasheet
Parameter
RI open load voltage
Burst mode base frequency
Soft start time
Symbol
VRI_OPEN
Condition
-
Min
Typ
2
Max
Unit
V
-
-
-
-
-
-
fBM
VDD=16V, RI=100k
-
22
7
kHz
ms
tSOFT
Gate Drive Output
VDD=16V, Io=-20mA
VDD=16V, Io=20mA
-
Output low level
VOL
VOH
VCLAMP
tr
-
10
-
-
0.8
V
V
Output high level
-
-
-
-
Output clamp voltage level
Output rising time
Output falling time
12
125
50
V
VDD =16V, CL =1nf
VDD=16V, CL=1nf
Frequency Shufling
RI=100k
-
ns
ns
tf
-
Shuffling frequency
fOSC
-
64
-
-
Hz
%
Modulation range/Base
frequency
ΔfOSC
RI=100k
-3
3
ble 4. Electrical Characteristics
December, 2013 Rev. 1.1
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Datasheet
Function Description
The SDC4565 is a highly integrated PWM controller IC
optimized for offline flyback converter applications in sub
60W power range. The extended burst mode control
greatly reduces the standby power consumption and helps
the design easily meet the international power
conservation requirements.
condition, the FB input drops below burst mode threshold
level, device enters burst mode control. The gate drive
output switches only when VDD voltage drops below a
preset level and FB input is active to output an on state,
otherwise the gate drive remains at off state to minimize
the switching loss and reduces the standby power
consumption to the greatest etend. The frequency
control also eliminatethe audio noise at any loading
conditions.
Startup Current and Start up Control
Startup current of SDC4565 is designed to be very low so
that VDD could be charged up above UVLO threshold level
and device starts up quickly. A large value startup resistor
can therefore be used to minimize the power loss yet
provides reliable startup in application.
Oscillator Operaton
A resistor coected between RI and GND sets the
constant current source to charge/discharge the internal
cand t hus the PWM oscillator frequency is determined.
Threlationship between RI and switching frequency
follows the below equation within the specified RI in kΩ
range at nominal loading operational condition.
Operating Current
The operating current of SDC4565 is low at 1.4mA. Good
efficiency is achieved with SDC4565 low operating current
together with extended burst mode control features.
6500
fosc =
(kHz)
Frequency shuffling for EMI improvement
RI(kΩ)
The frequency shuffling/jittering (switchg frequency
modulation) is implemented in SDC4565. The oscillation
frequency is modulated with a random source so that the
tone energy is spread out. The spread spectrum minimizes
the conduction band d therefore reduces system
design challenge.
Current Sensing and Leading Edge Blanking
Cycle-by-cycle current limiting is offered in SDC4565
current mode PWM control. The switch current is
detected by a sense resistor into the sense pin. An internal
leading edge blanking circuit chops off the sense voltage
spike at initial MOSFET on state due to snubber diode
reverse recovery so that the external RC filtering on sense
input is no longer required. The current limit comparator
is disabled and thus cannot turn off the external MOSFET
during the blanking period. PWM duty cycle is determined
by the current sense input voltage and the FB input
voltage.
Extended Burst Mode Operation
Under zero load or light load condition, meet of the power
dissiin a switching mode power supply is from
switching loss on the MOSFET transistor, the core loss of
the transformer and the loss on the snubber circuit. The
magnitude of power loss is in proportion to the number of
switching events within a fixed period of time, Reducing
switching frequence leads to the reduction on power loss
and thus conserves the energy.
Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage ramp
onto the current sense input voltage for PWM generation.
This greatly improves the close loop stability at CCM and
SDC4565 self adjusts the switching mode according to the
loading condition. Under no load to light/medium load
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Datasheet
prevents the sub-harmonic oscillation and thus reduces
the output ripple voltage.
easier to achieve with this dedicated control scheme. An
internal 12V clamp is added for MOSFET gate protection at
higher than expected VDD input.
Gate Drive
Protection Controls
SDC4565 gate is connected to an external MOSFET gate
for power switch control. Too weak the gate drive strength
results in higher conduction and switch loss of MOSFET
while too strong gate drive output compromises the EMI.
A good tradeoff is achieved through the built-in totem
pole gate design with right output strength and dead time
control. The low idle loss and good EMI system design is
Good power supply system reliability is achieved with its
rich protection features including cycle-by-cycle current
limiting (OCP), over load protection (OLP) and over voltage
clamp, under voltage lockout on VDD (UVLO).
Typical Application
V+
GND
GND GATE
DD
FB
RI
SENSE
SDC4565
Figure 4. Typical Application
December, 2013 Rev. 1.1
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Datasheet
Package Dimension
SOT-23-6
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
1.250
0.100
1.150
0.500
0.200
3.020
1.700
2.950
Min
Max
0.049
0.004
0.045
0.020
0.008
0.119
0.067
0.116
A
A1
A2
b
1.050
0.000
1.050
0.300
0.100
2.820
1.500
2.650
0.041
0000
0.041
0.012
0.004
0.111
0.059
0.104
c
D
E
E1
e
0.950(BSC)
0.037(BSC)
e1
L
1.800
0.300
0°
2.000
0.600
8°
0.071
0.012
0°
0.079
0.024
8°
θ
December, 2013 Rev. 1.1
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Datasheet
Shaoxing Devechip MicroelectronicCo., Ltd.
http://www.sdc-si.com/
IMPORTANT NOTICE
Information in this documprovided solely in connection with Shaoxing Devechip Microelectronics Co., Ltd. (abbr. SDC) products.
SDC reserves the right to mhanges, corrections, modifications or improvements, to this document, and the products and services
described herein aanytime, without notice. SDC does not assume any responsibility for use of any its products for any particular
purpose, nor does SDC assume any liability arising out of the application or use of any its products or circuits. SDC does not convey
any license under its patent rights or other rights nor the rights of others.
© 2013 Devechip Microelectronics - All rights reserved
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