LC87F1HC8A_0812 [SANYO]
8-bit 1-chip Microcontroller with USB-host controller; 8位单芯片微控制器， USB主机控制器
| 型号： | LC87F1HC8A_0812 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-bit 1-chip Microcontroller with USB-host controller |
| 文件： | 总27页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0956C
CMOS IC
128K-byte FROM and 16384-byte RAM integrated
LC87F1HC8A
8-bit 1-chip Microcontroller
with USB-host controller
Overview
The LC87F1HC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard
programmable), 16384-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit
timers), a 16-bit timer (may be divided into 8-bit timers or PWMs), four 8-bit timers with a prescaler, a base timer
serving as a time-of-day clock, 3 channels of synchronous SIO interface with automatic data transfer capabilities, an
asynchronous/synchronous SIO interface, a UART interface (full duplex), a full-speed USB interface (host control
function), an 8-bit 12-channel AD converter, 2 channels of 12-bit PWM, a system clock frequency divider, an infrared
remote control receiver circuit, and a 40-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5V
• Block-erasable in 128 byte units
• Writes data in 2-byte units
• 131072 × 8 bits
RAM
• 16384 × 9 bits
Bus Cycle Time
• 83.3ns (When CF=12MHz)
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.05
D2408HKIM 20081212-S00001 No.A0956-1/27
LC87F1HC8A
Minimum Instruction Cycle Time (tCYC)
• 250ns (When CF=12MHz)
Ports
• I/O ports
Ports whose I/O direction can be designated in 1-bit units 28 (P10 to P17, P20 to P27, P30 to P34,
P70 to P73, PWM0, PWM1, XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P00 to P07)
• USB ports
2 (UHD+, UHD-)
2 (CF1, CF2)
1 (XT1)
• Dedicated oscillator ports
• Input-only port (also used for oscillation)
• Reset pins
1 (
RES
)
• Power supply pins
6 (V 1 to 3, V 1 to 3)
SS DD
Timers
• Timer 0: 16-bit timer/counter with 2 capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(lower-order 8 bits may be used as a PWM output)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
SIO
• SIO0: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 512/3 tCYC
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units)
(Suspension and resumption of data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO4: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units)
(Suspension and resumption of data transmission possible in 1 byte units or in word units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
Continued on next page.
No.A0956-2/27
LC87F1HC8A
Continued from preceding page.
• SIO9: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units)
(Suspension and resumption of data transmission possible in 1 byte units or word units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
Full Duplex UART
1) Data length: 7/8/9 bits selectable
2) Stop bits: 1 bit (2 bits in continuous transmission mode)
3) Baud rate: 16/3 to 8192/3 tCYC
AD Converter: 8 bits × 12 channels
PWM: Multifrequency 12-bit PWM × 2 channels
Infrared Remote Control Receiver Circuit
1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is
selected as the base clock)
2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding.
3) X'tal HOLD mode reset function
USB Interface (host control function)
1) Compliant with full-speed (12M bps) specifications
2) Supports 4 transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer).
Audio Interface
1) Sampling frequency (fs):
32kHz, 44.1kHz, 48kHz
2) Master clock frequency (internal PLL): 12.288MHz, 16.9344MHz, 18.432MHz
3) Bit clock selectable:
4) Data bit length:
48fs/64fs
16/18/20/24 bits
5) LSB first/MSB firsts selectable
6) Left-justification/right-justification selectable
Watchdog Timer
• Watchdog timer using external RC circuitry
• Interrupt and reset signals selectable
Clock Output Function
1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected
as the system clock.
2) Can output the source oscillation clock for the subclock.
No.A0956-3/27
LC87F1HC8A
Interrupts
• 40 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
3
INT2/T0L/INT4/UHC bus active/remote control signal receive
INT3/INT5/base timer
4
0001BH
00023H
5
T0H/INT6/UHC device connected/UHC disconnected/UHC resume
T1L/T1H/INT7/SIO9/AIF start
6
0002BH
00033H
7
SIO0/UART1 receive
8
0003BH
00043H
SIO1/SIO4/UART1 transmit/end of AIF
9
ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC STALL
Port 0/PWM0/PWM1/T4/T5/UHC-SOF/DMCOPY
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 8192 levels maximum (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation and PLL Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit:
• Crystal oscillation circuit:
• PLL circuit (internal):
For system clock
For system clock, time-of-day clock
For USB interface (see Fig.5) ), audio interface (see Fig. 6)
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an bus active interrupt source established in the USB host controll circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are six ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an bus active interrupt source established in the USB host controll circuit
(6) Having an interrupt source established in the infrared remote controller receiver circuit
No.A0956-4/27
LC87F1HC8A
Package Form
• SQFP48(7×7): Lead-free type
Development Tools
• On-chip debugger: TCB87- type-B + LC87F1HC8A
Flash ROM Programming Boards
Package
Programming boards
W87F55256SQ
SQFP48(7×7)
Recommended EPROM Programmer
Maker
Model
Supported version
Rev 02.82 or later
Device
AF9708/
AF9709/AF9709B/AF9709C
(Including Ando Electric Co., Ltd. models)
AF9101/AF9103(Main body)
(FSG models)
Flash Support Group, Inc.
(FSG)
Single
LC87F1HC8A
Programmer
Flash Support Group, Inc.
Onboard
(FSG)
+
Single/Gang
Programmer
(Note 2)
LC87F1HC8A
LC87F1HC8
SIB87(Inter Face Driver)
(SANYO model)
SANYO(Note 1)
Single/Gang
Programmer
Onboard
SKK/SKK TypeB
Application Version
2.04 or later
(SANYO FWS)
SANYO
Chip Data Version
2.11 or later
SKK-DBG TypeB
(SANYO FWS)
Single/Gang
Programmer
Note 1: With the FSG onboard programmer (AF9101/AF9103) and the serial interface driver (SIB87) provided by
SANYO, PC-less standalone onboard programming is possible
Note 2: Depending on programming conditions, it is necessary to use a dedicated programming device and a program.
Please contact SANYO or FSG if you have any questions or difficulties regarding this matter.
Package Dimensions
unit : mm (typ)
3163B
9.0
7.0
36
25
24
13
37
48
1
12
0.5
0.15
0.18
(0.75)
SANYO : SQFP48(7X7)
No.A0956-5/27
LC87F1HC8A
Pin Assignment
UHD-
UHD+
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3/DBGP1
P02/AN2/DBGP0
P01/AN1
V
V
3
3
DD
SS
P00/AN0
P34/UFILT
P33/AFILT
P32
P31/URX1
P30/UTX1
V
V
2
2
SS
DD
PWM0/MCLKO
PWM1/MCLKI
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
LC87F1HC8A
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P14/SI1/SB1
Top view
SANYO : SQFP48(7×7) “Lead-free Type”
SQFP48
1
NAME
SQFP48
NAME
P73/INT3/T0IN/RMIN
RES
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P04/AN4/DBGP2
P05/AN5/CKO/SDAT
P06/AN6/T6O/BCLK
P07/AN7/T7O/LRCK
P20/INT4/INT6
2
3
XT1/AN10
XT2/AN11
4
5
V
1
SS
6
CF1
CF2
P21/INT4
RD
P22/INT4/SO4/
7
WR
P23/INT4/SI4/
8
V
1
DD
9
P10/SO0
P24/INT5/INT7/SCK4
RD9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P11/SI0/SB0
P12/SCK0
P25/INT5/SO9/
WR9
P26/INT5/SI9/
P13/SO1
P27/INT5/SCK9
UHD-
P14/SI1/SB1
P15/SCK1
UHD+
P16/T1PWML
P17/T1PWMH/BUZ
PWM1/MCLKI
PWM0/MCLKO
V
3
3
DD
V
SS
P34/UFILT
P33/AFILT
V
2
2
P32
DD
V
P31/URX1
SS
P00/AN0
P01/AN1
P30/UTX1
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P02/AN2/DBGP0
P03/AN3/DBGP1
No.A0956-6/27
LC87F1HC8A
System Block Diagram
PLA
Interrupt control
IR
Standby control
FROM
CF
RC
USB PLL
Clock
generator
PC
X’tal
SIO0
SIO1
SIO4
ACC
Bus interface
Port 0
B register
C register
Port 1
Port 2
Port 3
Port 7
SIO9
Timer 0
Timer 1
Timer 4
Timer 5
Timer 6
Timer 7
Base timer
PWM0
ALU
PSW
RAR
RAM
INT0 to INT7
Noise filter
UART1
Audio interface
ADC
Stack pointer
Watchdog timer
Infrared remote
control receiver circuit
Onchip debugger
PWM1
USB host
No.A0956-7/27
LC87F1HC8A
Pin Description
Pin Name
I/O
Description
Option
V
V
V
1,V 2,
-
- power supply
No
SS SS
3
SS
1, V
2
-
-
+ power supply
No
DD
DD
DD
V
3
USB reference voltage
Yes
Yes
Port 0
I/O
• 8-bit I/O ports
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions
AD converter input ports: AN0 to AN7(P00 to P07)
Onchip debugger pins: DBGP0 to DBGP2(P02 to P04)
P05: System clock output/audio interface SDAT input/output
P06: Timer 6 toggle output/audio interface BCLK input/output
P07: Timer 7 toggle output/audio interface LRCK input/output
• 8-bit I/O ports
Port 1
I/O
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus input/output
P12: SIO0 clock input/output
P13: SIO1 data output
P14: SIO1 data input/bus input/output
P15: SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/beeper output
Port 2
I/O
• 8-bit I/O ports
Yes
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P20: INT6 input/timer 0L capture 1 input
RD
P22: SIO4 data input/output/parallel interface
P23: SIO4 data input/output/parallel interface
output
output
WR
P24: SIO4 clock input/output/INT7 input/timer 0H capture 1 input
RD9
P25: SIO9 data input/output/parallel interface
P26: SIO9 data input/output/parallel interface
P27: SIO9 clock input/output
output
output
WR9
Interrupt acknowledge types
Rising &
Falling
Rising
Falling
H level
L level
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Port 3
I/O
• 5-bit I/O ports
Yes
• I/O specifiable in 1-bit units
P30 to P34
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P30: UART1 transmit
P31: UART1 receive
P33: Audio interface PLL filter pin (see Fig. 6.)
P34: USB interface PLL filter pin (see Fig. 5.)
Continued on next page.
No.A0956-8/27
LC87F1HC8A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input/
IR remote controller receiver input
AD converter input ports: AN8(P70), AN9(P71)
Interrupt acknowledge types
Rising &
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
PWM0
PWM1
I/O
PWM0, PWM1 output port
General-purpose input port
• Pin functions
No
PWM0: Audio interface master clock output
PWM1: Audio interface master clock input
USB data I/O pin UHD-/general-purpose I/O port
UHD-
UHD+
RES
I/O
I/O
No
No
No
No
USB data I/O pin UHD+/general-purpose I/O port
Reset pin
Input
Input
XT1
• 32.768kHz crystal oscillator input
• Pin functions
General-purpose input port
AD converter input ports: AN10
Must be connected to V 1 when not to be used.
DD
XT2
I/O
• 32.768kHz crystal oscillator output
• Pin functions
No
General-purpose I/O
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
Ceramic/crystal resonator input
CF1
CF2
Input
Output
No
No
Ceramic/crystal resonator output
No.A0956-9/27
LC87F1HC8A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option selected in
Port Name
Option type
Output type
Pull-up resistor
units of
1 bit
P00 to P07
1
2
1
CMOS
Programmable (Note 1)
No
Nch-open drain
CMOS
P10 to P17
P20 to P27
P30 to P34
P70
1 bit
Programmable
2
Nch-open drain
Programmable
-
-
-
-
-
-
No
No
No
No
No
No
Nch-open drain
CMOS
Programmable
P71 to P73
PWM0, PWM1
UHD+, UHD-
XT1
Programmable
CMOS
No
No
No
No
CMOS
Input only
XT2
32.768kHz crystal resonator output (N channel open
drain when in general-purpose output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
Power Pin Treatment
Connect the IC as shown below to minimize the noise input to the V 1 pin. and extend the backup period. Be sure to
DD
electrically short the V 1, V 2, and V 3 pins.
SS SS SS
Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of
output ports is supplied by their backup capacitors.
LSI
For backup
Power
supply
V
V
1
DD
2
DD
V
3
DD
V
2
V
V
1
3
SS
SS
SS
Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode.
LSI
For backup
Power
supply
V
V
1
DD
2
DD
V
3
DD
V
1 V 2 V
SS
3
SS
SS
No.A0956-10/27
LC87F1HC8A
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to V 1 and the internal USB reference voltage circuit is activated, the
DD
reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be
switched by option select. The procedure for marking the option selection is described below.
(1)
(2)
(3)
USE
(4)
Option settings
USB regulator
USE
USE
NONUSE
NONUSE
NONUSE
inactive
inactive
inactive
USB regulator at HOLD mode
USE
NONUSE
NONUSE
active
NONUSE
USE
USB regulator at HALT mode
Normal mode
USE
Reference voltage circuit state
active
active
active
active
inactive
active
HOLD mode
inactive
inactive
HALT mode
• When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is
equal to V 1.
DD
• Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with
when the reference voltage circuit is inactive.
Example 1: V 1=V 2=3.3V
DD DD
• Inactivating the reference voltage circuit (selection (4)).
• Connecting V 3 to V 1 and V 2.
DD DD DD
LSI
For backup
Power Supply
3.3V
V
1
DD
UHD+
UHD-
33Ω
To USB connector
V
2
DD
15kΩ
5pF
V
3
DD
UFILT
0Ω
V
2 V 3
SS
V
1
SS
SS
2.2μF
Example 2: V 1=V 2=5.0V
DD DD
• Activating the reference voltage circuit (selection (1)).
• Isolating V 3 from V 1 and V 2, and connecting capacitor between V 3 and V .
DD
DD
DD
DD
SS
LSI
For backup
V
V
1
UHD+
UHD-
Power Supply
5V
DD
33Ω
To USB connector
2
DD
15kΩ
5pF
V
3
DD
UFILT
2.2μF
0Ω
0.1μF
V
1
V
2 V
3
SS
SS
SS
2.2μF
No.A0956-11/27
LC87F1HC8A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
1= V 2= V 3
DD
V
[V]
min
-0.3
unit
V
DD
Maximum supply
voltage
V
max
V
1, V 2, V
3
V
DD
DD
DD
DD
DD
DD
+6.5
+0.3
Input voltage
V (1)
XT1, CF1
-0.3
-0.3
V
V
I
DD
Input/output
voltage
V
(1)
Ports 0, 1, 2, 3, 7
PWM0, PWM1
XT2
IO
+0.3
DD
Peak output
current
IOPH(1)
Ports 0, 1, 2
• When CMOS output
type is selected
-10
-20
-5
• Per 1 applicable pin
Per 1 applicable pin
IOPH(2)
IOPH(3)
PWM0, PWM1
Port 3
• When CMOS output
type is selected
P71 to P73
• Per 1 applicable pin
• When CMOS output
type is selected
Average
IOMH(1)
Ports 0, 1, 2
output current
(Note 1-1)
-7.5
-15
-3
• Per 1 applicable pin
Per 1 applicable pin
IOMH(2)
IOMH(3)
PWM0, PWM1
Port 3
• When CMOS output
type is selected
P71 to P73
• Per 1 applicable pin
Total current of all
applicable pins
Total output
current
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
IOPL(1)
Ports 0, 2
-25
-25
-45
-10
-25
Port 1
Total current of all
applicable pins
PWM0, PWM1
Ports 0, 1, 2
PWM0, PWM1
Port 3
Total current of all
applicable pins
Total current of all
applicable pins
P71 to P73
UHD+, UHD-
Total current of all
applicable pins
mA
Peak output
current
P02 to P07
Ports 1, 2
Per 1 applicable pin
20
PWM0, PWM1
P00, P01
IOPL(2)
IOPL(3)
Per 1 applicable pin
Per 1 applicable pin
30
10
Ports 3, 7
XT2
Average
IOML(1)
P02 to P07
Ports 1, 2
PWM0, PWM1
P00, P01
Per 1 applicable pin
output current
(Note 1-1)
15
IOML(2)
IOML(3)
Per 1 applicable pin
Per 1 applicable pin
20
Ports 3, 7
XT2
7.5
Total output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
Pd max
Topr
Ports 0, 2
Total current of all
applicable pins
45
45
Port 1
Total current of all
applicable pins
PWM0, PWM1
Ports 0, 1, 2
PWM0, PWM1
Ports 3, 7
Total current of all
applicable pins
80
Total current of all
applicable pins
15
XT2
UHD+, UHD-
Total current of all
applicable pins
25
Allowable power
Dissipation
SQFP48(7×7)
Ta=-40 to +85°C
140
+85
mW
Operating ambient
Temperature
-40
-55
°C
Storage ambient
temperature
Tstg
+125
Note 1-1: The average output current is an average of current values measured over 100ms intervals.
No.A0956-12/27
LC87F1HC8A
Allowable Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
1=V 2=V
DD
Conditions
V
[V]
unit
min
3.0
typ
max
DD
Operating
V
(1)
V
3
3
0.245µs ≤ tCYC ≤ 200µs
5.5
5.5
DD
DD
DD
DD
supply voltage
(Note 2-1)
0.490µs ≤ tCYC ≤ 200µs Except
in onboard programming mode
RAM and register contents
sustained in HOLD mode.
2.7
Memory
VHD
V
1=V 2=V
DD
DD
sustaining
supply voltage
High level
2.0
5.5
V
(1)
Port 0, 1, 2, 3
P71 to P73
IH
input voltage
0.3V
DD
P70 port input/
interrupt side
PWM0, PWM1
2.7 to 5.5
V
V
DD
+0.7
V
(2)
Port 70 watchdog
timer side
IH
2.7 to 5.5
2.7 to 5.5
4.0 to 5.5
0.9V
DD
DD
V
V
V
(3)
XT1, XT2, CF1,
RES
0.75V
V
IH
DD
DD
Low level
(1)
(2)
(3)
(4)
(5)
(6)
Port 1, 2, 3
P71 to P73
P70 port input/
interrupt side
Port 0
0.1V
IL
IL
IL
IL
IL
IL
DD
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
input voltage
+0.4
V
V
V
V
V
2.7 to 4.0
4.0 to 5.5
2.7 to 4.0
2.7 to 5.5
0.2V
DD
DD
0.15V
PWM0, PWM1
+0.4
0.2V
DD
DD
Port 70 watchdog
timer side
0.8V
-1.0
XT1, XT2, CF1,
RES
2.7 to 5.5
3.0 to 5.5
2.7 to 5.5
0.25V
DD
Instruction
cycle time
(Note 2-2)
tCYC
0.245
0.490
200
μs
Except for onboard programming
mode
200
12
External
FEXCF(1)
CF1
• CF2 pin open
system clock
frequency
• System clock frequency
division ratio=1/1
3.0 to 5.5
0.1
0.1
• External system clock duty
=50 5%
MHz
• CF2 pin open
• System clock frequency
division ratio=1/1
2.7 to 5.5
3.0 to 5.5
6
• External system clock duty
=50 5%
Oscillation
frequency
range
FmCF(1)
FmCF(2)
CF1, CF2
CF1, CF2
When 12MHz ceramic oscillation
See Fig. 1.
12
When 6MHz ceramic oscillation
See Fig. 1.
MHz
kHz
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
6
1.0
(Note 2-3)
FmRC
FsX’tal
Internal RC oscillation
0.3
2.0
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
32.768
Note 2-1: V
DD
must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0956-13/27
LC87F1HC8A
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
DD
High level input
current
I
(1)
Ports 0, 1, 2, 3
Port 7
Output disabled
Pull-up resistor off
=V
IH
V
2.7 to 5.5
1
RES
IN DD
PWM0, PWM1
UHD+, UHD-
XT1, XT2
(Including output Tr's off leakage
current)
I
(2)
(3)
Input port configuration
IH
2.7 to 5.5
2.7 to 5.5
1
V
=V
IN DD
I
I
CF1
V
=V
15
IH
IN DD
μA
Low level input
current
(1)
Ports 0, 1, 2, 3
Port 7
Output disabled
IL
Pull-up resistor off
V
=V
2.7 to 5.5
-1
-1
RES
IN SS
PWM0, PWM1
UHD+, UHD-
XT1, XT2
(Including output Tr's off leakage
current)
I
I
(2)
(3)
Input port configuration
IL
2.7 to 5.5
V
V
=V
IN SS
CF1
=V
2.7 to 5.5
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
3.0 to 5.5
2.7 to 5.5
4.5 to 5.5
2.7 to 5.5
-15
-1
IL
IN SS
High level output
voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
(1)
Ports 0, 1, 2, 3
P71 to P73
I
=-1mA
OH
V
OH
OH
OH
OH
OH
OH
DD
(2)
(3)
(4)
(5)
(6)
I
I
I
I
I
I
I
I
I
I
I
I
I
=-0.4mA
V
V
V
V
V
-0.4
-0.4
-1.5
-0.4
-0.4
OH
DD
DD
DD
DD
DD
=-0.2mA
=-10mA
=-1.6mA
=-1mA
OH
OH
OH
OH
PWM0, WM1
P05 to P07
(Note 3-1)
Low level output
voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
P00, P01
=30mA
1.5
0.4
0.4
1.5
0.4
0.4
0.4
0.4
80
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
V
=5mA
=2.5mA
=10mA
=1.6mA
=1mA
Ports 0, 1, 2
PWM0, PWM1
XT2
Ports 3, 7
=1.6mA
=1mA
Pull-up resistance
Rpu(1)
Rpu(2)
VHYS
Ports 0, 1, 2, 3
Port 7
V
=0.9V
15
18
35
OH
DD
kΩ
50
150
Hysteresis voltage
Pin capacitance
RES
2.7 to 5.5
0.1V
V
DD
Port 1, 2, 3, 7
All pins
CP
For pins other than that under test:
=V
V
IN SS
2.7 to 5.5
10
pF
f=1MHz
Ta=25°C
Note 3-1: When the CKO system clock output function (P05) or audio interface output function (P05 to P07) is used.
No.A0956-14/27
LC87F1HC8A
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Pin/
Parameter
Frequency
Symbol
tSCK(1)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK0(P12)
See Fig. 8.
2
1
1
Low level
tSCKL(1)
pulse width
High level
pulse width
tSCKH(1)
tSCKHA(1a)
• Continuous data transfer mode
• USB, AIF, SIO4, SIO9, and
DMCOPY not used at the same
time.
4
7
9
• See Fig. 8.
• (Note 4-1-2)
2.7 to 5.5
tSCKHA(1b)
tSCKHA(1c)
• Continuous data transfer mode
• USB used at the same time.
• AIF, SIO4, SIO9, and DMCOPY
not used at the same time.
• See Fig. 8.
tCYC
• (Note 4-1-2)
• Continuous data transfer mode
• USB, AIF, SIO4, SIO9, and
DMCOPY used at the same
time.
• See Fig. 8.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• When CMOS output type is
selected
4/3
• See Fig. 8.
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2a)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Continuous data transfer mode
• USB, AIF, SIO4, SIO9, and
DMCOPY not used at the same
time.
tSCKH(2)
+
tSCKH(2)
+2tCYC
• When CMOS output type is
selected
(10/3)tCYC
• See Fig. 8.
2.7 to 5.5
tSCKHA(2b)
• Continuous data transfer mode
• USB used at the same time.
• AIF, SIO4, SIO9, and DMCOPY
not used at the same time.
• When CMOS output type is
selected.
tSCKH(2)
+
tCYC
tSCKH(2)
+2tCYC
(19/3)tCYC
• See Fig. 8.
tSCKHA(2c)
• Continuous data transfer mode
• USB, AIF, SIO4, SIO9, and
DMCOPY used at the same time
• When CMOS output type is
selected
tSCKH(2)
+
tSCKH(2)
+2tCYC
(25/3)tCYC
• See Fig. 8.
Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-1-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the time
from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be longer
than tSCKHA.
Continued on next page.
No.A0956-15/27
LC87F1HC8A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Data setup time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 8.
0.03
2.7 to 5.5
Data hold time
0.03
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data transfer mode
• (Note 4-1-3)
(1/3)tCYC
+0.05
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
2.7 to 5.5
(Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 8.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Pin/
Parameter
Frequency
Symbol
tSCK(3)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK1(P15)
SCK1(P15)
See Fig. 8.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
• When CMOS output type is
selected
• See Fig. 8.
Low level
pulse width
High level
1/2
1/2
tSCK
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 8.
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
μs
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
change in open drain output
mode.
(1/3)tCYC
+0.05
2.7 to 5.5
• See Fig. 8.
Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
No.A0956-16/27
LC87F1HC8A
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
Frequency
tSCK(5)
SCK4(P24)
See Fig. 8.
2
1
1
Low level
tSCKL(5)
pulse width
High level
pulse width
tSCKH(5)
tSCKHA(5a)
• USB, SIO0 continuous transfer
mode, AIF, SIO9, and DMCOPY
not used at the same time.
• See Fig. 8.
4
• (Note 4-3-2)
tSCKHA(5b)
tSCKHA(5c)
• USB used at the same time
• SIO0 continuous transfer mode,
AIF, SIO9, DMCOPY not used at
the same time.
2.7 to 5.5
tCYC
7
• See Fig. 8.
• (Note 4-3-2)
• USB, SIO0 continuous transfer
mode, SIO9,
and DMCOPY used at the same
time.
12
• AIF not used at the same time.
• See Fig. 8.
• (Note 4-3-2)
Frequency
tSCK(6)
SCK4(P24)
• When CMOS output type is
selected.
4/3
Low level
tSCKL(6)
1/2
1/2
• See Fig. 8.
pulse width
High level
pulse width
(Note 4-3-3)
tSCK
tSCKH(6)
tSCKHA(6a)
• USB, SIO0 continuous transfer
mode, AIF, SIO9, and
DMCOPY not used at the same
time.
tSCKH(6)
+
tSCKH(6)
+
• When CMOS output type is
selected.
(5/3)tCYC
(10/3)tCYC
• See Fig. 8.
tSCKHA(6b)
• USB used at the same time.
• SIO0 continuous transfer mode,
AIF, SIO9, and DMCOPY not
used at the same time.
• When CMOS output type is
selected.
2.7 to 5.5
tSCKH(6)
+
tSCKH(6)
+
tCYC
(5/3)tCYC
(19/3)tCYC
• See Fig. 8.
tSCKHA(6c)
• USB, SIO0 continuous transfer
mode, SIO9, and DMCOPY used
at the same time.
tSCKH(6)
+
tSCKH(6)
+
• AIF not used at the same time.
• When CMOS output type is
selected.
(5/3)tCYC
(34/3)tCYC
• See Fig. 8.
Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-3-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period
from the time SI4RUN is set with the serial clock set high to the falling edge of the first serial clock must
be longer than tSCKHA.
Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following
conditions:
Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, V =3.3V
DD
Continued on next page.
No.A0956-17/27
LC87F1HC8A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Data setup time
tsDI(3)
thDI(3)
tdD0(5)
SO4(P22),
SI4(P23)
• Must be specified with respect
to falling edge of SIOCLK.
• See Fig. 8
0.03
2.7 to 5.5
Data hold time
0.03
μs
Output delay time
SO4(P22),
SI4(P23)
• Must be specified with respect
to rising edge of SIOCLK.
• Must be specified as the time to
the beginning of output state
change in open drain output
mode.
(1/3)tCYC
+0.05
2.7 to 5.5
• See Fig. 8.
4. SIO9 Serial I/O Characteristics (Note 4-4-1)
Specification
typ max
Pin/
Parameter
Frequency
Symbol
tSCK(7)
Conditions
Remarks
V
[V]
min
unit
DD
SCK9(P27)
See Fig. 8.
2
1
1
Low level
tSCKL(7)
pulse width
High level
pulse width
tSCKH(7)
tSCKHA(7a)
• USB, SIO0 continuous transfer
mode, AIF, SIO4 and DMCOPY
not used at the same time.
• See Fig. 8.
4
• (Note 4-4-2)
2.7 to 5.5
tCYC
tSCKHA(7b)
tSCKHA(7c)
• USB used at the same time.
• SIO0 continuous transfer mode,
AIF, SIO4, and DMCOPY not
used at the same time.
• See Fig. 8.
7
• (Note 4-4-2)
• USB, SIO0 continuous transfer
mode, SIO4 and DMCOPY used
at the same time.
15
• AIF not used at the same time.
• See Fig. 8.
• (Note 4-4-2)
Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-4-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period
from the time SI9RUN is set with the serial clock set high to the falling edge of the first serial clock must
be longer than tSCKHA.
Continued on next page
No.A0956-18/27
LC87F1HC8A
Continued from preceding page
Parameter Symbol
Frequency
Specification
Pin/
Conditions
Remarks
V
[V]
min
4/3
typ
max
unit
DD
tSCK(8)
SCK9(P27)
• When CMOS output type is
selected.
tCYC
• See Fig. 8.
Low level
tSCKL(8)
tSCKH(8)
tSCKHA(8a)
1/2
1/2
pulse width
High level
pulse width
(Note 4-4-3)
tSCK
• USB, SIO0 continuous transfer
mode, AIF SIO4 DMCOPY not
used at the same time.
• When CMOS output type is
selected.
tSCKH(8)
+
tSCKH(8)
+
(5/3)tCYC
(10/3)tCYC
• See Fig. 8.
tSCKHA(8b)
• USB used at the same time.
• SIO0 continuous transfer mode,
AIF, SIO4, and DMCOPY not
used at the same time.
• When CMOS output type is
selected
2.7 to 5.5
tSCKH(8)
+
tSCKH(8)
+
tCYC
(5/3)tCYC
(19/3)tCYC
• See Fig. 8.
tSCKHA(8c)
• USB, SIO0 continuous transfer
mode , SIO4, and DMCOPY
used at the same time.
• AIF not used at the same time.
• When CMOS output type is
selected.
tSCKH(8)
+
tSCKH(8)
+
(5/3)tCYC
(43/3)tCYC
• See Fig. 8.
Data setup time
Data hold time
tsDI(4)
thDI(4)
tdDO(6)
SO9(P25),
SI9(P26)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 8.
0.03
0.03
2.7 to 5.5
μs
Output delay time
SO9(P25),
SI9(P26)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time to
the beginning of output state
change in open drain output
mode
(1/3)tCYC
+0.05
2.7 to 5.5
• See Fig. 8.
Note 4-4-3: When using the serial clock output, make sure that the load at the SCK9 (P27) pin meets the following
conditions:
Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, V =3.3V
DD
No.A0956-19/27
LC87F1HC8A
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High/low level
pulse width
tP1H(1)
tP1L(1)
INT0(P70), INT1(P71),
INT2(P72),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
INT4(P20 to P23),
INT5(P24 to P27),
INT6(P20),
2.7 to 5.5
1
2
INT7(P24)
tPIH(2)
tPIL(2)
INT3(P73) when noise
filter time constant is
1/1
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
tCYC
tPIH(3)
tPIL(3)
INT3(P73) when noise
filter time constant is
1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are
nabled.
64
tPIH(4)
tPIL(4)
INT3(P73) when noise
filter time constant is
1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
256
tPIL(5)
RMIN(P73)
Recognized by the infrared remote
control receiver circuit as a signal
RMCK
2.7 to 5.5
2.7 to 5.5
4
(Note 5-1)
RES
tPIL(6)
Resetting is enabled.
200
μs
Note 5-1: Represents the period of the reference clock (1 tCYC to 128 tCYC or the source frequency of the subclock)
for the infrared remote control receiver circuit.
AD Converter Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
bit
DD
Resolution
N
AN0(P00) to
AN7(P07),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
3.0 to 5.5
8
Absolute
ET
(Note 6-1)
3.0 to 5.5
1.5
LSB
accuracy
Conversion time
TCAD
AD conversion time=32×tCYC
15.68
(tCYC=
0.490µs)
23.52
97.92
(tCYC=
3.06µs)
97.92
(when ADCR2=0) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
(tCYC=
0.735µs)
18.82
(tCYC=
3.06µs)
97.92
μs
AD conversion time=64×tCYC
(when ADCR2=1) (Note 6-2)
(tCYC=
0. 294µs)
47.04
(tCYC=
1.53µs)
97.92
3.0 to 5.5
3.0 to 5.5
(tCYC=
0.735µs)
(tCYC=
1.53µs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
μA
VAIN=V
SS
-1
Note 6-1: The quantization error ( 1/2LSB) is excluded from the absolute accuracy.
Note 6-2: The conversion time refers to the period from the time when an instruction for starting a conversion process is
issued to the time the conversion results register(s) are loaded with a complete digital conversion value
corresponding to the analog input value.
No.A0956-20/27
LC87F1HC8A
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• USB circuit stopped
DD
=V
2
3
DD
DD
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
9.8
24
=V
(Note 7-1)
IDDOP(2)
IDDOP(3)
5.7
15
14
35
20
• 1/1 frequency division ratio
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode active
• Internal RC oscillation stopped
• USB circuit active
IDDOP(4)
mA
7.7
• 1/1 frequency division ratio
IDDOP(5)
IDDOP(6)
IDDOP(7)
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal RC oscillation stopped
• 1/2 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.7 to 3.0
6.7
3.9
3.2
16
9.0
7.3
• FmCF=0Hz(oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation.
• 1/2 frequency division ratio
IDDOP(8)
IDDOP(9)
4.5 to 5.5
3.0 to 3.6
0.72
0.41
3.4
1.9
IDDOP(10)
IDDOP(11)
2.7 to 3.0
4.5 to 5.5
0.35
45
1.5
• FmCF=0Hz(oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to crystal oscillation.
(32.768kHz)
184
IDDOP(12)
IDDOP(13)
IDDHALT(1)
μA
3.0 to 3.6
2.7 to 3.0
18
14
65
47
• Internal RC oscillation stopped
• 1/2 frequency division ratio
HALT mode
consumption
current
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• USB circuit stopped
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.9
2.7
9.5
4.7
12
6.4
23
(Note7-1)
IDDHALT(2)
IDDHALT(3)
• 1/1 frequency division ratio
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode active
• Internal RC oscillation stopped
• USB circuit active
IDDHALT(4)
mA
12
• 1/1 frequency division ratio
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
• HALT mode
4.5 to 5.5
3.0 to 3.6
2.7 to 3.0
3.0
1.6
1.3
7.3
3.8
2.9
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal RC oscillation stopped
• 1/2 frequency division ratio
IDDHALT(8)
IDDHALT(9)
IDDHALT(10)
• HALT mode
4.5 to 5.5
3.0 to 3.6
2.7 to 3.0
0.41
0.20
0.17
2.0
0.95
0.70
• FmCF=0Hz(oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation.
• 1/2 frequency division ratio
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0956-21/27
LC87F1HC8A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(11)
V
1
• HALT mode
DD
4.5 to 5.5
3.0 to 3.6
31
132
=V
2
3
• FmCF=0MHz (oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to crystal oscillation.
(32.768kHz)
DD
DD
=V
IDDHALT(12)
IDDHALT(13)
9.1
6.3
39
27
(Note 7-1)
• Internal RC oscillation stopped
• 1/2 frequency division ratio
• HOLD mode
2.7 to 3.0
μA
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
IDDHOLD(5)
IDDHOLD(6)
V
1
4.5 to 5.5
3.0 to 3.6
2.7 to 3.0
4.5 to 5.5
3.0 to 3.6
0.14
0.04
0.04
25
39
19
DD
• CF1=V
DD
or open (External clock mode)
17
Timer HOLD
mode
• Timer HOLD mode
• CF1=V or open (External clock mode)
115
32
DD
• FsX’tal=32.768kHz crystal oscillation mode
6.0
consumption
current
2.7 to 3.0
3.7
20
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
USB Characteristics and Timing at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Conditions
min
typ
max
unit
V
High level output
Low level output
V
V
V
V
• 15kΩ 5% to GND
2.8
3.6
0.3
2.0
OH(USB)
OL(USB)
CRS
• 1.5kΩ 5% to 3.6V
• ⏐(UHD+)-(UHD-)⏐
0.0
1.3
0.2
V
Output signal crossover voltage
Differential input sensitivity
V
DI
V
Differential input common mode range
High level input
V
V
V
t
0.8
2.0
2.5
V
V
CM
IH(USB)
IL(USB)
Low level input
0.8
20
20
V
USB data rise time
• R =33Ω, C =50pF
4
4
ns
ns
R
S
L
USB data fall time
t
• R =33Ω, C =50pF
S L
F
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = 0V
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
10
unit
mA
DD
Onboard programming
current
IDDFW(1)
V
1
• Excluding power dissipation in the
microcontroller block
DD
3.0 to 5.5
3.0 to 5.5
5
Programming time
tFW(1)
tFW(2)
• Erase operation
20
40
30
60
ms
• Write operation
μs
No.A0956-22/27
LC87F1HC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 shows the characteristics of a oscillation circuit when USB host function is not used.
If USB host function is to be used, it is absolutely recommended to use an oscillator that satisfies the precision and
stability according to the USB standards.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[ms]
6MHz
8MHz
MURATA
MURATA
MURATA
MURATA
CSTCR6M00GH5L**-R0
CSTCE8M00GH5L**-R0
CSTCE10M0GH5L**-R0
CSTCE12M0GH5L**-R0
(39)
(33)
(33)
(33)
(39)
(33)
(33)
(33)
1k
2.7 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
0.1
0.1
0.1
0.1
0.5
0.5
0.5
0.5
C1 and C2
470
330
330
integrated
SMD type
10MHz
12MHz
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the
following cases (see Figure 4):
• Till the oscillation gets stabilized after V
goes above the operating voltage lower limit.
DD
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed
• Till the oscillation gets stabilized after the HOLD mode is reset.
• Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C3
C4
Rf
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
Applicable
CL value=12.5pF
SMD type
EPSON
32.768kHz
MC-306
18
18
OPEN
560k
2.7 to 5.5
1.1
3.0
TOYOCOM
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the
following cases (see Figure 4):
• Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed
• Till the oscillation gets stabilized after the HOLD mode is reset with EXTOSC (OCR register, bit 6) set to 1
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf
Rd1
Rd2
C1
C2
C3
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
No.A0956-23/27
LC87F1HC8A
0.5V
DD
Figure 3 AC Timing Measurement Point
V
DD
Operating V
lower limit
GND
DD
Power supply
RES
Reset time
Internal RC
oscillation
tmsCF
CF1, CF2
XT1, XT2
tmsX’tal
Operating
mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF1,CF2
tmsX’tal
XT1, XT2
HOLD
HALT
Operating mode
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A0956-24/27
LC87F1HC8A
P34/UFILT
When using the internal PLL circuit to generate the
Rd
0kΩ
48MHz clock for USB , it is necessary to connect a filter
circuit such to the P34/UFILT pin such as that shown in
the left Fig.
+
-
Cd
2.2μF
Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit
P33/AFILT
To generate the master clock for the audio
Rd
Cp
1μF
interface using the internal PLL circuit, it is
necessary to connect a filter circuit to the
P33/AFILT pin that is shown in the left Fig.
+
-
150Ω
+
Cd
4.7μF
-
Figure 6 External Filter Circuit for Audio Interface (Used with Internal PLL Circuit)
33Ω
UHD+
5pF
It’s necessary to adjust the Circuit Constant
of the USB Port Peripheral Circuit for each
mounting board.
15kΩ
15kΩ
33Ω
UHD-
5pF
Figure 7 USB Port Peripheral Circuit
No.A0956-25/27
LC87F1HC8A
V
DD
Note:
R
RES
Determine the value of C
and R so
RES
RES
that the reset signal is present for a period of
200µs after the supply voltage goes beyond the
lower limit of the IC's operating voltage.
RES
C
RES
Figure 8 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer
period (SIO0, 4, 9 only)
tSCK
tSCKL
tSCKH
thDI
SIOCLK:
tsDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer
period (SIO0, 4, 9 only)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 9 Serial Input/Output Waveform
No.A0956-26/27
LC87F1HC8A
tPIL
tPIH
Figure 10 Pulse Input Timing Signal Waveform
t
t
r
D+
D-
r
V
V
oh
90%
90%
crs
10%
10%
V
ol
Figure 11 USB Data Signal Timing and Voltage Level
tSCKR:
V
(1) min=0.3V +0.7V
IH DD
Defined as the time period from the time the
state of the output starts changing till the
time it reaches the minimum value of
tSCKR
V
(1).
IH
Figure 12 Serial Clock Output Timing Signal Waveform
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of December, 2008. Specifications and information herein are subject
to change without notice.
No.A0956-27/27
PS
相关型号：
LC87F1HC8SA
CMOS IC FROM 128K byte, RAM 16384 byte on-chip 8-bit 1-chip Microcontroller with USB-host controller
SANYO
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