LC72343W [SANYO]
Low-Voltage Single-Chip Microcontrollers with On- Chip PLL and LCD Driver Circuits; 低电压的单芯片微控制器与片上PLL和LCD驱动电路
| 型号： | LC72343W |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Low-Voltage Single-Chip Microcontrollers with On- Chip PLL and LCD Driver Circuits |
| 文件： | 总12页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN*5799
CMOS IC
LC72341G/W, LC72342G/W, LC72343G/W
Low-Voltage Single-Chip Microcontrollers with On-
Chip PLL and LCD Driver Circuits
Preliminary
Overview
The LC72341G/W, LC72342G/W, and LC72343G/W are
single-chip microcontrollers with both a 1/4-duty 1/2-bias
LCD driver circuit and a PLL circuit that can operate at up
to 250 MHz integrated on the same chip. These ICs are
ideal for use in portable audio equipment.
Reference frequencies of 1, 3, 5, 6.25, 12.5, and
25 kHz can be provided.
• Input frequency range
— FM band: 10 to 130 MHz
130 to 250 MHz
— AM band: 0.5 to 15 MHz
Functions
• High-speed programmable divider
• Program memory (ROM)
Package Dimensions
unit: mm
— LC72341G/W: 2048 words × 16 bits (4KB)
— LC72342G/W: 3072 words × 16 bits (6KB)
— LC72343G/W: 4096 words × 16 bits (8KB)
• Data memory (RAM)
3159-QFP64G
[LC72341G, 72342G, 72343G]
— LC72341G/W: 128 words × 4 bits
— LC72342G/W: 192 words × 4 bits
— LC72343G/W: 256 words × 4 bits
• Instruction cycle time
— 40 µs (for all single-word instructions.)
• Stack
— 4 levels (LC72341G/W)
— 8 levels (LC72342G/W, and LC72343G/W)
• LCD driver
— 48 to 80 segments (1/4-duty 1/2-bias drive)
• Timer interrupts
SANYO: QFP64G
— One timer circuit providing intervals of 1, 5, 10, and
50 ms.
• External interrupts
— One external interrupt (INT)
• A/D converter
unit: mm
3159-SQFP64
[LC72341W, 72342W, 72343W]
— Two channels (5-bit successive approximation)
• Input ports
— 7 (Of which two can be switched to function as A/D
converter inputs)
• Output ports
— 6 (Of which one can be switched to function as the
BEEP tone output. Two ports are open-drain ports.)
• I/O
ports
— 16 (Of which 8 can be selected to function as LCD
ports as mask options.)
• PLL circuit
— Two types of dead band control are supported, and an
unlock detection circuit is included.
SANYO: SQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
31398RM (OT) No. 5799-1/12
LC72341G/W, 72342G/W, 72343G/W
• IF counter
— HCTR input pin; 0.4 to 12 MHz
• Voltage detection circuit (VSENSE)
— Detects the V voltage and sets a flag
DD
• External reset pin
— Restarts execution from location 0 when the CPU and PLL circuits are operating
• Power on reset circuit
— Starts execution from location 0 at power on.
• Universal counter
— 20 bits
• Beep tones
— 3.1 and 1.5 kHz
• Halt mode: The microcontroller operating clock is stopped
• Backup mode: The crystal oscillator is stopped
• An amplifier for a low-pass filter is built in
• CPU and PLL circuit operating voltage
— 1.8 to 3.6 V
• RAM data retention voltage
— 1.0 V or higher
• Packages
— QIP-64G : 0.8-mm lead pitch
— SQFP-64 : 0.5-mm lead pitch
Pin Assignment
* PE0 and PE1 are open-drain outputs.
* The I/O ports can be set to input or output individually.
* The functions of the segment/general-purpose ports can be set in bit units.
No. 5799-2/12
LC72341G/W, 72342G/W, 72343G/W
Block Diagram
Phase-
detector
Reference divider
Divider
System clock
generator
Programmable divider
PLL data latch
PLL control
LCD
Port
Lach
Time base
control
driver
count end
Universal counter
(20 bits)
Pon
reset
Data
latch/
Bus
Address
decoder
driver
Bus
Bank
driver
Data
latch/
Bus
Data
latch/
Bus
Bus
driver
control
driver
Doubler
circuit
Instruction
decoder
Data
latch/
Bus
driver
Address decoder
Program counter
Skip
JMP CAL
Common
driver
Return
interrupt
reset
Data
latch/
Bus
Beep tone
driver
Stack
Bank
Data
latch/
Bus
Latch
Judge
A
driver
Latch
B
Timer 0
Data
latch/
Bus
driver
Data bus
No. 5799-3/12
LC72341G/W, 72342G/W, 72343G/W
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
–0.3 to +4.0
–0.3 to VDD + 0.3
–0.3 to +15
–0.3 to VDD to + 0.3
0 to 3
Unit
V
VDD max
Input voltage
VIN
All input pins
AOUT, PE
V
V
V
OUT1
OUT2
V
Output voltage
All output pins except VOUT
PC, PD, PG, PH, EO
PB
1
V
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
mA
mA
mA
µA
mA
mW
°C
°C
0 to 1
Output current
AOUT, PE
0 to 2
S1 to S20
300
COM1 to COM4
Ta = –20 to +70°C
3
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
300
–20 to +70
–45 to +125
Tstg
Allowable Operating Ranges at Ta = –20 to 70°C, V = 1.8 to 3.6 V
DD
Ratings
Parameter
Symbol
Conditions
Unit
min
1.8
typ
3.0
max
3.6
V
DD1
DD2
CPU and PLL operating voltage
Memory retention voltage
V
V
Supply voltage
V
1.0
VIH2, VIH3, AMIN, FMIN,
Input ports except HCTR and XIN.
VIH1
0.7 VDD
VDD
V
Input high-level voltage
Input low-level voltage
V
IH2
IH3
RES
0.8 VDD
0.6 VDD
VDD
VDD
V
V
V
Port PF
VIL2, VIL3, AMIN, FMIN,
Input ports except HCTR and XIN.
VIL1
0
0.3 VDD
V
VIL2
VIL3
RES
0
0
0.2 VDD
0.2 VDD
0.6
V
Port PF
V
VIN1
VIN2
VIN3
VIN4
VIN5
FIN1
FIN2
FIN3
XIN
0.5
0.035
0.05
0.035
0
Vrms
Vrms
Vrms
Vrms
V
FMIN, AMIN
FMIN
0.35
0.35
0.35
VDD
80
Input amplitude
HCTR
Input voltage range
ADI0, ADI1
XIN : CI ≤ 35 kΩ
70
75
kHz
MHz
MHz
MHz
MHz
MHz
FMIN : VIN2, VDD
1
1
10
130
250
40
FMIN : VIN3, VDD
130
2
Input frequency
FIN
4
AMIN (H) : VIN2, VDD
AMIN (L) : VIN2, VDD
HCTR : VIN4, VDD
1
F
F
IN5
IN6
1
0.5
0.4
10
1
12
Electrical Characteristics at Ta = –20 to 70°C, V = 1.8 to 3.6 V (in the allowable operating ranges)
DD
Ratings
Parameter
Symbol
Conditions
XIN : VI = VDD = 3.0 V
Unit
min
typ
max
I
IH1
IH2
3
µA
µA
I
FMIN, AMIN, HCTR : VI = VDD = 3.0 V
3
8
20
Input high-level current
Ports PA/PF (with no pull-down resistor), PC,
PD, PG, and PH. RES: VI = VDD = 3.0 V
IIH3
3
µA
IIL1
IIL2
XIN : VI = VDD = VSS
–3
µA
µA
FMIN, AMIN, HCTR : VI = VDD = VSS
–3
–8
–20
Input low-level current
Ports PA/PF (with no pull-down resistor), PC,
PD, PG, and PH. RES: VI = VDD = VSS
IIL3
VIF
–3
µA
Input floating voltage
PA/PF with pull-down resistors used
0.05 VDD
200
V
kΩ
V
Pull-down resistance
RPD1
PA/PF with pull-down resistors used, V = 3 V
DD
75
0.1 VDD
1.3
100
0.2 VDD
1.5
Hysteresis
VH
RES
Voltage doubler reference voltage
Voltage doubler step-up voltage
DBR4
Ta = 25°C, referenced to VDD, C3 = 0.47 µF
1.7
3.3
V
DBR1, 2, 3 Ta = 25°C, C1 = 0.45 µF, C2 = 0.47 µF, no load
2.7
3.0
V
No. 5799-4/12
LC72341G/W, 72342G/W, 72343G/W
Note: C1, C2, and C3 must be provided even if no LCD is used.
Electrical Characteristics at Ta = –30 to 70°C, V = 1.8 to 3.6 V (in the allowable operating ranges)
DD
Ratings
Parameter
Symbol
VOH
Conditions
Unit
min
typ
max
1
PB : IO = –1 mA
V
V
V
V
– 0.7 V
– 0.3 V
– 0.3 V
– 0.3 V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
OH2
OH3
OH4
OH5
PC, PD, PG, PH : IO = –1 mA
EO : IO = –500 µA
Output high-level voltage
XOUT : IO = –200 µA
S1 to S20 : IO = –20 µA: *1
2.0
2.0
COM1, COM2, COM3, COM4:
O = –100 µA : *1
VOH6
V
I
V
OL1
PB : IO = –50 µA
0.7 VDD
0.3 VDD
0.3 VDD
0.3 VDD
1.0
V
V
V
V
V
VOL
2
PC, PD, PE, PG, PH : IO = –1 mA
EO : IO = –500 µA
V
V
V
OL3
OL4
OL5
XOUT : IO = –200 µA
Output low-level voltage
S1 to S20 : IO = –20 µA: *1
COM1, COM2, COM3, COM4 :
VOL6
1.0
V
IO = –100 µA : *1
V
V
OL7
OL8
PE : IO = 5 mA
1.0
0.5
V
V
AOUT : IO = 1 mA, AIN = 1.3 V, VDD = 3 V
Ports PB, PC, PD, PG, PH, and EO
Ports AOUT and PE
I
OFF1
OFF2
–3
–100
–1/2
+3
µA
nA
LSB
Output off leakage current
A/D conversion error
I
+100
+1/2
ADI0, ADI1, VDD = VDD
1
Note: 1. Capacitors C1, C2, and C3 must be connected to the DBR pins.
Electrical Characteristics at Ta = –20 to 70°C, V = 1.8 to 3.6 V (in the allowable operating ranges)
DD
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
1.75
max
Falling supply voltage detection voltage
Rising supply voltage detection voltage
Pull-down resistance
VSENSE1 Ta = 25°C *2
1.6
1.9
V
VSENSE2 Ta = 25°C *2
VSENSE1 +0.1
VSENSE1 +0.2
V
R
PD2
TEST1, TEST2
10
10
kΩ
mA
mA
I
DD1
VDD1 : FIN2 130 MHz, Ta = 25°C
IDD
2
3
VDD2: In halt mode at Ta = 25°C, *3
0.1
VDD = 3.6 V, with the oscillator stopped,
Supply current
IDD
1
µA
µA
at Ta = 25°C, *4
VDD = 1.8 V, with the oscillator stopped,
I
DD4
0.5
at Ta = 25°C, *4
Note: The halt mode current is measured with the CPU executing 20 instructions every 125 ms.
No. 5799-5/12
LC72341G/W, 72342G/W, 72343G/W
Note: 2. The VSENSE voltage
When the VDD voltage falls, the VSENSE flag is set at the point that voltage falls under 1.75 V (typical). The TST instruction can be used to read the
value of the VSENSE flag. Applications can easily determine when the batteries are exhausted by monitoring this flag. After VSENSE is set when the
supply voltage falls, it will not be reset if the supply voltage rises by less than 0.1 V, because the voltages detected by the VSENSE circuit differ when
the supply voltage is falling and when the supply voltage is rising.
When the Supply Voltage is Rising
When the Supply Voltage is Falling
Note: 4. Backup Mode Current Test Circuit
Note: 3. Halt Mode Current Test Circuit
All ports other than those specified in the figure
must be left open.
All ports other than those specified in the figure
must be left open.
Set ports PC and PD to output.
Select segments S13 to S20.
Set ports PC and PD to output.
Select segments S13 to S20.
No. 5799-6/12
LC72341G/W, 72342G/W, 72343G/W
Pin Functions
Pin No.
Pin
I/O
Function
I/O circuit
64
1
XIN
I
Connections for a 75-kHz crystal oscillator element
XOUT
O
63
2
TEST1
TEST2
I
I
IC test pins. These pins must be tied to ground.
Input with built-in pull-
down resistor
6
5
4
3
PA0
PA1
PA2
PA3
Special-purpose key return signal input ports designed with a low threshold voltage.
When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key
presses can be detected. The four pull-down resistors are selected together in a single
operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually.
Input is disabled in backup mode, and the pull-down resistors are disabled after a reset.
I
Unbalanced CMOS
push-pull circuit
Special-purpose key source signal output ports. Since unbalanced CMOS output
transistor circuits are used, diodes to prevent short-circuits when multiple keys are
pressed are not required. These ports go to the output high-impedance state in backup
mode. These ports go to the output high-impedance state after a reset and remain in that
state until an output instruction (OUT, SPB, or RPB) is executed.
10
9
PB3
PB2
PB1
PB0
O
8
7
Care is required in designing the output loads if these pins are used for functions other
than key source outputs.
14
13
12
11
18
17
16
15
PC0
PC1
CMOS push-pull circuit
PC2
General-purpose I/O ports*. PD0 can be used as an external interrupt port. Input or
output mode can be set in a bit unit using the IOS instruction (Pwn = 4, 5). A value of 0
I/O specifies input, and 1 specifies output. These ports go to the input disabled high-
impedance state in backup mode. They are set to function as general-purpose input ports
after a reset.
PC3
INT/PD0
PD1
PD2
PD3
General-purpose output ports with shared beep tone output function (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port.
The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone
frequencies supported.
N-channel open drain
20
19
BEEP/PE0
PE1
When PE0 is set up as the beep tone output, executing an output instruction to PN0 only
changes the state of the internal output latch, it does not affect the beep tone output in
any way. Only the PE0 pin can be switched between the general-purpose output
function and the beep tone output function; the PE1 pin only functions as a general-
purpose output. These pins go to the high-impedance state in backup mode and remain
in that state until an output instruction or a BEEP instruction is executed. Since these
ports are open-drain ports, resistors must be inserted between these pins and VDD
These ports are set to their general-purpose output port function after a reset.
.
General-purpose input and A/D converter input shared function ports (PF2 is a general-
purpose input only port). The IOS instruction (Pwn = FH) is used to switch between the
general-purpose input and A/D converter port functions. The general-purpose input and
A/D converter port functions can be switched in a bit unit, with 0 specifying general-
purpose input, and 1 specifying the A/D converter input function. To select the A/D
converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1.
The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is
set when the conversion completes. The INR instruction is used to read in the data.
CMOS input/analog
input
23
22
21
PF0/ADI0
PF1/ADI1
PF2
I
If an input instruction is executed for one of these pins which is set up for analog input,
the read in data will be at the low level since CMOS input is disabled. In backup mode
these pins go to the input disabled high-impedance state. These ports are set to their
general-purpose input port function after a reset. The A/D converter is a 5-bit successive
approximation type converter, and features a conversion time of 1.28 ms. Note that the
full-scale A/D converter voltage (1FH) is (63 · 96)VDD
.
Note: * Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS
instruction when using the I/O switchable ports as output pins.
Continued on next page.
No. 5799-7/12
LC72341G/W, 72342G/W, 72343G/W
Continued from preceding page.
Pin No.
Pin
I/O
Function
I/O circuit
LCD driver segment output and general-purpose I/O shared function ports. The IOS
instruction is used for switching both between the segment output and general-purpose
I/O functions and between input and output for the general-purpose I/O port function.*
CMOS push-pull circuit
• When used as segment output ports
The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8).
b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3)
The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9).
b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3)
• When used as general-purpose I/O ports
25
26
27
28
PG3/S20
PG2/S19
PG1/S18
PG0/S17
The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can
be set in a bit unit.
I/O
29
30
31
32
PH3/S16
PH2/S15
PH1/S14
PH0/S13
b0 = PG0
b1 = PG1
b2 = PG2
b3 = PG3
b0 = PH0
b1 = PH1
b2 = PH2
b3 = PH3
[0: Input, 1: Output]
[0: Input, 1: Output]
In backup mode, these pins go to the input disabled, high-impedance state if set up as
general-purpose outputs, and are fixed at the low level if set up as segment outputs.
These ports are set up as segment outputs after a reset.
Although the general-purpose port/LCD port setting is a mask option, the IOS instruction
must be used as described above to set up the port function.
CMOS push-pull circuit
LCD driver segment output pins.
A 1/4-duty 1/2-bias drive technique is used.
The frame frequency is 75 Hz.
S16 to
S1
33 to 44
O
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
LCD driver common output pins.
COM4
COM3
COM2
COM1
45
46
47
48
A 1/4-duty 1/2-bias drive technique is used.
The frame frequency is 75 Hz.
O
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
DBR4
DBR3
DBR2
DBR1
49
50
51
52
LCD power supply stepped-up voltage pins.
System reset input.
In CPU operating mode or halt mode, applications must apply a low level for at least one
full machine cycle to reset the system and restart execution with the PC set to location 0.
This pin is connected in parallel with the internal power on reset circuit.
53
RES
I
Universal counter dedicated input port.
CMOS input/analog
input
• When taking frequency measurements, select the HCTR frequency measurement mode
and measurement time with the UCS instruction (b3 = 0, b2 = 0) and start the count with
a UCCinstruction.
UCS
b3,
0
b2
0
Input pin
HCTR
—
Measurement mode
UCS
b1,
0
b0
0
Measurement time
Frequency measurement
1 ms
4 ms
8 ms
32 ms
70
HCTR
I
0
1
0
1
1
0
—
1
0
1
1
—
1
1
The CNTEND flag is set when the count completes. Since this circuit functions as an AC
amplifier, always use capacitor coupling with the input signal. Input is disabled in backup
mode, in halt mode, after a reset, and in PLL stop mode.
Note: * Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS
instruction when using the I/O switchable ports as output pins.
Continued on next page.
No. 5799-8/12
LC72341G/W, 72342G/W, 72343G/W
Continued from preceding page.
Pin No.
Pin
I/O
Function
I/O circuit
CMOS amplifier input
FM VCO (local oscillator) input.
This pin is selected with the PLL instruction CW1.
56
FMIN
I
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
AM VCO (local oscillator) input.
CMOS amplifier input
This pin and the bandwidth are selected with the PLL instruction CW1.
CW1
b1,
1
b0
0
Bandwidth
57
AMIN
I
2 to 40 MHz (SW)
1
1
0.5 to 10 MHz (MW, LW)
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
Push-pull CMOS
output
The main charge pump output. When the local oscillator frequency divided by N is higher
than the reference frequency a high level is output, when lower, a low level is output, and
the pin is set to the high-impedance state when the frequencies match.
59
E0
O
Output goes to the high-impedance state in backup mode, in halt mode, after a reset, and
in PLL stop mode.
60
61
62
AIN
Transistor used for the low-pass filter amplifier.
Connect AGND to ground.
AOUT
AGND
O
VSS
VSS
VDD
Power supply pin. This pin must be connected to ground.
Power supply pin. This pin must be connected to ground.
24
58
55
—
—
—
Power supply pin. This pin must be connected to VDD
.
Handling of Unused Pins
Pin No.
3 to 6
Pin
I/O type
Pin handling
PA port
PB port
I
Connect to VDD or VSS. May be left open if the pull-up resistor is selected with the IOS instruction.
7 to 10
O
Open
11 to 14 PC port
15 to 18 PD port
I/O
Connect to VDD or VSS when input is selected. Leave open if output is selected.
I/O
Connect to VDD or VSS when input is selected. Leave open if output is selected.
19, 20
PE port
O
Open
21 to 23 PF port
25 to 28 PG/S ports
29 to 32 PH/S ports
I
Connect to VDD or VSS. The PF2 pin only may be left open if the pull-up resistor is selected with the IOS instruction.
I/O/S
Connect to VDD or VSS when input is selected. Leave open if output or LCD operation is selected.
I/O/S
Connect to VDD or VSS when input is selected. Leave open if output or LCD operation is selected.
33 to 41
45 to 48
49
S port
COM
DBR1
DBR2
DBR3
DBR4
RES
O
O
—
—
—
—
I
Open
Open
Connect to DBR2 through a capacitor.
50
Connect to DBR1 through a capacitor.
51
Connect to VSS through a capacitor.
52
Connect to VSS through a capacitor.
53
VDD
54
HCTR
FMIN
AMIN
EO
I
VSS Leave open if FMIN is used.
56
I
VSS
57
I
VSS
59
O
I
Open
60
AIN
VSS
61
AOUT
TEST1
TEST2
O
I
Open
63
Connect to VSS or leave open. Connection to VSS is preferable.
Connect to VSS or leave open. Connection to VSS is preferable.
2
I
No. 5799-9/12
LC72341G/W, 72342G/W, 72343G/W
Mask Options
Port
Selection
1
2
3
4
5
6
7
8
PG3/S20 General-purpose port
PG2/S19 General-purpose port
PG1/S18 General-purpose port
PG0/S17 General-purpose port
PH3/S16 General-purpose port
PH2/S15 General-purpose port
PH1/S14 General-purpose port
PH0/S13 General-purpose port
LCD port
LCD port
LCD port
LCD port
LCD port
LCD port
LCD port
LCD port
Development Environment and Tools
• The LC72P341 is available as a OTP version.
• The LC72EV340 is available as an evaluation chip.
• A total debugging system is formed by the combination of the TB-72EV32 evaluation chip board, the RE32 multi-
function emulator, and a personal computer for system control.
No. 5799-10/12
LC72341G/W, 72342G/W, 72343G/W
Instruction Set
Instruction
Opcode
1st
Machine code
Mnemonic
Operation
group
2nd
M
M
M
M
I
15
12 11
8
7
4 3
0
AD
ADS
AC
r
r
0100
0100
0100
0100
0101
0101
0101
0101
0110
0110
0110
0110
0111
0111
0111
0111
0001
0001
0000
0001
0001
0000
0010
0010
0011
0010
0010
00 DH
01 DH
10 DH
11 DH
00 DH
01 DH
10 DH
11 DH
00 DH
01 DH
10 DH
11 DH
00 DH
01 DH
10 DH
11 DH
00 DH
10 DH
01 DH
10 DH
11 DH
11 DH
01 DH
11 DH
10 DH
00 DH
10 DH
00 DH
00 00
00 DH
01 DH
10 DH
11 DH
00 DH
01 DH
00 DH
01 DH
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
1110
DL
DL
DL
DL
DL1
DL
DL
DL
r
r ← (r) + (M)
r
r ← (r) + (M), skip if carry
r ← (r) + (M) + C
r
r
ACS
AI
r
r
r ← (r) + (M) + C, skip if carry
M ← (M) + I
M
M
M
M
r
I
AIS
I
I
M ← (M) + I, skip if carry
M ← (M) + I + C
AIC
I
I
AICS
SU
I
I
M ← (M) + I + C, skip if carry
r ← (r) – (M)
M
M
M
M
I
r
SUS
SB
r
r
r ← (r) – (M), skip if borrow
r ← (r) – (M) – b
r
r
SBS
SI
r
r
r ← (r) – (M) – b, skip if borrow
M ← (M) – I
M
M
M
M
r
I
SIS
I
I
M ← (M) – I, skip if borrow
M ← (M) – I – b
SIB
I
I
SIBS
SEQ
SEQI
SNEI
SGE
SGEI
SLEI
ANDI
ORI
EXLI
AND
OR
I
I
M ← (M) – I – b, skip if borrow
(r) ← (M), skip if zero
(M) — I, skip if zero
(M) — I, skip if not zero
(r) — (M), skip if not borrow
(M) — I, skip if not borrow
(M) — I, skip if borrow
M ← (M) AND I
M
I
r
M
M
r
I
I
I
M
I
r
M
M
M
M
M
r
I
I
I
I
I
I
I
M ← (M) OR I
I
I
M ← (M) XOR I
M
M
M
r
r ← (r) AND M
r
r
r ← (r) OR M
EXL
SHR
LD
r
0011
0000
1101
1101
1101
1101
1110
1110
1111
1111
100
r
r ← (r) XOR M
r
r
Shift r right with carry
r ← (M)
r
M
r
r
ST
M
r
r
M ← (r)
MVRD
MVRS
MVSR
MVI
M
r
r
r
[DH, rn] ← (M)
M
M1
M
M
M
M ← [DH, rn]
M2
I
DL2
I
[DH, DL1] ← [DH, DL2]
M ← I
Memory
test
instructions
TMT
TMF
JMP
CAL
RT
N
N
N
if M (N) = all 1, then skip
if M (N) = all 0, then skip
PC ← ADDR
N
ADDR
ADDR
ADDR (13 bits)
ADDR (13 bits)
101
PC ← ADDR, Stack ← (PC) + 1
PC ← Stack
0000
0000
1111
1111
1111
1111
0000
0000
1000
1001
000 I
001 I
01 I
RTI
SS
0000
1111
1111
1111
1111
0000
PC ← Stack, BANK ← Stak, carry ← stack
(Status reg. I)N ← 1
(Status reg. I)N ← 0
if (Status reg. I)N = all 1, then skip
if (Status reg. I)N = all 0, then skip
if Unlock F/F (N) = all 0, then skip
I
I
N
N
N
N
N
N
N
N
N
RS
TST
TSF
TUL
I
I
10 I
N
1101
Continued on next page.
No. 5799-11/12
LC72341G, W, LC72342G, W, LC72343G, W
Continued from preceding page.
Instruction
Mnemonic
Opcode
1st
Machine code
Operation
group
2nd
r
15
12 11
8
7
4 3
0
PLL
TMS
UCS
UCC
BEEP
DZC
BANK
IOS
M
1111
0000
0000
0000
0000
0000
0000
1111
0011
1110
1110
0000
0000
1111
1111
1100
1100
1100
1100
0000
0000
0000
10 DH
0000
DL
1100
0001
0010
0110
1011
0111
Pn
r
PLL reg. ← PLL data
Timer reg. ← I
UCS reg. ← I
I
I
I
0000
I
I
0000
I
UCC reg. ← I
I
0000
I
BEEP reg. ← I
DZC reg. ← I
I
0000
I
I
0000
I
BANK ← I
Pn
M
M
M
Pn
Pn
Pn
Pn
M
M
M
M
I
I
Rn
Pn
Ph
N
N
N
N
I
1110
I
IOS reg. Pn ← I
M ← (Rn reg.)
M ← (Pn)
INR
10 DH
10 DH
11 DH
0010
DL
r
Pn
IN
DL
OUT
SPB
DL
Pn
Pn ← M
Pn
N
(Pn) N ← 1
RPB
TPT
0011
Pn
N
(Pn) N ← 0
1100
Pn
N
if (Pn) N = all 1, then skip
if (Pn) N = all 0, then skip
LCD (DIGIT) ← M
TPF
1101
Pn
N
LCDA
LCDB
LCPA
LCPB
HALT
CKSTP
NOP
00 DH
01 DH
10 DH
11 DH
0000
DL
DIGIT
DIGIT
DIGIT
DIGIT
I
I
DL
I
DL
LCD (DIGIT) ← Logic
Array ← M
I
DL
0100
0101
0000
HALT reg. ← I, then CPU Stop
Stop Xtal OSC
0000
0000
No operation
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 1998. Specifications and information herein are subject to
change without notice.
PS No. 5799-12/12
相关型号：
©2020 ICPDF网 联系我们和版权申明