LA6572 [SANYO]
5-CH Driver for Mini Disc; 迷你光盘5 -CH驱动程序
| 型号： | LA6572 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 5-CH Driver for Mini Disc |
| 文件： | 总9页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN7777A
Monolithic Linear IC
5-CH Driver for Mini Disc and
Compact Disk Applications (BTL : 5CH)
LA6572
Overview
The LA6572 power amplifier 5-channel (BTL) built-in.
Features
• Power amplifier 5-channel (BTL) built-in.
• I max 1A.
O
• Level shift circuit built-in.
• Three channels (2-1-1) of MUTE circuit (output ON/OFF) incorporated. Only CH5 normally ON.
(Operative independently for each of MUTE1: CH1, 2, MUTE2: CH3, MUTE3: CH4. Inoperative for 3.3REG).
• 3.3V power supply (3.3VREG) incorporated (PNP transistor connected externally).
• With 3.3V power supply (3.3VREG) ON/OFF function (EN-REG)
(Operative for 3.3VREG only (inoperative for BTL AMP).
(3.3VREG: OFF with EN-REG: L, 3.3VREG: ON with EN-REG : H).
• Operative for the fixed internal VREF (1.65V: TYP) for 5CH only.
• Overheat protection circuit (thermal shutdown) built-in.
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Power supply voltage
Symbol
max
Conditions
Ratings
Unit
V
V
I
14
1
CC
Maximum output current
Maximum input voltage
MUTE pin voltage
max
Each output for channel 1 to 5.
A
O
VINB max
VMUTE
Pd max
13
13
0.8
2
V
V
Allowable operation
Independent IC
W
Mounted on a specified board *
Operating temperature
Storage temperature
Topr
Tstg
-30 to +85
°C
°C
-55 to +150
* Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
11007 TI IM B8-5621 No.7777-1/9
LA6572
Allowable Operating Range at Ta = 25°C
Parameter
Power supply Voltage
Symbol
Conditions
Ratings
4.5 to 13
Unit
V
V
CC
Electrical Characteristics at Ta = 25°C, V 1 = V 2 = 8V, VREF = 1.65V, unless especially specified.
CC CC
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
All Blocks
No-load current drain ON
No-load current drain OFF
VREF input voltage range
VREF-OUT output voltage
VREF-OUT output current
VREF changeover voltage H
VREF changeover voltage L
Thermal shutdown temperature
I
I
-ON
All outputs ON *1
All outputs OFF *1
30
50
20
mA
mA
V
CC
-OFF
CC
10
VREF-IN
0.5
V
-1.5
CC
VREF-OUT
I-VREF-OUT
VREF-SW-H
VREF-SW-L
TSD
1.6
2
1.65
5
1.7
V
mA
V
External VREF selected (VREF-SW: H)
Internal VREF selected (VREF-SW: L)
Design guarantee value *
3.5
1.5
V
150
175
200
°C
BTL AMP (CH1 to CH5)
Output offset voltage
VOFF
Voltage difference between outputs for BTL
AMP, each channel. *2
-50
0
50
mV
V
Input voltage range
Output voltage
V
Input voltage range for input for OP-AMP.
V
-1.5
IN
CC
V
Each voltage between V + and V - when
O
O
O
5.7
3.6
6.5
V
R
= 8Ω. *2
L
Closed-circuit voltage gain
Slew rate
VG
Input and output gain. Input OP-AMP: BUFFER
AMP Independent Multiply 2 between outputs.
Each MUTE *3
4
4.4
0.5
deg
V/µs
V
SR
0.5
MUTE ON voltage
MUTE OFF voltage
VMUTE-ON
VMUTE-OFF
2
Each MUTE *3
V
Input Amp Block
Input voltage range
Output offset voltage
Outputcurrent(SINK)
V
-OP
0
-10
2
V
-1.5
10
V
IN
CC
VOFF-OP
SINK-OP
mV
mA
µA
Output current (SOURCE)
SOURCE-OP
*4
300
500
Power Supply Block (PNP Transistor: 2SB632K-Use)
3.3V power supply output
REG-IN SINK current
Line regulation
V
I
= 200mA
O
3.18
5
3.3
10
20
50
3.42
V
mA
mV
mV
V
OUT
REG-IN-SINK
∆VOLN
Base current to external PNP
6V ≤ V ≤ 12V, I = 200mA
150
200
CC
O
Load regulation
∆VOLD
5mA ≤ I ≤ 200mA
O
3.3V power supply ON voltage
3.3V power supply OFF voltage
REG-ON
REG-OFF
EN voltage at which 3.3V power is turned ON. *5
EN voltage at which 3.3V power is turned OFF. *5
2
0.5
V
*. This is design target value and is not measured.
*1. Current dissipation that is a sum of V 1 and V 2 at no load.
CC CC
*2. Input AMP is a BUFFER AMP. V 5+ of CH5 is connected to VREF-OUT (CH5) (internal VREF).
IN
*3. Voltage difference between both ends of load (8Ω). Output saturated.
*4. The source of input OP-AMP is a constant current. As the 11kΩ resistance to the next stage is a load, pay due
attention when setting the input OP-AMP gain.
*5. Output ON with MUTE : “H”, output OFF with MUTE : “L” (HI impedance)
No.7777-2/9
LA6572
Package Dimensions
unit : mm (typ)
3251
17.8
(6.2)
36
19
1
18
(0.5)
2.0
0.3
0.8
0.25
2.7
SANYO : HSOP36R(375mil)
Pd max - Ta
Mounted on a Specified board :
114.3mm×76.1mm×1.6mm, glass epoxy
3.0
2.5
2.0
1.5
Mounted on a specified board
1.04
0.42
1.0
0.8
Independent IC
0.5
0
--40 --30 --20
0
20
60
80 85
100
40
Ambient temperature, Ta - °C
ILA00922
No.7777-3/9
LA6572
Pin Description
Pin Name
Pin Name
Pin No.
Equivalent Circuit Diagram
Description
Each input pin
Input
V
1+
1-
17
16
15
20
19
18
23
22
21
29
30
31
32
33
34
IN
V *-
IN
V *
IN
V
V
V
IN
1
V
*
IN
CC
2+
IN
V
V
V
2-
IN
2
IN
3+
IN
V
IN
*+
V
V
V
3-
IN
3
IN
4-
4+
4
IN
V
IN
IN
V
IN
S-GND
V
5+
V
V
5-
IN
5
IN
Output
V
1+
1-
12
13
10
11
8
Each output
O
V
*
CC
V
V
O
2+
O
V
2-
O
V
3+
O
V
*
O
V
3-
9
O
V
4+
6
O
V
4-
7
O
RF
V
5+
5
O
V
5-
4
O
MUTE
MUTE1
MUTE2
MUTE3
1
2
Turns ON/OFF the output for
MUTE1 : CH1, 2,
V
*
CC
36
MUTE2 : CH3 and
MUTE3 : CH4.
Each MUTE operates
independently.
MUTE*
S-GND
100k
100k
Ω
Ω
MUTE : H output ON
MUTE : L output OFF
The output has a HI
impedance when OFF
3.3VREG ON/OFF pin.
EN-REG ”H” : ON
EN-VREG
EN-VREG
24
EN-REG ”L” : OFF
EN-REG
S-GND
100k
Ω
Ω
100k
No.7777-4/9
LA6572
Relation of MUTE and Power (V *)
CC
CH1
CH2
CH3
CH4
CH5
MUTE1
V
V
1
2
CC
MUTE2
MUTE3
CC
* Connect V 1 and V 2 externally (to reduce the effects of voltage drop in the internal metal wiring).
CC
CC
* MUTE operates independently for each CH.
Relation of Each Channel and VREF
CH1
CH2
CH3
CH4
CH5
External VREF
Internal VREF (1.65V : TYP)
* CH1 through CH4 operate for external VREF.
CH5 operates for internal VREF (1.65V (TYP) : fixed).
EN-REG (3.3 VREG) Operation
EN-REG voltage
3.3V power supply state
H
L
ON
OFF
3.3VREG : ON
3.3VREG : OFF
EN-VREG
0.5V
2V
Outline of Input and Output
22kΩ
22kΩ
11kΩ
11kΩ
11kΩ
-
V
*
IN
V
V
*+
*-
11kΩ
O
+
-
V
-
IN
+-
-
+
V
IN
+
-
O
-
+
+
VREF-IN
VREF-OUT
-
+
No.7777-5/9
LA6572
Block Diagram
Thermal Shutdown
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
MUTE1
MUTE2
CH1, 2
CH3
CH4
MUTE3
S-GND
MUTE1
MUTE2
MUTE3
Each MUTE operative independently
for a corresponding CH.
“H” : Output ON
CH3, 4, 5
“L” : Output OFF
V
2
V
V
V
V
V
V
5
CC
IN
IN
IN
IN
IN
IN
Power supply
22kΩ
V
5-
5-
5+
4
O
11kΩ
-
-
CH5
+
+
V
V
5+
4+
O
O
CH4
CH3
22kΩ
V
4-
4-
4+
O
11kΩ
-
-
+
+
V
3+
O
-
+
V
3-
VREF-IN
O
+
-
-
FR FR
FR
FR
+
1.65V(TYP)
10
11
12
13
14
15
16
17
18
27
26
V
2+
VREF-OUT(CH5)
REG-IN
O
O
CH2
CH1
3.3VREG
-
V
2-
O
+
V
1+
REG-OUT
EN-REG
25
24
EN-REG :
“H” :3.3VREG, ON
“L” :3.3VREG, OFF
V
1-
O
CH1, 2
22kΩ
23
22
21
20
19
V
1
1
V
V
V
V
V
3+
3-
3
CC
IN
IN
IN
IN
IN
Power supply
11kΩ
+
-
-
+
V
IN
22kΩ
V
1-
IN
11kΩ
-
-
+
22kΩ
+
V
1+
2+
2-
IN
11kΩ
+
-
-
+
V
2
IN
No.7777-6/9
LA6572
Pin Description
Pin No.
Pin Name
Description
1
MUTE1
MUTE2
CH1 and 2 output ON/OFF
CH3 output ON/OFF
2
3
V
2
Power supply for CH3, 4, and 5. Short-circuited with V 1.
CC
CC
4
V
5-
Output pin (-) for channel 5
Output pin (+) for channel 5
Output pin (+) for channel 4
Output pin (-) for channel 4
Output pin (+) for channel 3
Output pin (-) for channel 3
Output pin (+) for channel 2
Output pin (-) for channel 2
Output pin (+) for channel 1
Output pin (-) for channel 1
O
5
V
5+
4+
4-
O
6
V
O
7
V
V
O
8
3+
O
9
V
V
3-
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
2+
O
V
V
2-
O
1+
O
V
V
1-
O
1
Power supply for CH1, 2. Short-circuited with V 2.
CC
CC
V
V
1
Input pin for channel 1, input AMP output
Input pin (-) for channel 1
IN
1-
1+
2
IN
V
Input pin (+) for channel 1
IN
V
Input pin for channel 2, input AMP output
Input pin (-) for channel 2
IN
V 2-
IN
V
2+
Input pin (+) for channel 2
IN
V
V
3
Input pin for channel 3, input AMP output
Input pin (-) for channel 3
IN
3-
IN
V
3+
Input pin (+) for channel 1
IN
EN-REG
REG-OUT
3.3V ON/OFF pin that operates with 3.3VREG. EN: H→3.3VREG:ON, EN: L→3.3VREG:OFF
Collector of PNP transistor connected to output 3.3VREG.
PNP transistor base connected
VREF-AMP (CH5 output (TYP: 1.65V))
Reference voltage applied pin
REG-IN
VREF-OUT(CH5)
VREF-IN
V
4+
4-
Input pin (+) for channel 4
IN
V
V
V
Input pin (-) for channel 4
IN
4
Input pin for channel 4, input AMP output
Input pin (+) for channel 5
IN
5+
IN
V
V
5-
Input pin (-) for channel 5
IN
5
Input pin for channel 5, input AMP output
Signal system GND
IN
S-GND
MUTE3
CH4 output ON/OFF
* Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with
S-GND.
No.7777-7/9
LA6572
Sample Application Circuit
EN-REG
LOADING
1
2
3
4
5
6
7
8
9
MUTE1
36
35
34
33
32
31
30
29
28
MUTE3
S-GND
MUTE3
MUTE2
MUTE1
MUTE2
V
V
V
V
V
V
V
2
V
5
IN
CC
5-
V 5-
IN
O
O
O
O
O
O
M
M
M
LOADING MOTOR
5+
4+
4-
V
5+
4
IN
V
IN
SPINDLE MOTOR
SLED MOTOR
V 4-
IN
3+
3-
V 4+
IN
VREF-IN
FR
FR
10
11
12
13
14
15
16
17
18
V
V
V
V
V
V
V
V
V
2+
2-
1+
1-
1
27
26
25
24
23
22
21
20
19
VREF-OUT(CH5)
REG-IN
O
O
O
O
V
CC
TRACKING COIL
FOCUS COIL
3.3VREG
REG-OUT
EN-REG
V
CC
V 3+
IN
CC
1
IN
V 3-
IN
1-
V
3
IN
IN
IN
IN
1+
2
V 2+
IN
VREF
SPINDLE
V 2-
IN
SLED
TRACKING
FOCUS
Add a capacitor + resistor between outputs or between the output and GND as a countermeasure against
oscillation of the output.
No.7777-8/9
LA6572
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
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otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of January, 2007. Specifications and information herein are subject
to change without notice.
No.7777-9/9
PS
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