ENA1527 [SANYO]
Piezo Actuator Driver IC; 压电致动器驱动IC
| 型号： | ENA1527 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Piezo Actuator Driver IC |
| 文件： | 总15页 (文件大小：586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1527
Bi-CMOS IC
LV8094CT
Piezo Actuator Driver IC
Overview
The LV8094CT is a piezoelectric actuator driver IC. It internally generates drive waveforms and this makes it possible to
control piezoelectric actuators with simple instructions.
Features
• Actuators using piezoelectric elements can be driven and controlled simply by I2C communication.
• The piezoelectric drive waveforms are set externally by serial input signals using the I2C interface.
The rising and falling timings are determined with clock count.
• ENIN input that controls the startup/stop of the IC.
• The time for which the actuator is driven is determined with the drive frequency setting based on I2C communication.
• Provides a busy signal output during periods when the actuator is being driven by OUT pin output so that applications can
be aware of the actuator operating/stopped state.
• Built-in undervoltage protection circuits, and register power-on reset function.
Specifications
Absolute Maximum Ratings at Ta = 25°C, GND = 0V
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage
V
max
-0.5 to 5.0
300
CC
max
Output current
I
mA
mA
mA
V
O
Peak output current
I
I
peak1
peak2
max
t ≤ 1ms
t ≤ 10μs
750
O
O
1200
Input signal voltage
V
-0.5 to V +0.5
CC
IN
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
*Mounted on a specified board.
350
-30 to +85
-55 to +125
mW
°C
Tstg
°C
* Specified board : 40mm×40mm×1.6mm, glass epoxy board.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
80509 SY 20090710-S00001 No.A1527-1/15
LV8094CT
Allowable Operating Conditions at Ta = 25°C, GND = 0V
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage
V
2.2 to 3.3
CC
Input signal voltage
V
-0.3 to V
V
IN
CC
Corresponding CLK input frequency
Maximum operating frequency
Fclk
to 60
MHz
Times
Ct max
Set STP count × 512
Electrical Characteristics at Ta = 25°C, V
= 2.8V, GND = 0V, unless otherwise specified.
CC
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
1.0
Standby mode current drain
Operating mode current drain
High-level input voltage
I
I
0
1
No CLK input, When CLK/SDA=L
CLK = 10MHz, When SCL/SDA=L
μA
mA
V
CC
0.5
1.0
+0.3
0.3
CC
V
2.2V ≤ V
2.2V ≤ V
CLK
≤ 3.3V SCL, SDA
≤ 3.3V SCL, SDA
1.5
-0.3
V
V
IH
CC
CC
Low-level input voltage
V
V
IL
CC
CLK pin high-level input voltage
CLK pin low-level input voltage
Low voltage detection voltage
V
2
0.5×V
+0.3
V
IH
CC
CC
V
2
CLK
-0.3
0.2×V
V
IL
CC
2.2
Vres
V
voltage
1.8
2.0
0.8
V
CC
Output block upper-side on
resistance
RonP
1.5
Ω
Output block lower-side on resistance
RonN
TPLH
TPHL
0.6
1.2
Ω
Turn on time
Turn off time
With no load *1
With no load *1
0.15
0.1
μS
μS
*1 : Rising time from 10 to 90% and falling time from 90 to 10% are specified with regard to the OUT pin voltage.
Package Dimensions
unit : mm (typ)
3381
Pd max
Ta
TOP VIEW
1.67
SIDE VIEW
BOTTOM VIEW
0.4
0.35
0.3
Specified board : 40 40 1.6mm3
×
×
glass epoxy
4
3
2
1
LASER MARKED
INDEX
0.22
0.4
0.235
SIDE VIEW
0.14
0.1
0
SANYO : WLP8(1.67X0.87)
30
0
30
60
90
120
Ambient temperature, Ta -
C
No.A1527-2/15
LV8094CT
Pin Assignment
Ball side view
0.4
Top view
A
B
B
A
1
2
3
4
SCL
SDA
CLK
1
2
3
4
CLK
SCL
SDA
GND
GND
1.67
V
V
OUT1
CC
OUT1
CC
RFG
OUT2
RFG
OUT2
0.87
A1:SCL
A2:SDA
A3:OUT1
A4:RFG
B1:CLK
B2:GND
B3:V
CC
B4:OUT2
No.A1527-3/15
LV8094CT
Block Diagram
V
CC
OUT1
OUT2
RFG
Startup
control
block
Output control
Piezoelectric drive
waveform generation
register
I2C interface
GND
CLK
SCL SDA
Value of the resistor connected to the RFG pin
Inrush current flowing to the piezoelectric elements can be controlled in the LV8094CT by inserting a resistor between
the RFG pin and GND potential.
Since the resistance affects the actuator operation, the constant must be determined in a range from 0 to 3.3Ω while
monitoring the operation of the actuator.
Capacitor on the V
line
CC
Piezoelectric actuators are capacitive loads in electrical terms, and they operate units by charging and discharging the
charges. Since the charge between the capacitor on the V line and piezoelectric elements is transferred, the capacitor
CC
pin. The capacitance of the capacitor required is determined by the capacitance of the
must be mounted near the V
CC
piezoelectric element. A capacitance within a range that does not affect operation must be selected.
No.A1527-4/15
LV8094CT
Serial Bus Communication Specifications
I2C serial transfer timing conditions
twH
SCL
th1
twL
th2
tbuf
SDA
th1
ts2
ts1
ts3
Start condition
Resend start condition
Stop condition
ton
tof
Input waveform condition
Standard mode
Parameter
SCL clock frequency
Data setup time
symbol
Conditions
min
typ
max
unit
kHz
μs
ns
fscl
ts1
ts2
ts3
th1
th2
twL
twH
ton
tof
SCL clock frequency
0
100
Setup time of SCL with respect to the falling edge of SDA
Setup time of SDA with respect to the rising edge of SCL
Setup time of SCL with respect to the rising edge of SDA
Hold time of SCL with respect to the rising edge of SDA
Hold time of SDA with respect to the falling edge of SCL
SCL low period pulse width
4.7
250
4.0
μs
μs
μs
μs
μs
ns
Data hold time
4.0
0.06
4.7
Pulse width
SCL high period pulse width
4.0
Input waveform conditions
Bus free time
SCL/SDA (input) rising time
1000
300
SCL/ SDA (input) falling time
ns
tbuf
Interval between stop condition and start condition
4.7
μs
High-speed mode
Parameter
SCL clock frequency
Data setup time
Symbol
fscl
ts1
Conditions
min
typ
max
unit
kHz
μs
ns
Clock frequency of SCL
0
0.6
400
Setup time of SCL with respect to the falling edge of SDA
Setup time of SDA with respect to the rising edge of SCL
Setup time of SCL with respect to the rising edge of SDA
Hold time of SCL with respect to the rising edge of SDA
Hold time of SDA with respect to the falling edge of SCL
SCL low period pulse width
ts2
100
0.6
ts3
μs
μs
μs
μs
μs
ns
Data hold time
th1
0.6
th2
0.06
1.3
Pulse width
twL
twH
ton
SCL high period pulse width
0.6
Input waveform conditions
Bus free time
SCL/SDA (input) rise time
300
300
tof
SCL/SDA (input) fall time
ns
tbuf
Interval between the stop condition and the start condition
1.3
μs
No.A1527-5/15
LV8094CT
I2C bus transfer method
Start and stop conditions
The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during
a data transfer operation.
SCL
SDA
ts2
th2
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is
started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
Start condition
Stop condition
SCL
SDA
th1
th3
No.A1527-6/15
LV8094CT
Data transfer and acknowledgement response
After the start condition is generated, data is transferred one byte (8 bits) at a time. Any number of data bytes can be
transferred consecutively.
An ACK signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. The
transmission of an ACK signal is performed by setting the receiving side SDA to low after SDA at the sending side is
released immediately after the clock pulse of SCL bit 8 in the data transferred has fallen low.
After the receiving side has sent the ACK signal, if the next byte transfer operation is to receive only the byte, the
receiving side releases SDA on the falling edge of the 9th clock of SCL.
There are no CE signals in the I2C bus ; instead, a 7-bit slave address is assigned to each device, and the first byte of the
transfer data is allocated to the 7-bit slave address and to the command (R/W) which specifies the direction of
subsequent data transfer.
The READ function of the LV8094CT provides only the functionality to test the BUSY state.
7-bit address data is transferred sequentially starting at the MSB and the second and subsequent bytes are written if the
state of the 8th bit is low and read if the state is high.
In the LV8094CT, the slave address is stipulated to be “1110010.”.
WRITE mode timing
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
W
Start
Slave address
Register address
Data
Stop
SCL
SDA
X
X
X
X
X
X
X
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0 1
READ mode timing
M
S
B
L
A
M
L
A
S
B
R
C
S
S
C
Slave address
Data
Start
Stop
K
B
B
K
SCL
SDA
X
X
X
X
X
X
X
1
1
0
0
0
0
0
0
0
0
No.A1527-7/15
LV8094CT
Data transfer write format
The slave address and Write command must be allocated to the first byte and the register address in the serial map must
be designated in the second byte.
For the third byte, data transfer is carried out to the address designated by the register address which is written in the
second byte. Subsequently, if data continues, the register address value is automatically incremented for the fourth and
subsequent bytes.
Thus, continuous data transfer starting at the designated address is made possible.
After the register address reaches 07h, the transfer address for the next byte is set to 00h.
Data write example
S
1
1
1
0
0
1
0
0
A
0
0
0
0
0
0
1
0
A
Data 1
A
Slave address
Register address set to 02h
Write data to address 02h
R/W = 0 written
Data 2
A
Data 3
A
A
Data 4
A
P
Write data to address 03h
Write data to address 04h
Write data to address 05h
ACK signal
S
Start condition
P
Stop condition
A
Master side transmission
Slave side transmission
Data read example
A
S
1
1
1
0
0
1
0
1
A
Data
P
Slave address
Read data
R/W = 1 read
Notify end of read by not sending out ACK
A
S
Start condition
P
Stop condition
A
ACK signal
Master side transmission
Slave side transmission
No.A1527-8/15
LV8094CT
Serial Map
Register Address
Data
A7
0
A6
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
D7
D6
D5
D4
0
D3
D2
0
D1
0
D0
0
0
0
0
0
0
0
0
M/I
0
DRVPULSE [6 : 0]
0
0
1
2
3
4
5
6
7
8
0
×
0
0
ENIN
0
0
INIT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
GATE
0
CKSEL [1 : 0]
RET [1 : 0]
0
0
0
0
0
0
0
0
0
RST [7 : 0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GTAS [7 : 0]
0
0
0
GTBR [7 : 0]
0
0
0
GTBS [7 : 0]
0
0
0
0
STP [7 : 0]
0
0
×
0
×
0
0
×
0
×
0
0
×
0
×
0
0
×
INITMOV [7 : 4]
0
BUSY
0
0
×
0
0
×
0
0
×
0
0
×
0
READ mode only register
Upper : Register name Lower : Default value
Serial Mode Settings
0
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
D0 to D6: DRVPULSE [6 : 0]
Operation count setting register. Specify a number from 0 to 127.
The number of cyclic operations determined by <DRVPLUSE setting> × <STP setting> are performed.
Additional data can be input and data is added up to the equivalent of total of 512 pulses.
However, if the EN pin is set low or the ENIN register is set to 0, the DRVPULSE input is not accepted
because the DRVPULSE counter is in the reset state.
Since the output operation is carried out at the time the DRVPULSE input is recognized, the generation of
the OUT signal is started at the time an ACK signal is generated after the execution of the instruction at
address 00H according to the value of the waveform setup register established at that time.
D7
0
M/I
Operation direction switching
*Default Infinity distance direction
Macro direction
∞
1
macro
Operation direction switching register
The operation count setting register is reset when the register is switched. To stop the operation of the unit,
switch the M/I register and set DRVPULSE to 0 for input. This register is also used to set the direction of
operation when the initialization sequence is to be performed.
No.A1527-9/15
LV8094CT
1
0
0
0
0
0
0
0
1
D7
0
D5
D4
D3
D2
D1
D0
D0: Register for selecting whether the initialization sequence is to be performed when EN is set high and ENIN
is set to 1.
D0
INIT
Initialization to be performed/not to be performed setting
*Default
0
Initialization to be performed
Initialization not to be performed
1
D2
0
D1
0
RET
Number of initialization sequence swing back
*Default
2 times
1 time
3 times
4 times
0
1
1
0
1
1
D4
0
D3
0
CKSEL
Input clock division ratio switching
1/4
1/2
1
*Default
1/4
0
1
1/2
1
0
1 (no frequency division)
1 (no frequency division)
1
1
1
D5 : ENIN ENIN register is used to start up IC and to give a trigger for initialization.
Output operation of the IC is activated only when the EN pin is set high and EN pin is set to 1. A trigger for the
initialization is also issued at the timing when the EN pin is set high and EN pin is set to 1.
D7
0
GATE
Gate mode operation
*Default
MODE1
MODE2
Forward/reverse/braking
Forward/reverse/standby
1
2
3
4
0
0
0
0
0
0
0
0
0
0
1
0
D7
D6
D5
D4
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
RST7 to RST0 : Specifies the number of clocks per period (0 to 255). Default = 0
0
0
0
0
1
1
D7
D6
D5
D4
D3
GTAS7 to GTAS0 : Sets the GATE_A pulse set value (0 to 255). Default = 0
0
0
0
1
0
0
D7
D6
D5
D4
D3
GTBR7 to GTBR0 : Sets the GATE_B pulse reset value (0 to 255). Default = 0
No.A1527-10/15
LV8094CT
5
0
0
0
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
GTBS7 to GTBS0 : Sets the GATE_B pulse set value (0 to 255). Default = 0
RST7-0
GTAS7-0
GATEA
GTBS7-0
GTBR7-0
GATEB
6
0
0
0
0
0
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
STP7 to STP0 : Specifies the number of output pulse steps with regard to DRIVE input (1 to 256). Default = 1
The setting value range is handled as the data value plus 1.
When data is input in 8-bit units (0 to 255), it is handled as an STP period of 1 to 256.
7
0
0
0
0
0
1
1
1
0
0
0
0
D3
D2
D1
D0
INITMOV7 to INITMOV4 : Sets the number of swing back of the initialization sequence to be performed (16 to 256). Default = 16
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
INIT7 to 4
16 to 256
16
0
1
32
2
48
3
64
4
80
5
96
6
112
128
144
160
176
192
208
224
240
256
7
8
9
10
11
12
13
14
15
8
No register address
D7
0
0
0
0
0
0
0
READ only register line.
D7 : BUSY register Set to 1 when the IC is performing the output operation.
Set to 0 when the IC stops the output operation.
No.A1527-11/15
LV8094CT
Functional Description
1 period :
One period of OUT waveform operation is equivalent to one output operation.
Tf = 1 period
Initialization sequence (on or off and direction can be set by I2C) :
This is an internal sequence in which the actuator is moved to the initial position when the IC is started up.
Switching the value of the ENIN register from 0 to 1 when the EN pin is set high starts the IC (conversely, the IC is also
started by switching the state of the EN pin from low to high when the ENIN is set to 1).
The presence or absence of the initialization operation can be set using the initialization mode select register (INIT). If
the initialization operation is specified, the direction of the initialization sequence can be set using the M/I register.
• M/I register = 0 : Initialization processing in infinity direction
The IC performs the number of operations determined by STP setting period × INIT setting times in the infinite
direction, then waits for the period equivalent to STP setting period × 4 times, and performs the number of swing
back operations equal to STP setting period × RET setting times in the macro direction.
• M/I register = 1 : Auto macro operation in macro direction
The IC performs the number of operations determined by STP setting period × INIT setting times in the macro
direction, then waits for the period equivalent to STP setting periods × 4, and performs the number of swing back
operations equal to STP period setting period × RET setting times in the infinity direction.
CLK input :
The pin for the external CLK input that provides the reference time for generating drive waveforms.
The frequency division ratio for I2C communication can be selected from 1/4, 1/2, and 1/1. Drive waveforms are
generated by counting this frequency-divided clk pulses as the basic count unit. The LV8093CS supports frequency
from 10MHz to 60MHz depending on the frequency division ratio and counter settings.
Register setup sequence :
(1) Apply V
.
CC
(2) Set register addresses x01 to 0x07 (set the waveform and drive conditions).
(3) Set the ENIN register to 1 (invoke initialization procedures if initialization is enabled or start up the IC).
(4) Set up M/I and DRVPULSE to start the AF operation (actuator operation instruction).
I2C communication during output operation :
I2C communication with all the registers is possible even when the IC is in operation (OUT processing or BUSY is held
high).
No.A1527-12/15
LV8094CT
Actuator drive waveform settings :
Configuration of piezoelectric actuator drive waveform
f = 1 period
Ta
off
Tb
Since the counter starts from zero,
Drive parameter settings
a value minus 1 is set.
RST = Number of clock pulses in period minus 1
GTAS =
Ta + 1
Ta - 1 + 2 = Ta + 1
since the waveforms start after two clock pulses.
Rises here after two clock pulses from reference.
GTBR =
GTAS + off
GTBS =
GTBR + Tb
Waveform start
reference point
The drive waveforms are set using four parameters: RST, GTAS, GTBR and GTBS.
RST : Parameter determines the period, and sets the reference clock pulse count minus 1.
GTAS : Parameter determines the time taken for the gate signal A to the falling edge from the reference point.
Since the signal raises after two clock pulses from the reference, the Ta reference clock cycle count plus 1 is
set.
GTBR : Parameter determines the time taken for the gate signal B to the rising edge from the reference point.
It sets the value obtained by adding the reference clock pulse count during the time from GTAS to “off.”
GTBS : Parameter determines the time taken for the gate signal B to the falling ewdge from the reference point.
It sets the value obtained by adding the reference clock pulse count during the time from GTBR to “Tb.”
[Example of settings] When setting reference clock to 10MHz, period to 13μs, Ta to 2.0μs, off to 0.3μs, and Tb to 3.0μs
Since the reference clock time is 0.1μs :
The period is 130 clks. → Specify 129 (RST value of 130 -1).
Ta is 20 clks. → Specify 21 (GTAS value of 20 + 1).
off is 3 clks. → Specify 24 (GTBR value of 21 + 3).
Tb is 30 clks. → Specify 54 (GTBS value of 24 + 30).
No.A1527-13/15
LV8094CT
Timing charts
Enlarged view of the sequence of output signals
(RST setting + 1) ×
number of clock pulses
(GTAS setting - 1) ×
(GTAS setting - 1) ×
Operation toward infinity
OUT1
number of clock pulses number of clock pulses
(GTAS setting - 1) × number of clock pulses
OUT2
(GTBR setting -1) × number of clock pulses
(RST setting + 1) ×
Operation toward macro
number of clock pulses
(GTBR setting -1) × number of clock pulses
OUT1
OUT2
(GTBS setting - 1) × number of clock pulses
(GTAS setting - 1) ×
number of clock pulses
(GTAS setting - 1) ×
number of clock pulses
Sequence of initial setting operation (“on” or “off” can be set by the I2C settings.)
When M/I register = 00 → Movement toward infinity position
Startup when ENIN=1 , initial setting sequence starts
ENIN resister
1 period
OUT1
OUT2
Standby state
STP period
Operation toward infinity
STP period × INIT times
Operation toward macro
STP period × RET setting times
×
4
Initial setting operation time
BUSY resister
High during initial setting in wait state too
BUSY output is high during initial setting operation.
BUSY output is low after initial setting.
When M/I register = 01 → Movement toward macro position
Startup when ENIN=1 , initial setting sequence starts
ENIN resister
OUT1
1 period
OUT2
Standby state
Operation toward infinity
Operation toward macro
STP period
×
4
STP period × RET setting times
STP period × INIT times
Initial setting operation time
BUSY resister
High during initial setting in wait state too
BUSY output is high during initial setting operation.
BUSY output is low after initial setting.
No.A1527-14/15
LV8094CT
Sequence of operations triggered by DRVPULSE input
ENIN register
Operation stops when ENIN input is low.
Macro direction logic selection
Infinity direction logic selection
M/I register state
Serial communication operation instruction completed
00000000_00000010 (operation 2 times toward infinity)
Serial communication operation instruction completed
00000000_10000010 (operation 2 times toward macro)
DRVPULSE setting
Equivalent to 2 pulses = STP setting period
1 period
×
operation for 2 times
OUT1
OUT2
Operation toward macro
Operation toward infinity (STP setting period
Serial communication
×
2 times)
Operation starts on completion of DRVPULSE input.
Return to high when
EN is set to low even before the
completion of the operation.
BUSY register
BUSY output high, only during operation period
Gate setting output logic
1 period
Forward
Forward
GATE MODE1 : Forward, Braking, Reverse
OUT1
Output mode
Braking Braking
on off
off on
OUT2
OUT1
OUT1
OUT2 OUT1
OUT2
OUT2
Reverse
1 period
off on
on off
Forward
Reverse
Forward
Forward
GATE MODE2 : Forward, Wait, Reverse
OUT1
off off
off off
OUT2 OUT1
Wait
Wait
on on
Braking
off off
Wait
OUT2
Reverse
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PS No.A1527-15/15
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