ENA0928 [SANYO]
CMOS ICFROM 98K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller; CMOS ICFROM 98K字节， RAM 4096字节的片上8位单芯片微控制器
| 型号： | ENA0928 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | CMOS ICFROM 98K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller |
| 文件： | 总22页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0928
CMOS IC
FROM 98K byte, RAM 4096 byte on-chip
LC87F5R96B
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F5R96B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 83.3ns, integrates on a single chip a number of hardware features such as 98K-byte flash ROM (onboard
programmable), 4096-byte RAM, On-chip debugging function, sophisticated 16-bit timers/counters (may be divided into
8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with
automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full
duplex), an 8-bit 11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a 27-source
10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
• Block-erasable in 128 byte units
• 100352 × 8 bits (Address: 00000H to 17FFFH, 1F800H to 1FFFFH)
RAM
• 4096 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz)
• 125ns (8MHz)
• 500ns (2MHz)
V
DD
V
DD
V
DD
=2.8 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
• 375ns (8MHz)
• 1.5µs (2MHz)
V
V
V
=2.8 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
DD
DD
DD
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn,
PWM2, PWM3, XT2)
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
• Reset pins
• Power pins
6 (V 1 to 3, V 1 to 3)
SS DD
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Ver.1.00
91207HKIM 20070810-S00010 No. A0928-1/22
LC87F5R96B
Timers
• Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) ×2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter
with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bit in continuous data transmission)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 8 bits × 11 channels
PWM: Multifrequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
No.A0928-2/22
LC87F5R96B
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 27 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
2
0000BH
00013H
INT1
3
INT2/T0L/INT4
4
0001BH
00023H
INT3/INT5/base timer0/base timer1
T0H/INT6
5
6
0002BH
00033H
T1L/T1H/INT7
7
SIO0/UART1 receive/UART2 receive
SIO/UART1 transmit/UART2 transmit
ADC/T6/T7
8
0003BH
00043H
9
10
0004BH
Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits (5 tCYC execution time)
• 24-bits × 16-bits (12 tCYC execution time)
• 16-bits ÷ 8-bits (8 tCYC execution time)
• 24-bits ÷ 16-bits (12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal)
• CF oscillation circuit
• Crystal oscillation circuit
: For system clock
: For system clock, with internal Rf
: For low-speed system clock
• Multifrequency RC oscillation circuit (internal) : For system clock
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0µs, 2.0µs, 4.0µs, 8.0µs, 16.0µs, 32.0µs, and
64.0µs (at a main clock rate of 12MHz).
No.A0928-3/22
LC87F5R96B
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Package Form
• QIP64E (14 × 14) : “Lead-free type”
Development Tools
• Evaluation (EVA) chip
• Emulator
: LC87EV690
: EVA62S + ECB876600D + SUB875M00 + POD64QFP
ICE-B877300 + SUB875M00 + POD64QFP
: TCB87-TypeB + LC87F5R96B
• On-chip-debugger
Programming Boards
Package
Programming boards
W87F50256Q
QIP64E(14 × 14)
Flash ROM Programmer
Maker
Model
Support version(Note)
Device
Flash Support
Group,
AF9708/09/09B
Revision : After Rev.02.73
LC87F76C8A
(including product of Ando Electric Co.,Ltd)
Inc.(Single)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
AF9833(Unit)
Revision : After Rev.02.29
Revision : After Rev.01.88
Flash Support
LC87F5NC8A
LC87F5R96B
Group, Inc.(Gang)
(including product of Ando Electric Co.,Ltd)
Application Version:
After 1.04
SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
SANYO
Chip Data Version:
After2.11
No.A0928-4/22
LC87F5R96B
Package Dimensions
unit : mm (typ)
3159A
17.2
14.0
48
33
32
49
64
17
1
16
0.8
0.35
0.15
(1.0)
SANYO : QIP64E(14X14)
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/NKIN
P73/INT3/T0IN
RES
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P32/UTX1
49
P33/URX1
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P34/UTX2
P35/URX2
P36
XT1/AN10
P37
XT2/AN11
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN/INT7
P23/INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN/INT6
P07/T7O
V
1
SS
LC87F5R96B
CF1
CF2
1
V
DD
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
P06/T6O
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Top view
SANYO: QIP64E(14×14) “Lead-free Type”
No.A0928-5/22
LC87F5R96B
System Block Diagram
Interrupt control
Standby control
IR
PLA
CF
RC
Flash ROM
X’tal
MRC
PC
SIO0
Bus interface
Port 0
SIO1
ACC
B register
Timer 0
Timer 1
Timer 4
Timer 5
Timer 6
Port 1
Port 2
Port 7
Port 8
ADC
C register
ALU
PSW
RAR
INT0 to INT7
noise filter
Timer 7
Base timer
PWM2/3
RAM
Port 3
Port C
Stack pointer
UART1
UART2
Watchdog timer
On-chip debugger
No.A0928-6/22
LC87F5R96B
Pin Description
Pin Name
I/O
Description
Option
No
V
V
V
V
1, V 2
SS
-
- Power supply pin
+ Power supply pin
SS
SS
DD
DD
3
1, V
3
2
-
No
DD
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Shared Pins
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/beeper output
• 8-bit I/O port
Port 2
I/O
Yes
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
enable
enable
enable
enable
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Continued on next page.
No.A0928-7/22
LC87F5R96B
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Shared Pins
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Port 8
I/O
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
• Shared Pins
P80 to P86
AD converter input port : AN0 (P80) to AN6 (P86)
• PWM2 and PWM3 output ports
• General-purpose I/O available
• 8-bit I/O port
PWM2
PWM3
Port 3
I/O
I/O
No
Yes
• I/O specifiable in 1-bit units
P30 to P37
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
PC0 to PC7
DBGP0 to DBGP2(PC5 to PC7): On-chip Debugger
Reset pin
RES
XT1
Input
Input
No
No
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to V 1 if not to be used.
DD
XT2
I/O
• 32.768kHz crystal oscillator input pin
• Shared pins
No
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
No.A0928-8/22
LC87F5R96B
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Options Selected
Port
Option Type
Output Type
Pull-up Resistor
in Units of
1 bit
P00 to P07
1
2
CMOS
Programmable (Note 1)
No
Nch-open drain
CMOS
P10 to P17
P20 to P27
P30 to P37
1 bit
1 bit
1 bit
1
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
1
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
No
No
No
No
1
P71 to P73
P80 to P86
PWM2, PWM3
PC0 to PC7
-
-
-
Nch-open drain
CMOS
No
1 bit
CMOS
Programmable
Programmable
No
2
Nch-open drain
XT1
XT2
-
-
No
No
Input for 32.768kHz crystal oscillator (Input only)
Output for 32.768kHz crystal oscillator
No
(Nch-open drain when in general-purpose output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the V 1 pin and prolong the backup time.
DD
Be sure to electrically short the V 1, V 2, and V 3 pins.
SS SS SS
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Back-up
LSI
capacitor
V
1
DD
Power
Supply
V
2
DD
V
3
DD
V
1
V
2
V
3
SS
SS
SS
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up
capacitor
LSI
V
V
V
1
2
3
DD
DD
DD
Power
Supply
V
1
V
2
V
3
SS
SS
SS
No.A0928-9/22
LC87F5R96B
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pins/Remarks
1, V 2, V 3
DD
Conditions
V
[V]
min
-0.3
unit
V
DD
Maximum supply
voltage
V
max
V
V
1=V 2=V 3
DD
DD
DD
DD DD DD
+6.5
+0.3
Input voltage
V (1)
XT1, CF1
-0.3
V
V
I
DD
Input/Output voltage
V
(1)
IO
Ports 0, 1, 2
Ports 7, 8
Ports 3, C
-0.3
+0.3
DD
PWM0, PWM1, XT2
Ports 0, 1, 2
Peak output
current
IOPH(1)
CMOS output select
Per 1 application pin
Per 1 application pin.
-10
Ports 3, C
IOPH(2)
IOPH(3)
IOMH(1)
PWM2, PWM3
-20
-5
P71 to P73
Per 1 application pin.
Mean output
current
Ports 0, 1, 2
Ports 3, C
CMOS output select
Per 1 application pin
Per 1 application pin
-7.5
(Note1-1)
IOMH(2)
IOMH(3)
ΣIOAH(1)
ΣIOAH(2)
PWM2, PWM3
-10
-3
P71 to P73
P71 to P73
Per 1 application pin
Total output
current
Total of all applicable pins
Total of all applicable pins
-10
Port 1
-25
-25
-45
PWM2, PWM3
Ports 0, 2
ΣIOAH(3)
ΣIOAH(4)
Total of all applicable pins
Total of all applicable pins
Ports 0, 1, 2
PWM2, PWM3
Port 3
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
IOPL(1)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Per 1 application pin.
-25
-25
-45
Port C
Ports 3, C
Peak output
current
P02 to P07
Ports 1, 2
20
Ports 3, C
PWM2, PWM3
P00, P01
mA
IOPL(2)
IOPL(3)
IOML(1)
Per 1 application pin.
Per 1 application pin.
Per 1 application pin.
30
10
Ports 7, 8, XT2
Mean output
current
P02 to P07
Ports 1, 2
15
(Note1-1)
Ports 3, C
PWM2, PWM3
P00, P01
IOML(2)
IOML(3)
ΣIOAL(1)
Per 1 application pin.
Per 1 application pin.
Total of all applicable pins
20
Ports 7, 8, XT2
7.5
Total output
current
Port 7
15
P83 to P86, XT2
P80 to P82
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
15
20
Ports 7, 8, XT2
Port 1
45
45
80
PWM2, PWM3
Ports 0, 2
ΣIOAL(5)
ΣIOAL(6)
Total of all applicable pins
Total of all applicable pins
Ports 0, 1, 2
PWM2, PWM3
Port 3
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
Pd max
Topr
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ta=-40 to +85°C
45
45
Port C
Ports 3, C
QIP64E(14×14)
80
Power dissipation
300
mW
Operating ambient
temperature
-40
-55
+85
°C
Storage ambient
temperature
Tstg
+125
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0928-10/22
LC87F5R96B
Allowable Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
1=V 2=V
DD
Conditions
V
[V]
min
typ
max
unit
DD
Operating
V
(1)
V
3
3
0.245µs≤ tCYC≤200µs
0.367µs≤ tCYC≤200µs
1.47µs≤ tCYC≤200µs
2.8
5.5
5.5
5.5
DD
DD
DD
supply voltage
(Note2-1)
2.5
2.2
Memory
VHD
V
1=V 2=V
DD
RAM and register contents
sustained in HOLD mode
DD
DD
sustaining
supply voltage
High level input
voltage
2.0
5.5
V
(1)
Ports 1, 2
IH
P71 to P73
0.3V
DD
2.2 to 5.5
2.2 to 5.5
V
DD
P70 port input/
interrupt side
Ports 0, 8, 3, C
PWM2, PWM3
+0.7
V
V
(2)
(3)
(4)
0.3V
DD
IH
IH
IH
V
V
DD
+0.7
Port P70 watchdog
timer side
V
2.2 to 5.5
2.2 to 5.5
4.0 to 5.5
0.9V
DD
DD
RES
XT1, XT2, CF1,
V
V
0.75V
V
DD
DD
Low level input
voltage
(1)
Ports 1, 2
0.1V
IL
DD
V
V
SS
P71 to P73
+0.4
P70 port input/
Interrupt side
Ports 0, 8, 3, C
PWM2, PWM3
2.2 to 4.0
0.2V
SS
DD
V
(2)
0.15V
IL
DD
4.0 to 5.5
2.2 to 5.5
2.2 to 5.5
V
V
V
V
SS
SS
SS
SS
+0.4
0.2V
DD
V
V
(3)
(4)
Port 70 watchdog
timer side
0.8V
IL
DD
-1.0
RES
XT1, XT2, CF1,
2.2 to 5.5
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
2.8 to 5.5
2.5 to 5.5
0.25V
DD
IL
Instruction cycle
time
tCYC
0.245
0.367
1.47
0.1
200
µs
200
200
12
(Note2-2)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division rate=1/1
0.1
8
• External system clock
duty=50±5%
2.2 to 5.5
0.1
2
MHz
• CF2 pin open
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.1
0.1
24.4
16
4
• System clock frequency
division rate=1/2
Oscillation
frequency
range
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
CF1, CF2
12MHz ceramic oscillation
See Fig. 1.
2.8 to 5.5
2.5 to 5.5
12
8MHz ceramic oscillation
See Fig. 1.
8
(Note2-3)
4MHz ceramic oscillation
See Fig. 1.
MHz
kHz
2.2 to 5.5
2.2 to 5.5
2.5 to 5.5
4
1.0
16
FmRC
Internal RC oscillation
0.3
2.0
FmMRC
Frequency variable RC
oscillation source oscillation
32.768kHz crystal oscillation
See Fig. 2.
FsX’tal
XT1, XT2
2.2 to 5.5
32.768
Note 2-1: V
DD
must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0928-11/22
LC87F5R96B
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
DD
High level input
current
I
(1)
IH
Ports 0, 1, 2
Ports 7, 8
Ports 3, C
RES
Output disabled
Pull-up resistor off
=V
V
2.2 to 5.5
1
IN DD
(Including output Tr's off leakage
PWM2, PWM3
XT1, XT2
current))
I
(2)
IH
For input port specification
2.2 to 5.5
2.2 to 5.5
1
V
=V
IN DD
I
I
(3)
IH
CF1
V
=V
15
IN DD
µA
Low level input
current
(1)
IL
Ports 0, 1, 2
Ports 7, 8
Ports 3, C
RES
Output disabled
Pull-up resistor off
V
=V
2.2 to 5.5
-1
IN SS
(Including output Tr's off leakage
current))
PWM2, PWM3
XT1, XT2
I
I
(2)
IL
For input port specification
2.2 to 5.5
-1
V
V
=V
IN SS
(3)
IL
CF1
=V
2.2 to 5.5
4.5 to 5.5
-15
-1
IN SS
High level output
voltage
V
(1)
Ports 0, 1, 2
Ports 3, C
I
=-1mA
OH
V
OH
OH
DD
V
(2)
I
I
I
I
I
I
I
=-0.4mA
V
OH
DD
-0.4
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
V
V
V
V
V
V
(3)
(4)
(5)
(6)
(7)
(8)
=-0.2mA
=-0.4mA
=-0.2mA
=-10mA
=-1.6mA
=-1mA
V
DD
-0.4
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
Ports 71 to 73
PWM2, PWM3
V
DD
-0.4
V
DD
-0.4
V
DD
-1.5
V
DD
-0.4
V
V
DD
-0.4
Low level output
voltage
V
V
V
V
V
V
V
V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Ports 0, 1, 2
Ports 3, C
I
I
I
I
I
I
I
I
=10mA
=1.6mA
=1mA
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
2.2 to 5.5
1.5
0.4
0.4
0.4
0.4
1.5
0.4
0.4
80
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
PWM2, PWM3,
Ports 7, 8
XT2
=1.6mA
=1mA
P00, P01
=30mA
=5mA
=2.5mA
=0.9V
Pull-up resistance
Rpu(1)
Rpu(2)
VHYS
Ports 0, 1, 2, 7
Ports 3, C
V
15
18
35
OH
DD
kΩ
35
150
RES
Hysteresis voltage
Pin capacitance
2.2to 5.5
0.1V
V
DD
Ports 1, 2, 7
All pins
CP
• For pins other than that under
test: V =V
IN SS
• f=1MHz
2.2 to 5.5
10
pF
• Ta=25°C
No.A0928-12/22
LC87F5R96B
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Pins
Parameter
Frequency
Symbol
tSCK(1)
Conditions
/Remarks
V
[V]
min
typ
max
unit
DD
SCK0(P12)
• See Fig. 6.
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.2 to 5.5
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.2 to 5.5
• Continuous data
tSCKH(2)
+(10/3)
tCYC
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
0.03
0.03
Output
SO0(P10),
SB0(P11),
• Continuous data
(1/3)tCYC
+0.05
delay time
transmission/reception mode
• (Note 4-1-3)
µs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
• (Note 4-1-3)
(1/3)tCYC
+0.15
2.2 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0928-13/22
LC87F5R96B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Pins/
Parameter
Frequency
Symbol
tSCK(3)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK1(P15)
• See Fig. 6.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected.
• See Fig. 6.
Low level
pulse width
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14)
SI1(P14),
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
µs
Output delay
time
SO1(P13),
SB1(P14)
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
change in open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0928-14/22
LC87F5R96B
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
unit
tCYC
µs
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
INT1(P71),
INT2(P72)
INT4(P20 to P23),
INT5(P24 to P27),
INT6(P20)
2.2 to 5.5
1
INT7(P24)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
INT3(P73) when noise filter
time constant is 1/1.
INT3(P73) when noise filter
time constant is 1/32
INT3(P73) when noise filter
time constant is 1/128
RES
• Interrupt source flag can be set.
2.2 to 5.5
2.2 to 5.5
2
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
Resetting is enabled.
64
2.2 to 5.5
2.2 to 5.5
256
200
AD Converter Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
bit
DD
Resolution
N
AN0(P80) to
AN6(P86),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2),
3.0 to 5.5
8
Absolute
ET
(Note 6-1)
3.0 to 5.5
1.5
LSB
accuracy
Conversion time
TCAD
AD conversion time=32×tCYC
(when ADCR2=0) (Note 6-2)
11.74
97.92
(tCYC=
3.06µs)
97.92
4.5 to 5.5
(tCYC=
0.367µs)
23.53
3.0 to 5.5
4.5 to 5.5
(tCYC=
0.735µs)
15.68
(tCYC=
3.06µs)
97.92
µs
AD conversion time=64×tCYC
(when ADCR2=1)
(Note 6-2)
(tCYC=
0.245µs)
23.49
(tCYC=
1.53µs)
97.92
3.0 to 5.5
3.0 to 5.5
(tCYC=
0.376µs)
(tCYC=
1.53µs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
µA
VAIN=V
SS
-1
Note 6-1: The quantization error ( 1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0928-15/22
LC87F5R96B
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
=V
2
3
DD
DD
4.5 to 5.5
9.1
18.5
=V
(Note 7-1)
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
2.8 to 4.5
4.5 to 5.5
2.5 to 4.5
4.5 to 5.5
2.2 to 4.5
5.3
6.7
13.5
14
IDDOP(2)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(3)
IDDOP(4)
3.8
10
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
2.7
6
mA
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(5)
IDDOP(6)
1.45
3.8
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
2.2 to 4.5
0.95
0.53
4.3
3.0
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
IDDOP(7)
IDDOP(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
2.2 to 4.5
4.5 to 5.5
2.2 to 4.5
1.25
0.67
38
5.2
4.2
112
72
• System clock set to 1MHz with frequency
variable RC oscillation
IDDOP(9)
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
IDDOP(10)
µA
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
IDDOP(11)
19
HALT mode
consumption
current
IDDHALT(1)
V
1
DD
=V
2
3
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
DD
4.5 to 5.5
2.8 to 5.5
3.2
1.8
7.5
4
=V
(Note 7-1)
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• HALT mode
mA
IDDHALT(2)
IDDHALT(3)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
2.5 to 4.5
2.4
5.3
2.8
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
12.5
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A0928-16/22
LC87F5R96B
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(4)
V
1
• HALT mode
DD
=V
=V
2
3
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
DD
4.5 to 5.5
2.2 to 4.5
1
2.3
(Note 7-1)
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(5)
IDDHALT(6)
0.5
1.3
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
2.2 to 4.5
0.33
0.17
0.9
0.7
mA
IDDHALT(7)
IDDHALT(8)
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
2.2 to 4.5
4.5 to 5.5
2.2 to 4.5
1
0.5
18
5
3.8
2.7
73
• System clock set to 1MHz with frequency
variable RC oscillation
IDDHALT(9)
IDDHALT(10)
IDDHALT(11)
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
65
µA
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
V
1
• HOLD mode
DD
4.5 to 5.5
2.2 to 4.5
0.035
0.015
20
16
• CF1=V
DD
or open (External clock mode)
Timer HOLD
mode
• Timer HOLD mode
• CF1=V or open (External clock mode)
4.5 to 5.5
2.2 to 4.5
16
65
52
DD
consumption
current
• FmX'tal=32.768kHz by crystal oscillation
mode
IDDHOLD(4)
3.5
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
mA
DD
Onboard
IDDFW(1)
V
1
• Without CPU current
DD
programming
current
2.70 to 5.5
5
10
Programming
time
tFW(1)
tFW(2)
• Erasing
2.7 to 5.5
2.7 to 5.5
20
40
30
60
ms
• programming
µs
No.A0928-17/22
LC87F5R96B
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
Specification
SS
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
Transfer rate
UBR
P32 (UTX1),
P33 (URX1),
P34 (UTX2),
P35 (URX2)
2.5 to 5.5
16/3
8192/3
tCYC
Data length : 7/8/9 bits (LSB first)
Stop bits : 1-bit (2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Stop bit
End of
transmission
Start bit
Start of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Stop bit
End of
reception
Start bit
Start of
reception
Receive data (LSB first)
UBR
V 1, V 1 Terminal Condition
DD SS
It is necessary to place capacitors between V 1 and V 1 as describe below.
DD SS
• Place capacitors as close to V 1 and V 1 as possible.
DD SS
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1µF.
• Use thicker pattern for V 1 and V 1.
DD
SS
L2
L1
V
V
1
SS
C1
C2
1
DD
L1’
L2’
No.A0928-18/22
LC87F5R96B
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
12MHz
10MHz
CSTCE12M0G52-R0
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(10)
(15)
(10)
(15)
(15)
(15)
(10)
(10)
(15)
(10)
(15)
(15)
(15)
Open
Open
Open
Open
Open
Open
Open
470
470
680
680
1k
2.6 to 5.5
2.4 to 5.5
2.6 to 5.5
2.3 to 5.5
2.5 to 5.5
2.2 to 5.5
2.2 to 5.5
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
MURATA
8MHz
4MHz
1.5k
1.5k
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Fig. 4).
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation
Circuit Constant
Operating Voltage
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Range
[V]
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
SEIKO
Applicable
32.768kHz
MC-306
18
18
Open
560k
2.2 to 5.5
1.2
3.0
TOYOCOM
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf1
CF
Rd1
C2
Rf2
Rd2
C4
C1
C3
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A0928-19/22
LC87F5R96B
V
DD
Operating V
limit
0V
lower
DD
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
absent
HOLD reset signal
HOLD reset signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0928-20/22
LC87F5R96B
V
DD
R
C
RES
Note:
Determine the value of C
and R so that the
RES
RES
reset signal is present for a period of 200µs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKLA
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0928-21/22
LC87F5R96B
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of August, 2007. Specifications and information herein are subject
to change without notice.
PS
No.A0928-22/22
相关型号：
©2020 ICPDF网 联系我们和版权申明