EN6370B [SANYO]
LCD Display Driver with Key Input Function; 用按键输入功能的LCD显示驱动
| 型号： | EN6370B |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | LCD Display Driver with Key Input Function |
| 文件： | 总38页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN6370B
CMOS IC
1/8 to 1/10 Duty
LCD Display Driver
with Key Input Function
LC75808W
Overview
The LC75808W is 1/8 to 1/10 duty LCD display driver that can directly drive up to 600 segments and can control up to
four general-purpose output ports. This product also incorporates a key scan circuit that accepts input from up to 30 keys
to reduce printed circuit board wiring.
Features
• Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)
• 1/8duty–1/4bias, 1/9duty–1/4bias, and 1/10duty–1/4bias drive schemes can be controlled from serial data.
1/8duty–1/4bias: up to 480 segments
1/9duty–1/4bias: up to 540 segments
1/10duty–1/4bias: up to 600 segments
• Sleep mode and all segments off functions that are controlled from serial data.
• Serial data I/O supports CCB format communication with the system controller.
• Direct display of display data without the use of a decoder provides high generality.
• Built-in display contrast adjustment circuit.
• Up to 4 general-purpose output ports are included.
• Independent LCD driver block power supply V
.
LCD
• Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.
• The INH pin is provided. This pin turns off the display, disables key scanning, and forces the general-purpose
output ports to the low level.
• RC oscillator circuit.
• CCB is a registered trademark of SANYO Electric Co., Ltd.
• CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO
Semiconductor for this format.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
O2710HKIM B8-7237/31000RM(OT)/128000RM No.6370-1/38
LC75808W
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0V
SS
Parameter
Symbol
max
Conditions
Ratings
-0.3 to +7.0
Unit
V
Maximum supply voltage
V
V
V
V
V
V
V
V
I
V
V
DD
DD
max
-0.3 to +12.0
-0.3 to +7.0
LCD
LCD
INH
Input voltage
Output voltage
Output current
1
CE, CL, DI,
OSC, KI1 to KI5, TEST
1, V 2, V 3, V
IN
2
V
-0.3 to V +0.3
DD
IN
3
V
4
-0.3 to V
+0.3
IN
LCD LCD LCD LCD
LCD
1
DO
OSC, KS1 to KS6, P1 to P4
0, S1 to S60, COM1 to COM10
-0.3 to +7.0
OUT
OUT
OUT
2
3
V
-0.3 to V +0.3
DD
V
-0.3 to V
+0.3
300
3
LCD
LCD
1
S1 to S60
μA
mA
OUT
OUT
OUT
OUT
I
I
I
2
COM1 to COM10
KS1 to KS6
P1 to P4
3
4
1
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta=85°C
200
mW
°C
-40 to +85
Tstg
-55 to +125
°C
Allowable Operating Ranges at Ta = -40 to +85°C, V = 0V
SS
Ratings
typ
Parameter
Supply voltage
Symbol
Conditions
unit
min
4.5
max
6.0
V
V
V
V
DD
DD
, When the display contrast adjustment
LCD
LCD
7.0
11.0
11.0
V
V
circuit is used
, When the display contrast adjustment
V
V
V
V
V
V
LCD
LCD
circuit is not used
4.5
4
Output voltage
Input voltage
0
V
V
V
V
V
0
1
2
3
4
V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
V
LCD
+4.5
1
3/4(V 0
LCD
LCD
V
0
LCD
LCD
LCD
-V
LCD
4)
2
2/4(V
-V
0
LCD
LCD
V
V
0
0
4)
V
LCD
3
1/4(V
-V
0
LCD
LCD
4)
LCD
V
V
V
V
4
0
1.5
6.0
LCD
INH
INH
Input high level voltage
1
CE, CL, DI,
KI1 to KI5
CE, CL, DI,
OSC
0.8V
0.6V
V
V
IH
DD
2
V
IH
DD
0
DD
Input low level voltage
, KI1 to KI5
0.2V
V
IL
DD
Recommended external resistance
R
43
680
50
kΩ
OSC
OSC
Recommended external
capacitance
C
OSC
pF
Guaranteed oscillation range
f
OSC
25
100
kHz
ns
ns
ns
ns
ns
ns
ns
μs
μs
OSC
tds
Data setup time
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
160
160
160
160
160
160
160
Data hold time
tdh
tcp
tcs
tch
tφH
tφL
tdc
tdr
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
DO output delay time
DO rise time
CL
DO R =4.7kΩ, C =10pF *1
PU
1.5
1.5
L
DO R =4.7kΩ, C =10pF *1
PU
L
Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor R
and the
PU
load capacitance C .
L
No.6370-2/38
LC75808W
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Conditions
, KI1 to KI5
unit
min
max
INH
Hysteresis
V
CE, CL, DI,
0.1V
V
V
H
DD
Power-down detection
voltage
V
DET
2.5
3.0
3.5
INH
INH
Input high level current
I
CE, CL, DI,
CE, CL, DI,
KI1 to KI5
: V =6.0V
5.0
μA
μA
V
IH
I
Input low level current
Input floating voltage
I
: V =0V
I
-5.0
50
IL
V
0.05V
IF
DD
Pull-down resistance
R
KI1 to KI5: V =5.0V
DD
100
-0.5
250
6.0
kΩ
μA
PD
Output off leakage current
Output high level voltage
I
DO: V =6.0V
O
OFFH
V
1
2
3
4
S1 to S60: I =-20μA
V
V
0-0.6
0-0.6
-1.0
OH
OH
OH
OH
O
LCD
V
V
V
V
V
V
V
V
V
COM1 to COM10: I =-100μA
O
LCD
V
V
V
KS1 to KS6: I =-500μA
V
V
-0.2
DD
O
DD
DD
P1 to P4: I =-1mA
O
V
-1.0
DD
Output low level voltage
1
S1 to S60: I =20μA
V
V
4+0.6
4+0.6
1.5
OL
OL
OL
OL
OL
O
LCD
2
COM1 to COM10: I =100μA
O
LCD
3
4
5
KS1 to KS6: I =25μA
0.2
0.5
0.1
O
P1 to P4: I =1mA
O
1.0
DO: I =1mA
O
0.5
Output middle level voltage
*2
1
2
3
S1 to S60: I = 20μA
2/4(V
-V
0
2/4(V
-V
0
MID
MID
MID
O
LCD
4)
LCD
4)
LCD
-0.6
LCD
+0.6
V
V
f
COM1 to COM10: I = 100μA
3/4(V
-V
0
3/4(V
-V
0
O
LCD
4)
LCD
4)
V
LCD
-0.6
LCD
+0.6
COM1 to COM10: I = 100μA
1/4(V
-V
0
1/4(V
-V
0
O
LCD
4)
LCD
4)
LCD
LCD
-0.6
40
+0.6
60
Oscillator frequency
Current drain
OSC: R
=43kΩ, C =680pF
OSC
50
kHz
OSC
OSC
I
I
I
I
1
V
V
V
V
Sleep mode
100
500
5
DD
DD:
2
V
=6.0V, outputs open, f =50kHz
250
DD
DD: DD OSC
1
Sleep mode
LCD
LCD:
: V
2
=11.0V, Outputs open, f =50kHz
LCD LCD OSC
(When the display contrast adjustment circuit is used.)
V : V =11.0V, Outputs open, f =50kHz
LCD LCD OSC
LCD
μA
500
250
1000
I
3
LCD
(When the display contrast adjustment circuit is not
500
used.)
Note: *2 Excluding the bias voltage generation divider resistor built into V
0, V
LCD LCD
1, V
2, V
LCD
3, and
LCD
V
4. (See Figure 1.)
LCD
V
LCD
CONTRAST
ADJUSTER
V
0
1
2
3
4
LCD
LCD
LCD
LCD
LCD
V
V
V
V
To the common and segment drivers
Excluding these resistors.
A12899
Figure 1
No.6370-3/38
LC75808W
1. When CL is stopped at the low level
V 1
IH
CE
V
IL
tφH
tφL
V
1
IH
50%
CL
DI
V
IL
tcp
tcs
tch
V
1
IH
V
IL
tds
tdh
tdc
tdr
DO
D0
D1
A12900
2. When CL is stopped at the high level
V
1
IH
CE
V
IL
tφL
tφH
V
1
IH
50%
CL
DI
V
IL
tcp tcs
tch
V
V
1
IH
IL
tds
tdh
DO
D0
D1
tdc
tdr
A12901
Figure 2
Package Dimensions
unit:mm (typ)
3181C
16.0
14.0
75
51
50
76
100
26
1
25
0.5
0.145
0.2
(1.0)
SANYO : SQFP100(14X14)
No.6370-4/38
LC75808W
Pin Assignment
75
76
51
50
KS6
KI1
KI2
KI3
KI4
KI5
P1
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
P2
P3
P4
DD
V
V
LCD
LC75808W
(SQFP100)
V
V
V
V
V
0
1
2
3
4
LCD
LCD
LCD
LCD
LCD
V
SS
TEST
OSC
INH
DO
CE
CL
DI
100
26
25
1
A12898
Top view
Block Diagram
GENERAL
PORT
COMMON
DRIVER
SEGMENT DRIVER & LATCH
V
LCD
0
CONTROL
REGISTER
CONTRAST
ADJUSTER
V
LCD
LCD
LCD
LCD
V
V
V
V
1
2
3
4
SHIFT REGISTER
CCB INTERFACE
KEY BUFFER
KEY SCAN
LCD
V
CLOCK
DD
GENERATOR
V
DET
V
SS
TEST
A12902
No.6370-5/38
LC75808W
Pin Functions
Handling
when
Symbol
Pin No.
Function
Active
I/O
unused
Segment driver outputs.
Common driver outputs.
S1 to S60
1 to 60
-
-
O
O
OPEN
COM1 to
COM10
70 to 61
OPEN
Key scan outputs.
Although normal key scan timing lines require diodes to be inserted in the timing
lines to prevent shorts, since these outputs are unbalanced CMOS transistor
outputs, these outputs will not be damaged by shorting when these outputs are
used to form a key matrix.
KS1 to KS6
71 to 76
-
O
OPEN
Key scan inputs.
KI1 to KI5
P1 to P4
77 to 81
82 to 85
H
-
I
GND
These pins have built-in pull-down resistors.
General-purpose output ports.
O
OPEN
Oscillator connection.
OSC
95
An oscillator circuit is formed by connecting an external resistor and capacitor at
-
I/O
V
DD
this pin.
Serial data interface connections to the controller. Note that DO, being an open-
drain output, requires a pull-up resistor.
CE: Chip enable
CE
CL
DI
98
99
H
I
I
GND
CL: Synchronization clock
100
97
-
-
I
DI: Transfer data
DO
O
OPEN
DO: Output data
Input that turns the display off, disables key scanning, and forces the
general-purpose output ports low.
INH
• When
is low (V ):
SS
• Display off
S1 to S60 = “L” (V
4).
LCD
COM1 to COM10 = “L” (V
4).
LCD
• General-purpose output ports P1 to P4 = low (V
• Key scanning is disabled: KS1 to KS6 = low (V
)
SS
)
INH
96
L
I
V
SS
DD
• All the key data is reset to low.
INH
• When
is high (V ):
DD
• Display on
• The states of the general-purpose output ports can be set by the PC1 to PC4
control data.
• Key scanning is enabled.
INH
However, serial data can be transferred when the
This pin must be connected to ground.
pin is low.
TEST
94
88
-
-
I
-
LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be
changed by the display contrast adjustment circuit.
V
0
However, (V
0 - V
4) must be greater than or equal to 4.5V.
O
OPEN
LCD
LCD LCD
Also, external power must not be applied to this pin since the pin circuit includes
the display contrast adjustment circuit.
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to
V
V
V
1
2
3
89
90
91
-
-
-
I
I
I
OPEN
OPEN
OPEN
LCD
LCD
LCD
supply the 3/4 (V
0 - V 4) voltage level externally.
LCD
LCD
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to
supply the 2/4 (V 0 - V 4) voltage level externally.
LCD LCD
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to
supply the 1/4 (V 0 - V 4) voltage level externally.
LCD LCD
LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display
contrast can be implemented by connecting an external variable resistor to this pin.
V
4
92
-
I
GND
LCD
However, (V
0 - V
4) must be greater than or equal to 4.5V, and V 4
LCD
LCD LCD
must be in the range 0 V to 1.5V, inclusive.
Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V.
V
86
87
93
-
-
-
-
-
-
-
-
-
DD
LCD driver block power supply connection. Provide a voltage of between 7.0 and
11.0V when the display contrast adjustment circuit is used and provide a voltage of
between 4.5 and 11.0V when the circuit is not used.
V
LCD
Power supply connection. Connect to ground.
V
SS
No.6370-6/38
LC75808W
Serial Data Input
1. 1/8 duty
(1) When CL is stopped at the low level.
• When the display data is transferred.
CE
CL
D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
DI
0
1
0
0
0
0
1
0
D1
D121
D241
D361
D2
D122
D242
D362
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
DO
D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
0
1
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
D349 D350 D351 D352 D353 D354 D355 D356 D357 D358 D359 D360
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
D469 D470 D471 D472 D473 D474 D475 D476 D477 D478 D479 D480
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
• When the control data is transferred.
CE
CL
DI
0
1
0
0
0
0
1
0
KC1 KC2 KC3 KC4 KC5 KC6 PC1 PC2 PC3 PC4 CT0 CT1 CT2 CT3 CTC SC SP DT1 DT2
Control data
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2 A3
DD
DO
A12903
Note: B0 to B3, A0 to A3........ CCB address
DD ................................ Direction data
No.6370-7/38
LC75808W
(2) When CL is stopped at the high level.
• When the display data is transferred.
CE
CL
D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
DI
0
1
0
0
0
0
1
0
D1 D2
D121 D122
D241 D242
D361 D362
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
DO
D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
0
1
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
D349 D350 D351 D352 D353 D354 D355 D356 D357 D358 D359 D360
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
D469 D470 D471 D472 D473 D474 D475 D476 D477 D478 D479 D480
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
• When the control data is transferred.
CE
CL
DI
0
1
0
0
0
0
1
0
KC1 KC2 KC3 KC4 KC5 KC6 PC1 PC2 PC3 PC4 CT0 CT1 CT2 CT3 CTC SC SP DT1 DT2
Control data
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2
A3
DD
DO
A12904
Note: B0 to B3, A0 to A3.........CCB address
DD.................................. Direction data
• CCB address: …………….... 42H
• D1 to D480: .......................... Display data
• KC1 to KC6: …………......... Key scan output state setting data
• PC1 to PC4:……………....... General-purpose output port state setting data
• CT0 to CT3, CTC: ………… Display contrast setting data
• SC: ........................................ Segment on/off control data
• SP: ........................................ Normal mode/sleep mode control data
• DT1, DT2: ............................ Display technique setting data
No.6370-8/38
LC75808W
2. 1/9 duty
(1) When CL is stopped at the low level.
• When the display data is transferred.
CE
CL
D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135
DI
0
1
0
0
0
0
1
0
D1
D136
D271
D406
D2
D137
D272
D407
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
DO
D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270
0
1
0
0
0
0
1
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
D395 D396 D397 D398 D399 D400 D401 D402 D403 D404 D405
0
1
0
0
0
0
1
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
D530 D531 D532 D533 D534 D535 D536 D537 D538 D539 D540
0
1
0
0
0
0
1
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
• When the control data is transferred.
CE
CL
DI
0
1
0
0
0
0
1
0
KC1 KC2 KC3 KC4 KC5 KC6 PC1 PC2 PC3 PC4 CT0 CT1 CT2 CT3 CTC SC SP DT1 DT2
Control data
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2 A3
DD
DO
A12905
Note: B0 to B3, A0 to A3........ CCB address
DD ................................ Direction data
No.6370-9/38
LC75808W
(2) When CL is stopped at the high level.
• When the display data is transferred.
CE
CL
D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135
DI
0
1
0
0
0
0
1
0
D1 D2
D136 D137
D271 D272
D406 D407
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
DO
D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270
0
1
0
0
0
0
1
0
0
0
0
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
D395 D396 D397 D398 D399 D400 D401 D402 D403 D404 D405
0
1
0
0
0
0
1
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
D530 D531 D532 D533 D534 D535 D536 D537 D538 D539 D540
0
1
0
0
0
0
1
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
• When the control data is transferred.
CE
CL
DI
0
1
0
0
0
0
1
0
KC1 KC2 KC3 KC4 KC5 KC6 PC1 PC2 PC3 PC4 CT0 CT1 CT2 CT3 CTC SC SP DT1 DT2
Control data
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2
A3
DD
DO
A12906
Note: B0 to B3, A0 to A3.........CCB address
DD.................................. Direction data
• CCB address: …………….... 42H
• D1 to D540: .......................... Display data
• KC1 to KC6: …………......... Key scan output state setting data
• PC1 to PC4:……………....... General-purpose output port state setting data
• CT0 to CT3, CTC: ………… Display contrast setting data
• SC: ........................................ Segment on/off control data
• SP: ........................................ Normal mode/sleep mode control data
• DT1, DT2: ............................ Display technique setting data
No.6370-10/38
LC75808W
3. 1/10 duty
(1) When CL is stopped at the low level.
• When the display data is transferred.
CE
CL
D141 D142 D143 D144 D145 D146 D147 D148 D149 D150
DI
0
1
0
0
0
0
1
0
D1
D151
D301
D451
D2
D152
D302
D452
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
DO
D291 D292 D293 D294 D295 D296 D297 D298 D299 D300
0
1
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
D441 D442 D443 D444 D445 D446 D447 D448 D449 D450
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
D591 D592 D593 D594 D595 D596 D597 D598 D599 D600
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
• When the control data is transferred.
CE
CL
DI
0
1
0
0
0
0
1
0
KC1 KC2 KC3 KC4 KC5 KC6 PC1 PC2 PC3 PC4 CT0 CT1 CT2 CT3 CTC SC SP DT1 DT
2
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
DD
DO
A12907
Note: B0 to B3, A0 to A3........ CCB address
DD ................................ Direction data
No.6370-11/38
LC75808W
(2) When CL is stopped at the high level.
• When the display data is transferred.
CE
CL
D141 D142 D143 D144 D145 D146 D147 D148 D149 D150
DI
0
1
0
0
0
0
1
0
D1 D2
D151 D152
D301 D302
D451 D452
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
DO
D291 D292 D293 D294 D295 D296 D297 D298 D299 D300
0
1
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
D441 D442 D443 D444 D445 D446 D447 D448 D449 D450
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
D591 D592 D593 D594 D595 D596 D597 D598 D599 D600
0
1
0
0
0
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
A3
Display data
Fixed data
DD
• When the control data is transferred.
CE
CL
DI
0
1
0
0
0
0
1
0
KC1 KC2 KC3 KC4 KC5 KC6 PC1 PC2 PC3 PC4 CT0 CT1 CT2 CT3 CTC SC SP DT1 DT2
Control data
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2
A3
DD
DO
A12908
Note: B0 to B3, A0 to A3.........CCB address
DD.................................. Direction data
• CCB address: …………….... 42H
• D1 to D600: .......................... Display data
• KC1 to KC6: …………......... Key scan output state setting data
• PC1 to PC4:……………....... General-purpose output port state setting data
• CT0 to CT3, CTC: ………… Display contrast setting data
• SC: ........................................ Segment on/off control data
• SP: ........................................ Normal mode/sleep mode control data
• DT1, DT2: ............................ Display technique setting data
No.6370-12/38
LC75808W
Control Data Functions
1. KC1 to KC6: Key scan output state setting data
These control data bits set the states of the key scan output pins KS1 to KS6.
Output pin
KS1
KS2
KS3
KS4
KS5
KC5
KS6
KC6
Key scan output state setting data
KC1
KC2
KC3
KC4
For example, if KC1 to KC3 are set to 1, and KC4 to KC6 are set to 0, then the output pins KS1 to KS3 will output
high levels (V ) and the output pins KS4 to KS6 will output low levels (V ) in the key scan standby state.
DD
SS
Note that key scan output signal is not output from output pins that are set low.
2. PC1 to PC4: General-purpose output port state setting data
These control data bits set the states of the general-purpose output ports P1 to P4.
Output pin
P1
P2
P3
P4
General-purpose output port state setting data
PC1
PC2
PC3
PC4
For example, if PC1 and PC2 are set to 1, and PC3 and PC4 are set to 0, then the output pins P1 and P2 will output
high levels (V ) and the output pins P3 and P4 will output low levels (V ).
DD
SS
3. CT0 to CT3, CTC: Display contrast setting data
These control data bits set the display contrast.
CT0 to CT3: Display contrast setting (11 steps)
CT0
CT1
CT2
CT3
LCD drive 4/4 bias voltage supply V
0 level
LCD
0
0
0
0
0.94V
0.91V
0.88V
0.85V
0.82V
0.79V
0.76V
0.73V
0.70V
0.67V
0.64V
=V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
-(0.03V
×2)
LCD LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
1
0
0
0
=V
LCD LCD
×3)
0
1
0
0
=V
LCD LCD
×4)
1
1
0
0
=V
LCD LCD
×5)
0
0
1
0
=V
LCD LCD
×6)
1
0
1
0
=V
LCD LCD
×7)
0
1
1
0
=V
LCD LCD
×8)
1
1
1
0
=V
LCD LCD
×9)
0
0
0
1
=V
LCD LCD
×10)
×11)
×12)
1
0
0
1
=V
LCD LCD
0
1
0
1
=V
LCD LCD
CTC: Display contrast adjustment circuit state setting
CTC
Display contrast adjustment circuit state
0
1
The display contrast adjustment circuit is disabled, and the V 0 pin level is forced to the V
level.
LCD LCD
The display contrast adjustment circuit operates and the display contrast is adjusted.
Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it
is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the V 4 pin
LCD
4) ≥ 4.5V,
and modifying the V
4 pin voltage. However, the following conditions must be met: (V
0 - V
LCD
LCD
LCD
and 1.5V ≥ V
4 ≥ 0V.
LCD
No.6370-13/38
LC75808W
4. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
Off
1
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
5. SP: Normal mode/sleep mode control data
This control data bit controls the normal mode and sleep mode.
BU
Mode
0
Normal mode
Sleep mode
The common and segment pins go to the V
4 level and the oscillator on the OSC pin is stopped (although it
LCD
1
operates during key scan operations) to reduce current drain. Note that the states of the general-purpose output ports
P1 to P4 are set by PC1 to PC4 in the control data during sleep mode as well as normal mode.
6. DT1, DT2: Display technique setting data
These control data bits set the display technique.
Output pins
DT1
DT2
Display technique
COM9
Fixed at the V
COM10
0
1
0
0
0
1
1/8 duty 1/4 bias drive
1/9 duty 1/4 bias drive
1/10 duty 1/4 bias drive
4 level
LCD
Fixed at the V
4 level
4 level
LCD
COM9
COM9
Fixed at the V
LCD
COM10
Note: COMn (n = 9 or 10): Common outputs
No.6370-14/38
LC75808W
Display Data and Output Pin Correspondence
• 1/8 duty
Output Pin
COM1
D1
COM2
D2
COM3
D3
COM4
COM5
D5
COM6
COM7
D7
COM8
D8
S1
D4
D6
S2
D9
D10
D11
D12
D13
D14
D15
D16
S3
D17
D18
D19
D20
D21
D22
D23
D24
S4
D25
D26
D27
D28
D29
D30
D31
D32
S5
D33
D34
D35
D36
D37
D38
D39
D40
S6
D41
D42
D43
D44
D45
D46
D47
D48
S7
D49
D50
D51
D52
D53
D54
D55
D56
S8
D57
D58
D59
D60
D61
D62
D63
D64
S9
D65
D66
D67
D68
D69
D70
D71
D72
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D108
D116
D124
D132
D140
D148
D156
D164
D172
D180
D188
D196
D204
D212
D220
D228
D236
D244
D252
D260
D268
D276
D284
D292
D300
D308
D316
D324
D332
D340
D348
D356
D101
D109
D117
D125
D133
D141
D149
D157
D165
D173
D181
D189
D197
D205
D213
D221
D229
D237
D245
D253
D261
D269
D277
D285
D293
D301
D309
D317
D325
D333
D341
D349
D357
D102
D110
D118
D126
D134
D142
D150
D158
D166
D174
D182
D190
D198
D206
D214
D222
D230
D238
D246
D254
D262
D270
D278
D286
D294
D302
D310
D318
D326
D334
D342
D350
D358
D103
D111
D119
D127
D135
D143
D151
D159
D167
D175
D183
D191
D199
D207
D215
D223
D231
D239
D247
D255
D263
D271
D279
D287
D295
D303
D311
D319
D327
D335
D343
D351
D359
D104
D112
D120
D128
D136
D144
D152
D160
D168
D176
D184
D192
D200
D208
D216
D224
D232
D240
D248
D256
D264
D272
D280
D288
D296
D304
D312
D320
D328
D336
D344
D352
D360
D105
D113
D121
D129
D137
D145
D153
D161
D169
D177
D185
D193
D201
D209
D217
D225
D233
D241
D249
D257
D265
D273
D281
D289
D297
D305
D313
D321
D329
D337
D345
D353
D106
D114
D122
D130
D138
D146
D154
D162
D170
D178
D186
D194
D202
D210
D218
D226
D234
D242
D250
D258
D266
D274
D282
D290
D298
D306
D314
D322
D330
D338
D346
D354
D107
D115
D123
D131
D139
D147
D155
D163
D171
D179
D187
D195
D203
D211
D219
D227
D235
D243
D251
D259
D267
D275
D283
D291
D299
D307
D315
D323
D331
D339
D347
D355
Continued on next page.
No.6370-15/38
LC75808W
Continued from preceding page.
Output Pin
S46
COM1
D361
D369
D377
D385
D393
D401
D409
D417
D425
D433
D441
D449
D457
D465
D473
COM2
D362
D370
D378
D386
D394
D402
D410
D418
D426
D434
D442
D450
D458
D466
D474
COM3
D363
D371
D379
D387
D395
D403
D411
D419
D427
D435
D443
D451
D459
D467
D475
COM4
COM5
D365
D373
D381
D389
D397
D405
D413
D421
D429
D437
D445
D453
D461
D469
D477
COM6
COM7
D367
D375
D383
D391
D399
D407
D415
D423
D431
D439
D447
D455
D463
D471
D479
COM8
D368
D376
D384
D392
D400
D408
D416
D424
D432
D440
D448
D456
D464
D472
D480
D364
D372
D380
D388
D396
D404
D412
D420
D428
D436
D444
D452
D460
D468
D476
D366
D374
D382
D390
D398
D406
D414
D422
D430
D438
D446
D454
D462
D470
D478
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D81
0
D82
0
D83
0
D84
0
D85
0
D86
0
D87
0
D88
0
The LCD segments for COM1 to COM8 are off
The LCD segment for COM1 is on
The LCD segment for COM2 is on
The LCD segment for COM3 is on
The LCD segment for COM4 is on
The LCD segment for COM5 is on
The LCD segment for COM6 is on
The LCD segment for COM7 is on
The LCD segment for COM8 is on
The LCD segments for COM1 to COM8 are on
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
No.6370-16/38
LC75808W
• 1/9 duty
Output Pin
S1
COM1
D1
COM2
D2
COM3
D3
COM4
D4
COM5
D5
COM6
COM7
D7
COM8
D8
COM9
D9
D6
S2
D10
D11
D12
D13
D14
D15
D16
D17
D18
S3
D19
D20
D21
D22
D23
D24
D25
D26
D27
S4
D28
D29
D30
D31
D32
D33
D34
D35
D36
S5
D37
D38
D39
D40
D41
D42
D43
D44
D45
S6
D46
D47
D48
D49
D50
D51
D52
D53
D54
S7
D55
D56
D57
D58
D59
D60
D61
D62
D63
S8
D64
D65
D66
D67
D68
D69
D70
D71
D72
S9
D73
D74
D75
D76
D77
D78
D79
D80
D81
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D109
D118
D127
D136
D145
D154
D163
D172
D181
D190
D199
D208
D217
D226
D235
D244
D253
D262
D271
D280
D289
D298
D307
D316
D325
D334
D343
D352
D361
D370
D379
D388
D397
D101
D110
D119
D128
D137
D146
D155
D164
D173
D182
D191
D200
D209
D218
D227
D236
D245
D254
D263
D272
D281
D290
D299
D308
D317
D326
D335
D344
D353
D362
D371
D380
D389
D398
D102
D111
D120
D129
D138
D147
D156
D165
D174
D183
D192
D201
D210
D219
D228
D237
D246
D255
D264
D273
D282
D291
D300
D309
D318
D327
D336
D345
D354
D363
D372
D381
D390
D399
D103
D112
D121
D130
D139
D148
D157
D166
D175
D184
D193
D202
D211
D220
D229
D238
D247
D256
D265
D274
D283
D292
D301
D310
D319
D328
D337
D346
D355
D364
D373
D382
D391
D400
D104
D113
D122
D131
D140
D149
D158
D167
D176
D185
D194
D203
D212
D221
D230
D239
D248
D257
D266
D275
D284
D293
D302
D311
D320
D329
D338
D347
D356
D365
D374
D383
D392
D401
D105
D114
D123
D132
D141
D150
D159
D168
D177
D186
D195
D204
D213
D222
D231
D240
D249
D258
D267
D276
D285
D294
D303
D312
D321
D330
D339
D348
D357
D366
D375
D384
D393
D402
D106
D115
D124
D133
D142
D151
D160
D169
D178
D187
D196
D205
D214
D223
D232
D241
D250
D259
D268
D277
D286
D295
D304
D313
D322
D331
D340
D349
D358
D367
D376
D385
D394
D403
D107
D116
D125
D134
D143
D152
D161
D170
D179
D188
D197
D206
D215
D224
D233
D242
D251
D260
D269
D278
D287
D296
D305
D314
D323
D332
D341
D350
D359
D368
D377
D386
D395
D404
D108
D117
D126
D135
D144
D153
D162
D171
D180
D189
D198
D207
D216
D225
D234
D243
D252
D261
D270
D279
D288
D297
D306
D315
D324
D333
D342
D351
D360
D369
D378
D387
D396
D405
Continued on next page.
No.6370-17/38
LC75808W
Continued from preceding page.
Output Pin
S46
COM1
D406
D415
D424
D433
D442
D451
D460
D469
D478
D487
D496
D505
D514
D523
D532
COM2
D407
D416
D425
D434
D443
D452
D461
D470
D479
D488
D497
D506
D515
D524
D533
COM3
D408
D417
D426
D435
D444
D453
D462
D471
D480
D489
D498
D507
D516
D525
D534
COM4
D409
D418
D427
D436
D445
D454
D463
D472
D481
D490
D499
D508
D517
D526
D535
COM5
D410
D419
D428
D437
D446
D455
D464
D473
D482
D491
D500
D509
D518
D527
D536
COM6
COM7
D412
D421
D430
D439
D448
D457
D466
D475
D484
D493
D502
D511
D520
D529
D538
COM8
D413
D422
D431
D440
D449
D458
D467
D476
D485
D494
D503
D512
D521
D530
D539
COM9
D414
D423
D432
D441
D450
D459
D468
D477
D486
D495
D504
D513
D522
D531
D540
D411
D420
D429
D438
D447
D456
D465
D474
D483
D492
D501
D510
D519
D528
D537
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D91
0
D92
0
D93
0
D94
0
D95
0
D96
0
D97
0
D98
0
D99
0
The LCD segments for COM1 to COM9 are off
The LCD segment for COM1 is on
The LCD segment for COM2 is on
The LCD segment for COM3 is on
The LCD segment for COM4 is on
The LCD segment for COM5 is on
The LCD segment for COM6 is on
The LCD segment for COM7 is on
The LCD segment for COM8 is on
The LCD segment for COM9 is on
The LCD segments for COM1 to COM9 are on
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
No.6370-18/38
LC75808W
• 1/10 duty
Output Pin
S1
COM1
D1
COM2
D2
COM3
D3
COM4
D4
COM5
D5
COM6
COM7
D7
COM8
D8
COM9
D9
COM10
D10
D6
S2
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
S3
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
S4
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
S5
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
S6
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
S7
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
S8
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
S9
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D110
D120
D130
D140
D150
D160
D170
D180
D190
D200
D210
D220
D230
D240
D250
D260
D270
D280
D290
D300
D310
D320
D330
D340
D350
D360
D370
D380
D390
D400
D410
D420
D430
D440
D450
D101
D111
D121
D131
D141
D151
D161
D171
D181
D191
D201
D211
D221
D231
D241
D251
D261
D271
D281
D291
D301
D311
D321
D331
D341
D351
D361
D371
D381
D391
D401
D411
D421
D431
D441
D102
D112
D122
D132
D142
D152
D162
D172
D182
D192
D202
D212
D222
D232
D242
D252
D262
D272
D282
D292
D302
D312
D322
D332
D342
D352
D362
D372
D382
D392
D402
D412
D422
D432
D442
D103
D113
D123
D133
D143
D153
D163
D173
D183
D193
D203
D213
D223
D233
D243
D253
D263
D273
D283
D293
D303
D313
D323
D333
D343
D353
D363
D373
D383
D393
D403
D413
D423
D433
D443
D104
D114
D124
D134
D144
D154
D164
D174
D184
D194
D204
D214
D224
D234
D244
D254
D264
D274
D284
D294
D304
D314
D324
D334
D344
D354
D364
D374
D384
D394
D404
D414
D424
D434
D444
D105
D115
D125
D135
D145
D155
D165
D175
D185
D195
D205
D215
D225
D235
D245
D255
D265
D275
D285
D295
D305
D315
D325
D335
D345
D355
D365
D375
D385
D395
D405
D415
D425
D435
D445
D106
D116
D126
D136
D146
D156
D166
D176
D186
D196
D206
D216
D226
D236
D246
D256
D266
D276
D286
D296
D306
D316
D326
D336
D346
D356
D366
D376
D386
D396
D406
D416
D426
D436
D446
D107
D117
D127
D137
D147
D157
D167
D177
D187
D197
D207
D217
D227
D237
D247
D257
D267
D277
D287
D297
D307
D317
D327
D337
D347
D357
D367
D377
D387
D397
D407
D417
D427
D437
D447
D108
D118
D128
D138
D148
D158
D168
D178
D188
D198
D208
D218
D228
D238
D248
D258
D268
D278
D288
D298
D308
D318
D328
D338
D348
D358
D368
D378
D388
D398
D408
D418
D428
D438
D448
D109
D119
D129
D139
D149
D159
D169
D179
D189
D199
D209
D219
D229
D239
D249
D259
D269
D279
D289
D299
D309
D319
D329
D339
D349
D359
D369
D379
D389
D399
D409
D419
D429
D439
D449
Continued on next page.
No.6370-19/38
LC75808W
Continued from preceding page.
Output Pin
S46
COM1
D451
D461
D471
D481
D491
D501
D511
D521
D531
D541
D551
D561
D571
D581
D591
COM2
D452
D462
D472
D482
D492
D502
D512
D522
D532
D542
D552
D562
D572
D582
D592
COM3
D453
D463
D473
D483
D493
D503
D513
D523
D533
D543
D553
D563
D573
D583
D593
COM4
D454
D464
D474
D484
D494
D504
D514
D524
D534
D544
D554
D564
D574
D584
D594
COM5
D455
D465
D475
D485
D495
D505
D515
D525
D535
D545
D555
D565
D575
D585
D595
COM6
COM7
D457
D467
D477
D487
D497
D507
D517
D527
D537
D547
D557
D567
D577
D587
D597
COM8
D458
D468
D478
D488
D498
D508
D518
D528
D538
D548
D558
D568
D578
D588
D598
COM9
D459
D469
D479
D489
D499
D509
D519
D529
D539
D549
D559
D569
D579
D589
D599
COM10
D460
D470
D480
D490
D500
D510
D520
D530
D540
D550
D560
D570
D580
D590
D600
D456
D466
D476
D486
D496
D506
D516
D526
D536
D546
D556
D566
D576
D586
D596
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
The LCD segments for COM1 to COM10 are off
The LCD segment for COM1 is on
The LCD segment for COM2 is on
The LCD segment for COM3 is on
The LCD segment for COM4 is on
The LCD segment for COM5 is on
The LCD segment for COM6 is on
The LCD segment for COM7 is on
The LCD segment for COM8 is on
The LCD segment for COM9 is on
The LCD segment for COM10 is on
The LCD segments for COM1 to COM10 are on
No.6370-20/38
LC75808W
Serial Data Output
1. When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
DO
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X : don't care
A12909
2. When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2
A3
DO
X
KD1 KD2 KD3
KD28 KD29 KD30 SA
X
Output data
X : don't care
A12910
Note: B0 to B3, A0 to A3…….. CCB address ‘43H’
KD1 to KD30 .................. Key data
SA ................................... Sleep acknowledge data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep
acknowledge data(SA) will be invalid.
Output Data
1. KD1 to KD30: Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1
KS2
KS3
KS4
KS5
KS6
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
When the states of the KS1 to KS6 output pins during key scan standby are set to low for KS1 and KS2 and to high
for KS3 to KS6 by the KC1 to KC6 bits in the control data and a key matrix of up to 20 keys is formed from the KS3
to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0.
2. SA: Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
No.6370-21/38
LC75808W
Key Scan Operation Functions
1. Key scan timing
The key scan period is 384T(s). To reliably determine the on/off state of the keys, the LC75808W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75808W cannot detect a key press shorter than 800T(s).
KS1
KS2
KS3
KS4
KS5
KS6
*3
*3
*3
*3
*3
*3
1
1
*3
*3
*3
*3
*3
*3
2
2
3
3
1
fosc
T=
4
4
5
5
6
6
768T [s]
Key on
A12911
Note: *3. Note that the high/low states of these pins are determined by the KC1 to KC6 bits in the control data, and
that key scan output signals are not output from pins that are set to low.
2. In normal mode
• The pins KS1 to KS6 are set to high or low by the KC1 to KC6 bits in the control data.
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, a key scan is started
and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether
multiple key data bits are set.
1
• If a key is pressed for longer than 800T(s) (Where T= fOSC ) the LC75808W outputs a key data read request (a low
level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is
high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75808W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1kΩ
and 10kΩ).
Key input 1
Key input 2
Key scan
800T [s]
800T [s]
800T [s]
CE
DI
Serial data
transfer
Serial data
transfer
Serial data
transfer
Key address(43H)
Key data read
Key address
Key address
DO
Key data read
Key data read
Key data read request
Key data read request
Key data read request
1
fosc
T=
A12912
No.6370-22/38
LC75808W
3. In sleep mode
• The pins KS1 to KS6 are set to high or low by the KC1 to KC6 bits in the control data.
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
1
• If a key is pressed for longer than 800T(s)(where T=
) the LC75808W outputs a key data read request (a
f
OSC
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75808W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 kΩ and 10 kΩ).
• Sleep mode key scan example
Example: When the control data bits KC1 to KC5 are 0, KC6 is 1, and SP is 1. (sleep with only KS6 high)
[L] KS1
[L] KS2
When any one of these keys is pressed,
[L] KS3
the oscillator on the OSC pin is started
[L] KS4
and the keys are scanned.
[L] KS5
[H] KS6
*4
KI1
KI2
KI3
KI4
KI5
A12913
Note: *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state
with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak
currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
Key input
(KS6 line)
Key scan
800T [s]
800T [s]
CE
DI
Serial data
transfer
Serial data
transfer
Serial data
transfer
1
fosc
Key address(43H)
Key address
T=
DO
Key data read
Key data read
Key data read request
Key data read request
A12914
Multiple Key Presses
Although the LC75808W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No.6370-23/38
LC75808W
1/8 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM1
COM2
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM8
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
LCD driver output when all
LCD segments corresponding
to COM1 to COM8 are turned off
LCD driver output when only
LCD segments corresponding
to COM1 are turned on
LCD driver output when only
LCD segments corresponding
to COM2 are turned on
LCD driver output when all
LCD segments corresponding
to COM1 to COM8 are turned on
64T
512T
1
T=
fosc
A12915
No.6370-24/38
LC75808W
1/9 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM1
COM2
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM9
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
LCD driver output when all
LCD segments corresponding
to COM1 to COM9 are turned off
LCD driver output when only
LCD segments corresponding
to COM1 are turned on
LCD driver output when only
LCD segments corresponding
to COM2 are turned on
LCD driver output when all
LCD segments corresponding
to COM1 to COM9 are turned on
64T
576T
1
T=
fosc
A12916
No.6370-25/38
LC75808W
1/10 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM1
COM2
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM10
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
LCD driver output when all
LCD segments corresponding
to COM1 to COM10 are turned off
LCD driver output when only
LCD segments corresponding
to COM1 are turned on
LCD driver output when only
LCD segments corresponding
to COM2 are turned on
LCD driver output when all
LCD segments corresponding
to COM1 to COM10 are turned on
64T
640T
1
T=
fosc
A12917
No.6370-26/38
LC75808W
Voltage Detection Type Reset Circuit (V
This circuit generates an output signal and resets the system when logic block power is first applied and when the
)
DET
voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage
V
, which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic
DET
block power supply line so that the logic block power supply voltage V
applied and the logic block power supply voltage V
Figure 3, 4, and 5.)
rise time when the logic block power is first
DD
fall time when the voltage drops are both at least 1 ms. (See
DD
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3, 4, and 5.)
• Power on: Logic block power supply(V ) on → LCD driver block power supply(V ) on
DD LCD
• Power off: LCD driver block power supply(V ) off → Logic block power supply(V ) off
LCD DD
However, if the logic and LCD driver blocks use a shared power supply, then the power supplies can be turned on and
off at the same time.
System Reset
1. Reset Function
The LC75808W performs a system reset with the V
. When a system reset is applied, the display is turned off,
key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low
DET
level (V ). These states that are created as a result of the system reset can be cleared by executing the instruction
SS
described below. (See figure 3, 4, and 5.)
• Clearing the display off state
Transferring all the serial data (the display data and the control data) creates a state in which the display is turned on.
• Clearing the key scan disabled and key data reset states
Transferring the control data not only creates a state in which key scanning can be performed, but also clears the key
data reset.
• Clearing the general-purpose output ports locked at the low level (V ) state
SS
Transferring the control data clears the general-purpose output ports locked at the low level (V ) state and sets the
SS
states of the general-purpose output ports.
• 1/8 duty
t1 t2
V
t3 t4
DET
V
V
DD
V
DET
LCD
V
CE
KC1 to KC6, PC1 to PC4,
IL
Internal data CT0 to CT3, CTC,
SC, SP, DT1, DT2
Undefined
Defined
Defined
Defined
Defined
Defined
Undefined
Internal data (D1 to D120)
Internal data (D121 to D240)
Internal data (D241 to D360)
Internal data (D361 to D480)
Key scan
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Disabled
Execution enabled
Can be set to either the high (V ) or low (V ) level.
Fixed at the low level (V
)
General-purpose output ports
Display state
DD
SS
SS
Display off
Display on
• t1 ≥ 1 [ms] (Logic block power supply voltage V
• t2 ≥ 0
• t3 ≥ 0
rise time)
DD
DD
• t4 ≥ 1 [ms] (Logic block power supply voltage V
fall time)
A12918
Figure 3
No.6370-27/38
LC75808W
• 1/9 duty
t1 t2
V
t3 t4
DET
V
V
DD
V
DET
LCD
V
CE
KC1 to KC6, PC1 to PC4,
IL
Internal data CT0 to CT3, CTC,
SC, SP, DT1, DT2
Undefined
Undefined
Defined
Defined
Defined
Defined
Defined
Undefined
Internal data (D1 to D135)
Internal data (D136 to D270)
Internal data (D271 to D405)
Internal data (D406 to D540)
Key scan
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Disabled
Execution enabled
Can be set to either the high (V ) or low (V ) level.
Fixed at the low level (V
)
General-purpose output ports
Display state
DD
SS
SS
Display off
Display on
• t1 ≥ 1 [ms] (Logic block power supply voltage V
• t2 ≥ 0
• t3 ≥ 0
rise time)
DD
DD
• t4 ≥ 1 [ms] (Logic block power supply voltage V
fall time)
A12919
Figure 4
• 1/10 duty
t1 t2
t3 t4
V
DD
V
V
DET
DET
V
LCD
V
CE
IL
KC1 to KC6, PC1 to PC4,
Undefined
Undefined
Undefined
Undefined
Undefined
Disabled
Defined
Undefined
Undefined
Undefined
Undefined
Undefined
Internal data CT0 to CT3, CTC,
SC, SP, DT1, DT2
Internal data (D1 to D150)
Internal data (D151 to D300)
Internal data (D301 to D450)
Internal data (D451 to D600)
Key scan
Defined
Defined
Defined
Defined
Execution enabled
Can be set to either the high (V ) or low (V ) level.
Fixed at the low level (V
)
General-purpose output ports
Display state
DD
SS
SS
Display off
Display on
• t1 ≥ 1 [ms] (Logic block power supply voltage V
• t2 ≥ 0
• t3 ≥ 0
rise time)
DD
DD
• t4 ≥ 1 [ms] (Logic block power supply voltage V
fall time)
A12920
Figure 5
No.6370-28/38
LC75808W
2. LC75808W internal block states during the system reset
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the SP control data bit is transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• CONTRAST ADJUSTER
Reset is applied and operation of the display contrast adjustment circuit is disabled. After that, once CT0 to CT3
and CTC in the control data have been transferred to the IC it will then be possible to set the display contrast.
• KEY SCAN, KEY BUFFER
Reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the key
data is all set to 0. After that, once KC1 to KC6 in the control data have been transferred to the IC it will then be
possible to perform key scan operations.
• GENERAL PORT
Reset is applied and the states of the general-purpose output ports are held fixed at the low level (V ).
SS
• CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER
Since serial data transfer is possible, these circuits are not reset.
GENERAL
PORT
COMMON
DRIVER
SEGMENT DRIVER & LATCH
V
LCD
0
CONTROL
REGISTER
CONTRAST
ADJUSTER
V
LCD
LCD
LCD
LCD
V
V
V
V
1
2
3
4
SHIFT REGISTER
CCB INTERFACE
KEY BUFFER
LCD
V
CLOCK
DD
GENERATOR
V
DET
KEY SCAN
V
SS
TEST
Blocks that are reset
A12921
3. Output pin states during the system reset
Output pin
State during reset
S1 to S60
COM1 to COM10
KS1 to KS6
P1 to P4
L(V
L(V
4)
4)
LCD
LCD
L(V
)
SS
SS
L(V
)
DO
H *5
Note: *5. Since this output pin is an open-drain output, a pull-up resistor of between 1kΩ and 10 kΩ is required.
This pin is held at the high level even if a key data read operation is performed before the KC1 to KC6
control data has been transferred to the IC.
No.6370-29/38
LC75808W
Sample Application Circuit 1
1/8 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
+5V
+8V
V
DD
COM1
*6
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
V
SS
V
LCD
OPEN
V
0
1
2
3
LCD
V
LCD
COM9
COM10
OPEN
OPEN
V
LCD
V
LCD
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
C
C
C
V
4 *7
LCD
C≥0.047μF
OSC
S56
S57
S58
S59
S60
INH *8
CE
CL
DI
From the controller
To the controller
general-purpose output ports
P1
P2
P3
P4
DO
Used with the backlight
controller or other circuit.
K K K K K K K K K K K
I
I
I
I
I
S S S S S S
6 5 4 3 2 1
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
A12922
Note: *6. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise
fall time when power drops are
DD
time when power is applied and the logic block power supply voltage V
DD
both at least 1ms, as the LC75808W is reset by the V
.
DET
*7. If a variable resistor is not used for display contrast fine adjustment, the V
4 pin must be connected to
LCD
ground.
*8. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply
V
.
DD
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ to
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.6370-30/38
LC75808W
Sample Application Circuit 2
1/8 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
+5V
+8V
V
DD
COM1
*6
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
V
SS
V
V
LCD
LCD
0
R
R
R
R
V
V
V
V
1
LCD
LCD
LCD
LCD
COM9
COM10
OPEN
OPEN
2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
3
C
C
C
4 *7
OSC
C≥0.047μF
10kΩ≥R≥2.2kΩ
S56
S57
S58
S59
S60
INH *8
CE
From the controller
To the controller
CL
P1
P2
P3
P4
general-purpose output ports
DI
DO
K K K K K K K K K K K
Used with the backlight
controller or other circuit.
I
I
I
I
I
S S S S S S
6 5 4 3 2 1
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
A12923
Note: *6. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise
fall time when power drops are
DD
time when power is applied and the logic block power supply voltage V
DD
both at least 1ms, as the LC75808W is reset by the V
.
DET
*7. If a variable resistor is not used for display contrast fine adjustment, the V
4 pin must be connected to
LCD
ground.
*8. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply
V
.
DD
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ to
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.6370-31/38
LC75808W
Sample Application Circuit 3
1/9 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
+5V
V
DD
COM1
*6
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
V
SS
+8V
V
V
V
V
V
LCD
LCD
LCD
LCD
LCD
OPEN
0
1
2
3
COM10
OPEN
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
C
C
C
V
4 *7
LCD
C≥0.047μF
OSC
S56
S57
S58
S59
S60
INH *8
CE
From the controller
To the controller
CL
general-purpose output ports
P1
P2
P3
P4
DI
DO
K K K K K K K K K K K
Used with the backlight
controller or other circuit.
I
I
I
I
I
S S S S S S
6 5 4 3 2 1
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
A12924
Note: *6. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise
fall time when power drops are
DD
time when power is applied and the logic block power supply voltage V
DD
both at least 1ms, as the LC75808W is reset by the V
.
DET
*7. If a variable resistor is not used for display contrast fine adjustment, the V
4 pin must be connected to
LCD
ground.
*8. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply
V
.
DD
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ to
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.6370-32/38
LC75808W
Sample Application Circuit 4
1/9 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
+5V
+8V
V
DD
COM1
*6
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
V
SS
V
LCD
V
0
LCD
R
R
R
R
V
1
LCD
COM10
OPEN
V
2
LCD
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
V
3
LCD
C
C
C
V
4 *7
LCD
OSC
C≥0.047μF
10kΩ≥R≥2.2kΩ
S56
S57
S58
S59
S60
INH *8
CE
From the controller
To the controller
CL
P1
P2
P3
P4
general-purpose output ports
DI
DO
K K K K K K K K K K K
Used with the backlight
controller or other circuit.
I
I
I
I
I
S S S S S S
6 5 4 3 2 1
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
A12925
Note: *6. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise
fall time when power drops are
DD
time when power is applied and the logic block power supply voltage V
DD
both at least 1ms, as the LC75808W is reset by the V
.
DET
*7. If a variable resistor is not used for display contrast fine adjustment, the V
4 pin must be connected to
LCD
ground.
*8. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply
V
.
DD
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ to
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.6370-33/38
LC75808W
Sample Application Circuit 5
1/10 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
+5V
+8V
V
DD
COM1
*6
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
V
SS
V
LCD
OPEN
V
0
1
2
3
LCD
V
LCD
V
LCD
V
LCD
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
C
C
C
V
4 *7
LCD
C≥0.047μF
OSC
S56
S57
S58
S59
S60
INH *8
CE
From the controller
To the controller
CL
P1
P2
P3
P4
general-purpose output ports
DI
DO
K K K K K K K K K K K
Used with the backlight
controller or other circuit.
I
I
I
I
I
S S S S S S
6 5 4 3 2 1
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
A12926
Note: *6. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise
fall time when power drops are
DD
time when power is applied and the logic block power supply voltage V
DD
both at least 1ms, as the LC75808W is reset by the V
.
DET
*7. If a variable resistor is not used for display contrast fine adjustment, the V
4 pin must be connected to
LCD
ground.
*8. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply
V
.
DD
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ to
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.6370-34/38
LC75808W
Sample Application Circuit 6
1/10 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
+5V
+8V
V
DD
COM1
*6
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
V
DD
V
LCD
V
0
LCD
R
R
R
R
V
1
LCD
V
2
LCD
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
V
3
LCD
C
C
C
V
4 *7
LCD
OSC
C≥0.047μF
10kΩ≥R≥2.2kΩ
S56
S57
S58
S59
S60
INH *8
CE
From the controller
To the controller
CL
P1
P2
P3
P4
general-purpose output ports
DI
DO
K K K K K K K K K K K
Used with the backlight
controller or other circuit.
I
I
I
I
I
S S S S S S
6 5 4 3 2 1
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
A12927
Note: *6. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise
fall time when power drops are
DD
time when power is applied and the logic block power supply voltage V
DD
both at least 1ms, as the LC75808W is reset by the V
.
DET
*7. If a variable resistor is not used for display contrast fine adjustment, the V
4 pin must be connected to
LCD
ground.
*8. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply
V
.
DD
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ to
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
Notes on Transferring Display Data from the Controller
The display data is transferred to the LC75808W in four operations. All of the display data should be transferred within
30ms to maintain the quality of the displayed image.
No.6370-35/38
LC75808W
Notes on the Controller Key Data Read Techniques
1. Timer based key data acquisition
• Flowchart
CE=[L]
NO
DO=[L]
YES
Key data
read processing
A12928
• Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
DI
t8
Key
address
t8
t8
t7
t7
t7
Key data read
DO
Key data read request
t9
t9
t9
t9
Controller
detemination
(Key on)
Controller
detemination
(Key on)
Controller
detemination
(Key off)
Controller
detemination
(Key on)
Controller
detemination
(Key off)
A12929
t5: Key scan execution time when the key data agreed for two key scans. (800T(s))
t6: Key scan execution time when the key data did not agree for two key scans and
the key scan was executed again. (1600T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
OSC
T=
f
• Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9 > t6 + t7 + t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No.6370-36/38
LC75808W
2. Interrupt based key data acquisition
• Flowchart
CE=[L]
DO=[L]
NO
YES
Key data
read processing
Wait for at least t10
CE=[L]
NO
DO=[H]
YES
Key OFF
A12930
• Timing chart
Key on
Key on
Key input
Key scan
CE
t5
t5
t6
t5
t8
t8
t8
t8
Key
address
DI
t7
t7
t7
t7
Key data read
DO
Key data read request
t10
t10
t10
t10
Controller
detemination
(Key on)
Controller
detemination detemination
(Key off) (Key on)
Controller
Controller
detemination
(Key on)
Controller
detemination
(Key on)
Controller
detemination
(Key off)
A12931
t5: Key scan execution time when the key data agreed for two key scans. (800T(S))
t6: Key scan execution time when the key data did not agree for two key scans and
the key scan was executed again. (1600T(S))
t7: Key address (43H) transfer time
t8: Key data read time
1
OSC
T=
f
• Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10 has
elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must
satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No.6370-37/38
LC75808W
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
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In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
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No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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This catalog provides information as of October, 2010. Specifications and information herein are subject
to change without notice.
PS No.6370-38/38
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