S524AB0X91 [SAMSUNG]
32K/64K-bit Serial EEPROM for Low Power; 32K / 64K位串行EEPROM用于低功耗
| 型号： | S524AB0X91 |
| 厂家： | 
SAMSUNG |
| 描述： | 32K/64K-bit Serial EEPROM for Low Power |
| 文件： | 总16页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S524AB0X91/B0XB1
32K/64K-bit
Serial EEPROM
for Low Power
Data Sheet
OVERVIEW
The S524AB0X91/B0XB1 serial EEPROM has a 32K/64K-bit (4,096/8,192 bytes) capacity, supporting the
standard I2C™-bus serial interface. It is fabricated using Samsungs’ most advanced CMOS technology. It has
been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 32 bytes of data into
the EEPROM in a single write operation. Another significant feature of the S524AB0X91/B0XB1 is its support for
fast mode and standard mode.
FEATURES
I2C-Bus Interface
Operating Characteristics
·
·
Two-wire serial interface
·
Operating voltage
— 1.8 V to 5.5 V
Automatic word address increment
EEPROM
·
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 400 mA at 5.5 V
— Maximum stand-by current: < 1 mA at 5.5 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
·
·
·
32K/64K-bit (4,096/8,192 bytes) storage area
32-byte page buffer
Typical 3 ms write cycle time with
auto-erase function
·
·
·
·
·
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
·
·
1,000,000 erase/write cycles
100 years data retention
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
·
6-1
S524AB0X91/B0XB1 SERIAL EEPROM
DATA SHEET
SDA
WP
Start/Stop
Logic
HV Generation
Timing Control
Control Logic
EEPROM
Cell Array
4,096 x 8 bits
8,192 x 8 bits
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
A0
A1
A2
Column Decoder
Data Register
DOUT and ACK
Figure 6-1. S524AB0X91/B0XB1 Block Diagram
6-2
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
VCC WP SCL SDA
S524AB0X91/B0XB1
A0
A1
A2
VSS
NOTE:
The S524AB0X91/B0XB1 is available in
8-pin DIP, SOP, and TSSOP package.
Figure 6-2. Pin Assignment Diagram
Table 6-1. S524AB0X91/B0XB1 Pin Descriptions
Description
Name
Type
Circuit
Type
A0, A1, A2
Input
Input pins for device address selection. To configure a device address,
these pins should be connected to the VCC or VSS of the device.
1
These pins are internally pulled down to VSS
.
VSS
–
Ground pin.
–
3
SDA
I/O
Bi-directional data pin for the I2C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to VDD.
SCL
WP
Input
Input
Schmitt trigger input pin for serial clock input.
2
1
Input pin for hardware write protection control. If you tie this pin to VCC,
the write function is disabled to protect previously written data in the
entire memory; if you tie it to VSS, the write function is enabled.
This pin is internally pulled down to VSS
.
VCC
–
Single power supply.
–
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
6-3
S524AB0X91/B0XB1 SERIAL EEPROM
DATA SHEET
A0, A1,
A2, WP
Noise
Filter
SCL
Figure 6-4. Pin Circuit Type 2
Figure 6-3. Pin Circuit Type 1
SDA
Data Out
Data In
VSS
Noise
Filter
Figure 6-5. Pin Circuit Type 3
6-4
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524AB0X91/B0XB1 supports the I2C-bus serial interface data transmission protocol. The two-wire bus
consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected
to VCC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device whic h generates the serial clock and start/stop conditions,
controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524AB0X91/B0XB1 devices can be
connected to the same I2C-bus as slaves (see Figure 6-6). Both the master and slaves can operate as a
transmitter or a receiver, but the master device determines which bus operating mode would be active.
CC
V
CC
V
R
R
SDA
SCL
Slave 1
S524AB0X91/
Slave 2
S524AB0X91/
Slave 3
S524AB0X91/
Slave 8
S524AB0X91/
Bus Master
(Transmitter/
Receiver)
B0XB1
Tx/Rx
A0 A1 A2
B0XB1
Tx/Rx
A0 A1 A2
B0XB1
Tx/Rx
A0 A1 A2
B0XB1
Tx/Rx
A0 A1 A2
MCU
CC
SS
CC
SS
CC
SS
CC
SS
To V or V
To V or V
To V or V
To V or V
Figure 6-6. Typical Configuration
6-5
S524AB0X91/B0XB1 SERIAL EEPROM
DATA SHEET
I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.
— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High.
The I2C-bus interface supports the following communication protocols:
·
·
Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active.
Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in
High level. All bus commands must be preceded by a start condition.
·
Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in
High level. All bus operations must be completed by a stop condition (see Figure 6-7).
SCL
SDA
Start
Data or
Data
Stop
Condition
ACK Valid Change
Condition
Figure 6-7. Data Transmission Sequence
·
·
Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total
number of bytes that can be transferred in one operation is theoretically unlimited.
ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master
generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits
of data (see Figure 6-8). But the slave does not send an ACK if an internal write cycle is still in progress.
In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors
the line for an ACK signal during the 9th clock period. If an ACK is detected but no stop condition, the slave
will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for
a stop condition to be issued by the master before returning to its stand-by mode.
6-6
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
Master
SCL Line
Bit 1
Bit 9
Data from
Transmitter
ACK from
Receiver
ACK
Figure 6-8. Acknowledge Response From Receiver
·
·
Slave Address: After the master initiates a start condition, it must output the address of the device to be
accessed. The most significant four bits of the slave address are called the “device identifier.” The identifier
for the S524AB0X91/B0XB1 is “1010B”. The next three bits comprise the address of a specific device. The
device address is defined by the state of the A0, A1, and A2 pins. Using this addressing scheme, you can
cascade up to eight S524AB0X91/B0XB1s on the bus (see Figure 6-9 below).
Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the
R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.
Device Identifier
Device Select
A2 A1 A0 R/W
Slave
Address
1
X
0
1
0
First (High) Address
First Word
Address
X
X(2) A12(1) A11 A10
A9
A1
A8
A0
Second (Low) Address
Second Word
Address
A7
A6
A5
A4
A3
A2
NOTES:
1. The A12 is "don't care" for the S524AB0X91.
2. X = Don't care.
Figure 6-9. Device Address
6-7
S524AB0X91/B0XB1 SERIAL EEPROM
BYTE WRITE OPERATION
DATA SHEET
A write operation requires 2-byte word addresses, the first (high) word address and the second (low) word
address. In a byte write operation, the master transmits the slave address, the first word address, the second
word address, and one data byte to the S524AB0X91/B0XB1 slave device (see Figure 6-10).
Data
Stop
Start Slave Address
First Word Address
Second t Word Address
A
C
K
A
C
K
A
C
K
A
C
K
Figure 6-10. Byte Write Operation
Following a start condition, the master puts the device identifier (4 bits), the device address (3 bits), and an R/W
bit set to “0” onto the bus. Upon the receipt of the slave address, the S524AB0X91/B0XB1 responds with an ACK.
And the master transmits the first word address, the second word address, and one byte data to be written into
the addressed memory location.
The master terminates the transfer by generating a stop condition, at which time the S524AB0X91/B0XB1 begins
the internal write cycle. While the internal write cycle is in progress, all S524AB0X91/B0XB1 inputs are disabled
and the S524AB0X91/B0XB1 does not respond to any additional request from the master.
6-8
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
PAGE WRITE OPERATION
The S524AB0X91/B0XB1 can also perform 32-byte page write operation. A page write operation is initiated in the
same way as a byte write operation. However, instead of finishing the write operation after the first data byte is
transferred, the master can transmit up to 31 additional bytes. The S524AB0X91/B0XB1 responds with an ACK
each time it receives a complete byte of data (see Figure 6-11).
Data Byte N
(N
£ 31)
Start Slave Address
First Word Address
Second Word Address
Data Byte 0
Stop
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 6-11. Page Write Operation
The S524AB0X91/B0XB1 automatically increments the word address pointer each time it receives a complete
data byte. When one byte is received, the internal word address pointer increments to the next address so that
the next data byte can be received.
If the master transmits more than 32 bytes before it generates a stop condition to end the page write operation,
the S524AB0X91/B0XB1 word address pointer value “rolls over” and the previously received data is overwritten.
If the master transmits less than 32 bytes and generates a stop condition, the S524AB0X91/B0XB1 writes the
received data to the corresponding EEPROM address.
During a page write operation, all inputs are disabled and there would be no response to additional requests from
the master until the internal write cycle is completed.
6-9
S524AB0X91/B0XB1 SERIAL EEPROM
POLLING FOR AN ACK SIGNAL
DATA SHEET
When the master issues a stop condition to initiate a write cycle, the S524AB0X91/B0XB1 starts an internal write
cycle. The master can then immediately begin polling for an ACK from the slave device to determine whether the
write cycle is completed.
To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address.
As long as the S524AB0X91/B0XB1 remains busy with the write operation, no ACK is returned. When the
S524AB0X91/B0XB1 completes the write operation, it returns an ACK and the master can then proceed with the
next read or write operation (see Figure 6-12).
Send Write
Command
Send Stop Condition to
Initiate Write Cycle
Send Start
Condition
Send Slave Address
with R/
W bit = "0"
No
ACK = "0" ?
Yes
Start Next
Operation
Figure 6-12. Master Polling for an ACK Signal from a Slave Device
6-10
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the S524AB0X91/B0XB1. This write protection is controlled
by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to it is ignored. The S524AB0X91/B0XB1 will
acknowledge slave and word addresses, but it will not generate an acknowledge after receiving the first byte of
data. In this situation, the write cycle will not be started when a stop condition is generated. By connecting the
WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to protect data from being
overwritten. Whenever the write function is disabled, a slave address and word addresses are acknowledged on
the bus, but data bytes are not acknowledged.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would be to
access data at address “n+1”.
When the S524AB0X91/B0XB1 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends
the eight bits of data. In a current address byte read operation, the master does not acknowledge the data, and it
generates a stop condition, forcing the S524AB0X91/B0XB1 to stop the transmission (see Figure 6-13).
Start Slave Address
Data
Stop
A
C
K
N
O
A
C
K
Figure 6-13. Current Address Byte Read Operation
6-11
S524AB0X91/B0XB1 SERIAL EEPROM
DATA SHEET
RANDOM ADDRESS BYTE READ OPERATION
Using random read operations, the master can access any memory location at any time. Before it issues the
slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. This operation
is performed in the following steps:
1. The master first issues a start condition, the slave address, and the word address (the first and the second
addresses) to be read. (This step sets the internal word address pointer of the S524AB0X91/B0XB1 to the
desired address.)
2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed
by another slave address, with the R/W bit set to “1”.
3. The S524AB0X91/B0XB1 then sends an ACK and the 8-bit data stored at the pointed address.
4. At this point, the master does not acknowledge the transmission, generating a stop condition.
5. The S524AB0X91/B0XB1 stops transmitting data and reverts to stand-by mode (see Figure 6-14).
Start Slave Address
First Word Address
Second Word Address Start Slave Address
Data
Stop
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 6-14. Random Address Byte Read Operation
6-12
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
SEQUENTIAL READ OPERATION
Sequential read operations can be performed in two ways: current address sequential read operation, and
random address sequential read operation. The first data is sent in either of the two ways, current address byte
read operation or random address byte read operation described earlier. If the master responds with an ACK, the
S524AB0X91/B0XB1 continues transmitting data. If the master does not issue an ACK, generating a stop
condition, the slave stops transmission, ending the sequential read operation.
Using this method, data is output sequentially from address “n” followed by address “n+1”. The word address
pointer for read operations increments to all word addresses, allowing the entire EEPROM to be read sequentially
in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the
S524AB0X91/B0XB1 continues to transmit data for each ACK it receives from the master (see Figure 6-15).
Start Slave Address
Data (n)
Data (n + x)
Stop
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 6-15. Sequential Read Operation
6-13
S524AB0X91/B0XB1 SERIAL EEPROM
DATA SHEET
ELECTRICAL DATA
Table 6-2. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Unit
VCC
VIN
–
– 0.3 to + 7.0
V
Supply voltage
–
–
– 0.3 to + 7.0
– 0.3 to + 7.0
– 40 to + 85
– 65 to + 150
5000
V
V
Input voltage
VO
Output voltage
°
C
TA
–
Operating temperature
Storage temperature
Electrostatic discharge
°
C
TSTG
VESD
–
HBM
MM
V
500
Table 6-3. D.C. Electrical Characteristics
°
°
°
°
(TA = – 25 C to + 70 C (Commercial), – 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V)
Parameter
Input low voltage
Symbol
Conditions
Min
–
Typ
Max
Unit
VIL
0.3 VCC
–
V
V
SCL, SDA, A0, A1, A2
VIH
ILI
0.7 VCC
–
–
–
–
–
–
–
–
–
–
10
10
0.4
3
Input high voltage
Input leakage current
–
–
–
–
–
–
–
–
VIN = 0 to VCC
µA
µA
V
ILO
VO = 0 to VCC
Output leakage current
Output Low voltage
VOL
ICC1
ICC2
ICC3
ICC4
ICC5
IOL = 3 mA, VCC = 2.0 V
VCC = 5.5 V, 400 kHz
VCC = 1.8 V, 100 kHz
VCC = 5.5 V, 400 kHz
VCC = 1.8 V, 100 kHz
mA
Supply current
Write
1
0.4
60
1
Read
µA
µA
VCC = SDA = SCL = 5.5 V,
all other inputs = 0 V
Stand-by current
ICC6
–
–
1
VCC = SDA = SCL = 1.8 V,
all other inputs = 0 V
6-14
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
Table 6-3. D.C. Electrical Characteristics (Continued)
°
°
°
°
(TA = – 25 C to + 70 C (Commercial), – 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CIN
–
–
10
pF
°
Input capacitance
25 C, 1MHz,
VCC = 5 V, VIN = 0 V,
A0, A1, A2, SCL and WP pin
CI/O
–
–
10
°
Input/Output capacitance
25 C, 1MHz,
VCC = 5 V, VI/O = 0 V,
SDA pin
Table 6-4. A.C. Electrical Characteristics
°
°
°
°
(TA = – 25 C to + 70 C (Commercial), – 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V)
Parameter
Symbol Conditions
VCC = 1.8 to 5.5 V
(Standard Mode)
VCC = 2.5 to 5.5 V
(Fast Mode)
Unit
Min
Max
Min
Max
100 (1)
400 (1)
Fclk
tHIGH
tLOW
External clock frequency
Clock High time
–
0
0
kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
–
4
4.7
–
–
–
0.6
1.3
–
–
–
Clock Low time
–
tR
Rising time
SDA, SCL
1
0.3
0.3
–
tF
Falling time
SDA, SCL
–
0.3
–
–
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Bus free time
–
–
–
–
–
4
0.6
0.6
0
4.7
0
–
–
–
–
0.25
4
–
0.1
0.6
1.3
–
–
–
Before new
4.7
–
–
transmission
tAA
Data output valid from
clock low (2)
–
0.3
3.5
–
0.9
ms
tSP
Noise spike width
Write cycle time
–
–
–
–
100
5
–
–
50
5
ns
tWR
ms
NOTES:
1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available.
2. When acting as a transmitter, the S524AB0X91/B0XB1 must provide an internal minimum delay time to bridge the
undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a
start or stop condition.
6-15
S524AB0X91/B0XB1 SERIAL EEPROM
DATA SHEET
tF
tHIGH
tR
tLOW
SCL
tSU:STO
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SDA In
tAA
tBUF
SDA Out
Figure 6-16. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
ACK
WORDn
tWR
Stop
Condition
Start
Condition
Figure 6-17. Write Cycle Timing Diagram
6-16
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