S3C825A [SAMSUNG]
8-BIT CMOS MICROCONTROLLERS; 8位CMOS微控制器
| 型号： | S3C825A |
| 厂家： | 
SAMSUNG |
| 描述： | 8-BIT CMOS MICROCONTROLLERS |
| 文件： | 总346页 (文件大小：1750K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C825A/P825A
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1
Important Notice
The information in this publication has been
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
carefully checked and is believed to be entirely
accurate at the time of publication. Samsung
assumes no responsibility, however, for possible
errors or omissions, or for any consequences
resulting from the use of the information contained
herein.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
personal injury or death may occur.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all
claims, costs, damages, expenses, and reasonable
attorney fees arising out of, either directly or
indirectly, any claim of personal injury or death that
may be associated with such unintended or
unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or
manufacture of said product.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.
S3C825A/P825A 8-Bit CMOS Microcontrollers
User's Manual, Revision 1
Publication Number: 21-S3-C825A/P825A-032002
© 2002 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are designed
and manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 440-900
TEL: (82)-(31)-209-1934
FAX: (82)-(31)-209-1899
Home Page: http://www.samsungsemi.com
Printed in the Republic of Korea
Preface
The S3C825A/P825A Microcontroller User's Manual is designed for application designers and programmers who
are using the S3C825A/P825A microcontroller for application development. It is organized in two main parts:
Part I Programming Model
Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture,
programming model, instruction set, and interrupt structure. It has six chapters:
Chapter 1
Chapter 2
Chapter 3
Product Overview
Address Spaces
Addressing Modes
Chapter 4
Chapter 5
Chapter 6
Control Registers
Interrupt Structure
Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to S3C825A/P825A with general product descriptions,
as well as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack
operations.
Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
S3C8-series CPU.
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.
Chapter 5, "Interrupt Structure," describes the S3C825A/P825A interrupt structure in detail and further prepares
you for additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of
each instruction are presented in a standard format. Each instruction description includes one or more practical
examples of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed
information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.
Part II "hardware Descriptions," has detailed information about specific hardware components of the
S3C825A/P825A microcontroller. Also included in Part II are electrical, mechanical, OTP, and development tools
data. It has 15 chapters:
Chapter 7
Clock Circuit
Chapter 15
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
LCD Controller/Driver
10-bit Analog-to-Digital Converter
Serial I/O Interface
UART
Electrical Data
Mechanical Data
S3P825A OTP
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
RESET and Power-Down
I/O Ports
Basic Timer and Timer 0
Timer 1
8-bit Timer 2
16-bit Timer 3
Watch Timer
Development Tools
Two order forms are included at the back of this manual to facilitate customer order for S3C825A/P825A
microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these
forms, fill them out, and then forward them to your local Samsung Sales Representative.
S3C825A/P825A MICROCONTROLLER
iii
Table of Contents
Part I — Programming Model
Chapter 1
Product Overview
S3C8-Series Microcontrollers...................................................................................................................1-1
S3C825A Microcontroller.........................................................................................................................1-1
OTP.........................................................................................................................................................1-1
Features ..................................................................................................................................................1-2
Block Diagram.........................................................................................................................................1-3
Pin Assignment........................................................................................................................................1-4
Pin Descriptions.......................................................................................................................................1-6
Pin Circuits..............................................................................................................................................1-8
Chapter 2
Address Spaces
Overview.................................................................................................................................................2-1
Program Memory (ROM) .........................................................................................................................2-2
Register Architecture ...............................................................................................................................2-3
Register Page Pointer (PP)..................................................................................................................2-5
Register Set 1......................................................................................................................................2-6
Register Set 2......................................................................................................................................2-6
Prime Register Space..........................................................................................................................2-7
Working Registers...............................................................................................................................2-8
Using the Register Points ....................................................................................................................2-9
Register Addressing.................................................................................................................................2-11
Common Working Register Area (C0H–CFH)......................................................................................2-13
4-Bit Working Register Addressing ......................................................................................................2-14
8-Bit Working Register Addressing ......................................................................................................2-16
System and User Stack ...........................................................................................................................2-18
Chapter 3
Addressing Modes
Overview.................................................................................................................................................3-1
Register Addressing Mode (R) .................................................................................................................3-2
Indirect Register Addressing Mode (IR)....................................................................................................3-3
Indexed Addressing Mode (X)..................................................................................................................3-7
Direct Address Mode (DA) .......................................................................................................................3-10
Indirect Address Mode (IA) ......................................................................................................................3-12
Relative Address Mode (RA)....................................................................................................................3-13
Immediate Mode (IM) ..............................................................................................................................3-14
S3C825A/P825A MICROCONTROLLER
v
Table of Contents (Continued)
Chapter 4
Control Registers
Overview ................................................................................................................................................ 4-1
Chapter 5
Interrupt Structure
Overview ................................................................................................................................................ 5-1
Interrupt Types ............................................................................................................................... 5-2
S3C825A Interrupt Structure........................................................................................................... 5-3
Interrupt Vector Addresses ............................................................................................................. 5-5
Enable/Disable Interrupt Instructions (EI, DI) .................................................................................. 5-7
System-Level Interrupt Control Registers........................................................................................ 5-7
Interrupt Processing Control Points................................................................................................. 5-8
Peripheral Interrupt Control Registers............................................................................................. 5-9
System Mode Register (SYM)......................................................................................................... 5-10
Interrupt Mask Register (IMR)......................................................................................................... 5-11
Interrupt Priority Register (IPR)....................................................................................................... 5-12
Interrupt Request Register (IRQ) .................................................................................................... 5-14
Interrupt Pending Function Types................................................................................................... 5-15
Interrupt Source Polling Sequence.................................................................................................. 5-16
Interrupt Service Routines .............................................................................................................. 5-16
Generating Interrupt Vector Addresses ........................................................................................... 5-17
Nesting of Vectored Interrupts ........................................................................................................ 5-17
Instruction Pointer (IP).................................................................................................................... 5-17
Fast Interrupt Processing................................................................................................................ 5-17
Chapter 6
Instruction Set
Overview ................................................................................................................................................ 6-1
Data Types..................................................................................................................................... 6-1
Register Addressing........................................................................................................................ 6-1
Addressing Modes.......................................................................................................................... 6-1
Flags Register (Flags) .................................................................................................................... 6-6
Flag Descriptions............................................................................................................................ 6-7
Instruction Set Notation .................................................................................................................. 6-8
Condition Codes............................................................................................................................. 6-12
Instruction Descriptions................................................................................................................... 6-13
vi
S3C825A/P825A MICROCONTROLLER
Table of Contents (Continued)
Part II Hardware Descriptions
Chapter 7
Clock Circuit
Overview.................................................................................................................................................7-1
System Clock Circuit .......................................................................................................................7-1
Main Oscillator Circuits....................................................................................................................7-2
Sub Oscillator Circuits.....................................................................................................................7-2
Clock Status During Power-Down Modes.........................................................................................7-3
System Clock Control Register (CLKCON) ......................................................................................7-4
Oscillator Control Register (OSCCON)............................................................................................7-5
Switching the CPU Clock.................................................................................................................7-6
Chapter 8
RESET and Power-Down
System Reset ..........................................................................................................................................8-1
Overview.........................................................................................................................................8-1
Normal Mode Reset Operation ........................................................................................................8-1
Hardware Reset Values...................................................................................................................8-2
Power-Down Modes.................................................................................................................................8-5
Stop Mode.......................................................................................................................................8-5
Idle Mode ........................................................................................................................................8-6
Chapter 9
I/O Ports
Overview.................................................................................................................................................9-1
Port Data Registers .........................................................................................................................9-3
Port 0, 1 ..........................................................................................................................................9-4
Port 2 ..............................................................................................................................................9-5
Port 3 ..............................................................................................................................................9-8
Port 4 ..............................................................................................................................................9-10
Port 5 ..............................................................................................................................................9-13
Port 6, 7, 8 ......................................................................................................................................9-15
Chapter 10
Basic Timer and Timer 0
Overview.................................................................................................................................................10-1
Basic Timer (BT) .....................................................................................................................................10-1
Basic Timer Control Register (BTCON) ...........................................................................................10-2
Basic Timer Function Description....................................................................................................10-3
8-Bit Timer/Counter 0 ..............................................................................................................................10-5
Timer/Counter 0 Control Register (T0CON).....................................................................................10-5
Timer 0 Function Description...........................................................................................................10-8
S3C825A/P825A MICROCONTROLLER
vii
Table of Contents (Continued)
Chapter 11
Timer 1
One 16-Bit Timer Mode (Timer 1) ........................................................................................................... 11-1
Overview........................................................................................................................................ 11-1
Function Description....................................................................................................................... 11-1
Block Diagram................................................................................................................................ 11-3
Two 8-Bit Timers Mode (Timer A and B)................................................................................................. 11-4
Overview........................................................................................................................................ 11-4
Function Description....................................................................................................................... 11-4
Chapter 12
8-bit Timer 2
Overview ................................................................................................................................................ 12-1
Function Description....................................................................................................................... 12-1
Timer 2 Control Register (T2CON) ................................................................................................. 12-2
Block Diagram................................................................................................................................ 12-3
Chapter 13
16-bit Timer 3
Overview ................................................................................................................................................ 13-1
Timer/Counter 3 Control Register (T3CON) ............................................................................................ 13-1
Timer 3 Function Description .................................................................................................................. 13-4
Chapter 14
Watch Timer
Overview ................................................................................................................................................ 14-1
Watch Timer Control Register (WTCON)........................................................................................ 14-2
Watch Timer Circuit Diagram ......................................................................................................... 14-3
Chapter 15
LCD Controller/Driver
Overview ................................................................................................................................................ 15-1
LCD Circuit Diagram....................................................................................................................... 15-2
LCD Ram Address Area ................................................................................................................. 15-3
LCD Control Register (LCON)......................................................................................................... 15-4
LCD Mode Control Register (LMOD), F3H at Bank 0 of Set 1......................................................... 15-5
LCD Voltage Dividing Resistors...................................................................................................... 15-6
viii
S3C825A/P825A MICROCONTROLLER
Table of Contents (Continued)
Chapter 16
10-bit Analog-to-Digital Converter
Overview.................................................................................................................................................16-1
Function Description................................................................................................................................16-1
Conversion Timing ..........................................................................................................................16-2
A/D Converter Control Register (ADCON) .......................................................................................16-2
Internal Reference Voltage Levels...................................................................................................16-3
Block Diagram.........................................................................................................................................16-3
Chapter 17
Serial I/O Interface
Overview.................................................................................................................................................17-1
Programming Procedure......................................................................................................................17-1
SIO Control Registers (SIOCON).........................................................................................................17-2
SIO Pre-Scaler Register (SIOPS)........................................................................................................17-3
SIO Block Diagram..................................................................................................................................17-3
Serial I/O Timing Diagram (SIO0, SIO1)..............................................................................................17-4
Chapter 18
UART
Overview.................................................................................................................................................18-1
Programming Procedure......................................................................................................................18-1
UART Control Register (UARTCON) ...................................................................................................18-2
UART Interrupt Pending Bits................................................................................................................18-3
UART Data Register (Udata) ...............................................................................................................18-4
UART Baud Rate Data Register (BRDATA).........................................................................................18-4
BAUD Rate Calculations......................................................................................................................18-4
Block Diagram.........................................................................................................................................18-6
UART Mode 0 Function Description.....................................................................................................18-7
Serial Port Mode 1 Function Description..............................................................................................18-8
Serial Port Mode 2 Function Description..............................................................................................18-9
Serial Port Mode 3 Function Description..............................................................................................18-10
Serial Communication for Multiprocessor Configurations.....................................................................18-11
S3C825A/P825A MICROCONTROLLER
ix
Table of Contents (Concluded)
Chapter 19
Electrical Data
Overview ................................................................................................................................................ 19-1
Chapter 20
Mechanical Data
Overview ................................................................................................................................................ 20-1
Chapter 21
S3P825A OTP
Overview ................................................................................................................................................ 21-1
Operating Mode Characteristics...................................................................................................... 21-4
Chapter 22
Development Tools
Overview ................................................................................................................................................ 22-1
SHINE............................................................................................................................................ 22-1
SAMA Assembler ........................................................................................................................... 22-1
SASM88......................................................................................................................................... 22-1
HEX2ROM...................................................................................................................................... 22-1
Target Boards................................................................................................................................. 22-1
TB825A Target Board..................................................................................................................... 22-3
SMDS2+ Selection (SAM8) ............................................................................................................ 22-4
Idle LED ......................................................................................................................................... 22-4
Stop LED........................................................................................................................................ 22-4
x
S3C825A/P825A MICROCONTROLLER
List of Figures
Figure
Title
Page
Number
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
Block Diagram........................................................................................................1-3
S3C825A Pin Assignments (80-TQFP-1212) ..........................................................1-4
S3C825A Pin Assignments (80-QFP-1420) ............................................................1-5
Pin Circuit Type A ..................................................................................................1-8
Pin Circuit Type B (RESET) ...................................................................................1-8
Pin Circuit Type C ..................................................................................................1-8
Pin Circuit Type E-4 (P2, P3.4–P3.7, P4, P5)........................................................1-8
Pin Circuit Type F-16 (P3.0-P3.3)...........................................................................1-9
Pin Circuit Type H-23 .............................................................................................1-9
Pin Circuit Type H-32(P0, P1, P6-P8).....................................................................1-9
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Program Memory Address Space...........................................................................2-2
Internal Register File Organization .........................................................................2-4
Register Page Pointer (PP) ....................................................................................2-5
Set 1, Set 2, Prime Area Register, and LCD Data Register Map.............................2-7
8-Byte Working Register Areas (Slices)..................................................................2-8
Contiguous 16-Byte Working Register Block...........................................................2-9
Non-Contiguous 16-Byte Working Register Block...................................................2-10
16-Bit Register Pair ................................................................................................2-11
Register File Addressing.........................................................................................2-12
Common Working Register Area............................................................................2-13
4-Bit Working Register Addressing.........................................................................2-15
4-Bit Working Register Addressing Example ..........................................................2-15
8-Bit Working Register Addressing.........................................................................2-16
8-Bit Working Register Addressing Example ..........................................................2-17
Stack Operations....................................................................................................2-18
2-9
2-10
2-11
2-12
2-13
2-14
2-15
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Register Addressing ...............................................................................................3-2
Working Register Addressing .................................................................................3-2
Indirect Register Addressing to Register File ..........................................................3-3
Indirect Register Addressing to Program Memory...................................................3-4
Indirect Working Register Addressing to Register File ............................................3-5
Indirect Working Register Addressing to Program or Data Memory ........................3-6
Indexed Addressing to Register File .......................................................................3-7
Indexed Addressing to Program or Data Memory with Short Offset ........................3-8
Indexed Addressing to Program or Data Memory ...................................................3-9
Direct Addressing for Load Instructions...................................................................3-10
Direct Addressing for Call and Jump Instructions....................................................3-11
Indirect Addressing.................................................................................................3-12
Relative Addressing ...............................................................................................3-13
Immediate Addressing............................................................................................3-14
3-9
3-10
3-11
3-12
3-13
3-14
S3C825A/P825A MICROCONTROLLER
xi
List of Figures (Continued)
Figure
Title
Page
Number
Number
4-1
Register Description Format .................................................................................. 4-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
S3C8-Series Interrupt Types.................................................................................. 5-2
S3C825A Interrupt Structure.................................................................................. 5-4
ROM Vector Address Area..................................................................................... 5-5
Interrupt Function Diagram.................................................................................... 5-8
System Mode Register (SYM)................................................................................ 5-10
Interrupt Mask Register (IMR)................................................................................ 5-11
Interrupt Request Priority Groups........................................................................... 5-12
Interrupt Priority Register (IPR).............................................................................. 5-13
Interrupt Request Register (IRQ) ........................................................................... 5-14
6-1
System Flags Register (FLAGS)............................................................................ 6-6
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
Crystal/Ceramic Oscillator (fx)............................................................................... 7-2
External Oscillator (fx)........................................................................................... 7-2
RC Oscillator (fx)................................................................................................... 7-2
Crystal/Ceramic Oscillator (fxt).............................................................................. 7-2
External Oscillator (fxt).......................................................................................... 7-2
System Clock Circuit Diagram............................................................................... 7-3
System Clock Control Register (CLKCON) ............................................................ 7-4
Oscillator Control Register (OSCCON) .................................................................. 7-5
STOP Control Register (STPCON)........................................................................ 7-7
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
Port Group 0 Control Register (PG0CON) ............................................................. 9-4
Port 2 High-Byte Control Register (P2CONH)........................................................ 9-6
Port 2 Low-Byte Control Register (P2CONL).......................................................... 9-6
Port 2 Pull-up Control Register (P2PUR) ............................................................... 9-7
Port 2 Interrupt Control Register (P2INT)............................................................... 9-7
Port 3 High-Byte Control Register (P3CONH)........................................................ 9-8
Port 3 Low-Byte Control Register (P3CONL).......................................................... 9-9
Port 3 Pull-up Control Register (P3PUR) ............................................................... 9-9
Port 4 High-Byte Control Register (P4CONH)........................................................ 9-10
Port 4 Low-Byte Control Register (P4CONL).......................................................... 9-11
Port 4 Interrupt Control Register (P4INT)............................................................... 9-11
Port 4 Interrupt Pending Control Register (P4PND)................................................ 9-12
Port 4 Interrupt Edge Selection Register (P4EDGE) .............................................. 9-12
Port 5 High-Byte Control Register (P5CONH)........................................................ 9-13
Port 5 Low-Byte Control Register (P5CONL).......................................................... 9-14
Port 5 Pull-up Control Register (P5PUR) ............................................................... 9-14
Port Group 1 Control Register (PG1CON) ............................................................. 9-15
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
xii
S3C825A/P825A MICROCONTROLLER
List of Figures (Continued)
Page
Title
Page
Number
Number
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
Basic Timer Control Register (BTCON) ..................................................................10-2
Basic Timer Block Diagram ....................................................................................10-4
Timer 0 Control Register (T0CON) .........................................................................10-6
Interrupt Pending Register (INTPND)......................................................................10-7
Simplified Timer 0 Function Diagram: Interval Timer Mode....................................10-8
Simplified Timer 0 Function Diagram: PWM Mode.................................................10-9
Simplified Timer 0 Function Diagram: Capture Mode .............................................10-10
Timer 0 Block Diagram...........................................................................................10-11
11-1
11-2
11-3
11-4
11-5
Timer 1 Control Register (TACON).........................................................................11-2
Timer 1 Functional Block Diagram..........................................................................11-3
Timer A Control Register (TACON) ........................................................................11-5
Timer B Control Register (TBCON) ........................................................................11-6
Timer A and B Function Block Diagram..................................................................11-7
12-1
12-2
Timer 2 Control Register (T2CON) .........................................................................12-2
Timer 2 Functional Block Diagram..........................................................................12-3
13-1
13-2
13-3
13-4
13-5
13-6
Timer 3 Control Register (T3CON) .........................................................................13-2
Interrupt Pending Register (INTPND)......................................................................13-3
Simplified Timer 3 Function Diagram: Interval Timer Mode....................................13-4
Simplified Timer 3 Function Diagram: PWM Mode.................................................13-5
Simplified Timer 3 Function Diagram: Capture Mode .............................................13-6
Timer 3 Block Diagram...........................................................................................13-7
14-1
14-2
Watch Timer Control Register (WTCON) ...............................................................14-2
Watch Timer Circuit Diagram .................................................................................14-3
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
LCD Function Diagram...........................................................................................15-1
LCD Circuit Diagram ..............................................................................................15-2
LCD Display Data RAM Organization .....................................................................15-3
LCD Control Register (LCON) ................................................................................15-4
LCD Bias Circuit Connection ..................................................................................15-6
Example 1 for the Usage of LCON.7–.6..................................................................15-7
Example 2 for the Usage of LCON.7–.6..................................................................15-8
LCD Signal Waveforms (1/3 Duty, 1/3 Bias)...........................................................15-9
LCD Signal Waveforms (1/4 Duty, 1/3 Bias)...........................................................15-10
LCD Signal Waveforms (1/8 Duty, 1/4 Bias)...........................................................15-11
LCD Signal Waveforms (1/8 Duty, 1/5 Bias)...........................................................15-13
16-1
16-2
16-3
16-4
A/D Converter Control Register (ADCON) ..............................................................16-2
A/D Converter Data Register (ADDATAH/ADDATAL).............................................16-3
A/D Converter Functional Block Diagram ...............................................................16-3
Recommended A/D Converter Circuit for Highest Absolute Accuracy.....................16-4
S3C825A/P825A MICROCONTROLLER
xiii
List of Figures (Concluded)
Page
Title
Page
Number
Number
17-1
17-2
17-3
17-4
17-5
Serial I/O Module Control Register (SIOCON) ....................................................... 17-2
SIO Prescaler Register (SIOPS)............................................................................ 17-3
SIO Functional Block Diagram............................................................................... 17-3
Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) ........... 17-4
Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) ............ 17-4
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
UART Control Register (UARTCON) ..................................................................... 18-2
UART Interrupt Pending Bits (INTPND.5–.4).......................................................... 18-3
UART Data Register (UDATA)............................................................................... 18-4
UART Baud Rate Data Register (BRDATA)........................................................... 18-4
UART Functional Block Diagram ........................................................................... 18-6
Timing Diagram for Serial Port Mode 0 Operation ................................................. 18-7
Timing Diagram for Serial Port Mode 1 Operation ................................................. 18-8
Timing Diagram for Serial Port Mode 2 Operation ................................................. 18-9
Timing Diagram for Serial Port Mode 3 Operation ................................................. 18-10
Connection Example for Multiprocessor Serial Data Communications ................... 18-12
19-1
19-2
Input Timing for External Interrupts (P2.4–P2.7, P4).............................................. 19-5
Input Timing for RESET ........................................................................................ 19-5
19-3
19-4
19-5
19-6
Stop Mode Release Timing Initiated by RESET..................................................... 19-6
Stop Mode Release Timing Initiated by Interrupts.................................................. 19-7
Serial Data Transfer Timing................................................................................... 19-9
Clock Timing Measurement at XIN ......................................................................... 19-11
19-7
Clock Timing Measurement at XTIN....................................................................... 19-11
19-8
19-9
19-10
Operating Voltage Range ...................................................................................... 19-12
Waveform for UART Timing Characteristics.......................................................... 19-13
A.C. Timing Waveform for the UART Module........................................................ 19-14
20-1
20-2
Package Dimensions (80-QFP-1420C).................................................................. 20-1
Package Dimension (80-TQFP-1212).................................................................... 20-2
21-1
21-2
21-3
S3P825A Pin Assignments (80-Pin TQFP Package).............................................. 21-2
S3P825A Pin Assignments (80-Pin QFP Package)................................................ 21-3
Operating Voltage Range ...................................................................................... 21-5
22-1
22-2
22-3
22-4
SMDS Product Configuration (SMDS2+) ............................................................... 22-2
TB825A Target Board Configuration...................................................................... 22-3
40-Pin Connectors (J101, J102) for TB825A.......................................................... 22-5
S3C825A Cables for 80-TQFP Package................................................................ 22-6
xiv
S3C825A/P825A MICROCONTROLLER
List of Tables
Table
Title
Page
Number
Number
1-1
2-1
S3C825A Pin Descriptions......................................................................................1-6
S3C825A Register Type Summary.........................................................................2-3
4-1
4-2
4-3
Set 1 Registers (INTPND/STPCON/OSCCON are in bank 0 of set 1).....................4-1
Set 1, Bank 0 Registers..........................................................................................4-2
Set 1, Bank 1 Registers..........................................................................................4-3
5-1
5-2
5-3
Interrupt Vectors.....................................................................................................5-6
Interrupt Control Register Overview........................................................................5-7
Interrupt Source Control and Data Registers...........................................................5-9
6-1
6-2
6-3
6-4
6-5
6-6
Instruction Group Summary....................................................................................6-2
Flag Notation Conventions .....................................................................................6-8
Instruction Set Symbols..........................................................................................6-8
Instruction Notation Conventions............................................................................6-9
Opcode Quick Reference .......................................................................................6-10
Condition Codes.....................................................................................................6-12
8-1
8-2
8-3
S3C825A Set 1 Register and Values after RESET..................................................8-2
S3C825A Set 1, Bank 0 Register Values after RESET ...........................................8-3
S3C825A Set 1, Bank 1 Register Values after RESET ...........................................8-4
9-1
9-2
S3C825A Port Configuration Overview...................................................................9-2
Port Data Register Summary..................................................................................9-3
15-1
18-1
LCD Mode Control Register (LMOD) Organization..................................................15-5
Commonly Used Baud Rates Generated by BRDATA ............................................18-5
S3C825A/P825A MICROCONTROLLER
xv
List of Tables (Continued)
Table
Title
Page
Number
Number
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
Absolute Maximum Ratings................................................................................... 19-2
D.C. Electrical Characteristics ............................................................................... 19-2
A.C. Electrical Characteristics................................................................................ 19-5
Input/Output Capacitance...................................................................................... 19-6
Data Retention Supply Voltage in Stop Mode ........................................................ 19-6
A/D Converter Electrical Characteristics................................................................ 19-8
Synchronous SIO Electrical Characteristics........................................................... 19-9
Main Oscillator Characteristics .............................................................................. 19-10
Sub Oscillator Characteristics................................................................................ 19-10
Main Oscillator Stabilization Time.......................................................................... 19-11
Sub Oscillator Stabilization Time........................................................................... 19-11
UART Timing Characteristics in Mode 0 (8 MHz)................................................... 19-13
21-1
21-2
21-3
Descriptions of Pins Used to Read/Write the EPROM............................................ 21-4
Comparison of S3P825A and S3C825A Features.................................................. 21-4
Operating Mode Selection Criteria......................................................................... 21-4
22-1
22-2
Power Selection Settings for TB825A .................................................................... 22-4
The SMDS2+ Tool Selection Setting ..................................................................... 22-4
xvi
S3C825A/P825A MICROCONTROLLER
List of Programming Tips
Description
Chapter 2:
Page
Number
Address Spaces
Using the Page Pointer for RAM clear (Page 0, Page1).......................................................................2-5
Setting the Register Pointers ...............................................................................................................2-9
Using the RPs to Calculate the Sum of a Series of Registers...............................................................2-10
Addressing the Common Working Register Area.................................................................................2-14
Standard Stack Operations Using PUSH and POP ..............................................................................2-19
Chapter 7:
Clock Circuit
Switching the CPU clock......................................................................................................................7-6
S3C825A/P825A MICROCONTROLLER
xvii
List of Register Descriptions
Register
Identifier
Full Register Name
Page
Number
ADCON
BTCON
CLKCON
FLAGS
IMR
INTPND
IPH
IPL
IPR
IRQ
LCON
LMOD
OSSCON
P2CONH
P2CONL
P2PUR
P2INT
P3CONH
P3CONL
P3PUR
P4CONH
P4CONL
P4EDGE
P4INT
P4PND
P5CONH
P5CONL
P5PUR
PG0CON
PG1CON
PP
A/D Converter Control Register..............................................................................4-5
Basic Timer Control Register..................................................................................4-6
System Clock Control Register...............................................................................4-7
System Flags Register ...........................................................................................4-8
Interrupt Mask Register ..........................................................................................4-9
Interrupt Pending Register......................................................................................4-10
Instruction Pointer (High Byte) ...............................................................................4-11
Instruction Pointer (Low Byte) ................................................................................4-11
Interrupt Priority Register........................................................................................4-12
Interrupt Request Register......................................................................................4-13
LCD Control Register .............................................................................................4-14
LCD Mode Control Register....................................................................................4-15
Oscillator Control Register......................................................................................4-16
Port 2 Control Register (High Byte) ........................................................................4-17
Port 2 Control Register (Low Byte) .........................................................................4-18
Port 2 Pull-up Control Register...............................................................................4-19
Port 2 Interrupt Control Register.............................................................................4-20
Port 3 Control Register (High Byte) ........................................................................4-21
Port 3 Control Register (Low Byte) .........................................................................4-22
Port 3 Pull-up Control Register...............................................................................4-23
Port 4 Control Register (High Byte) ........................................................................4-24
Port 4 Control Register (Low Byte) .........................................................................4-25
Port 4 Interrupt Edge Selection Register.................................................................4-26
Port 4 Interrupt Control Register.............................................................................4-27
Port 4 Interrupt Pending Register ...........................................................................4-28
Port 5 Control Register (High Byte) ........................................................................4-29
Port 5 Control Register (Low Byte) .........................................................................4-30
Port 5 Pull-up Control Register...............................................................................4-31
Port Group 0 Control Register ................................................................................4-32
Port Group 1 Control Register ................................................................................4-33
Register Page Pointer ............................................................................................4-34
Register Pointer 0...................................................................................................4-35
Register Pointer 1...................................................................................................4-35
SIO Control Register ..............................................................................................4-36
Stack Pointer (High Byte).......................................................................................4-37
Stack Pointer (Low Byte)........................................................................................4-37
Stop Control Register.............................................................................................4-38
System Mode Register ...........................................................................................4-39
Timer 0 Control Register ........................................................................................4-40
Timer 1/A Control Register.....................................................................................4-41
Timer B Control Register........................................................................................4-42
Timer 2 Control Register ........................................................................................4-43
Timer 3 Control Register ........................................................................................4-44
UART Control Register...........................................................................................4-45
Watch Timer Control Register ................................................................................4-46
RP0
RP1
SIOCON
SPH
SPL
STPCON
SYM
T0CON
TACON
TBCON
T2CON
T3CON
UARTCON
WTCON
S3C825A/P825A MICROCONTROLLER
xix
xx
S3C825A/P825A MICROCONTROLLER
List of Instruction Descriptions
Instruction
Mnemonic
Full Register Name
Page
Number
ADC
ADD
AND
BAND
BCP
BITC
BITR
BITS
BOR
BTJRF
BTJRT
BXOR
CALL
CCF
CLR
Add with Carry........................................................................................................6-14
Add ........................................................................................................................6-15
Logical AND...........................................................................................................6-16
Bit AND..................................................................................................................6-17
Bit Compare...........................................................................................................6-18
Bit Complement .....................................................................................................6-19
Bit Reset ................................................................................................................6-20
Bit Set....................................................................................................................6-21
Bit OR....................................................................................................................6-22
Bit Test, Jump Relative on False............................................................................6-23
Bit Test, Jump Relative on True .............................................................................6-24
Bit XOR..................................................................................................................6-25
Call Procedure .......................................................................................................6-26
Complement Carry Flag .........................................................................................6-27
Clear......................................................................................................................6-28
Complement...........................................................................................................6-29
Compare................................................................................................................6-30
Compare, Increment, and Jump on Equal ..............................................................6-31
Compare, Increment, and Jump on Non-Equal.......................................................6-32
Decimal Adjust.......................................................................................................6-33
Decrement .............................................................................................................6-35
Decrement Word....................................................................................................6-36
Disable Interrupts ...................................................................................................6-37
Divide (Unsigned)...................................................................................................6-38
Decrement and Jump if Non-Zero ..........................................................................6-39
Enable Interrupts....................................................................................................6-40
Enter......................................................................................................................6-41
Exit ........................................................................................................................6-42
Idle Operation ........................................................................................................6-43
Increment...............................................................................................................6-44
Increment Word .....................................................................................................6-45
Interrupt Return......................................................................................................6-46
Jump......................................................................................................................6-47
Jump Relative........................................................................................................6-48
Load.......................................................................................................................6-49
Load Bit..................................................................................................................6-51
COM
CP
CPIJE
CPIJNE
DA
DEC
DECW
DI
DIV
DJNZ
EI
ENTER
EXIT
IDLE
INC
INCW
IRET
JP
JR
LD
LDB
S3C825A/P825A MICROCONTROLLER
xxi
List of Instruction Descriptions (Continued)
Instruction
Mnemonic
Full Register Name
Page
Number
LDC/LDE
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
LDCPI/LDEPI
LDW
Load Memory .........................................................................................................6-52
Load Memory and Decrement ................................................................................6-54
Load Memory and Increment..................................................................................6-55
Load Memory with Pre-Decrement .........................................................................6-56
Load Memory with Pre-Increment...........................................................................6-57
Load Word .............................................................................................................6-58
Multiply (Unsigned).................................................................................................6-59
Next .......................................................................................................................6-60
No Operation..........................................................................................................6-61
Logical OR .............................................................................................................6-62
Pop from Stack.......................................................................................................6-63
Pop User Stack (Decrementing) .............................................................................6-64
Pop User Stack (Incrementing)...............................................................................6-65
Push to Stack .........................................................................................................6-66
Push User Stack (Decrementing)............................................................................6-67
Push User Stack (Incrementing) .............................................................................6-68
Reset Carry Flag ....................................................................................................6-69
Return ....................................................................................................................6-70
Rotate Left .............................................................................................................6-71
Rotate Left through Carry .......................................................................................6-72
Rotate Right ...........................................................................................................6-73
Rotate Right through Carry.....................................................................................6-74
Select Bank 0.........................................................................................................6-75
Select Bank 1.........................................................................................................6-76
Subtract with Carry.................................................................................................6-77
Set Carry Flag........................................................................................................6-78
Shift Right Arithmetic..............................................................................................6-79
Set Register Pointer ...............................................................................................6-80
Stop Operation.......................................................................................................6-81
Subtract..................................................................................................................6-82
Swap Nibbles .........................................................................................................6-83
Test Complement under Mask................................................................................6-84
Test under Mask.....................................................................................................6-85
Wait for Interrupt ....................................................................................................6-86
Logical Exclusive OR .............................................................................................6-87
MULT
NEXT
NOP
OR
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
RCF
RET
RL
RLC
RR
RRC
SB0
SB1
SBC
SCF
SRA
SRP/SRP0/SRP1
STOP
SUB
SWAP
TCM
TM
WFI
XOR
xxii
S3C825A/P825A MICROCONTROLLER
S3C825A/P825A
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned
to specific interrupt levels.
S3C825A MICROCONTROLLER
The S3C825A single-chip microcontroller are fabricated using the highly advanced CMOS process. Its design is
based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented to reduce
power consumption.
The S3C825A is a microcontroller with a 48K-byte mask-programmable ROM embedded.
The S3P825A is a microcontroller with a 48K-byte one-time-programmable ROM embedded.
Using the SAM88RC modular design approach, the following peripherals were integrated with the SAM88RC
CPU core:
— Large number of programmable I/O ports (Total 67 pins)
— Synchronous SIO module
— Two 8-bit timer/counters
— Two 16-bit timer/counters
— LCD controller/driver
— A/D converter with 4 selectable input pins
OTP
The S3C825A microcontroller is also available in OTP (One Time Programmable) version, S3P825A.
The S3P825A microcontroller has an on-chip 48K-byte one-time-programmable EPROM instead of masked
ROM. The S3P825A is comparable to S3C825A, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C825A/P825A
FEATURES
CPU
Watch Timer
•
SAM88RC CPU core
•
Interval Time: 3.19ms, 0.25s, 0.5s, 1.0s at
32.768 kHz
0.5/1/2/4 kHz buzzer output selectable
Memory
•
•
•
2064-byte internal register file (including LCD
display RAM)
48K-byte internal program memory area
Analog to Digital Converter
•
•
•
4-channel analog input
10-bit conversion resolution
25ms conversion time
Instruction Set
•
•
78 instructions
Idle and Stop instructions
Serial I/O Interface
•
•
•
8-bit transmit/receive mode
8-bit receive mode
Selectable baud rate or external clock source
67 I/O Pins
•
•
31 normal I/O pins
36 pins sharing with LCD signals
UART
Interrupts
•
•
Full-duplex serial I/O interface
Four programmable operating modes
•
•
8 interrupt levels and 23 internal sources
Fast interrupt processing feature
LCD Controller/Driver
8-Bit Basic Timer
•
•
•
28 segments and 8 common terminals
3, 4, and 8 common selectable
Internal resistor circuit for LCD bias
•
•
Watchdog timer function
4 kinds of clock source
Timer/Counter 0
Two Power-Down Modes
•
•
•
Programmable 8-bit internal timer
External event counter function
PWM and capture function
•
•
Idle mode: only CPU clock stops
Stop mode: system clock and CPU clock stop
Oscillation Source
Timer/Counter 1
•
•
Crystal, ceramic, or RC for main clock
Crystal for sub clock (32.768 kHz)
•
•
•
One 16-bit timer/counter mode
Two 8-bit timer/counters A/B mode
External event counter function
Instruction Execution Time
•
•
500 ns at fx=8 MHz (minimum, main clock)
122ms at fxt=32.768 kHz (sub clock)
Timer/Counter 2
•
•
Programmable 8-bit interval timer
External event counter function
Operating Temperature Range
–25 °C to +85 °C
•
Timer/Counter 3
•
•
•
Programmable 16-bit interval timer
External event counter function
PWM and capture function
Operating Voltage Range
•
•
•
2.0 V to 5.5 V at 4 MHz (main clock)
2.2 V to 5.5 V at 8 MHz (main clock)
2.0 V to 5.5 V at 32.768 kHz (sub clock)
Package Type
80-pin TQFP-1212, 80-pin QFP-1420
•
1-2
S3C825A/P825A
PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.4-P1.7/
INT0-INT3
P4.0-P4.7/
INT4-INT11
RESET
XIN
P0.0-P0.7/
SEG16-SEG23
Main OSC
Sub OSC
Port 0
Port 1
XOUT
XTIN
P1.0-P1.7/
SEG24-SEG31
XTOUT
P2.0
P2.4/T0CLK
P3.7/T0CAP
P3.7/T0OUT/T0PWM
I/O Port and Interrupt Control
8-Bit
Timer/Counter0
P2.1
P2.2/T2CLK
P2.3/T2OUT
P2.4/INT0/T0CLK
P2.5/INT1/T1CLK
P2.6/INT2/TAOUT
P2.7/INT3/TBOUT
Port 2
P2.5/T1CLK
P2.6/TAOUT
P2.7/TBOUT
8-bit Timer A
8-bit Timer A
P3.0/AD0
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3.4
P3.5/T3CLK
P3.6/T3OUT/P
P3.6/T3OUT/
P2.2/T2CLK
P2.3/T2OUT
8-Bit
Timer/Counter2
Port 3
Port 4
Port 5
P3.5/T3CLK
P3.6/T3CAP
P3.6/T3OUT/T3PWM
16-Bit
Timer/Counter3
P3.7/T0OUT/
T0PWM/T0CAP
P4.0-P4.7/
INT4-INT11
SAM88RC Core
P5.0/SCK
P5.1/SI
P5.2/SO
SIO
P5.0/SCK
P5.1/SI
P5.2/SO
P5.3/BUZ
P5.4/RXD
P5.5/TXD
Watchdog
Timer
Basic Timer
Watch Timer
UART
P6.0/COM0
P6.1/COM1
P5.0/BUZ
P6.2/COM2
P6.3/COM3
Port 6
P6.4/COM4/SEG0
P6.5/COM5/SEG1
P6.6/COM6/SEG2
P6.7/COM7/SEG3
P5.4/RXD
P5.5/TXD
P6.0-P6.3/
COM0-COM3
P7.0-P7.7/
SEG4-SEG11
2064-byte
Register File
48K-byte
ROM
Port 7
Port 8
P6.4-P6.7/
COM4-COM7/
SEG0-SEG3
P8.0-P8.3/
SEG12-SEG15
LCD
Driver/Controller
P7.0-P8.3/
SEG4-SEG15
P0.0-P1.7/
SEG16-SEG31
P3.0-P3.3/
AD0-AD3
10-bit ADC
VLC1
TEST
VDD1/VDD2
VSS1/VSS2
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C825A/P825A
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.0/SEG4
P1.1/SEG25
P1.2/SEG26
P1.3/SEG27
P1.4/SEG28
P1.5/SEG29
P1.6/SEG30
P1.7/SEG31
P2.0
P6.7/SEG3/COM7
P6.6/SEG2/COM6
P6.5/SEG1/COM5
P6.4/SEG0/COM4
P6.3/COM3
P6.2/COM2
P6.1/COM1
P6.0/COM0
VDD2
VSS2
VLC1
P5.6
P5.5/TXD
9
P2.1
VDD1
VSS1
XOUT
XIN
TEST
XTIN
XTOUT
S3C825A
10
11
12
13
14
15
16
17
18
19
20
(80-TQFP-1212)
P5.4/RXD
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
RESET
P2.2/T2CLK
P2.3/T2OUT
P2.4/INT0/T0CLK
P4.7/INT11
Figure 1-2. S3C825A Pin Assignments (80-TQFP-1212)
1-4
S3C825A/P825A
PRODUCT OVERVIEW
1
2
3
4
5
6
7
8
P0.7/SEG23
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.2/SEG6
P1.0/SEG24
P1.1/SEG25
P1.2/SEG26
P1.3/SEG27
P1.4/SEG28
P1.5/SEG29
P1.6/SEG30
P1.7/SEG31
P2.0
P7.1/SEG5
P7.0/SEG4
P6.7/SEG3/COM7
P6.6/SEG2/COM6
P6.5/SEG1/COM5
P6.4/SEG0/COM4
P6.3/COM3
P6.2/COM2
P6.1/COM1
P6.0/COM0
VDD2
VSS2
VLC1
P5.6
P5.5/TXD
P5.4/RXD
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P2.1
VDD1
VSS1
XOUT
XIN
TEST
XTIN
XTOUT
S3C825A
(80-QFP-1420C)
RESET
P2.2/T2CLK
P2.3/T2OUT
P2.4/INT0/T0CLK
P2.5/INT1/T1CLK
P2.6/INT2/TAOUT
P4.7/INT11
P4.6/INT10
P4.5/INT9
Figure 1-3. S3C825A Pin Assignments (80-QFP-1420)
1-5
PRODUCT OVERVIEW
S3C825A/P825A
PIN DESCRIPTIONS
Table 1-1. S3C825A Pin Descriptions
Pin
Type
Pin
Description
Circuit
Type
Pin
Numbers
Share
Pins
Pin
Names
P0.0–P0.7
I/O
I/O
I/O
4-bit-programmable I/O port.
Input or push-pull, open-drain output and
software assignable pull-ups.
H-32
H-32
E-4
72–79
(74-80, 1)
SEG16
–
SEG23
P1.0–1.7
4-bit-programmable I/O port.
Input or push-pull, open-drain output and
software assignable pull-ups.
80, 1–7
(2-9)
SEG24
–
SEG31
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
1-bit-programmable I/O port.
Schmitt trigger input or push-pull, open-
drain output and software assignable pull-
ups.
8 (10)
9 (11)
–
–
18 (20)
19 (21)
20 (22)
21 (23)
22 (24)
23 (25)
T2CLK
T2OUT
INT0/T0CLK
INT1/T1CLK
INT2/TAOUT
INT3/TBOUT
P2.4–P2.7: Alternately used for external
interrupt input (Noise filters, interrupt
enable and pending control)
1-bit-programmable I/O port.
Schmitt trigger input or push-pull,
open-drain output, and software
assignable pull-ups.
P3.0–P3.3
I/O
I/O
F-16
E-4
25–28
(27–30)
AD0–AD3
P3.4
P3.5
P3.6
P3.7
30(32)
31(33)
32(34)
33(35)
–
T3CLK
T3OUT/T3PWM/T3CAP
T0OUT/T0PWM/T0CAP
P4.0–P4.7
1-bit-programmable I/O port.
Schmitt trigger input or push-pull, open-
drain output and software assignable pull-
ups.
E-4
34–41
(36–43)
INT4–INT11
P4.0–P4.7: Alternately used for external
interrupt input (Noise filters, interrupt
enable and pending control)
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
I/O
I/O
1-bit-programmable I/O port.
Schmitt trigger input or push-pull, open-
drain output and software assignable pull-
ups.
E-4
42 (44)
43 (45)
44 (46)
45 (47)
46 (48)
47 (49)
48 (50)
SCK
SI
SO
BUZ
RXD
TXD
–
P6.0-P6.3
P6.4–P6.7
H-32
52-55(54-57)
56-59(58-61)
COM0–COM3
4-bit programmable I/O port. Input or
push-pull, open-drain output and software
assignable pull-ups.
COM4–COM7/
SEG0–SEG3
P7.0–P7.7
P8.0–P8.3
I/O
I/O
H-32
H-32
60-67(62-69)
68-71(70-73)
SEG4–SEG11
SEG12–SEG15
NOTE: Parentheses indicate pin number for 80-QFP-1420 package.
1-6
S3C825A/P825A
PRODUCT OVERVIEW
Table 1-1. S3C825A Pin Descriptions (Continued)
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Pin
Share
Pins
Numbers (note)
VSS1, VDD1
–
–
–
Power input pins for core block
Main oscillator pins
–
–
–
10, 11 (12, 13)
12, 13 (14, 15)
14 (16)
–
–
–
XOUT
X
IN
,
TEST
Test signal input pin (must be connected
to VSS
)
XTIN, XTOUT
–
I
Sub oscillator pins
System reset pin
–
15, 16 (17,18)
17 (19)
–
–
B
RESET
INT0–INT3
T0CLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
External interrupt input pins
Timer 0 external clock input.
Timer 0 clock output
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
20–23 (22–25)
20 (22)
P2.4–P2.7
P2.4
T0OUT
T0PWM
T0CAP
33 (35)
P3.7
Timer 0 PWM output
33 (35)
P3.7
Timer 0 capture input
33 (35)
P3.7
T1CLK
Timer 1/A external clock input.
Timer 1/A clock output
Timer B clock output
21 (23)
P2.5
TAOUT
TBOUT
T2CLK
22 (24)
P2.6
23 (25)
P2.7
Timer 2 external clock input.
Timer 2 clock output
18 (20)
P2.2
T2OUT
T3CLK
19 (21)
P2.3
Timer 3 external clock input.
Timer 3 clock output
31 (33)
P3.5
T3OUT
T3PWM
T3CAP
32 (34)
P3.6
Timer 3 PWM output
32 (34)
P3.6
Timer 3 capture input
32 (34)
P3.6
AD0–AD3
AVREF, AVSS
Analog input pins for A/D convert module F-16
25–28 (27–30)
24, 29 (26, 31)
P3.0–P3.3
–
A/D converter reference voltage and ground
–
INT4–INT11
BUZ
I/O
I/O
I/O
External interrupt input pins
Buzzer signal output
E-4
E-4
E-4
34–41 (36–43)
45 (47)
P4.0–P4.7
P5.3
SCK, SI, SO
Serial clock, serial data input, serial data
output
42–44 (44–46)
P5.0–P5.2
RXD, TXD
VLC1
I/O
–
UART data input, output
E-4
–
46-47 (48-49)
49 (51)
P5.4-P5.5
–
LCD bias voltage input pins
VSS2, VDD2
–
Power input pins for peripheral block
–
50, 51 (52, 53)
–
COM0–COM3
I/O
I/O
LCD Common signal output
H-32
H-32
52–55 (54–57)
56–59 (58–61)
P6.0-P6.3
P6.4-P6.7
SEG0–SEG3
LCD Common or Segment signal output
(COM4–COM7)
SEG4–SEG11
SEG12–SEG15
SEG16–SEG23
SEG24–SEG31
I/O
I/O
I/O
I/O
LCD segment signal output
LCD segment signal output
LCD segment signal output
LCD segment signal output
H-32
H-32
H-32
H-32
60–67 (62–69)
68–71 (70–73)
P7.0-P7.7
P8.0-P8.3
72–79 (74–80, 1) P0.0–P0.7
80, 1–7 (2–9) P1.0–P1.7
NOTE: Parentheses indicate pin number for 80-QFP-1420 package.
1-7
PRODUCT OVERVIEW
S3C825A/P825A
PIN CIRCUITS
VDD
VDD
Open-drain
Data
P-Channel
Out
P-Channel
N-Channel
In
N-Channel
Output
Disable
Figure 1-6. Pin Circuit Type C
Figure 1-4. Pin Circuit Type A
VDD
Open-Drain
Enable
Pull-up
Resistor
VDD
VDD
Pull-up
Enable
P-CH
N-CH
Pull-up
Resistor
Data
I/O
In
Output
Disable
Schmitt Trigger
VSS
Schmitt Trigger
Figure 1-5. Pin Circuit Type B (RESET)
Figure 1-7. Pin Circuit Type E-4 (P2, P3.4–P3.7,
P4, P5)
1-8
S3C825A/P825A
PRODUCT OVERVIEW
VDD
VLC1
VLC2
Pull-up
Enable
VLC3
Open-drain
Data
Circuit
Output
Disable
Type C
I/O
Out
COM/SEG
ADCEN
Output
Disable
ADC Select
Data
VLC4
VLC5
VSS
To ADC
Figure 1-8. Pin Circuit Type F-16 (P3.0-P3.3)
Figure 1-9. Pin Circuit Type H-23
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open
Drain
P-CH
N-CH
Data
I/O
Output
Disable1
COM/SEG
Circuit
Type H-23
Output
Disable2
Figure 1-10. Pin Circuit Type H-32(P0, P1, P6-P8)
1-9
PRODUCT OVERVIEW
S3C825A/P825A
NOTES
1-10
S3C825A/P825A
ADDRESS SPACES
2
ADDRESS SPACES
OVERVIEW
The S3C825A microcontroller has two types of address space:
— Internal program memory (ROM)
— Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3C825A has an internal 48-Kbyte mask-programmable ROM.
The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes.
A 32-byte LCD display register file is implemented.
There are 2,137 mapped registers in the internal register file. Of these, 2,064 are for general-purpose.
(This number includes a 16-byte working register common area used as a "scratch area" for data operations,
eight 192-byte prime register areas, and eight 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the
CPU and the system control, and 60 registers are mapped for peripheral controls and data registers. Seven
register locations are not mapped.
2-1
ADDRESS SPACES
S3C825A/P825A
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3C825A has 48K bytes internal mask-
programmable program memory.
The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program
code, be careful not to overwrite the vector addresses stored in these locations.
The ROM address at which a program execution starts after a reset is 0100H.
(Decimal)
49,151
(HEX)
BFFFH
48K-bytes
Internal
Program
Memory Area
255
0
FFH
0H
Interrupt
Vector Area
Figure 2-1. Program Memory Address Space
2-2
S3C825A/P825A
ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3C825A implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called
set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank
1), and the lower 32-byte area is a single 32-byte common area.
In case of S3C825A the total number of addressable 8-bit registers is 2137. Of these 2137 registers, 13 bytes are
for CPU and system control registers, 60 bytes are for peripheral control and data registers, 16 bytes are used as
a shared working registers, and 2048 registers are for general-purpose use, page 0-page 7 (including 32 bytes for
LCD display registers).
You can always address set 1 register locations, regardless of which of the eight register pages is currently
selected. Set 1 locations, however, can only be addressed using register addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer
(PP).
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2–1.
Table 2-1. S3C825A Register Type Summary
Register Type
Number of Bytes
General-purpose registers (including the 16-byte
common working register area, eight 192-byte prime
register area (including LCD data registers), and eight
64-byte set 2 area).
2,064
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers
13
60
2,137
Total Addressable Bytes
2-3
ADDRESS SPACES
S3C825A/P825A
FFH
FFH
FFH
FFH
Page 7
Set 1
FFH
FFH
Bank 1
Page 1
Page 0
Bank 0
32
Bytes
System and
Peripheral Control
Set 2
Registers
(Register Addressing Mode)
Registers
(Indirect Register,
Indexed Mode,
E0H
DFH
64
Bytes
System Registers
(Register Addressing Mode)
and Stack Operations)
256
Bytes
D0H
CFH
Working Registers
(Working Register
Addressing Only)
C0H
BFH
Page 0
C0H
1FH
~
~
~
Prime
Data Registers
(All Addressing Modes)
192
Page 7
~
~
Bytes
Prime
Data Registers
(All Addressing Modes)
LCD Display Register
32
Bytes
~
~
00H
00H
Figure 2-2. Internal Register File Organization
2-4
S3C825A/P825A
ADDRESS SPACES
REGISTER PAGE POINTER (PP)
The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH). In the S3C825A microcontroller, a paged register file expansion is implemented
for LCD data registers, and the register page pointer must be changed to address other pages.
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP)
DFH ,Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Destination register page selection bits:
Source register page selection bits:
0000 Source: Page 0
0000
Destination: Page 0
NOTE:
A hardware reset operation writes the 4-bit destination and
source values shown above to the register page pointer. These values should
be modified to address other pages.
Figure 2-3. Register Page Pointer (PP)
+
PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1)
LD
SRP
LD
CLR
DJNZ
CLR
PP,#00H
#0C0H
R0,#0FFH
@R0
R0,RAMCL0
@R0
; Destination ¬ 0, Source ¬
0
; Page 0 RAM clear starts
RAMCL0
; R0 = 00H
LD
LD
CLR
DJNZ
CLR
PP,#10H
R0,#0FFH
@R0
R0,RAMCL1
@R0
; Destination ¬ 1, Source ¬
; Page 1 RAM clear starts
0
RAMCL1
; R0 = 00H
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.
2-5
ADDRESS SPACES
S3C825A/P825A
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and
bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware
reset operation always selects bank 0 addressing.
The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 57 mapped system and
peripheral control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte
common working register area (C0H–CFH). You can use the common working register area as a “scratch” area
for data operations being performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing (For more information about
working register addressing, please refer to Chapter 3, "Addressing Modes.")
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. For the S3C825A,
the set 2 address range (C0H–FFH) is accessible on pages 0-7.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
The set 2 register area of page 0 is commonly used for stack operations.
2-6
S3C825A/P825A
ADDRESS SPACES
PRIME REGISTER SPACE
The lower 192 bytes (00H–BFH) of the S3C825A's eight 256-byte register pages is called prime register area.
Prime registers can be accessed using any of the seven addressing modes
(see Chapter 3, "Addressing Modes.")
The prime register area on page 0 is immediately addressable following a reset. In order to address prime
registers on pages 0, 1, 2, 3, 4, 5, 6, or 7, you must set the register page pointer (PP) to the appropriate source
and destination values.
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
FFH
Set 1
Page 1
Bank 0
Bank 1
Page 0
FFH
FCH
E0H
D0H
C0H
0
Set 2
Page 7
C0H
BFH
Page 0
1FH
00H
LCD Data
Register Area
Prime
Space
CPU and system control
General-purpose
Peripheral and I/O
LCD data register
00H
Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map
2-7
ADDRESS SPACES
S3C825A/P825A
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one
that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)
— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)
All the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).
FFH
Slice 32
F8H
F7H
F0H
Slice 31
1 1 1 1 1 X X X
Set 1
Only
RP1 (Registers R8-R15)
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.
CFH
C0H
~
~
0 0 0 0 0 X X X
10H
FH
8H
7H
0H
RP0 (Registers R0-R7)
Slice 2
Slice 1
Figure 2-5. 8-Byte Working Register Areas (Slices)
2-8
S3C825A/P825A
ADDRESS SPACES
USING THE REGISTER POINTS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.
(see Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-
contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to either of the two 8-byte slices in the working register block, you can
flexibly define the working register area to support program requirements.
+
PROGRAMMING TIP — Setting the Register Pointers
SRP
SRP1
SRP0
CLR
LD
#70H
#48H
#0A0H
RP0
RP1,#0F8H
; RP0 ¬ 70H, RP1 ¬ 78H
; RP0 ¬ no change, RP1 ¬ 48H,
; RP0 ¬ A0H, RP1 ¬ no change
; RP0 ¬ 00H, RP1 ¬ no change
; RP0 ¬ no change, RP1 ¬ 0F8H
Register File
Contains 32
8-Byte Slices
0 0 0 0 1 X X X
RP1
FH (R15)
16-Byte
Contiguous
Working
8-Byte Slice
8-Byte Slice
8H
7H
0 0 0 0 0 X X X
RP0
Register block
0H (R0)
Figure 2-6. Contiguous 16-Byte Working Register Block
2-9
ADDRESS SPACES
S3C825A/P825A
F7H (R7)
F0H (R0)
8-Byte Slice
16-Byte
Contiguous
working
Register File
Contains 32
8-Byte Slices
1 1 1 1 0 X X X
Register block
RP0
0 0 0 0 0 X X X
RP1
7H (R15)
0H (R0)
8-Byte Slice
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
+
PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H
contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0
ADD
ADC
ADC
ADC
ADC
#80H
; RP0 ¬ 80H
; R0 ¬ R0 + R1
; R0 ¬ R0 + R2 + C
; R0 ¬ R0 + R3 + C
; R0 ¬ R0 + R4 + C
; R0 ¬ R0 + R5 + C
R0,R1
R0,R2
R0,R3
R0,R4
R0,R5
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used
to calculate the sum of these registers, the following instruction sequence would have to be used:
ADD
ADC
ADC
ADC
ADC
80H,81H
80H,82H
80H,83H
80H,84H
80H,85H
; 80H ¬ (80H) + (81H)
; 80H ¬ (80H) + (82H) + C
; 80H ¬ (80H) + (83H) + C
; 80H ¬ (80H) + (84H) + C
; 80H ¬ (80H) + (85H) + C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
2-10
S3C825A/P825A
ADDRESS SPACES
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access any location in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+1) odd-numbered register.
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific
8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
n = Even address
Rn+1
Figure 2-8. 16-Bit Register Pair
2-11
ADDRESS SPACES
S3C825A/P825A
Special-Purpose Registers
Bank 1 Bank 0
General-Purpose Register
FFH
FFH
Control
Registers
E0H
D0H
Set 2
System
Registers
CFH
C0H
C0H
BFH
RP1
RP0
Register
Pointers
Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).
Prime
Registers
LCD Data
Registers
NOTE: In the S3C825A microcontroller,
pages 0-7 are implemented.
Pages 0-7 contain all of the addressable
registers in the internal register file.
00H
Page 0
Page 0
Register Addressing Only
All
Indirect Register,
Indexed
All
Addressing
Modes
Addressing
Modes
Addressing
Modes
Can be Pointed
Can be Pointed by Register Pointer
by register Pointer
Figure 2-9. Register File Addressing
2-12
S3C825A/P825A
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H–CFH, as the active 16-byte working register block:
RP0 ® C0H–C7H
RP1 ® C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
Page 1
Set 1
FFH
Page 0
FFH
FCH
0
Set 2
E0H
~
~
D0H
C0H
Page 7
C0H
BFH
~
Page 0
1FH
00H
~
LCD Data
Registers
~
~
~
Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.
Prime
Space
~
~
RP0 = 1 1 0 0
RP1 = 1 1 0 0
0 0 0 0
1 0 0 0
00H
Figure 2-10. Common Working Register Area
2-13
ADDRESS SPACES
S3C825A/P825A
+
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples 1. LD
0C2H,40H
; Invalid addressing mode!
Use working register addressing instead:
SRP
LD
#0C0H
R2,40H
; R2 (C2H) ¬ the value in location 40H
2. ADD
0C3H,#45H
; Invalid addressing mode!
Use working register addressing instead:
SRP
ADD
#0C0H
R3,#45H
; R3 (C3H) ¬ R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
— The five high-order bits in the register pointer select an 8-byte slice of the register space.
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
2-14
S3C825A/P825A
ADDRESS SPACES
RP0
RP1
Selects
RP0 or RP1
Address
OPCODE
4-bit address
provides three
low-order bits
Register pointer
provides five
high-order bits
Together they create an
8-bit register address
Figure 2-11. 4-Bit Working Register Addressing
RP0
RP1
0 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0
Selects RP0
R6
OPCODE
Register
Instruction
'INC R6'
address
(76H)
0 1 1 1 0 1 1 0
0 1 1 0 1 1 1 0
Figure 2-12. 4-Bit Working Register Addressing Example
2-15
ADDRESS SPACES
S3C825A/P825A
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).
RP0
RP1
Selects
RP0 or RP1
Address
These address
bits indicate 8-bit
working register
addressing
8-bit logical
address
1
1
0
0
Register pointer
provides five
Three low-order bits
high-order bits
8-bit physical address
Figure 2-13. 8-Bit Working Register Addressing
2-16
S3C825A/P825A
ADDRESS SPACES
RP0
0 1 1 0 0
RP1
1 0 1 0 1
0 0 0
0 0 0
Selects RP1
R11
8-bit address
form instruction
'LD R11, R2'
Register
address
(0ABH)
1 1 0 0
1
0 1 1
1 0 1 0 1
0 1 1
Specifies working
register addressing
Figure 2-14. 8-Bit Working Register Addressing Example
2-17
ADDRESS SPACES
S3C825A/P825A
SYSTEM AND USER STACK
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3C825A architecture supports stack
operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-15.
High Address
PCL
PCL
PCH
Top of
PCH
Top of
stack
stack
Flags
Stack contents
after a call
Stack contents
after an
instruction
interrupt
Low Address
Figure 2-15. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL, SPH)
Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.
The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least
significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.
Because only internal memory space is implemented in the S3C825A, the SPL must be initialized to an 8-bit
value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if
necessary.
When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the
register file), you can use the SPH register as a general-purpose data register. However, if an overflow or
underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register
during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,
overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can
initialize the SPL value to "FFH" instead of "00H".
2-18
S3C825A/P825A
ADDRESS SPACES
+
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD
SPL,#0FFH
; SPL ¬ FFH
; (Normally, the SPL is set to 0FFH by the initialization
; routine)
•
•
•
PUSH
PUSH
PUSH
PUSH
•
PP
; Stack address 0FEH ¬ PP
; Stack address 0FDH ¬ RP0
; Stack address 0FCH ¬ RP1
; Stack address 0FBH ¬ R3
RP0
RP1
R3
•
•
POP
POP
POP
POP
R3
; R3 ¬ Stack address 0FBH
; RP1 ¬ Stack address 0FCH
; RP0 ¬ Stack address 0FDH
; PP ¬ Stack address 0FEH
RP1
RP0
PP
2-19
ADDRESS SPACES
S3C825A/P825A
NOTES
2-20
S3C825A/P825A
ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Indirect Address (IA)
— Relative Address (RA)
— Immediate (IM)
3-1
ADDRESSING MODES
S3C825A/P825A
REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).
Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory
Register File
OPERAND
8-bit Register
File Address
dst
Point to One
Register in Register
File
OPCODE
One-Operand
Instruction
(Example)
Value used in
Instruction Execution
Sample Instruction:
DEC
CNTR
;
Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File
MSB Point to
RP0 or RP1
RP0 or RP1
Selected
RP points
to start
Program Memory
of working
register
block
4-bit
Working Register
3 LSBs
dst
src
Point to the
Working Register
(1 of 8)
OPCODE
OPERAND
Two-Operand
Instruction
(Example)
Sample Instruction:
ADD R1, R2
;
Where R1 and R2 are registers in the curruntly
selected working register area.
Figure 3-2. Working Register Addressing
3-2
S3C825A/P825A
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of
the operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in
set 1 using the Indirect Register addressing mode.
Program Memory
Register File
ADDRESS
8-bit Register
File Address
dst
Point to One
Register in Register
File
OPCODE
One-Operand
Instruction
(Example)
Address of Operand
used by Instruction
OPERAND
Value used in
Instruction Execution
Sample Instruction:
RL
@SHIFT
;
Where SHIFT is the label of an 8-bit register address
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES
S3C825A/P825A
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory
Example
REGISTER
PAIR
dst
Instruction
References
Program
Points to
Register Pair
OPCODE
16-Bit
Memory
Address
Points to
Program
Memory
Program Memory
OPERAND
Sample Instructions:
Value used in
Instruction
CALL
JP
@RR2
@RR2
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
S3C825A/P825A
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
Selected
RP points
to start fo
working register
block
Program Memory
~
~
~
~
4-bit
Working
Register
Address
3 LSBs
dst
src
Point to the
Working Register
(1 of 8)
ADDRESS
OPERAND
OPCODE
Sample Instruction:
OR R3, @R6
Value used in
Instruction
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
S3C825A/P825A
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Program Memory
4-bit Working
Register Address
dst
src
Register
Pair
Next 2-bit Point
to Working
Register Pair
(1 of 4)
OPCODE
Example Instruction
References either
Program Memory or
Data Memory
16-Bit
address
points to
program
memory
or data
Program Memory
or
Data Memory
LSB Selects
memory
Value used in
Instruction
OPERAND
Sample Instructions:
LDC
LDE
LDE
R5,@RR6
R3,@RR14
@RR4, R8
;
;
;
Program memory access
External data memory access
External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
S3C825A/P825A
ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory. Please note, however, that you cannot access
locations C0H–FFH in set 1 using Indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128
to +127. This applies to external memory accesses only (see Figure 3-8.)
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory, when implemented.
Register File
RP0 or RP1
~
~
~
~
Selected RP
points to
start of
working
register
block
Value used in
Instruction
OPERAND
+
Program Memory
Base Address
3 LSBs
Two-Operand
Instruction
Example
dst/src
x
INDEX
Point to One of the
Woking Register
(1 of 8)
OPCODE
Sample Instruction:
LD R0, #BASE[R1]
;
Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
S3C825A/P825A
INDEXED ADDRESSING MODE (Continued)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
~
~
Program Memory
OFFSET
NEXT 2 Bits
4-bit Working
Register Address
dst/src
OPCODE
Register
Pair
x
Point to Working
Register Pair
(1 of 4)
16-Bit
address
added to
offset
Program Memory
or
LSB Selects
Data Memory
+
16-Bits
8-Bits
Value used in
Instruction
OPERAND
16-Bits
Sample Instructions:
LDC
LDE
R4, #04H[RR2]
R4,#04H[RR2]
; The values in the program address (RR2 + 04H)
are loaded into register R4.
; Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3C825A/P825A
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Program Memory
~
~
OFFSET
OFFSET
NEXT 2 Bits
4-bit Working
Register Address
Register
Pair
dst/src
src
Point to Working
Register Pair
OPCODE
16-Bit
address
added to
offset
Program Memory
or
LSB Selects
Data Memory
+
16-Bits
8-Bits
Value used in
Instruction
OPERAND
16-Bits
Sample Instructions:
LDC
LDE
R4, #1000H[RR2]
R4,#1000H[RR2]
;
;
The values in the program address (RR2 + 1000H)
are loaded into register R4.
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
ADDRESSING MODES
S3C825A/P825A
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Address
Used
Program Memory
Upper Address Byte
Lower Address Byte
dst/src "0" or "1"
OPCODE
LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Sample Instructions:
LDC
LDE
R5,1234H
R5,1234H
;
;
The values in the program address (1234H)
are loaded into register R5.
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3C825A/P825A
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Memory
Address
Used
Upper Address Byte
Lower Address Byte
OPCODE
Sample Instructions:
JP
C,JOB1
;
;
Where JOB1 is a 16-bit immediate address
Where DISPLAY is a 16-bit immediate address
CALL DISPLAY
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES
S3C825A/P825A
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be
executed. Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.
Program Memory
Next Instruction
LSB Must be Zero
dst
Current
OPCODE
Instruction
Lower Address Byte
Upper Address Byte
Program Memory
Locations 0-255
Sample Instruction:
CALL #40H
;
The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
3-12
S3C825A/P825A
ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current
PC Value
+
Displacement
OPCODE
Current Instruction
Signed
Displacement Value
Sample Instructions:
JR
ULT,$+OFFSET
;
Where OFFSET is a value in the range +127 to -128
Figure 3-13. Relative Addressing
3-13
ADDRESSING MODES
S3C825A/P825A
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the
operand field itself. The operand may be one byte or one word in length, depending on the instruction used.
Immediate addressing mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The Operand value is in the instruction)
Sample Instruction:
LD
R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
S3C825A/P825A
CONTROL REGISTER
4
CONTROL REGISTERS
OVERVIEW
In this chapter, detailed descriptions of the S3C825A control registers are presented in an easy-to-read format.
You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates
the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
The locations and read/write characteristics of all mapped registers in the S3C825A register file are listed in
Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “RESET and Power-
Down."
Table 4-1. Set 1 Registers (INTPND/STPCON/OSCCON are in bank 0 of set 1)
Register Name
Mnemonic
Address
Decimal
R/W
RESET Values (bit)
Hex
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
7
–
0
–
0
0
x
1
1
x
x
x
x
0
x
0
0
6
–
0
–
0
0
x
1
1
x
x
x
x
0
x
–
0
5
0
0
–
0
0
x
0
0
x
x
x
x
0
x
–
0
4
0
0
–
0
0
x
0
0
x
x
x
x
0
x
x
0
3
0
0
0
0
0
x
0
1
x
x
x
x
0
x
x
0
2
0
0
0
0
0
x
–
–
x
x
x
x
0
x
x
0
1
0
0
–
0
0
0
–
–
x
x
x
x
0
x
0
0
0
0
0
0
0
0
0
–
–
x
x
x
x
0
x
0
0
Interrupt pending register
STOP control register
Oscillator control register
Basic timer control register
System clock control register
System flags register
INTPND
STPCON
OSCCON
BTCON
CLKCON
FLAGS
RP0
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Register pointer 0
Register pointer 1
RP1
Stack pointer (high byte)
Stack pointer (low byte)
Instruction pointer (high byte)
Instruction pointer (low byte)
Interrupt request register
Interrupt mask register
System mode register
Register page pointer
SPH
SPL
IPH
IPL
IRQ
IMR
R/W
R/W
R/W
SYM
PP
4-1
CONTROL REGISTERS
Register Name
S3C825A/P825A
Table 4-2. Set 1, Bank 0 Registers
Mnemonic
Address
Decimal
R/W
RESETB Value(bit)
Hex
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
7
0
0
0
0
1
0
0
0
1
1
–
0
0
1
0
–
x
6
0
0
0
0
1
0
0
0
1
1
–
0
0
1
0
–
x
5
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
4
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
3
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
2
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
SIO Control Register
SIOCON
SIODATA
SIOPS
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
R/W
R/W
R/W
R
SIO Data Register
SIO Prescaler Register
Timer 0 Counter Register
Timer 0 Data Register
T0CNT
T0DATA
T0CON
TBCNT
R/W
R/W
R
Timer 0 Control Register
Timer B Counter Register
Timer A Counter Register
Timer B Data Register
TACNT
R
TBDATA
TADATA
TBCON
TACON
T2CNT
R/W
R/W
R/W
R/W
R
Timer A Data Register
Timer B Control Register
Timer 1/A Control Register
Timer 2 Counter Register
Timer 2 Data Register
T2DATA
T2CON
ADCON
ADDATAH
ADDATAL
LCON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Timer 2 Control Register
A/D Converter Control Register
A/D Converter Data Register (high byte)
A/D Converter Data Register (low byte)
LCD Control Register
–
0
–
0
0
1
1
0
x
–
0
–
0
0
1
1
0
x
–
–
–
0
0
1
1
0
x
–
–
–
0
0
1
1
0
x
–
0
0
0
0
1
1
0
x
–
0
0
0
0
1
1
0
x
x
x
0
0
0
0
1
1
0
x
0
0
0
0
1
1
0
x
LCD Mode Register
LMOD
Timer 3 Counter (high byte)
Timer 3 Counter (low byte)
Timer 3 Data Register (high byte)
T3CNTH
T3CNTL
T3DATAH
R
R/W
R/W
R/W
R/W
Timer 3 Data Register (low byte) T3DATAL
Timer 3 Control Register
UART data register
T3CON
UDATA
UART control register
UARTCON
BRDATA
250
251
FAH
FBH
R/W
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UART Baud Rate data register
Location FCH is not mapped.
BTCNT 253 FDH
Location FEH is not mapped.
IPR 255 FFH
Basic Timer Counter
R/W
R/W
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
Interrupt Priority Register
4-2
S3C825A/P825A
CONTROL REGISTER
RESETB Value(bit)
Table 4-3. Set 1, Bank 1 Registers
Register Name
Mnemonic
Address
Decimal
R/W
Hex
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 2 Control Register(High Byte)
Port 2 Control Register(Low Byte)
Port 2 Pull-up Resistors enable Register
Port 2 Interrupt Control Register
Port 3 Control Register(High Byte)
Port 3 Control Register(Low Byte)
Port 3 Pull-up Resistors enable Register
Port 4 Interrupt Edge Selection Register
Port 4 Control Register(High Byte)
Port 4 Control Register(Low Byte)
Port 4 Interrupt Control Register
Port 4 Interrupt Pending Register
Port 5 Control Register(High Byte)
Port 5 Control Register(Low Byte)
Port 5 Pull-up Resistors enable Register
Watch timer control register
Port 0 Data Register
P2CONH
P2CONL
P2PUR
P2INT
P3CONH
P3CONL
P3PUR
P4EDGE
P4CONH
P4CONL
P4INT
P4PND
P5CONH
P5CONL
P5PUR
WTCON
P0
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
251
252
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 Data Register
P1
Port 2 Data Register
P2
Port 3 Data Register
P3
Port 4 Data Register
P4
Port 5 Data Register
P5
Port 6 Data Register
P6
Port 7 Data Register
P7
Port 8 Data Register
P8
Port Group 0 Control Register
Port Group 1 Control Register
PG0CON
PG1CON
Locations FBH-FFH are not mapped.
4-3
CONTROL REGISTERS
S3C825A/P825A
Bit number(s) that is/are appended to
the register name for bit addressing
Name of individual
bit or related bits
Register location
in the internal
register file
Register address
(hexadecimal)
Register ID
Register name
FLAGS
-
System Flags Register
D5H
Set 1
Bit Identifier
RESET Value
Read/Write
Bit Addressing
Mode
.7
x
.6
x
.5
x
.4
x
.3
x
.2
.1
.0
0
x
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register addressing mode only
.7
Carry Flag (C)
Operation does not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit 7
0
0
.6
.5
Zero Flag (Z)
Operation result is a non-zero value
Operation result is zero
0
0
Sign Flag (S)
Operation generates positive number (MSB = "0")
0
0
Operation generates negative number (MSB = "1")
R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used
Description of the
effect of specific
bit settings
Bit number:
MSB = Bit 7
LSB = Bit 0
Type of addressing
that must be used to
address the bit
RESET value notation:
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
(1-bit, 4-bit, or 8-bit)
'1' = Logic one
Figure 4-1. Register Description Format
4-4
S3C825A/P825A
CONTROL REGISTER
ADCON — A/D Converter Control Register
EFH
Set 1, Bank 0
Bit Identifier
.7
–
.6
–
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
–
R/W
R/W
R
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
Not used for the S3C825A
A/D Input Pin Selection Bits
0
0
1
1
0
1
0
1
AD0 (P3.0)
AD1 (P3.1)
AD2 (P3.2)
AD3 (P3.3)
.3
End-of-Conversion Bit (read-only)
0
1
Conversion not complete
Conversion complete
.2–.1
Clock Source Selection Bits
0
0
1
1
0
1
0
1
fxx/16
fxx/8
fxx/4
fxx
.0
Start or Enable Bit
0
1
Disable operation
Start operation (automatically disable operation after conversion complete).
4-5
CONTROL REGISTERS
S3C825A/P825A
BTCON — Basic Timer Control Register
D3H
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.4
.3–.2
Watchdog Timer Function Disable Code (for System Reset)
1
0
1
0
Disable watchdog timer function
Enable watchdog timer function
Others
Basic Timer Input Clock Selection Bits
fxx/4096 (3)
fxx/1024
fxx/128
0
0
1
1
0
1
0
1
fxx/16
Basic Timer Counter Clear Bit (1)
.1
0
1
No effect
Clear the basic timer counter value
Clock Frequency Divider Clear Bit for all Timers (2)
.0
0
1
No effect
Clear both clock frequency dividers
NOTES:
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to “00H”. Immediately following the write
operation, the BTCON.1 value is automatically cleared to “0”.
2. When you write a “1” to BTCON.0, the corresponding frequency divider is cleared to “00H”. Immediately following the
write operation, the BTCON.0 value is automatically cleared to “0”.
3. The fxx is selected clock for system.
4-6
S3C825A/P825A
CONTROL REGISTER
CLKCON— System Clock Control Register
D4H
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
–
–
R/W
R/W
–
–
–
Addressing Mode
Register addressing mode only
.7
Oscillator IRQ Wake-up Function Bit
0
1
Enable IRQ for main wake-up in power down mode
Disable IRQ for main wake-up in power down mode
.6–.5
.4–.3
Not used for the S3C825A.
CPU Clock (System Clock) Selection Bits (note)
0
0
1
1
0
1
0
1
fxx/16
fxx/8
fxx/2
fxx
.2–.0
Not used for the S3C825A.
NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load
the appropriate values to CLKCON.3 and CLKCON.4.
4-7
CONTROL REGISTERS
S3C825A/P825A
FLAGS— System Flags Register
D5H
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
Carry Flag (C)
0
1
Operation does not generate a carry or borrow condition
Operation generates a carry-out or borrow into high-order bit 7
Zero Flag (Z)
0
1
Operation result is a non-zero value
Operation result is zero
Sign Flag (S)
0
1
Operation generates a positive number (MSB = "0")
Operation generates a negative number (MSB = "1")
Overflow Flag (V)
0
1
Operation result is £ +127 or ³ –128
Operation result is > +127 or < –128
Decimal Adjust Flag (D)
0
1
Add operation completed
Subtraction operation completed
Half-Carry Flag (H)
0
1
No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
Fast Interrupt Status Flag (FIS)
0
1
Interrupt return (IRET) in progress (when read)
Fast interrupt service routine in progress (when read)
Bank Address Selection Flag (BA)
0
1
Bank 0 is selected
Bank 1 is selected
4-8
S3C825A/P825A
CONTROL REGISTER
IMR— Interrupt Mask Register
DDH
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
Interrupt Level 7 (IRQ7) Enable Bit; P4.0-P4.3
Disable (mask)
0
1
Enable (unmask)
Interrupt Level 6 (IRQ6) Enable Bit; P4.4-P4.7
Disable (mask)
0
1
Enable (unmask)
Interrupt Level 5 (IRQ5) Enable Bit; P2.4-P2.7
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 4 (IRQ4) Enable Bit; Watch Timer
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 3 (IRQ3) Enable Bit; SIO, UART Transmit, UART Receive
0
1
Disable (mask)
Enable (unmask)
.2
.1
.0
Interrupt Level 2 (IRQ2) Enable Bit;Timer 2, Timer 3 match/capture or overflow
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 1 (IRQ1) Enable Bit; Timer B, Timer 1/A
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture or Overflow
0
1
Disable (mask)
Enable (unmask)
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
4-9
CONTROL REGISTERS
S3C825A/P825A
INTPND— Interrupt Pending Register
D0H
Set 1, Bank 0
Bit Identifier
.7
–
.6
–
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5
Not used for the S3C825A
Rx Interrupt Pending Bit (for UART)
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
.4
.3
.2
.1
.0
Tx Interrupt Pending Bit (for UART)
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
Timer 3 Match/Capture Interrupt Pending Bit
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
Timer 3 Overflow Interrupt Pending bit
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
Timer 0 Match/Capture Interrupt Pending Bit
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
Timer 0 Overflow Interrupt Pending bit
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
4-10
S3C825A/P825A
CONTROL REGISTER
IPH— Instruction Pointer (High Byte)
DAH
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).
IPL— Instruction Pointer (Low Byte)
DBH
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).
4-11
CONTROL REGISTERS
S3C825A/P825A
IPR— Interrupt Priority Register
FFH
Set 1, Bank 0
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
.0
x
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Priority Control Bits for Interrupt Groups A, B, and C (note)
.7, .4, and .1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Group priority undefined
B > C > A
A > B > C
B > A > C
C > A > B
C > B > A
A > C > B
Group priority undefined
.6
.5
.3
.2
.0
Interrupt Subgroup C Priority Control Bit
0
1
IRQ6 > IRQ7
IRQ7 > IRQ6
Interrupt Group C Priority Control Bit
0
1
IRQ5 > (IRQ6, IRQ7)
(IRQ6, IRQ7) > IRQ5
Interrupt Subgroup B Priority Control Bit
0
1
IRQ3 > IRQ4
IRQ4 > IRQ3
Interrupt Group B Priority Control Bit
0
1
IRQ2 > (IRQ3, IRQ4)
(IRQ3, IRQ4) > IRQ2
Interrupt Group A Priority Control Bit
0
1
IRQ0 > IRQ1
IRQ1 > IRQ0
NOTE: Interrupt Group A - IRQ0, IRQ1
Interrupt Group B - IRQ2, IRQ3, IRQ4
Interrupt Group C - IRQ5, IRQ6, IRQ7
4-12
S3C825A/P825A
CONTROL REGISTER
IRQ— Interrupt Request Register
DCH
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R
R
R
R
R
R
R
R
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
Level 7 (IRQ7) Request Pending Bit; External Interrupt P4.0-P4.3
0
1
Not pending
Pending
Level 6 (IRQ6) Request Pending Bit; External Interrupt P4.4-P4.7
0
1
Not pending
Pending
Level 5 (IRQ5) Request Pending Bit; External Interrupt P2.4-P2.7
0
1
Not pending
Pending
Level 4 (IRQ4) Request Pending Bit; Watch Timer
0
1
Not pending
Pending
Level 3 (IRQ3) Request Pending Bit; SIO, UART Transmit, UART Receive
0
1
Not pending
Pending
Level 2 (IRQ2) Request Pending Bit; Timer 2, Timer 3 Match/Capture or
Overflow
0
1
Not pending
Pending
.1
.0
Level 1 (IRQ1) Request Pending Bit; Timer B, Timer 1/A
0
1
Not pending
Pending
Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow
0
1
Not pending
Pending
4-13
CONTROL REGISTERS
S3C825A/P825A
LCON — LCD Control Register
F2H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
–
.4
–
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
–
–
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
LCD Display Control Bits
0
0
0
1
Display off, P-Tr off
Normal display (using VLC1 with external voltage), P-Tr off
Normal display (using VLC1 with internal voltage), P-Tr on
1
1
.5 and .4
.3 and .2
Not used for the S3C825A.
LCD Duty and Bias Selection Bits
0
0
1
1
0
1
0
1
1/3 duty, 1/3 bias; COM0–COM2/SEG0–SEG31
1/4 duty, 1/3 bias; COM0–COM3/SEG0–SEG31
1/8 duty, 1/4 bias; COM0–COM7/SEG4–SEG31
1/8 duty, 1/5 bias; COM0–COM7/SEG4–SEG31
.1 and .0
LCD Clock Selection Bits
fw/27 (256 Hz when fw is 32.768 kHz)
fw/26 (512 Hz when fw is 32.768 kHz)
fw/25 (1,024 Hz when fw is 32.768 kHz)
fw/24 (2,048 Hz when fw is 32.768 kHz)
0
0
1
1
0
1
0
1
4-14
S3C825A/P825A
CONTROL REGISTER
LMOD — LCD Mode Control Register
F3H
Set 1, Bank 0
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
–
–
–
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Not used for the S3C825A.
LCD Port Selection Bit
.7-.4
.3–.0
P6.0-
P6.3
P6.4-
P6.7
P7.0- P7.4- P8.0- P0.0- P0.4- P1.0- P1.4-
P7.3
P7.7
P8.3
P0.3
P0.7
P1.3
P1.7
COM COM4-7/
SEG
4-7
SEG
8-11
SEG
SEG
SEG
SEG
SEG
0-3
0 0 0 0 Port
0 0 0 1 COM
0 0 1 0 COM
0 0 1 1 COM
0 1 0 0 COM
0 1 0 1 COM
0 1 1 0 COM
0 1 1 1 COM
1 0 0 0 COM
SEG0-3
12-15 16-19 20-23 24-27 28-31
Port
Port
Port
SEG
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
COM/SEG
COM/SEG
COM/SEG
COM/SEG
COM/SEG
COM/SEG
COM/SEG
COM/SEG
SEG SEG
SEG SEG SEG
SEG SEG SEG SEG
SEG SEG SEG SEG SEG
SEG SEG SEG SEG SEG SEG
SEG SEG SEG SEG SEG SEG SEG
NOTE: The SEG0-SEG3 or COM4-COM7 signals are controlled by LCON.3-.2.
4-15
CONTROL REGISTERS
S3C825A/P825A
OSCCON— Oscillator Control Register
D2H
Set 1, Bank 0
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
0
.2
.1
.0
0
0
–
–
RESET Value
Read/Write
–
–
–
–
R/W
R/W
R/W
.7-.4
.3
Not used for S3C825A
Main Oscillator Control Bit
0
1
Main oscillator RUN
Main oscillator STOP
.2
Sub Oscillator Control Bit
0
1
Sub oscillator RUN
Sub oscillator STOP
.1
.0
Not used for S3C825A
System Clock Selection Bit
0
1
Select main oscillator for system clock
Select sub oscillator for system clock
4-16
S3C825A/P825A
CONTROL REGISTER
P2CONH— Port 2 Control Register (High Byte)
E0H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P2.7/INT3/TBOUT
0
0
1
1
0
1
0
1
Input mode; interrupt on falling edge
Output mode, open-drain
Alternative function (TBOUT)
Output mode, push-pull
P2.6/INT2/TAOUT
0
0
1
1
0
1
0
1
Input mode; interrupt on falling edge
Output mode, open-drain
Alternative function (TAOUT)
Output mode, push-pull
P2.5/INT1/T1CLK
0
0
1
1
0
1
0
1
Input mode (T1CLK); interrupt on falling edge
Output mode, open-drain
Not available
Output mode, push-pull
P2.4/INT0/T0CLK
0
0
1
1
0
1
0
1
Input mode (T0CLK); interrupt on falling edge
Output mode, open-drain
Not available
Output mode, push-pull
4-17
CONTROL REGISTERS
S3C825A/P825A
P2CONL— Port 2 Control Register (Low Byte)
E1H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P2.3/T2OUT
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (T2OUT)
Output mode, push-pull
P2.2/T2CLK
0
0
1
1
0
1
0
1
Input mode (T2CLK)
Output mode, open-drain
Not available
Output mode, push-pull
P2.1
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Not available
Output mode, push-pull
P2.0
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Not available
Output mode, push-pull
4-18
S3C825A/P825A
CONTROL REGISTER
P2PUR— Port 2 Pull-up Control Register
E2H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P2.7 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P2.6 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P2.5 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P2.4 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P2.3 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P2.2 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P2.1 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P2.0 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
4-19
CONTROL REGISTERS
S3C825A/P825A
P2INT— Port 2 Interrupt Control Register
E3H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
Port 2 Interrupt Request Pending Bit (P2.7/INT3)
0
0
1
No interrupt request pending
Clear pending bit (when write)
Interrupt request is pending
.6
.5
Interrupt Control Settings (P2.7/INT3)
0
1
Disable interrupt on P2.7
Enable interrupt at falling edge on P2.7
Port 2 Interrupt Request Pending Bit (P2.6/INT2)
0
0
1
No interrupt request pending
Clear pending bit (when write)
Interrupt request is pending
.4
.3
Interrupt Control Settings (P2.6/INT2)
0
1
Disable interrupt on P2.6
Enable interrupt at falling edge on P2.6
Port 2 Interrupt Request Pending Bit (P2.5/INT1)
0
0
1
No interrupt request pending
Clear pending bit (when write)
Interrupt request is pending
.2
.1
Interrupt Control Settings (P2.5/INT1)
0
1
Disable interrupt on P2.5
Enable interrupt at falling edge on P2.5
Port 2 Interrupt Request Pending Bit (P2.4/INT0)
0
0
1
No interrupt request pending
Clear pending bit (when write)
Interrupt request is pending
.0
Interrupt Control Settings (P2.4/INT0)
0
1
Disable interrupt on P2.4
Enable interrupt at falling edge on P2.4
4-20
S3C825A/P825A
CONTROL REGISTER
P3CONH — Port 3 Control Register (High Byte)
E4H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P3.7/T0OUT/T0PWM/T0CAP
0
0
1
1
0
1
0
1
Input mode (T0CAP)
Output mode, open-drain
Alternative function (T0OUT/T0PWM)
Output mode, push-pull
P3.6/T3OUT/T3PWM/T3CAP
0
0
1
1
0
1
0
1
Input mode (T3CAP)
Output mode, open-drain
Alternative function (T3OUT/T3PWM)
Output mode, push-pull
P3.5/T3CLK
0
0
1
1
0
1
0
1
Input mode(T3CLK)
Output mode, open-drain
Not available
Output mode, push-pull
P3.4
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Not available
Output mode, push-pull
4-21
CONTROL REGISTERS
S3C825A/P825A
P3CONL — Port 3 Control Register (Low Byte)
E5H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P3.3/AD3
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (ADC mode)
Output mode, push-pull
P3.2/AD2
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (ADC mode)
Output mode, push-pull
P3.1/AD1
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (ADC mode)
Output mode, push-pull
P3.0/AD0
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (ADC mode)
Output mode, push-pull
4-22
S3C825A/P825A
CONTROL REGISTER
P3PUR — Port 3 Pull-up Control Register
E6H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
P3.7 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.6 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.5 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.4 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.3 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.2 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
.1
.0
P3.1 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.0 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
4-23
CONTROL REGISTERS
S3C825A/P825A
P4CONH— Port 4 Control Register (High Byte)
E8H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
.1 and .0
P4.7/INT11 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
P4.6/INT10 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
P4.5/INT9 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
P4.4/INT8 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
NOTE: Pins configured as input can be used as interrupt input with noise filter.
4-24
S3C825A/P825A
CONTROL REGISTER
P4CONL— Port 4 Control Register (Low Byte)
E9H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
.1 and .0
P4.3/INT7 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
P4.2/INT6 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
P4.1/INT5 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
P4.0/INT4 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input, pull-up mode
Open-drain output mode
Push-pull output mode
NOTE: Pins configured as input can be used as interrupt input with noise filter.
4-25
CONTROL REGISTERS
S3C825A/P825A
P4EDGE— Port 4 Interrupt Edge Selection Register
E7H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P4.7 External Interrupt (INT11) State Bit
0
1
Falling edge detection
Rising edge detection
P4.6 External Interrupt (INT10) State Bit
0
1
Falling edge detection
Rising edge detection
P4.5 External Interrupt (INT9) State Bit
0
1
Falling edge detection
Rising edge detection
P4.4 External Interrupt (INT8) State Bit
0
1
Falling edge detection
Rising edge detection
P4.3 External Interrupt (INT7) State Bit
0
1
Falling edge detection
Rising edge detection
P4.2 External Interrupt (INT6) State Bit
0
1
Falling edge detection
Rising edge detection
P4.1 External Interrupt (INT5) State Bit
0
1
Falling edge detection
Rising edge detection
P4.0 External Interrupt (INT4) State Bit
0
1
Falling edge detection
Rising edge detection
4-26
S3C825A/P825A
CONTROL REGISTER
P4INT— Port 4 Interrupt Control Register
EAH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P4.7 External Interrupt (INT11) Enable Bit
0
1
Disable interrupt
Enable interrupt
P4.6 External Interrupt (INT10) Enable Bit
0
1
Disable interrupt
Enable interrupt
P4.5 External Interrupt (INT9) Enable Bit
0
1
Disable interrupt
Enable interrupt
P4.4 External Interrupt (INT8) Enable Bit
0
1
Disable interrupt
Enable interrupt
P4.3 External Interrupt (INT7) Enable Bit
0
1
Disable interrupt
Enable interrupt
P4.2 External Interrupt (INT6) Enable Bit
0
1
Disable interrupt
Enable interrupt
P4.1 External Interrupt (INT5) Enable Bit
0
1
Disable interrupt
Enable interrupt
P4.0 External Interrupt (INT4) Enable Bit
0
1
Disable interrupt
Enable interrupt
4-27
CONTROL REGISTERS
S3C825A/P825A
P4PND— Port 4 Interrupt Pending Register
EBH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P4.7 External Interrupt (INT11) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.7 interrupt request is pending (when read)
P4.6 External Interrupt (INT10) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.6 interrupt request is pending (when read)
P4.5 External Interrupt (INT9) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.5 interrupt request is pending (when read)
P4.4 External Interrupt (INT8) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.4 interrupt request is pending (when read)
P4.3 External Interrupt (INT7) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.3 interrupt request is pending (when read)
P4.2 External Interrupt (INT6) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.2 interrupt request is pending (when read)
P4.1 External Interrupt (INT5) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.1 interrupt request is pending (when read)
P4.0 External Interrupt (INT4) Pending Flag
0
1
No interrupt request pending (When read), Clear pending bit (when write)
P4.0 interrupt request is pending (when read)
NOTE: Writing a “1” to an interrupt pending flag (P4PND.0–.7) has no effect.
4-28
S3C825A/P825A
CONTROL REGISTER
P5CONH — Port 5 Control Register (High Byte)
ECH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
TXD output control bit
0
1
Disable TXD output at P5.5
Enable TXD output at P5.5
.6
RXD output control bit
0
1
Disable RXD output at P5.4
Enable RXD output at P5.4
.5–.4
P5.6
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Not available
Output mode, push-pull
.3–.2
.1–.0
P5.5/TXD
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain (TXD output depends on P5CONH.7)
Not available
Output mode, push-pull (TXD output depends on P5CONH.7)
P5.4/RXD
0
0
1
1
0
1
0
1
Input mode (RXD)
Output mode, open-drain (RXD output depends on P5CONH.6)
Not available
Output mode, push-pull (RXD output depends on P5CONH.6)
4-29
CONTROL REGISTERS
S3C825A/P825A
P5CONL — Port 5 Control Register (Low Byte)
EDH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P5.3/BUZ
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (BUZ)
Output mode, push-pull
P5.2/SO
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (SO)
Output mode, push-pull
P5.1/SI
0
0
1
1
0
Input mode (SI)
1
0
1
Output mode, open-drain
Not available
Output mode, push-pull
P5.0/SCK
0
0
1
1
0
1
0
1
Input mode (SCK)
Output mode, open-drain
Alternative function (SCK out)
Output mode, push-pull
4-30
S3C825A/P825A
CONTROL REGISTER
P5PUR — Port 5 Pull-up Control Register
EEH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
Not used for the S3C825A
P5.6 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
.5
.4
.3
.2
.1
.0
P5.5 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P5.4 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P5.3 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P5.2 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P5.1 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P5.0 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
4-31
CONTROL REGISTERS
S3C825A/P825A
PG0CON— Port Group 0 Control Register
F9H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P1.4-1.7/SEG28-31 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P1.0-1.3/SEG24-27 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P0.4-0.7/SEG20-23 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P0.0-0.3/SEG16-19 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
4-32
S3C825A/P825A
CONTROL REGISTER
PG1CON— Port Group 1 Control Register
FAH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P8.0-P8.3/SEG12-15 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P7.4-P7.7/SEG8-11 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P7.0-P7.3/SEG4-7 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P6.0-P6.3/COM0-3 and P6.4-P6.7/COM4-7/SEG0-3 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
4-33
CONTROL REGISTERS
S3C825A/P825A
PP— Register Page Pointer
DFH
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.4
Destination Register Page Selection Bits
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Destination: page 0
Destination: page 1
Destination: page 2
Destination: page 3
Destination: page 4
Destination: page 5
Destination: page 6
Destination: page 7
.3 – .0
Source Register Page Selection Bits
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Source: page 0
Source: page 1
Source: page 2
Source: page 3
Source: page 4
Source: page 5
Source: page 6
Source: page 7
NOTE: In the S3C825A microcontroller, the internal register file is configured as eight pages (Pages 0-7).
The pages 0-6 are used for general purpose register file, and page 4 is used for LCD data register or general
purpose registers.
4-34
S3C825A/P825A
CONTROL REGISTER
RP0— Register Pointer 0
D6H
Set 1
Bit Identifier
.7
1
.6
1
.5
0
.4
0
.3
0
.2
–
.1
–
.0
–
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
–
–
–
Addressing Mode
Register addressing only
.7–.3
.2–.0
Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1, selecting the 8-byte working register
slice C0H–C7H.
Not used for the S3C825A
RP1— Register Pointer 1
D7H
Set 1
Bit Identifier
.7
1
.6
1
.5
0
.4
0
.3
1
.2
–
.1
–
.0
–
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
–
–
–
Addressing Mode
Register addressing only
.7 – .3
Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, selecting the 8-byte working register
slice C8H–CFH.
.2 – .0
Not used for the S3C825A
4-35
CONTROL REGISTERS
S3C825A/P825A
SIOCON— SIO Control Register
E0H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
SIO Shift Clock Selection Bit
.7
.6
.5
.4
0
1
Internal clock (P.S clock)
External clock (SCK)
Data Direction Control Bit
0
1
MSB-first mode
LSB-first mode
SIO Mode Selection Bit
0
1
Receive-only mode
Transmit/receive mode
Shift Clock Edge Selection Bit
0
1
Tx at falling edges, Rx at rising edges
Tx at rising edges, Rx at falling edges
SIO Counter Clear and Shift Start Bit
.3
.2
.1
.0
0
1
No action
Clear 3-bit counter and start shifting
SIO Shift Operation Enable Bit
0
1
Disable shifter and clock counter
Enable shifter and clock counter
SIO Interrupt Enable Bit
0
1
Disable SIO Interrupt
Enable SIO Interrupt
SIO Interrupt Pending Bit
0
0
1
No interrupt pending
Clear pending condition (when write)
Interrupt is pending
4-36
S3C825A/P825A
CONTROL REGISTER
SPH— Stack Pointer (High Byte)
D8H
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Stack Pointer Address (High Byte)
The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer
address (SP15–SP8). The lower byte of the stack pointer value is located in register
SPL (D9H). The SP value is undefined following a reset.
SPL— Stack Pointer (Low Byte)
D9H
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Stack Pointer Address (Low Byte)
The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer
address (SP7–SP0). The upper byte of the stack pointer value is located in register
SPH (D8H). The SP value is undefined following a reset.
4-37
CONTROL REGISTERS
S3C825A/P825A
STPCON— Stop Control Register
D1H
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
STOP Control Bits
1 0 1 0 0 1 0 1 Enable stop instruction
Other values Disable stop instruction
NOTE: Before execute the STOP instruction, set this STPCON register as “10100101b”. Otherwise the STOP
instruction will not execute as well as reset will be generated.
4-38
S3C825A/P825A
CONTROL REGISTER
SYM— System Mode Register
DEH
Set 1
Bit Identifier
.7
0
.6
–
.5
–
.4
x
.3
x
.2
x
.1
0
.0
0
RESET Value
Read/Write
R/W
–
–
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Not used, But you must keep "0"
Not used for the S3C825A
.7
.6–.5
.4–.2
Fast Interrupt Level Selection Bits (1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Fast Interrupt Enable Bit (2)
.1
0
1
Disable fast interrupt processing
Enable fast interrupt processing
Global Interrupt Enable Bit (3)
.0
0
1
Disable all interrupt processing
Enable all interrupt processing
NOTES:
1. You can select only one interrupt level at a time for fast interrupt processing.
2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2-SYM.4.
3. Following a reset, you must enable global interrupt processing by executing an EI instruction
(not by writing a "1" to SYM.0).
4-39
CONTROL REGISTERS
S3C825A/P825A
T0CON— Timer 0 Control Register
E5H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.5
Timer 0 Input Clock Selection Bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fxx/1024
fxx/256
fxx/64
fxx/8
fxx
External clock (T0CLK) falling edge
External clock (T0CLK) rising edge
Counter stop
.4–.3
Timer 0 Operating Mode Selection Bits
0
0
1
1
0
1
0
1
Interval mode
Capture mode (capture on rising edge, counter running, OVF can occur)
Capture mode (capture on falling edge, counter running, OVF can occur)
PWM mode (OVF & match interrupt can occur)
Timer 0 Counter Clear Bit (note)
.2
.1
.0
0
1
No effect
Clear the timer 0 counter (when write)
Timer 0 Match/Capture Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
Timer 0 Overflow Interrupt Enable
0
1
Disable overflow interrupt
Enable overflow interrupt
NOTE: When you write a "1" to T0CON.2, the timer 0 counter value is cleared to "00H". Immediately following the write
operation, the T0CON.2 value is automatically cleared to "0".
4-40
S3C825A/P825A
CONTROL REGISTER
TACON— Timer 1/A Control Register
EBH
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
Timer 1 Operating Mode Selection Bit
0
1
Two 8-bit timers mode (Timer A/B)
One 16-bit timer mode (Timer 1)
.6–.4
Timer 1/A Clock Selection Bits
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
fxx/256
fxx/64
fxx/8
fxx
External clock (T1CLK) rising edge
Timer 1/A Counter Clear Bit (NOTE)
.3
.2
.1
.0
0
1
No effect
Clear the timer 1/A counter (when write)
Timer 1/A Counter Run Enable Bit
0
1
Disable Counter Running
Enable Counter Running
Timer 1/A Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
Timer 1/A Interrupt Pending Bit
0
0
1
No interrupt pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
NOTE: When you write a "1" to TACON.3, the Timer 1/A counter value is cleared to "00H". Immediately following the write
operation, the TACON.3 value is automatically cleared to "0".
4-41
CONTROL REGISTERS
S3C825A/P825A
TBCON— Timer B Control Register
EAH
Set 1, Bank0
Bit Identifier
.7
–
.6
–
.5
0
.4
0
.3
0
.2
.1
.0
0
0
0
RESET Value
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
Not used for the S3C825A
Timer B Clock Selection Bits
0
0
1
1
0
1
0
1
fxx/256
fxx/64
fxx/8
fxx
Timer B Counter Clear Bit (NOTE)
.3
.2
.1
.0
0
1
No effect
Clear the timer B counter (when write)
Timer B Counter Run Enable Bit
0
1
Disable Counter Running
Enable Counter Running
Timer B Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
Timer B Interrupt Pending Bit
0
0
1
No interrupt pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
NOTE: When you write a "1" to TBCON.3, the Timer B counter value is cleared to "00H". Immediately following the write
operation, the TBCON.3 value is automatically cleared to "0".
4-42
S3C825A/P825A
CONTROL REGISTER
T2CON— Timer 2 Control Register
EEH
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.5
Timer 2 Input Clock Selection Bits
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
fxx/256
fxx/64
fxx/8
fxx
External clock (T2CLK) input
.4
.3
Not used for the S3C825A
Timer 2 Counter Clear Bit (Note)
0
1
No effect
Clear the timer 2 counter (when write)
.2
.1
.0
Timer 2 Counter Enable Bit
0
1
Disable counting operation
Enable counting operation
Timer 2 Interrupt Enable Bit
0
1
Disable timer 2 interrupt
Enable timer 2 interrupt
Timer 2 Interrupt Pending Bit
0
0
1
No timer 2 interrupt pending (when read)
Clear timer 2 interrupt pending bit (when write)
T2 interrupt is pending
NOTE: When you write a "1" to T2CON.3, the timer 2 counter value is cleared to "00H". Immediately following the write
operation, the T2CON.3 value is automatically cleared to "0".
4-43
CONTROL REGISTERS
S3C825A/P825A
T3CON— Timer 3 Control Register
F8H
Set 1, Bank0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
.1
.0
0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.5
Timer 3 Input Clock Selection Bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fxx/1024
fxx/256
fxx/64
fxx/8
fxx
External clock (T3CLK) falling edge
External clock (T3CLK) rising edge
Counter stop
.4 - .3
Timer 3 Operating Mode Selection Bits
0
0
1
1
0
1
0
1
Interval mode
Capture mode (capture on rising edge, counter running, OVF can occur)
Capture mode (capture on falling edge, counter running, OVF can occur)
PWM mode (OVF & match interrupt can occur)
Timer 3 Counter Clear Bit (NOTE)
.2
.1
.0
0
1
No effect
Clear the timer 3 counter (when write)
Timer 3 match/capture interrupt enable bit
0
1
Disable interrupt
Enable interrupt
Timer 3 overflow interrupt enable
0
1
Disable overflow interrupt
Enable overflow interrupt
NOTE: When you write a "1" T3CON.2, the timer 3 counter value is cleared to "00H". Immediately following the write
operation, the T3CON.2 value is automatically cleared to "0".
4-44
S3C825A/P825A
CONTROL REGISTER
UARTCON— UART Control Register
FAH
Set 1, Bank0
Bit Identifier
RESET Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
.1
0
.0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 – .6
0
0
1
1
0
1
0
1
Mode 0: shift register (fOSC/(16 ´ (BRDATA + 1))
Mode 1: 8-Bit UART (fOSC/(16 ´ (BRDATA + 1))
Mode 2: 9-Bit UART fOSC/16
Mode 3: 9-Bit UART (fOSC/(16 ´ (BRDATA + 1))
.5
.4
Multiprocessor Communication Enable Bit (for modes 2 and 3 only)
0
1
Disable
Enable
Serial Data Receive Enable Bit
0
1
Disable
Enable
.3
.2
.1
TB8
Location of the 9th data bit to be transmitted in UART mode 2 or 3 (“0” or “1”)
RB8
Location of the 9th data bit to be received in UART mode 2 or 3 (“0” or “1”)
Receive Interrupt Enable Bit
0
1
Disable Rx interrupt
Enable Rx interrupt
.0
Transmit Interrupt Enable Bit
0
1
Disable Tx interrupt
Enable Tx interrupt
NOTES:
1. In mode 2 or 3, if the MCE bit is set to "1" then the receive interrupt will not be activated if the received 9th data bit "0".
In mode 1, if MCE = "1" the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the
MCE bit should be “0”.
2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
3. Rx / Tx interrupt pending bits are in INTPND register.
4-45
CONTROL REGISTERS
S3C825A/P825A
WTCON— Watch Timer Control Register
EFH
Set 1, Bank1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Watch Timer Clock Selection Bit
Select main clock divided by 27 (fx/128)
Select sub clock(fxt)
0
1
.6
Watch Timer Interrupt Enable Bit
0
1
Disable watch timer interrupt
Enable watch timer interrupt
.5-.4
Buzzer Signal Selection Bits
0
0
1
1
0
1
0
1
0.5 kHz
1 kHz
2 kHz
4 kHz
.3-.2
Watch Timer Speed Selection Bits
0
0
1
1
0
1
0
1
Set watch timer interrupt to 1s
Set watch timer interrupt to 0.5s
Set watch timer interrupt to 0.25s
Set watch timer interrupt to 3.91ms
.1
.0
Watch Timer Enable Bit
0
1
Disable watch timer; Clear frequency dividing circuits
Enable watch timer
Watch Timer Interrupt Pending Bit
0
0
1
No interrupt pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
4-46
S3C825A/P825A
INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM88RC
CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt
level has more than one vector address, the vector priorities are established in hardware. A vector address can
be assigned to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The S3C825A interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels
is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by
IPR settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all.
The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors
used for S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the
vector priorities are set in hardware. S3C825A uses twenty three vectors.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.
Each vector can have several interrupt sources. In the S3C825A interrupt structure, there are twenty three
possible interrupt sources.
When a service routine starts, the respective pending bit should be either cleared automatically by hardware or
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method would be used to clear its respective pending bit.
5-1
INTERRUPT STRUCTURE
INTERRUPT TYPES
S3C825A/P825A
The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are
combined to determine the interrupt structure of an individual device and to make full use of its available
interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1,
2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):
Type 1:
Type 2:
Type 3:
One level (IRQn) + one vector (V1) + one source (S1)
One level (IRQn) + one vector (V1) + multiple sources (S1 – Sn)
One level (IRQn) + multiple vectors (V1 – Vn) + multiple sources (S1 – Sn , Sn+1 – Sn+m
)
In the S3C825A microcontroller, two interrupt types are implemented.
Levels
Vectors
Sources
Type 1:
Type 2:
IRQn
V1
S1
S1
IRQn
IRQn
V1
S2
S3
Sn
V1
V2
V3
Vn
S1
Type 3:
NOTES:
S2
S3
Sn
Sn + 1
Sn + 2
Sn + m
1. The number of Sn and Vn value is expandable.
2. In the S3C825A implementation,
interrupt types 1 and 3 are used.
Figure 5-1. S3C8-Series Interrupt Types
5-2
S3C825A/P825A
INTERRUPT STRUCTURE
S3C825A INTERRUPT STRUCTURE
The S3C825A microcontroller supports twenty three interrupt sources. All twenty three of the interrupt sources
have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-
specific interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a
single level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed.
5-3
INTERRUPT STRUCTURE
S3C825A/P825A
Levels
Vectors
Sources
Reset/Clear
100H
H/W
RESET
Basic timer overflow
Timer 0 match/capture
Timer 0 overflow
S/W
E0H
E2H
E4H
E6H
E8H
EAH
ECH
D0H
D2H
IRQ0
IRQ1
H/W,S/W
S/W
Timer B match
S/W
Timer 1/A match
S/W
Timer 2 match
S/W
IRQ2
Timer 3 match/capture
Timer 3 overflow
H/W, S/W
S/W
SIO interrrupt
S/W
IRQ3
IRQ4
UART data transmit
UART data receive
Watch timer
S/W
D4H
D6H
S/W
S/W
D8H
DAH
DBH
DCH
C0H
C2H
C4H
P1.0 external interrupt
P1.1 external interrupt
P1.2 external interrupt
P1.3 external interrupt
P1.4 external interrupt
P1.5 external interrupt
P1.6 external interrupt
S/W
IRQ5
IRQ6
S/W
S/W
S/W
S/W
S/W
S/W
S/W
C6H
C8H
P1.7 external interrupt
P4.0 external interrupt
S/W
S/W
S/W
CAH
CCH
CEH
P4.1 external interrupt
P4.2 external interrupt
P4.3 external interrupt
IRQ7
NOTES:
1. Within a given interrupt level, the low vector address has high priority.
For example, E0H has higher priority than E2H within the level IRQ0 the priorities
within each level are set at the factory.
2. External interrupts are triggered by a rising or falling edge, depending on the
corresponding control register setting.
Figure 5-2. S3C825A Interrupt Structure
5-4
S3C825A/P825A
INTERRUPT STRUCTURE
INTERRUPT VECTOR ADDRESSES
All interrupt vector addresses for the S3C825A interrupt structure are stored in the vector address area of the first
256 bytes of the program memory (ROM).
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be
careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
The program reset address in the ROM is 0100H.
(Decimal)
49,151
(HEX)
BFFFH
48K-byte
Program Memory
Area
100H
FFH
RESET
Address
255
0
Interrupt
Vector Address
Area
00H
Figure 5-3. ROM Vector Address Area
5-5
INTERRUPT STRUCTURE
Vector Address
S3C825A/P825A
Reset/Clear
Table 5-1. Interrupt Vectors
Interrupt Source
Request
Interrupt
Decimal
Value
Hex
Value
Priority in H/W
S/W
Level
Level
256
100H
Basic timer overflow
–
Ö
Ö
RESET
226
224
230
228
236
234
232
212
210
208
214
222
220
218
216
198
196
194
192
206
204
202
200
E2H
E0H
E6H
E4H
ECH
EAH
E8H
D4H
D2H
D0H
D6H
DEH
DCH
DAH
D8H
C6H
C4H
C2H
C0H
CEH
CCH
CAH
C8H
Timer 0 overflow
IRQ0
1
0
1
0
2
1
0
2
1
0
–
3
2
1
0
3
2
1
0
3
2
1
0
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Timer 0 match/capture
Timer 1/A match
IRQ1
IRQ2
Timer B match
Timer 3 overflow
Ö
Timer 3 match/capture
Timer 2 match
UART data receive
UART data transmit
SIO interrupt
IRQ3
Watch timer
IRQ4
IRQ5
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P4.7 external interrupt
P4.6 external interrupt
P4.5 external interrupt
P4.4 external interrupt
P4.3 external interrupt
P4.2 external interrupt
P4.1 external interrupt
P4.0 external interrupt
IRQ6
IRQ7
NOTES:
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.
5-6
S3C825A/P825A
INTERRUPT STRUCTURE
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur according to the established priorities.
NOTE
The system initialization routine executed after a reset must always contain an EI instruction to globally
enable the interrupt structure.
During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.
SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:
— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).
— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).
Table 5-2. Interrupt Control Register Overview
Control Register
ID
R/W
Function Description
Interrupt mask register
IMR
R/W
Bit settings in the IMR register enable or disable interrupt
processing for each of the eight interrupt levels: IRQ0–IRQ7.
Interrupt priority register
IPR
R/W
Controls the relative processing priorities of the interrupt
levels. The eight levels of S3C825A are organized into three
groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is
IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
Interrupt request register
System mode register
IRQ
R
This register contains a request pending bit for each interrupt
level.
SYM
R/W
This register enables/disables fast interrupt processing, and
dynamic global interrupt processing.
NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.
5-7
INTERRUPT STRUCTURE
S3C825A/P825A
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.
The system-level control points in the interrupt structure are:
— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )
— Interrupt level enable/disable settings (IMR register)
— Interrupt level priority settings (IPR register)
— Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing an application program that handles interrupt processing, be sure to include the necessary
register file address (register pointer) information.
EI
S
R
Q
Interrupt Request Register
(Read-only)
Polling
Cycle
RESET
IRQ0-IRQ7,
Interrupts
Interrupt Priority
Register
Vector
Interrupt
Cycle
Interrupt Mask
Register
Global Interrupt Control
(EI, DI or SYM.0
manipulation)
Figure 5-4. Interrupt Function Diagram
5-8
S3C825A/P825A
INTERRUPT STRUCTURE
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by the related peripheral (see Table 5-3).
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Source
Timer 0 overflow
Interrupt Level
Register(s)
Location(s) in Set 1
IRQ0
T0CON
T0CNT
T0DATA
INTPND
E5H, bank 0
E3H, bank 0
E4H, bank 0
D0H, bank 0
Timer 0 match/capture
Timer 1/A match
Timer B match
IRQ1
IRQ2
IRQ3
TACON
TACNT
TADATA
EBH, bank 0
E7H, bank 0
E9H, bank0
TBCON
TBCNT
TBDATA
EAH, bank 0
E6H, bank 0
E8H, bank 0
Timer 3 overflow
Timer 3 match/capture
T3CON
T3CNTH, T3CNTL
T3DATAH, T3DATAL
F8H, bank 0
F4H, F5H, bank 0
F6H, F7H, bank 0
Timer 2 match
T2CON
T2CNT
T2DATA
EEH, bank 0
ECH, bank 0
EDH, bank 0
UART data receive
UART data transmit
UARTCON
UDATA
BRDATA
FAH, bank 0
F9H, bank 0
FBH, bank 0
SIO interrupt
SIOCON
SIODATA
SIOPS
E0H, bank 0
E1H, bank 0
E2H, bank 0
Watch timer
IRQ4
IRQ5
WTCON
EFH, bank 1
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P2CONH
P2INT
E0H, bank 1
E3H, bank 1
P4.7 external interrupt
P4.6 external interrupt
P4.5 external interrupt
P4.4 external interrupt
IRQ6
IRQ7
P4CONH
P4INT
P4PND
P4EDGE
E8H, bank 1
EAH, bank 1
EBH, bank 1
E7H, bank 1
P4.3 external interrupt
P4.2 external interrupt
P4.1 external interrupt
P4.0 external interrupt
P4CONL
P4INT
4PND
E9H, bank 1
EAH, bank 1
EBH, bank 1
E7H, bank 1
P4EDGE
5-9
INTERRUPT STRUCTURE
S3C825A/P825A
SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing (see Figure 5-5).
A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is
undetermined.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be
included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly
to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions
for this purpose.
System Mode Register (SYM)
DEH, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Global interrupt enable bit:
0 = Disable all interrupts processing
1 = Enable all interrupts processing
Always logic "0"
Not used for the Fast interrupt level
S3C825A selection bits:
Fast interrupt enable bit:
0 = Disable fast interrupts processing
1 = Enable fast interrupts processing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Figure 5-5. System Mode Register (SYM)
5-10
S3C825A/P825A
INTERRUPT STRUCTURE
INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit
of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a
level's IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions
using the Register addressing mode.
Interrupt Mask Register (IMR)
DDH, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt level enable bits
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level
NOTE:
Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.
Figure 5-6. Interrupt Mask Register (IMR)
5-11
INTERRUPT STRUCTURE
S3C825A/P825A
INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels
in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore
be written to their required settings by the initialization routine.
When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two
sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5-7):
Group A
Group B
Group C
IRQ0, IRQ1
IRQ2, IRQ3, IRQ3
IRQ5, IRQ6, IRQ7
IPR
IPR
IPR
Group A
Group B
Group C
A1
A2
B1
B2
C1
C2
B21
B22
C21
C22
IRQ0
IRQ1
IRQ2 IRQ3
IRQ4
IRQ5 IRQ6
IRQ7
Figure 5-7. Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B"
would select the relationship C > B > A.
The functions of the other IPR bit settings are as follows:
— IPR.5 controls the relative priorities of group C interrupts.
— Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,
6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.
— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
5-12
S3C825A/P825A
INTERRUPT STRUCTURE
Interrupt Priority Register (IPR)
FFH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Group priority:
D7 D4 D1
Group A
0 = IRQ0 > IRQ1
1 = IRQ1 > IRQ0
Group B
0 = IRQ2 > (IRQ3, IRQ4)
1 = (IRQ3, IRQ4) > IRQ2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 = Undefined
1 = B > C > A
0 = A > B > C
1 = B > A > C
0 = C > A > B
1 = C > B > A
0 = A > C > B
1 = Undefined
Subgroup B
0 = IRQ3 > IRQ4
1 = IRQ4 > IRQ3
Group C
0 = IRQ5 > (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) > IRQ5
Subgroup C
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
Figure 5-8. Interrupt Priority Register (IPR)
5-13
INTERRUPT STRUCTURE
S3C825A/P825A
INTERRUPT REQUEST REGISTER (IRQ)
You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for
all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same
number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued
for that level. A "1" indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of
the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of
specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing
is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.
Interrupt Request Register (IRQ)
DCH, Set 1, Read-only
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt level request pending bits:
0 = Interrupt level is not pending
1 = Interrupt level is pending
Figure 5-9. Interrupt Request Register (IRQ)
5-14
S3C825A/P825A
INTERRUPT STRUCTURE
INTERRUPT PENDING FUNCTION TYPES
Overview
There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the
interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service
routine.
Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is
waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service
routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or
written by application software.
In the S3C825A interrupt structure, the timer 0 overflow interrupt (IRQ0) and Timer 3 overflow interrupt (IRQ2)
belongs to this category of interrupts in which pending condition is cleared automatically by hardware.
Pending Bits Cleared by the Service Routine
The second type of pending bit is the one that should be cleared by program software. The service routine must
clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must
be written to the corresponding pending bit location in the source’s mode or control register.
5-15
INTERRUPT STRUCTURE
S3C825A/P825A
INTERRUPT SOURCE POLLING SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request bit to "1".
2. The CPU polling procedure identifies a pending condition for that source.
3. The CPU checks the source's interrupt level.
4. The CPU generates an interrupt acknowledge signal.
5. Interrupt logic determines the interrupt's vector address.
6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).
7. The CPU continues polling for interrupt requests.
INTERRUPT SERVICE ROUTINES
Before an interrupt request is serviced, the following conditions must be met:
— Interrupt processing must be globally enabled (EI, SYM.0 = "1")
— The interrupt level must be enabled (IMR register)
— The interrupt level must have the highest priority if more than one levels are currently requesting service
— The interrupt must be enabled at the interrupt's source (peripheral control register)
When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.
The CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.
2. Save the program counter (PC) and status flags to the system stack.
3. Branch to the interrupt vector to fetch the address of the service routine.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores
the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.
5-16
S3C825A/P825A
INTERRUPT STRUCTURE
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that
correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:
1. Push the program counter's low-byte value to the stack.
2. Push the program counter's high-byte value to the stack.
3. Push the FLAG register values to the stack.
4. Fetch the service routine's high-byte address from the vector location.
5. Fetch the service routine's low-byte address from the vector location.
6. Branch to the service routine specified by the concatenated 16-bit vector address.
NOTE
A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.
NESTING OF VECTORED INTERRUPTS
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,
you must follow these steps:
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it
occurs).
4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the
previous mask value from the stack (POP IMR).
5. Execute an IRET.
Depending on the application, you may be able to simplify the procedure above to some extent.
INSTRUCTION POINTER (IP)
The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed
interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP
registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).
FAST INTERRUPT PROCESSING
The feature called fast interrupt processing allows an interrupt within a given level to be completed in
approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast
interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt
processing for the selected level, you set SYM.1 to “1”.
5-17
INTERRUPT STRUCTURE
S3C825A/P825A
FAST INTERRUPT PROCESSING (Continued)
Two other system registers support fast interrupt processing:
— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the
program counter values), and
— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated
register called FLAGS' ("FLAGS prime").
NOTE
For the S3C825A microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–
IRQ7, can be selected for fast interrupt processing.
Procedure for Initiating Fast Interrupts
To initiate fast interrupt processing, follow these steps:
1. Load the start address of the service routine into the instruction pointer (IP).
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)
3. Write a "1" to the fast interrupt enable bit in the SYM register.
Fast Interrupt Service Routine
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:
1. The contents of the instruction pointer and the PC are swapped.
2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.
3. The fast interrupt status bit in the FLAGS register is set.
4. The interrupt is serviced.
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction
pointer and PC values are swapped back.
6. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.
7. The fast interrupt status bit in FLAGS is cleared automatically.
Relationship to Interrupt Pending Bit Types
As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by
hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the
application program's interrupt service routine. You can select fast interrupt processing for interrupts with either
type of pending condition clear function — by hardware or by software.
Programming Guidelines
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,
including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast
interrupt service routine ends.
5-18
S3C825A/P825A
INSTRUCTION SET
6
INSTRUCTION SET
OVERVIEW
The SAM88RC instruction set is specifically designed to support the large register files that are typical of most
SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of
the instruction set include:
— A full complement of 8-bit arithmetic and logic operations, including multiply and divide
— No special I/O instructions (I/O control/data registers are mapped directly into the register file)
— Decimal adjustment included in binary-coded decimal (BCD) operations
— 16-bit (word) data can be incremented and decremented
— Flexible instructions for bit addressing, rotate, and shift operations
DATA TYPES
The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can
be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least
significant (right-most) bit.
REGISTER ADDRESSING
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory
addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."
ADDRESSING MODES
There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA),
Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please
refer to Section 3, "Addressing Modes."
6-1
INSTRUCTION SET
S3C825A/P825A
Table 6-1. Instruction Group Summary
Operands Instruction
Mnemonic
Load Instructions
CLR
dst
Clear
LD
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst
Load
LDB
Load bit
LDE
Load external data memory
Load program memory
LDC
LDED
LDCD
LDEI
Load external data memory and decrement
Load program memory and decrement
Load external data memory and increment
Load program memory and increment
Load external data memory with pre-decrement
Load program memory with pre-decrement
Load external data memory with pre-increment
Load program memory with pre-increment
Load word
LDCI
LDEPD
LDCPD
LDEPI
LDCPI
LDW
POP
Pop from stack
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
dst,src
dst,src
src
Pop user stack (decrementing)
Pop user stack (incrementing)
Push to stack
dst,src
dst,src
Push user stack (decrementing)
Push user stack (incrementing)
6-2
S3C825A/P825A
INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued)
Operands Instruction
Mnemonic
Arithmetic Instructions
ADC
ADD
CP
dst,src
dst,src
Add with carry
Add
dst,src
dst
Compare
DA
Decimal adjust
Decrement
Decrement word
Divide
DEC
DECW
DIV
dst
dst
dst,src
dst
INC
Increment
INCW
MULT
SBC
SUB
dst
Increment word
Multiply
dst,src
dst,src
dst,src
Subtract with carry
Subtract
Logic Instructions
AND
COM
OR
dst,src
dst
Logical AND
Complement
dst,src
dst,src
Logical OR
XOR
Logical exclusive OR
6-3
INSTRUCTION SET
Mnemonic
S3C825A/P825A
Table 6-1. Instruction Group Summary (Continued)
Operands Instruction
Program Control Instructions
BTJRF
BTJRT
CALL
CPIJE
CPIJNE
DJNZ
ENTER
EXIT
IRET
JP
dst,src
dst,src
dst
Bit test and jump relative on false
Bit test and jump relative on true
Call procedure
dst,src
dst,src
r,dst
Compare, increment and jump on equal
Compare, increment and jump on non-equal
Decrement register and jump on non-zero
Enter
Exit
Interrupt return
cc,dst
dst
Jump on condition code
Jump unconditional
JP
JR
cc,dst
Jump relative on condition code
Next
NEXT
RET
Return
WFI
Wait for interrupt
Bit Manipulation Instructions
BAND
BCP
BITC
BITR
BITS
BOR
BXOR
TCM
TM
dst,src
dst,src
dst
Bit AND
Bit compare
Bit complement
Bit reset
dst
dst
Bit set
dst,src
dst,src
dst,src
dst,src
Bit OR
Bit XOR
Test complement under mask
Test under mask
6-4
S3C825A/P825A
Mnemonic
INSTRUCTION SET
Table 6-1. Instruction Group Summary (Concluded)
Operands Instruction
Rotate and Shift Instructions
RL
dst
dst
dst
dst
dst
dst
Rotate left
RLC
RR
Rotate left through carry
Rotate right
RRC
SRA
SWAP
Rotate right through carry
Shift right arithmetic
Swap nibbles
CPU Control Instructions
CCF
DI
Complement carry flag
Disable interrupts
Enable interrupts
Enter Idle mode
No operation
EI
IDLE
NOP
RCF
SB0
SB1
SCF
Reset carry flag
Set bank 0
Set bank 1
Set carry flag
SRP
src
src
src
Set register pointers
Set register pointer 0
Set register pointer 1
Enter Stop mode
SRP0
SRP1
STOP
6-5
INSTRUCTION SET
S3C825A/P825A
FLAGS REGISTER (FLAGS)
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these
bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and
FLAGS.2 are used for BCD arithmetic.
The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank
address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register
can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For
example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will
occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS)
D5H, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Bank address
status flag (BA)
Carry flag (C)
Fast interrupt
status flag (FIS)
Zero flag (Z)
Sign flag (S)
Half-carry flag (H)
Decimal adjust flag (D)
Overflow flag (V)
Figure 6-1. System Flags Register (FLAGS)
6-6
S3C825A/P825A
INSTRUCTION SET
FLAG DESCRIPTIONS
C
Carry Flag (FLAGS.7)
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to
the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the
specified register. Program instructions can set, clear, or complement the carry flag.
Z
Zero Flag (FLAGS.6)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For
operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is
logic zero.
S
V
D
Sign Flag (FLAGS.5)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the
result. A logic zero indicates a positive number and a logic one indicates a negative number.
Overflow Flag (FLAGS.4)
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than
– 128. It is also cleared to "0" following logic operations.
Decimal Adjust Flag (FLAGS.3)
The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a
subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by
programmers, and cannot be used as a test condition.
H
Half-Carry Flag (FLAGS.2)
The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows
out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous
addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a
program.
FIS Fast Interrupt Status Flag (FLAGS.1)
The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.
When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET
instruction is executed.
BA Bank Address Flag (FLAGS.0)
The BA flag indicates which register bank in the set 1 area of the internal register file is currently
selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0
instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.
6-7
INSTRUCTION SET
S3C825A/P825A
INSTRUCTION SET NOTATION
Table 6-2. Flag Notation Conventions
Flag
C
Z
Description
Carry flag
Zero flag
S
V
D
H
0
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Cleared to logic zero
Set to logic one
1
*
Set or cleared according to operation
Value is unaffected
Value is undefined
–
x
Table 6-3. Instruction Set Symbols
Symbol
dst
src
@
Description
Destination operand
Source operand
Indirect register address prefix
Program counter
PC
IP
Instruction pointer
FLAGS
RP
#
Flags register (D5H)
Register pointer
Immediate operand or register address prefix
Hexadecimal number suffix
Decimal number suffix
Binary number suffix
Opcode
H
D
B
opc
6-8
S3C825A/P825A
Notation
INSTRUCTION SET
Table 6-4. Instruction Notation Conventions
Description Actual Operand Range
cc
r
Condition code
Working register only
See list of condition codes in Table 6-6.
Rn (n = 0–15)
rb
r0
rr
Bit (b) of working register
Rn.b (n = 0–15, b = 0–7)
Rn (n = 0–15)
Bit 0 (LSB) of working register
Working register pair
RRp (p = 0, 2, 4, ..., 14)
reg or Rn (reg = 0–255, n = 0–15)
reg.b (reg = 0–255, b = 0–7)
R
Register or working register
Bit 'b' of register or working register
Register pair or working register pair
Rb
RR
reg or RRp (reg = 0–254, even number only, where
p = 0, 2, ..., 14)
IA
Ir
Indirect addressing mode
addr (addr = 0–254, even number only)
@Rn (n = 0–15)
Indirect working register only
IR
Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)
Irr
Indirect working register pair only
@RRp (p = 0, 2, ..., 14)
IRR
Indirect register pair or indirect working
register pair
@RRp or @reg (reg = 0–254, even only, where
p = 0, 2, ..., 14)
X
Indexed addressing mode
#reg [Rn] (reg = 0–255, n = 0–15)
XS
Indexed (short offset) addressing mode
#addr [RRp] (addr = range –128 to +127, where
p = 0, 2, ..., 14)
xl
Indexed (long offset) addressing mode
#addr [RRp] (addr = range 0–65535, where
p = 0, 2, ..., 14)
da
ra
Direct addressing mode
Relative addressing mode
addr (addr = range 0–65535)
addr (addr = number in the range +127 to –128 that is
an offset relative to the address of the next instruction)
im
Immediate addressing mode
#data (data = 0–255)
iml
Immediate (long) addressing mode
#data (data = range 0–65535)
6-9
INSTRUCTION SET
S3C825A/P825A
Table 6-5. Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
1
2
3
4
5
6
7
DEC
R1
DEC
IR1
ADD
r1,r2
ADD
r1,Ir2
ADD
R2,R1
ADD
IR2,R1
ADD
R1,IM
BOR
r0–Rb
U
P
P
E
R
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC
R1
RLC
IR1
ADC
r1,r2
ADC
r1,Ir2
ADC
R2,R1
ADC
IR2,R1
ADC
R1,IM
BCP
r1.b, R2
INC
R1
INC
IR1
SUB
r1,r2
SUB
r1,Ir2
SUB
R2,R1
SUB
IR2,R1
SUB
R1,IM
BXOR
r0–Rb
JP
IRR1
SRP/0/1
IM
SBC
r1,r2
SBC
r1,Ir2
SBC
R2,R1
SBC
IR2,R1
SBC
R1,IM
BTJR
r2.b, RA
DA
R1
DA
IR1
OR
r1,r2
OR
r1,Ir2
OR
R2,R1
OR
IR2,R1
OR
R1,IM
LDB
r0–Rb
POP
R1
POP
IR1
AND
r1,r2
AND
r1,Ir2
AND
R2,R1
AND
IR2,R1
AND
R1,IM
BITC
r1.b
COM
R1
COM
IR1
TCM
r1,r2
TCM
r1,Ir2
TCM
R2,R1
TCM
IR2,R1
TCM
R1,IM
BAND
r0–Rb
N
I
PUSH
R2
PUSH
IR2
TM
r1,r2
TM
r1,Ir2
TM
R2,R1
TM
IR2,R1
TM
R1,IM
BIT
r1.b
DECW
RR1
DECW
IR1
PUSHUD PUSHUI
IR1,R2
MULT
R2,RR1
MULT
IR2,RR1
MULT
IM,RR1
LD
r1, x, r2
B
B
L
E
IR1,R2
RL
R1
RL
IR1
POPUD
IR2,R1
POPUI
IR2,R1
DIV
R2,RR1
DIV
IR2,RR1
DIV
IM,RR1
LD
r2, x, r1
INCW
RR1
INCW
IR1
CP
r1,r2
CP
r1,Ir2
CP
R2,R1
CP
IR2,R1
CP
R1,IM
LDC
r1, Irr2, xL
CLR
R1
CLR
IR1
XOR
r1,r2
XOR
r1,Ir2
XOR
R2,R1
XOR
IR2,R1
XOR
R1,IM
LDC
r2, Irr2, xL
RRC
R1
RRC
IR1
CPIJE
Ir,r2,RA
LDC
r1,Irr2
LDW
LDW
LDW
LD
r1, Ir2
RR2,RR1 IR2,RR1 RR1,IML
SRA
R1
SRA
IR1
CPIJNE
Irr,r2,RA
LDC
r2,Irr1
CALL
IA1
LD
IR1,IM
LD
Ir1, r2
H
E
X
RR
R1
RR
IR1
LDCD
r1,Irr2
LDCI
r1,Irr2
LD
R2,R1
LD
R2,IR1
LD
R1,IM
LDC
r1, Irr2, xs
SWAP
R1
SWAP
IR1
LDCPD
r2,Irr1
LDCPI
r2,Irr1
CALL
IRR1
LD
IR2,R1
CALL
DA1
LDC
r2, Irr1, xs
6-10
S3C825A/P825A
INSTRUCTION SET
Table 6-5. Opcode Quick Reference (Continued)
OPCODE MAP
LOWER NIBBLE (HEX)
–
8
9
A
B
C
D
E
F
U
P
P
E
R
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
NEXT
ENTER
EXIT
WFI
SB0
SB1
IDLE
STOP
DI
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
N
I
B
B
L
E
EI
RET
IRET
RCF
SCF
CCF
NOP
H
E
X
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
6-11
INSTRUCTION SET
S3C825A/P825A
CONDITION CODES
The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"
after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
Table 6-6. Condition Codes
Binary
Mnemonic
Description
Always false
Flags Set
0000
1000
F
–
T
Always true
–
0111 (note)
1111 (note)
0110 (note)
1110 (note)
1101
C
Carry
C = 1
C = 0
Z = 1
Z = 0
S = 0
S = 1
V = 1
V = 0
Z = 1
Z = 0
NC
Z
No carry
Zero
NZ
PL
MI
OV
Not zero
Plus
0101
Minus
0100
Overflow
1100
NOV
EQ
No overflow
Equal
0110 (note)
1110 (note)
1001
NE
Not equal
GE
Greater than or equal
Less than
(S XOR V) = 0
(S XOR V) = 1
(Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1
C = 0
0001
LT
1010
GT
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
0010
LE
1111 (note)
0111 (note)
1011
UGE
ULT
UGT
ULE
C = 1
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
0011
NOTES:
1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For
example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
6-12
S3C825A/P825A
INSTRUCTION SET
INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction in the SAM8
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
The following information is included in each instruction description:
— Instruction name (mnemonic)
— Full instruction name
— Source/destination format of the instruction operand
— Shorthand notation of the instruction's operation
— Textual description of the instruction's effect
— Specific flag settings affected by the instruction
— Detailed description of the instruction's format, execution time, and addressing mode(s)
— Programming example(s) explaining how to use the instruction
6-13
INSTRUCTION SET
S3C825A/P825A
ADC — Add with carry
ADC
dst,src
Operation:
dst ¬ dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected. Two's-
complement addition is performed. In multiple precision arithmetic, this instruction permits the
carry from the addition of low-order operands to be carried into the addition of high-order
operands.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result
is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
12
13
r
r
r
lr
dst
src
3
3
6
6
14
15
R
R
R
IR
dst
6
16
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:
ADC R1,R2
®
®
®
®
®
R1 = 14H, R2 = 03H
ADC R1,@R2
ADC 01H,02H
ADC 01H,@02H
ADC 01H,#11H
R1 = 1BH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1",
and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds
03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
6-14
S3C825A/P825A
INSTRUCTION SET
ADD — Add
ADD
dst,src
Operation:
dst ¬ dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
02
03
r
r
r
lr
dst
src
3
3
6
6
04
05
R
R
R
IR
dst
6
06
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD R1,R2
®
®
®
®
®
R1 = 15H, R2 = 03H
ADD R1,@R2
ADD 01H,02H
ADD 01H,@02H
ADD 01H,#25H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working
register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H
in register R1.
6-15
INSTRUCTION SET
S3C825A/P825A
AND — Logical AND
AND
dst,src
Operation:
dst ¬ dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits
in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the
source are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
52
53
r
r
r
lr
dst
src
3
3
6
6
54
55
R
R
R
IR
dst
6
56
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND R1,R2
®
®
®
®
®
R1 = 02H, R2 = 03H
AND R1,@R2
AND 01H,02H
AND 01H,@02H
AND 01H,#25H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source
operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
6-16
S3C825A/P825A
INSTRUCTION SET
BAND — Bit AND
BAND
dst,src.b
BAND
dst.b,src
Operation:
dst(0) ¬ dst(0) AND src(b)
or
dst(b) ¬ dst(b) AND src(0)
The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of
the destination (or source). The resultant bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
67
r0
Rb
3
6
67
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four
bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H and register 01H = 05H:
BAND R1,01H.1
BAND 01H.1,R1
®
®
R1 = 06H, register 01H = 05H
Register 01H = 05H, R1 = 07H
In the first example, source register 01H contains the value 05H (00000101B) and destination
working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1
value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the
value 06H (00000110B) in register R1.
6-17
INSTRUCTION SET
S3C825A/P825A
BCP — Bit Compare
BCP
dst,src.b
Operation:
dst(0) – src(b)
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both
operands are unaffected by the comparison.
Flags:
C: Unaffected.
Z: Set if the two bits are the same; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | b | 0
src
3
6
17
r0
Rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H and register 01H = 01H:
BCP
R1,01H.1
®
R1 = 07H, register 01H = 01H
If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of
the source register (01H) and bit zero of the destination register (R1). Because the bit values are
not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).
6-18
S3C825A/P825A
INSTRUCTION SET
BITC — Bit Complement
BITC
dst.b
Operation:
dst(b) ¬ NOT dst(b)
This instruction complements the specified bit within the destination without affecting any other
bits in the destination.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst | b | 0
2
4
57
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H
BITC R1.1
®
R1 = 05H
If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H)
is cleared.
6-19
INSTRUCTION SET
S3C825A/P825A
BITR— Bit Reset
BITR
dst.b
Operation:
dst(b) ¬ 0
The BITR instruction clears the specified bit within the destination without affecting any other bits
in the destination.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst | b | 0
2
4
77
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITR R1.1
®
R1 = 05H
If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one
of the destination register R1, leaving the value 05H (00000101B).
6-20
S3C825A/P825A
INSTRUCTION SET
BITS— Bit Set
BITS
dst.b
Operation:
dst(b) ¬ 1
The BITS instruction sets the specified bit within the destination without affecting any other bits
in the destination.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst | b | 1
2
4
77
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITS R1.3
®
R1 = 0FH
If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit
three of the destination register R1 to "1", leaving the value 0FH (00001111B).
6-21
INSTRUCTION SET
S3C825A/P825A
BOR— Bit OR
BOR
BOR
dst,src.b
dst.b,src
Operation:
dst(0) ¬ dst(0) OR src(b)
or
dst(b) ¬ dst(b) OR src(0)
The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the
destination (or the source). The resulting bit value is stored in the specified bit of the destination.
No other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
07
r0
Rb
3
6
07
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four
bits, the bit address 'b' is three bits, and the LSB address value is one bit.
Examples:
Given: R1 = 07H and register 01H = 03H:
BOR R1, 01H.1
BOR 01H.2, R1
®
®
R1 = 07H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 contains the value 07H (00000111B) and
source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs
bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value
(07H) in working register R1.
In the second example, destination register 01H contains the value 03H (00000011B) and the
source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H
in register 01H.
6-22
S3C825A/P825A
INSTRUCTION SET
BTJRF — Bit Test, Jump Relative on False
BTJRF
dst,src.b
Operation:
If src(b) is a "0", then PC ¬ PC + dst
The specified bit within the source operand is tested. If it is a "0", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRF instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
(Note 1)
dst
src
opc
src | b | 0
dst
3
10
37
RA
rb
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRF SKIP,R1.3
®
PC jumps to SKIP location
If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3"
tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the
memory location pointed to by the SKIP. (Remember that the memory location must be within
the allowed range of + 127 to – 128.)
6-23
INSTRUCTION SET
S3C825A/P825A
BTJRT— Bit Test, Jump Relative on True
BTJRT
dst,src.b
Operation:
If src(b) is a "1", then PC ¬ PC + dst
The specified bit within the source operand is tested. If it is a "1", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRT instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
(Note 1)
dst
src
opc
src | b | 1
dst
3
10
37
RA
rb
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRT
SKIP,R1.1
If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1"
tests bit one in the source register (R1). Because it is a "1", the relative address is added to the
PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the
memory location must be within the allowed range of + 127 to – 128.)
6-24
S3C825A/P825A
INSTRUCTION SET
BXOR— Bit XOR
BXOR
BXOR
dst,src.b
dst.b,src
Operation:
dst(0) ¬ dst(0) XOR src(b)
or
dst(b) ¬ dst(b) XOR src(0)
The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)
of the destination (or source). The result bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
27
r0
Rb
3
6
27
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four
bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):
BXOR R1,01H.1
BXOR 01H.2,R1
®
®
R1 = 06H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 has the value 07H (00000111B) and source
register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs
bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in
bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is
unaffected.
6-25
INSTRUCTION SET
S3C825A/P825A
CALL— Call Procedure
CALL
dst
Operation:
SP
@SP
SP
@SP
PC
¬
¬
¬
¬
¬
SP – 1
PCL
SP –1
PCH
dst
The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The
specified destination address is then loaded into the program counter and points to the first
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used
to return to the original program flow. RET pops the top of the stack back into the program
counter.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
opc
opc
dst
3
14
F6
F4
D4
DA
IRR
IA
dst
dst
2
2
12
14
Examples:
Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:
CALL 3521H ®
SP = 0000H
(Memory locations 0000H = 1AH, 0001H = 4AH, where
4AH is the address that follows the instruction.)
SP = 0000H (0000H = 1AH, 0001H = 49H)
SP = 0000H (0000H = 1AH, 0001H = 49H)
CALL @RR0 ®
CALL #40H
®
In the first example, if the program counter value is 1A47H and the stack pointer contains the
value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the
stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the
value 3521H, the address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack
location 0001H (because the two-byte instruction format was used). The PC is then loaded with
the value 3521H, the address of the first instruction in the program sequence to be executed.
Assuming that the contents of the program counter and stack pointer are the same as in the first
example, if program address 0040H contains 35H and program address 0041H contains 21H, the
statement "CALL #40H" produces the same result as in the second example.
6-26
S3C825A/P825A
INSTRUCTION SET
CCF— Complement Carry Flag
CCF
Operation:
C ¬ NOT C
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic
zero; if C = "0", the value of the carry flag is changed to logic one.
Flags:
C: Complemented.
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
EF
Example:
Given: The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H),
changing its value from logic zero to logic one.
6-27
INSTRUCTION SET
S3C825A/P825A
CLR— Clear
CLR
dst
Operation:
dst ¬ "0"
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
B0
B1
R
IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
CLR
00H
®
Register 00H = 00H
@01H ®
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
6-28
S3C825A/P825A
INSTRUCTION SET
COM— Complement
COM
dst
Operation:
dst ¬ NOT dst
The contents of the destination location are complemented (one's complement); all "1s" are
changed to "0s", and vice-versa.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
60
61
R
IR
Examples:
Given: R1 = 07H and register 07H = 0F1H:
COM R1
®
®
R1 = 0F8H
R1 = 07H, register 07H = 0EH
COM @R1
In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,
and vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value
of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
6-29
INSTRUCTION SET
S3C825A/P825A
CP— Compare
CP
dst,src
Operation:
dst – src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
comparison.
Flags:
C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst |
src
2
4
6
A2
r
r
A3
r
lr
opc
opc
src
dst
dst
src
3
3
6
6
A4
A5
R
R
R
IR
6
A6
R
IM
Examples:
1. Given: R1 = 02H and R2 = 03H:
CP R1,R2 ® Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the
value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1
value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S
are "1".
2. Given: R1 = 05H and R2 = 0AH:
CP
JP
INC
R1,R2
UGE,SKIP
R1
SKIP LD
R3,R1
In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"
and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"
executes, the value 06H remains in working register R3.
6-30
S3C825A/P825A
INSTRUCTION SET
CPIJE— Compare, Increment, and Jump on Equal
CPIJE
dst,src,RA
Operation:
If dst – src = "0", PC ¬ PC + RA
Ir ¬ Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is "0",
the relative address is added to the program counter and control passes to the statement whose
address is now in the program counter. Otherwise, the instruction immediately following the
CPIJE instruction is executed. In either case, the source pointer is incremented by one before
the next instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src dst
RA
3
12
C2
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 02H:
CPIJE R1,@R2,SKIP ®
R2 = 04H, PC jumps to SKIP location
In this example, working register R1 contains the value 02H, working register R2 the value 03H,
and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value
02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that
the memory location must be within the allowed range of + 127 to – 128.)
6-31
INSTRUCTION SET
S3C825A/P825A
CPIJNE— Compare, Increment, and Jump on Non-Equal
CPIJNE
dst,src,RA
Operation:
If dst – src "0", PC ¬ PC + RA
Ir ¬ Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is not
"0", the relative address is added to the program counter and control passes to the statement
whose address is now in the program counter; otherwise the instruction following the CPIJNE
instruction is executed. In either case the source pointer is incremented by one before the next
instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src dst
RA
3
12
D2
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 04H:
CPIJNE
R1,@R2,SKIP ®
R2 = 04H, PC jumps to SKIP location
Working register R1 contains the value 02H, working register R2 (the source pointer) the value
03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts
04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal,
the relative address is added to the PC and the PC then jumps to the memory location pointed to
by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.
(Remember that the memory location must be within the allowed range of + 127 to – 128.)
6-32
S3C825A/P825A
INSTRUCTION SET
DA— Decimal Adjust
DA
dst
Operation:
dst ¬ DA dst
The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table
indicates the operation performed. (The operation is undefined if the destination operand was not
the result of a valid addition or subtraction of BCD digits):
Instruction
Carry
Before DA
Bits 4–7
Value (Hex)
H Flag
Before DA
Bits 0–3
Value (Hex)
Number Added
to Byte
Carry
After DA
0
0
0
0
0
0
1
1
1
0
0
1
1
0–9
0–8
0–9
A–F
9–F
A–F
0–2
0–2
0–3
0–9
0–8
7–F
6–F
0
0
1
0
0
1
0
0
1
0
1
0
1
0–9
A–F
0–3
0–9
A–F
0–3
0–9
A–F
0–3
0–9
6–F
0–9
6–F
00
0
0
0
1
1
1
1
1
1
0
0
1
1
06
06
ADD
ADC
60
66
66
60
66
66
00 = – 00
FA = – 06
A0 = – 60
9A = – 66
SUB
SBC
Flags:
C: Set if there was a carry from the most significant bit; cleared otherwise (see table).
Z: Set if result is "0"; cleared otherwise.
S: Set if result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
40
41
R
IR
6-33
INSTRUCTION SET
S3C825A/P825A
DA— Decimal Adjust
DA
(Continued)
Example:
Given: Working register R0 contains the value 15 (BCD), working register R1 contains
27 (BCD), and address 27H contains 46 (BCD):
ADD
DA
R1,R0
R1
;
;
C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = C, R1 ¬ 3CH
R1 ¬ 3CH + 06
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is
incorrect, however, when the binary representations are added in the destination location using
standard binary arithmetic:
0 0 0 1 0 1 0 1
+ 0 0 1 0 0 1 1 1
15
27
0 0 1 1 1 1 0 0
=
3CH
The DA instruction adjusts this result so that the correct BCD representation is obtained:
0 0 1 1 1 1 0 0
+ 0 0 0 0 0 1 1 0
0 1 0 0 0 0 1 0
=
42
Assuming the same values given above, the statements
SUB
DA
27H,R0 ;
@R1
C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = 1
@R1 ¬ 31–0
;
leave the value 31 (BCD) in address 27H (@R1).
6-34
S3C825A/P825A
INSTRUCTION SET
DEC— Decrement
DEC
dst
Operation:
dst ¬ dst – 1
The contents of the destination operand are decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
00
01
R
IR
Examples:
Given: R1 = 03H and register 03H = 10H:
DEC R1
®
®
R1 = 02H
DEC @R1
Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by
one, leaving the value 0FH.
6-35
INSTRUCTION SET
S3C825A/P825A
DECW— Decrement Word
DECW
dst
Operation:
dst ¬ dst – 1
The contents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value that is decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
80
81
RR
IR
Examples:
Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:
DECW RR0
DECW @R2
®
®
R0 = 12H, R1 = 33H
Register 30H = 0FH, register 31H = 20H
In the first example, destination register R0 contains the value 12H and register R1 the value
34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word
and decrements the value of R1 by one, leaving the value 33H.
NOTE:
A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW
instruction. To avoid this problem, we recommend that you use DECW as shown in the following
example:
LOOP: DECW RR0
LD
OR
JR
R2,R1
R2,R0
NZ,LOOP
6-36
S3C825A/P825A
INSTRUCTION SET
DI— Disable Interrupts
DI
Operation:
SYM (0) ¬ 0
Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,
but the CPU will not service them while interrupt processing is disabled.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
8F
Example:
Given: SYM = 01H:
DI
If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the
register and clears SYM.0 to "0", disabling interrupt processing.
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.
6-37
INSTRUCTION SET
S3C825A/P825A
DIV— Divide (Unsigned)
DIV
dst,src
Operation:
dst ÷ src
dst (UPPER) ¬ REMAINDER
dst (LOWER) ¬ QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)
is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of
8
the destination. When the quotient is ³ 2 , the numbers stored in the upper and lower halves of
the destination for quotient and remainder are incorrect. Both operands are treated as unsigned
integers.
Flags:
C: Set if the V flag is set and quotient is between 28 and 29 –1; cleared otherwise.
Z: Set if divisor or quotient = "0"; cleared otherwise.
S: Set if MSB of quotient = "1"; cleared otherwise.
V: Set if quotient is ³ 28 or if divisor = "0"; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
RR
src
opc
src
dst
3
26/10
26/10
26/10
94
95
96
R
IR
IM
NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.
Examples:
Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:
DIV
DIV
DIV
RR0,R2
®
®
®
R0 = 03H, R1 = 40H
R0 = 03H, R1 = 20H
R0 = 03H, R1 = 80H
RR0,@R2
RR0,#20H
In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains
the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the
destination register RR0 (R0) and the quotient in the lower half (R1).
6-38
S3C825A/P825A
INSTRUCTION SET
DJNZ— Decrement and Jump if Non-Zero
DJNZ
r,dst
Operation:
r ¬ r – 1
If r ¹ 0, PC ¬ PC + dst
The working register being used as a counter is decremented. If the contents of the register are
not logic zero after decrementing, the relative address is added to the program counter and
control passes to the statement whose address is now in the PC. The range of the relative
address is +127 to –128, and the original value of the PC is taken to be the address of the
instruction byte following the DJNZ statement.
NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at
the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
r | opc
dst
2
8 (jump taken)
8 (no jump)
rA
RA
r = 0 to F
Example:
Given: R1 = 02H and LOOP is the label of a relative address:
SRP
#0C0H
DJNZ R1,LOOP
DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the
destination operand instead of a numeric relative address value. In the example, working register
R1 contains the value 02H, and LOOP is the label for a relative address.
The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.
Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative
address specified by the LOOP label.
6-39
INSTRUCTION SET
S3C825A/P825A
EI— Enable Interrupts
EI
Operation:
SYM (0) ¬ 1
An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to
be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was
set while interrupt processing was disabled (by executing a DI instruction), it will be serviced
when you execute the EI instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
9F
Example:
Given: SYM = 00H:
EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the
statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for
global interrupt processing.)
6-40
S3C825A/P825A
INSTRUCTION SET
ENTER— Enter
ENTER
Operation:
SP
@SP
IP
¬
¬
¬
¬
¬
SP – 2
IP
PC
PC
IP
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The contents of the
instruction pointer are pushed to the stack. The program counter (PC) value is then written to the
instruction pointer. The program memory word that is pointed to by the instruction pointer is
loaded into the PC, and the instruction pointer is incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
14
1F
Example:
The diagram below shows one example of how to use an ENTER statement.
Before
After
Data
Address
IP
Data
Address
IP
0050
0040
0022
0043
0110
0020
Address
Data
1F
Address
40 Enter
Data
1F
PC
SP
40 Enter
PC
SP
41 Address H 01
42 Address L 10
43 Address H
41 Address H 01
42 Address L 10
43 Address H
20
21
22
00
50
IPH
IPL
Data
110 Routine
Memory
Memory
22
Data
Stack
Stack
6-41
INSTRUCTION SET
S3C825A/P825A
EXIT— Exit
EXIT
Operation:
IP
¬
¬
¬
¬
@SP
SP
PC
IP
SP + 2
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The stack value is
popped and loaded into the instruction pointer. The program memory word that is pointed to by
the instruction pointer is then loaded into the program counter, and the instruction pointer is
incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode (Hex)
opc
1
14 (internal stack)
16 (internal stack)
2F
Example:
The diagram below shows one example of how to use an EXIT statement.
Before
After
Data
Address
IP
Data
Address
IP
0050
0040
0022
0052
0060
0022
Address
Data
Address
Data
PC
SP
PC
SP
50 PCL old
51 PCH
60
00
60
Main
140 Exit
2F
20
21
22
00
50
IPH
IPL
Data
Memory
Memory
Data
22
Stack
Stack
6-42
S3C825A/P825A
INSTRUCTION SET
IDLE— Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
In application programs, a IDLE instruction must be immediately followed by at least three NOP
instructions. This ensures an adeguate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructons are not used after IDLE instruction,
leakage current could be flown because of the floating state in the internal bus.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
6F
–
–
Example:
The instruction
IDLE
NOP
NOP
NOP
; stops the CPU clock but not the system clock
6-43
INSTRUCTION SET
S3C825A/P825A
INC— Increment
INC
dst
Operation:
dst ¬ dst + 1
The contents of the destination operand are incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
dst | opc
opc
1
4
rE
r
r = 0 to F
dst
2
4
4
20
21
R
IR
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC
INC
INC
R0
®
®
®
R0 = 1CH
00H
@R0
Register 00H = 0DH
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement
"INC R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the
value of register 1BH from 0FH to 10H.
6-44
S3C825A/P825A
INSTRUCTION SET
INCW— Increment Word
INCW
dst
Operation:
dst ¬ dst + 1
The contents of the destination (which must be an even address) and the byte following that
location are treated as a single 16-bit value that is incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
A0
A1
RR
IR
Examples:
Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:
INCW RR0
INCW @R1
®
®
R0 = 1AH, R1 = 03H
Register 02H = 10H, register 03H = 00H
In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H
in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the
value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to
00H and register 02H from 0FH to 10H.
NOTE:
A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an
INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the
following example:
LOOP:
INCW
LD
OR
RR0
R2,R1
R2,R0
NZ,LOOP
JR
6-45
INSTRUCTION SET
S3C825A/P825A
IRET— Interrupt Return
IRET
IRET (Normal)
IRET (Fast)
Operation:
FLAGS ¬ @SP
SP ¬ SP + 1
PC ¬ @SP
PC « IP
FLAGS ¬ FLAGS'
FIS ¬
0
SP ¬ SP + 2
SYM(0) ¬
1
This instruction is used at the end of an interrupt service routine. It restores the flag register and
the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the
fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast
interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.
Flags:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
Bytes
Cycles
Opcode (Hex)
IRET
(Normal)
opc
1
10 (internal stack)
12 (internal stack)
BF
Bytes
Cycles
Opcode (Hex)
IRET
(Fast)
opc
1
6
BF
Example:
In the figure below, the instruction pointer is initially loaded with 100H in the main program
before interrupts are enabled. When an interrupt occurs, the program counter and instruction
pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return
address. The last instruction in the service routine normally is a jump to IRET at address FFH.
This causes the instruction pointer to be loaded with 100H "again" and the program counter to
jump back to the main program. Now, the next interrupt can occur and the IP is still correct at
100H.
0H
FFH
IRET
100H
Interrupt
Service
Routine
JP to FFH
FFFFH
NOTE:
In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay
attention to the order of the last two instructions. The IRET cannot be immediately proceeded by
a clearing of the interrupt status (as with a reset of the IPR register).
6-46
S3C825A/P825A
INSTRUCTION SET
JP— Jump
JP
cc,dst
(Conditional)
JP
dst
(Unconditional)
Operation:
If cc is true, PC ¬ dst
The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
instruction is executed. The unconditional JP simply replaces the contents of the PC with the
contents of the specified register pair. Control then passes to the statement addressed by the
PC.
Flags:
No flags are affected.
Format: (1)
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(2)
cc | opc
dst
3
8
ccD
DA
cc = 0 to F
opc
dst
2
8
30
IRR
NOTES:
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the
opcode are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
JP
C,LABEL_W
@00H
®
®
LABEL_W = 1000H, PC = 1000H
PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the
statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents
of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6-47
INSTRUCTION SET
S3C825A/P825A
JR— Jump Relative
JR
cc,dst
Operation:
If cc is true, PC ¬ PC + dst
If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program
counter; otherwise, the instruction following the JR instruction is executed. (See list of condition
codes).
The range of the relative address is +127, –128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(1)
cc | opc
dst
2
6
ccB
RA
cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each
four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H:
JR
C,LABEL_X
®
PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will
pass control to the statement whose address is now in the PC. Otherwise, the program
instruction following the JR would be executed.
6-48
S3C825A/P825A
INSTRUCTION SET
LD— Load
LD
dst,src
Operation:
dst ¬ src
The contents of the source are loaded into the destination. The source's contents are unaffected.
No flags are affected.
Flags:
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
IM
R
dst | opc
src | opc
opc
src
dst
2
4
4
rC
r8
r
r
2
2
3
3
4
r9
R
r
r = 0 to F
dst | src
4
4
C7
D7
r
lr
r
Ir
opc
src
dst
src
6
6
E4
E5
R
R
R
IR
opc
dst
6
6
E6
D6
R
IM
IM
IR
opc
opc
opc
src
dst
x
3
3
3
6
6
6
F5
87
97
IR
r
R
x [r]
r
dst | src
src | dst
x
x [r]
6-49
INSTRUCTION SET
S3C825A/P825A
LD— Load
LD
(Continued)
Examples:
Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
R0,#10H
R0,01H
®
®
®
®
®
®
®
®
®
®
R0 = 10H
R0 = 20H, register 01H = 20H
Register 01H = 01H, R0 = 01H
R1 = 20H, R0 = 01H
01H,R0
R1,@R0
@R0,R1
00H,01H
02H,@00H
00H,#0AH
@00H,#10H
@00H,02H
R0 = 01H, R1 = 0AH, register 01H = 0AH
Register 00H = 20H, register 01H = 20H
Register 02H = 20H, register 00H = 01H
Register 00H = 0AH
Register 00H = 01H, register 01H = 10H
Register 00H = 01H, register 01H = 02, register 02H = 02H
R0 = 0FFH, R1 = 0AH
R0,#LOOP[R1] ®
#LOOP[R0],R1 ®
Register 31H = 0AH, R0 = 01H, R1 = 0AH
6-50
S3C825A/P825A
INSTRUCTION SET
LDB— Load Bit
LDB
dst,src.b
LDB
dst.b,src
Operation:
dst(0) ¬ src(b)
or
dst(b) ¬ src(0)
The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the
source is loaded into the specified bit of the destination. No other bits of the destination are
affected. The source is unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
47
r0
Rb
3
6
47
Rb
r0
NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the
bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R0 = 06H and general register 00H = 05H:
LDB
LDB
R0,00H.2
00H.0,R0
®
®
R0 = 07H, register 00H = 05H
R0 = 06H, register 00H = 04H
In the first example, destination working register R0 contains the value 06H and the source
general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the
00H register into bit zero of the R0 register, leaving the value 07H in register R0.
In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit
zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in
general register 00H.
6-51
INSTRUCTION SET
S3C825A/P825A
LDC/LDE— Load Memory
LDC/LDE
dst,src
Operation:
dst ¬ src
This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory.
The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd
number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
1.
2.
3.
4.
5.
opc
opc
opc
opc
opc
dst | src
src | dst
dst | src
src | dst
dst | src
2
10
C3
D3
E7
F7
A7
r
Irr
2
3
3
4
10
12
12
14
Irr
r
XS
XS
r
XS [rr]
r
XS [rr]
r
XLL
XLH
XLH
DAH
DAH
DAH
DAH
XL [rr]
XLL
DAL
DAL
DAL
DAL
6.
7.
8.
9.
opc
opc
opc
opc
src | dst
dst | 0000
src | 0000
dst | 0001
src | 0001
4
4
4
4
4
14
14
14
14
14
B7
A7
B7
A7
B7
XL [rr]
r
DA
r
r
DA
r
DA
r
10.
opc
DA
NOTES:
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one
byte.
3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two
bytes.
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set
of values, used in formats 9 and 10, are used to address data memory.
6-52
S3C825A/P825A
INSTRUCTION SET
LDC/LDE— Load Memory
LDC/LDE
(Continued)
Examples:
Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory
locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:
LDC
R0,@RR2
; R0 ¬ contents of program memory location 0104H
; R0 = 1AH, R2 = 01H, R3 = 04H
LDE
R0,@RR2
; R0 ¬ contents of external data memory location 0104H
; R0 = 2AH, R2 = 01H, R3 = 04H
LDC (note) @RR2,R0
; 11H (contents of R0) is loaded into program memory
; location 0104H (RR2),
; working registers R0, R2, R3 ® no change
LDE
LDC
LDE
@RR2,R0
; 11H (contents of R0) is loaded into external data memory
; location 0104H (RR2),
; working registers R0, R2, R3 ® no change
R0,#01H[RR2]
R0,#01H[RR2]
; R0 ¬ contents of program memory location 0105H
; (01H + RR2),
; R0 = 6DH, R2 = 01H, R3 = 04H
; R0 ¬ contents of external data memory location 0105H
; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H
LDC (note) #01H[RR2],R0
; 11H (contents of R0) is loaded into program memory location
; 0105H (01H + 0104H)
LDE
LDC
LDE
#01H[RR2],R0
; 11H (contents of R0) is loaded into external data memory
; location 0105H (01H + 0104H)
R0,#1000H[RR2] ; R0 ¬ contents of program memory location 1104H
; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
R0,#1000H[RR2] ; R0 ¬ contents of external data memory location 1104H
; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
LDC
LDE
R0,1104H
R0,1104H
; R0 ¬ contents of program memory location 1104H, R0 = 88H
; R0 ¬ contents of external data memory location 1104H,
; R0 = 98H
LDC (note) 1105H,R0
; 11H (contents of R0) is loaded into program memory location
; 1105H, (1105H) ¬ 11H
LDE
1105H,R0
; 11H (contents of R0) is loaded into external data memory
; location 1105H, (1105H) ¬ 11H
NOTE: These instructions are not supported by masked ROM type devices.
6-53
INSTRUCTION SET
S3C825A/P825A
LDCD/LDED— Load Memory and Decrement
LDCD/LDED dst,src
Operation:
dst ¬ src
rr ¬ rr – 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E2
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:
LDCD
R8,@RR6
; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is decremented by one
; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ¬ RR6 – 1)
LDED
R8,@RR6
; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is decremented by one (RR6 ¬ RR6 – 1)
; R8 = 0DDH, R6 = 10H, R7 = 32H
6-54
S3C825A/P825A
INSTRUCTION SET
LDCI/LDEI— Load Memory and Increment
LDCI/LDEI
dst,src
Operation:
dst ¬ src
rr ¬ rr + 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler
makes 'Irr' even for program memory and odd for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E3
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI
R8,@RR6
; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)
; R8 = 0CDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)
; R8 = 0DDH, R6 = 10H, R7 = 34H
6-55
INSTRUCTION SET
S3C825A/P825A
LDCPD/LDEPD— Load Memory with Pre-Decrement
LDCPD/
LDEPD
dst,src
Operation:
rr ¬ rr – 1
dst ¬ src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is
first decremented. The contents of the source location are then loaded into the destination
location. The contents of the source are unaffected.
LDCPD refers to program memory and LDEPD refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for external data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src | dst
2
14
F2
Irr
r
Examples:
Given: R0 = 77H, R6 = 30H, and R7 = 00H:
LDCPD @RR6,R0
; (RR6 ¬ RR6 – 1)
; 77H (contents of R0) is loaded into program memory location
; 2FFFH (3000H – 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH
LDEPD @RR6,R0
; (RR6 ¬ RR6 – 1)
; 77H (contents of R0) is loaded into external data memory
; location 2FFFH (3000H – 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH
6-56
S3C825A/P825A
INSTRUCTION SET
LDCPI/LDEPI— Load Memory with Pre-Increment
LDCPI/
LDEPI
dst,src
Operation:
rr ¬ rr + 1
dst ¬ src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is
first incremented. The contents of the source location are loaded into the destination location.
The contents of the source are unaffected.
LDCPI refers to program memory and LDEPI refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src | dst
2
14
F3
Irr
r
Examples:
Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:
LDCPI
@RR6,R0
; (RR6 ¬ RR6 + 1)
; 7FH (contents of R0) is loaded into program memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H
LDEPI
@RR6,R0
; (RR6 ¬ RR6 + 1)
; 7FH (contents of R0) is loaded into external data memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H
6-57
INSTRUCTION SET
S3C825A/P825A
LDW— Load Word
LDW
dst,src
Operation:
dst ¬ src
The contents of the source (a word) are loaded into the destination. The contents of the source
are unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
src
RR
IR
opc
opc
src
dst
dst
3
8
8
C4
C5
src
4
8
C6
RR
IML
Examples:
Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,
register 01H = 02H, register 02H = 03H, and register 03H = 0FH:
LDW
LDW
RR6,RR4
00H,02H
®
®
R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH
Register 00H = 03H, register 01H = 0FH,
register 02H = 03H, register 03H = 0FH
LDW
LDW
LDW
LDW
RR2,@R7
®
®
®
®
R2 = 03H, R3 = 0FH,
04H,@01H
RR6,#1234H
02H,#0FEDH
Register 04H = 03H, register 05H = 0FH
R6 = 12H, R7 = 34H
Register 02H = 0FH, register 03H = 0EDH
In the second example, please note that the statement "LDW 00H,02H" loads the contents of
the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in
general register 00H and the value 0FH in register 01H.
The other examples show how to use the LDW instruction with various addressing modes and
formats.
6-58
S3C825A/P825A
INSTRUCTION SET
MULT— Multiply (Unsigned)
MULT
dst,src
Operation:
dst ¬ dst ´ src
The 8-bit destination operand (even register of the register pair) is multiplied by the source
operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination
address. Both operands are treated as unsigned integers.
Flags:
C: Set if result is > 255; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if MSB of the result is a "1"; cleared otherwise.
V: Cleared.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
RR
src
opc
src
dst
3
22
22
22
84
85
86
R
IR
IM
Examples:
Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:
MULT
MULT
MULT
00H, 02H
®
®
®
Register 00H = 01H, register 01H = 20H, register 02H = 09H
Register 00H = 00H, register 01H = 0C0H
00H, @01H
00H, #30H
Register 00H = 06H, register 01H = 00H
In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in
the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The
16-bit product, 0120H, is stored in the register pair 00H, 01H.
6-59
INSTRUCTION SET
S3C825A/P825A
NEXT— Next
NEXT
Operation:
PC ¬ @ IP
IP ¬ IP + 2
The NEXT instruction is useful when implementing threaded-code languages. The program
memory word that is pointed to by the instruction pointer is loaded into the program counter. The
instruction pointer is then incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
10
0F
Example:
The following diagram shows one example of how to use the NEXT instruction.
Before
After
Data
Address
IP
Data
Address
IP
0043
0120
0045
0130
Address
Data
Address
43 Address H
Data
PC
43 Address H 01
PC
44 Address L 10
45 Address H
44 Address L
45 Address H
120 Next
Memory
130 Routine
Memory
6-60
S3C825A/P825A
INSTRUCTION SET
NOP— No Operation
NOP
Operation:
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
FF
Example:
When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction
execution time.
6-61
INSTRUCTION SET
S3C825A/P825A
OR— Logical OR
OR
dst,src
Operation:
dst ¬ dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
42
43
r
r
r
lr
dst
src
3
3
6
6
44
45
R
R
R
IR
dst
6
46
R
IM
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and
register 08H = 8AH:
OR
OR
OR
OR
OR
R0,R1
®
®
®
®
®
R0 = 3FH, R1 = 2AH
R0,@R2
00H,01H
01H,@00H
00H,#02H
R0 = 37H, R2 = 01H, register 01H = 37H
Register 00H = 3FH, register 01H = 37H
Register 00H = 08H, register 01H = 0BFH
Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value
2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the
result (3FH) in destination register R0.
The other examples show the use of the logical OR instruction with the various addressing
modes and formats.
6-62
S3C825A/P825A
INSTRUCTION SET
POP— Pop From Stack
POP
dst
Operation:
dst ¬ @SP
SP ¬ SP + 1
The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags:
No flags affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
50
51
R
IR
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH,
and stack register 0FBH = 55H:
POP
POP
00H
®
®
Register 00H = 55H, SP = 00FCH
@00H
Register 00H = 01H, register 01H = 55H, SP = 00FCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H"
loads the contents of location 00FBH (55H) into destination register 00H and then increments the
stack pointer by one. Register 00H then contains the value 55H and the SP points to location
00FCH.
6-63
INSTRUCTION SET
S3C825A/P825A
POPUD— Pop User Stack (Decrementing)
POPUD
dst,src
Operation:
dst ¬ src
IR ¬ IR – 1
This instruction is used for user-defined stacks in the register file. The contents of the register file
location addressed by the user stack pointer are loaded into the destination. The user stack
pointer is then decremented.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src
dst
3
8
92
R
IR
Example:
Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and
register 02H = 70H:
POPUD 02H,@00H
®
Register 00H = 41H, register 02H = 6FH, register 42H = 6FH
If general register 00H contains the value 42H and register 42H the value 6FH, the statement
"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The
user stack pointer is then decremented by one, leaving the value 41H.
6-64
S3C825A/P825A
INSTRUCTION SET
POPUI— Pop User Stack (Incrementing)
POPUI
dst,src
Operation:
dst ¬ src
IR ¬ IR + 1
The POPUI instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user stack pointer are loaded into the destination. The user
stack pointer is then incremented.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src
dst
3
8
93
R
IR
Example:
Given: Register 00H = 01H and register 01H = 70H:
POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H
®
If general register 00H contains the value 01H and register 01H the value 70H, the statement
"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user
stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.
6-65
INSTRUCTION SET
S3C825A/P825A
PUSH— Push To Stack
PUSH
src
Operation:
SP ¬ SP – 1
@SP ¬ src
A PUSH instruction decrements the stack pointer value and loads the contents of the source
(src) into the location addressed by the decremented stack pointer. The operation then adds the
new value to the top of the stack.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
src
2
8 (internal clock)
8 (external clock)
70
R
8 (internal clock)
8 (external clock)
71
IR
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:
PUSH
PUSH
40H
®
Register 40H = 4FH, stack register 0FFH = 4FH,
SPH = 0FFH, SPL = 0FFH
@40H
®
Register 40H = 4FH, register 4FH = 0AAH, stack register
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
In the first example, if the stack pointer contains the value 0000H, and general register 40H the
value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It
then loads the contents of register 40H into location 0FFFFH and adds this new value to the top
of the stack.
6-66
S3C825A/P825A
INSTRUCTION SET
PUSHUD— Push User Stack (Decrementing)
PUSHUD
dst,src
Operation:
IR ¬ IR – 1
dst ¬ src
This instruction is used to address user-defined stacks in the register file. PUSHUD decrements
the user stack pointer and loads the contents of the source into the register addressed by the
decremented stack pointer.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst
src
3
8
82
IR
R
Example:
Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:
PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H
®
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The
01H register value, 05H, is then loaded into the register addressed by the decremented user
stack pointer.
6-67
INSTRUCTION SET
S3C825A/P825A
PUSHUI— Push User Stack (Incrementing)
PUSHUI
dst,src
Operation:
IR ¬ IR + 1
dst ¬ src
This instruction is used for user-defined stacks in the register file. PUSHUI increments the user
stack pointer and then loads the contents of the source into the register location addressed by
the incremented user stack pointer.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst
src
3
8
83
IR
R
Example:
Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:
PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H
®
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H
register value, 05H, is then loaded into the location addressed by the incremented user stack
pointer.
6-68
S3C825A/P825A
INSTRUCTION SET
RCF— Reset Carry Flag
RCF
RCF
Operation:
C ¬ 0
The carry flag is cleared to logic zero, regardless of its previous value.
C: Cleared to "0".
Flags:
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
CF
Example:
Given: C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
6-69
INSTRUCTION SET
S3C825A/P825A
RET— Return
RET
Operation:
PC ¬ @SP
SP ¬ SP + 2
The RET instruction is normally used to return to the previously executing procedure at the end
of a procedure entered by a CALL instruction. The contents of the location addressed by the
stack pointer are popped into the program counter. The next statement that is executed is the
one that is addressed by the new program counter value.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode (Hex)
opc
1
8 (internal stack)
10 (internal stack)
AF
Example:
Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:
RET PC = 101AH, SP = 00FEH
®
The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte
of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the
PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to
memory location 00FEH.
6-70
S3C825A/P825A
INSTRUCTION SET
RL— Rotate Left
RL
dst
Operation:
C ¬ dst (7)
dst (0) ¬ dst (7)
dst (n + 1) ¬ dst (n), n = 0–6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7
is moved to the bit zero (LSB) position and also replaces the carry flag.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
90
91
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL
RL
00H
®
®
Register 00H = 55H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
@01H
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)
and setting the carry and overflow flags.
6-71
INSTRUCTION SET
S3C825A/P825A
RLC— Rotate Left Through Carry
RLC
dst
Operation:
dst (0) ¬ C
C ¬ dst (7)
dst (n + 1) ¬ dst (n), n = 0–6
The contents of the destination operand with the carry flag are rotated left one bit position. The
initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
10
11
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC
RLC
00H
®
®
Register 00H = 54H, C = "1"
@01H
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement
"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag
and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H
(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6-72
S3C825A/P825A
INSTRUCTION SET
RR— Rotate Right
RR
dst
Operation:
C ¬ dst (0)
dst (7) ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
The contents of the destination operand are rotated right one bit position. The initial value of bit
zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
E0
E1
R
IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR
RR
00H
®
®
Register 00H = 98H, C = "1"
Register 01H = 02H, register 02H = 8BH, C = "1"
@01H
In the first example, if general register 00H contains the value 31H (00110001B), the statement
"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to
bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also
resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
6-73
INSTRUCTION SET
S3C825A/P825A
RRC— Rotate Right Through Carry
RRC
dst
Operation:
dst (7) ¬ C
C ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit
7 (MSB).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
C0
C1
R
IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC
RRC
00H
®
®
Register 00H = 2AH, C = "1"
@01H
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")
replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new
value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both
cleared to "0".
6-74
S3C825A/P825A
INSTRUCTION SET
SB0— Select Bank 0
SB0
Operation:
BANK ¬ 0
The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,
selecting bank 0 register addressing in the set 1 area of the register file.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
4F
Example:
The statement
SB0
clears FLAGS.0 to "0", selecting bank 0 register addressing.
6-75
INSTRUCTION SET
S3C825A/P825A
SB1— Select Bank 1
SB1
Operation:
BANK ¬ 1
The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,
selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not
implemented in some S3C8-series microcontrollers.)
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
5F
Example:
The statement
SB1
sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.
6-76
S3C825A/P825A
INSTRUCTION SET
SBC— Subtract with Carry
SBC
dst,src
Operation:
dst ¬ dst – src – c
The source operand, along with the current value of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source are
unaffected. Subtraction is performed by adding the two's-complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction permits the carry
("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of
high-order operands.
Flags:
C: Set if a borrow occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
of the result is the same as the sign of the source; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise, indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
32
33
r
r
r
lr
dst
src
3
3
6
6
34
35
R
R
R
IR
dst
6
36
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:
SBC
SBC
SBC
SBC
SBC
R1,R2
®
®
®
®
®
R1 = 0CH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#8AH
R1 = 05H, R2 = 03H, register 03H = 0AH
Register 01H = 1CH, register 02H = 03H
Register 01H = 15H,register 02H = 03H, register 03H = 0AH
Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H,
the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.
6-77
INSTRUCTION SET
S3C825A/P825A
SCF— Set Carry Flag
SCF
Operation:
Flags:
C ¬ 1
The carry flag (C) is set to logic one, regardless of its previous value.
C: Set to "1".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
DF
Example:
The statement
SCF
sets the carry flag to logic one.
6-78
S3C825A/P825A
INSTRUCTION SET
SRA— Shift Right Arithmetic
SRA
dst
Operation:
dst (7) ¬ dst (7)
C ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
7
6
0
C
Flags:
C: Set if the bit shifted from the LSB position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
D0
D1
R
IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA
SRA
00H
®
®
Register 00H = 0CD, C = "0"
@02H
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C
flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves
the value 0CDH (11001101B) in destination register 00H.
6-79
INSTRUCTION SET
S3C825A/P825A
SRP/SRP0/SRP1— Set Register Pointer
SRP
src
src
src
SRP0
SRP1
Operation:
If src (1) = 1 and src (0) = 0 then: RP0 (3–7)
¬
¬
¬
¬
¬
¬
src (3–7)
src (3–7)
src (4–7),
0
If src (1) = 0 and src (0) = 1 then: RP1 (3–7)
If src (1) = 0 and src (0) = 0 then: RP0 (4–7)
RP0 (3)
RP1 (4–7)
RP1 (3)
src (4–7),
1
The source data bits one and zero (LSB) determine whether to write one or both of the register
pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
src
opc
src
2
4
31
IM
Examples:
The statement
SRP #40H
sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.
The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to
68H.
6-80
S3C825A/P825A
INSTRUCTION SET
STOP— Stop Operation
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,
peripheral registers, and I/O port control and data registers are retained. Stop mode can be
released by an external reset operation or by external interrupts. For the reset operation, the
RESET pin must be held to Low level until the required oscillation stabilization interval has
elapsed.
In application programs, a STOP instruction must be immediately followed by at least three NOP
instructions. This ensures an adeguate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructons are not used after STOP instruction,
leakage current could be flown because of the floating state in the internal bus.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
7F
–
–
Example:
The statement
STOP
NOP
NOP
NOP
; halts all microcontroller operations
6-81
INSTRUCTION SET
S3C825A/P825A
SUB— Subtract
SUB
dst,src
Operation:
dst ¬ dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags:
C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst |
src
2
4
6
22
r
r
23
r
lr
opc
opc
src
dst
dst
src
3
3
6
6
24
25
R
R
R
IR
6
26
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB
SUB
SUB
SUB
SUB
SUB
R1,R2
®
®
®
®
®
®
R1 = 0FH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#90H
01H,#65H
R1 = 08H, R2 = 03H
Register 01H = 1EH, register 02H = 03H
Register 01H = 17H, register 02H = 03H
Register 01H = 91H; C, S, and V = "1"
Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.
6-82
S3C825A/P825A
INSTRUCTION SET
SWAP— Swap Nibbles
SWAP
dst
Operation:
dst (0 – 3) « dst (4 – 7)
The contents of the lower four bits and upper four bits of the destination operand are swapped.
7
4 3
0
Flags:
C: Undefined.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
F0
F1
R
IR
Examples:
Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:
SWAP
SWAP
00H
®
®
Register 00H = 0E3H
@02H
Register 02H = 03H, register 03H = 4AH
In the first example, if general register 00H contains the value 3EH (00111110B), the statement
"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value
0E3H (11100011B).
6-83
INSTRUCTION SET
S3C825A/P825A
TCM— Test Complement Under Mask
TCM
dst,src
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
62
63
r
r
r
lr
dst
src
3
3
6
6
64
65
R
R
R
IR
dst
6
66
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TCM
TCM
TCM
TCM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "1"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
TCM
00H,#34
®
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register
for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.
6-84
S3C825A/P825A
INSTRUCTION SET
TM— Test Under Mask
TM
dst,src
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
72
73
r
r
r
lr
dst
src
3
3
6
6
74
75
R
R
R
IR
dst
6
76
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TM
TM
TM
TM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "0"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
TM
00H,#54H
®
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register
for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.
6-85
INSTRUCTION SET
S3C825A/P825A
WFI— Wait for Interrupt
WFI
Operation:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take
place during this wait state. The WFI status can be released by an internal interrupt, including a
fast interrupt .
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4n
3F
( n = 1, 2, 3, … )
Example:
The following sample program structure shows the sequence of operations that follow a "WFI"
statement:
Main program
.
.
.
EI
WFI
(Enable global interrupt)
(Wait for interrupt)
(Next instruction)
.
.
.
Interrupt occurs
Interrupt service routine
.
.
.
Clear interrupt flag
IRET
Service routine completed
6-86
S3C825A/P825A
INSTRUCTION SET
XOR— Logical Exclusive OR
XOR
dst,src
Operation:
dst ¬ dst XOR src
The source operand is logically exclusive-ORed with the destination operand and the result is
stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever
the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
B2
B3
r
r
r
lr
dst
src
3
3
6
6
B4
B5
R
R
R
IR
dst
6
B6
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
XOR
XOR
XOR
XOR
XOR
R0,R1
®
®
®
®
®
R0 = 0C5H, R1 = 02H
R0,@R1
00H,01H
00H,@01H
00H,#54H
R0 = 0E4H, R1 = 02H, register 02H = 23H
Register 00H = 29H, register 01H = 02H
Register 00H = 08H, register 01H = 02H, register 02H = 23H
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains
the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0
value and stores the result (0C5H) in the destination register R0.
6-87
INSTRUCTION SET
S3C825A/P825A
NOTES
6-88
S3C825A/P825A
CLOCK CIRCUIT
7
CLOCK CIRCUIT
OVERVIEW
The S3C825A microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and
peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU
clock frequency of S3C825A is determined by CLKCON register settings.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
— External crystal, ceramic resonator, RC oscillation source, or an external clock source
— Oscillator stop and wake-up functions
— Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)
— System clock control register, CLKCON
— STOP control register, STPCON
CPU Clock Notation
In this document, the following notation is used for descriptions of the CPU clock;
fx: main clock
fxt: sub clock
fxx: selected system clock
7-1
CLOCK CIRCUIT
S3C825A/P825A
MAIN OSCILLATOR CIRCUITS
SUB OSCILLATOR CIRCUITS
XTIN
XIN
XTOUT
XOUT
32.768 kHz
Figure 7-4. Crystal/Ceramic Oscillator (fxt)
Figure 7-1. Crystal/Ceramic Oscillator (fx)
XTIN
XTOUT
XIN
XOUT
Figure 7-2. External Oscillator (fx)
Figure 7-5. External Oscillator (fxt)
XIN
R
XOUT
Figure 7-3. RC Oscillator (fx)
7-2
S3C825A/P825A
CLOCK CIRCUIT
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset
operation or an external interrupt (with RC delay noise filter).
— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers, timer/
counters, and watch timer. Idle mode is released by a reset or by an external or internal interrupt.
Stop Release
INT
Main-System
Oscillator
Circuit
Sub-system
Oscillator
Circuit
fx
fxt
Watch Timer
LCD Controller
Selector 1
fXX
Stop
OSCCON.3
OSCCON.0
Stop
OSCCON.2
1/8-1/4096
Basic Timer
Timer/Counters
STOP OSC
inst.
Watch Timer
LCD Controller
SIO
STPCON
Frequency
Dividing
Circuit
A/D Converter
UART
1/1 1/2 1/8 1/16
Selector 2
System Clock
CLKCON.4-.3
CPU Clock
IDLE Instruction
Figure 7-6. System Clock Circuit Diagram
7-3
CLOCK CIRCUIT
S3C825A/P825A
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and
has the following functions:
— Oscillator frequency divide-by value
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If
necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
System Clock Control Register (CLKCON)
D4H, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
(must keep always 0)
Not used
(must keep always 0)
Oscillator IRQ wake-up
function bit:
0 = Enable IRQ for main
wake-up in power down mode
1 = Disable IRQ for main
wake-up in power down mode
Divide-by selection bits for
CPU clock frequency:
00 = fXX/16
01 = fXX/8
10 = fXX/2
11 = fXX/1 (non-divided)
Figure 7-7. System Clock Control Register (CLKCON)
7-4
S3C825A/P825A
CLOCK CIRCUIT
OSCILLATOR CONTROL REGISTER (OSCCON)
The oscillator control register, OSCCON, is located in set 1, bank 0, at address D2H. It is read/write addressable
and has the following functions:
— System clock selection
— Main oscillator control
— Sub oscillator control
OSCCON.0 register settings select Main clock or Sub clock as system clock.
After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0".
The main oscillator can be stopped or run by setting OSCCON.3.
The sub oscillator can be stopped or run by setting OSCCON.2.
Oscillator Control Register (OSCCON)
D2H, Bank 0, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
System clock selection bit:
0 = Main select
1 = Sub select
Not used for S3C825A
Not used for S3C825A
Sub system oscillator control bit:
0 = Sub oscillator RUN
1 = Sub oscillator STOP
Main system oscillator control bit:
0 = Main oscillator RUN
1 = Main oscillator STOP
Figure 7-8. Oscillator Control Register (OSCCON)
7-5
CLOCK CIRCUIT
S3C825A/P825A
SWITCHING THE CPU CLOCK
Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as
the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch
dynamically between main and sub clocks and to modify operating frequencies.
OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the CPU clock. OSCCON .3 start or stop main
clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4–.3 control the frequency divider
circuit, and divide the selected fxx clock by 1, 2, 8, 16.
For example, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you
want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set
CLKCON.4-.3 to "11", OSCCON.0 to “1”, and OSCCON.3 to “1” simultaneously. This switches the clock from fx
to fxt and stops main clock oscillation.
The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to “0” to
enable main clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main clock
by setting OSCCON.0 to “0”.
+
PROGRAMMING TIP — Switching the CPU clock
1. This example shows how to change from the main clock to the sub clock:
MA2SUB LD
OSCCON,#01H
; Switches to the sub clock
; Stop the main clock oscillation
RET
2. This example shows how to change from sub clock to main clock:
SUB2MA AND
OSCCON,#07H
DLY16
OSCCON,#06H
; Start the main clock oscillation
; Delay 16 ms
; Switch to the main clock
CALL
AND
RET
DLY16
DEL
SRP
LD
NOP
DJNZ
RET
#0C0H
R0,#20H
R0,DEL
7-6
S3C825A/P825A
CLOCK CIRCUIT
STOP Control Register (STPCON)
D1H, Bank 0, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
STOP Control bits:
Other values = Disable STOP instruction
10100101 = Enable STOP instruction
NOTE: Before execute the STOP instruction, set this STPCON register as "10100101B".
Otherwise the STOP instruction will not execute as well as reset will be generated.
Figure 7-9. STOP Control Register (STPCON)
7-7
CLOCK CIRCUIT
S3C825A/P825A
NOTES
7-8
S3C825A/P825A
RESET and POWER-DOWN
8
RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW
During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The
RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings the S3C825A into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a
minimum time interval after the power supply comes within tolerance. The minimum required time of a reset
operation for oscillation stabilization is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both VDD and RESET are High level), the
RESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then
reset to their default hardware values
In summary, the following sequence of events occurs during a reset operation:
— All interrupt is disabled.
— The watchdog function (basic timer) is enabled.
— Ports 0-8 are set to input mode, and all pull-up resistors are disabled for the I/O port.
— Peripheral control and data register settings are disabled and reset to their default hardware values.
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 0100H (and 0101H) is fetched and executed.
NORMAL MODE RESET OPERATION
In normal (masked ROM) mode, the Test pin is tied to VSS. A reset enables access to the 48-Kbyte on-chip
ROM.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing "1010B" to the upper nibble of BTCON.
8-1
RESET and POWER-DOWN
S3C825A/P825A
HARDWARE RESET VALUES
Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral
data registers following a reset operation. The following notation is used to represent reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An "x" means that the bit value is undefined after a reset.
— A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.
Table 8-1. S3C825A Set 1 Register and Values after RESET
Register Name
Mnemonic
Address
Dec
Bit Values after RESET
Hex
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
7
–
0
–
0
0
x
1
1
x
x
x
x
0
x
0
0
6
–
0
–
0
0
x
1
1
x
x
x
x
0
x
–
0
5
0
0
–
0
0
x
0
0
x
x
x
x
0
x
–
0
4
0
0
–
0
0
x
0
0
x
x
x
x
0
x
x
0
3
0
0
0
0
0
x
0
1
x
x
x
x
0
x
x
0
2
0
0
0
0
0
x
–
–
x
x
x
x
0
x
x
0
1
0
0
–
0
0
0
–
–
x
x
x
x
0
x
0
0
0
0
0
0
0
0
0
–
–
x
x
x
x
0
x
0
0
Interrupt Pending Register (NOTE)
STOP Control Register (NOTE)
Oscillator Control Register (NOTE)
Basic Timer Control Register
Clock Control Register
INTPND
STPCON
OSCCON
BTCON
CLKCON
FLAGS
RP0
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
System Flags Register
Register Pointer (High Byte)
Register Pointer (Low Byte)
Stack Pointer (High Byte)
Stack Pointer (Low Byte)
Instruction Pointer (High Byte)
Instruction Pointer (Low Byte)
Interrupt Request Register
Interrupt Mask Register
RP1
SPH
SPL
IPH
IPL
IRQ
IMR
System Mode Register
SYM
Register Page Pointer
PP
NOTE: The registers, INTPND/STPCON/OSCCON, are in bank 0 of set 1.
8-2
S3C825A/P825A
RESET and POWER-DOWN
Table 8-2. S3C825A Set 1, Bank 0 Register Values after RESET
Register Name
Mnemonic
Address
Dec
Bit Values after RESET
Hex
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
7
0
0
0
0
1
0
0
0
1
1
–
0
0
1
0
–
x
6
0
0
0
0
1
0
0
0
1
1
–
0
0
1
0
–
x
5
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
4
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
3
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
2
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
x
SIO Control Register
SIOCON
SIODATA
SIOPS
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
SIO Data Register
SIO Prescaler Register
Timer 0 Counter Register
Timer 0 Data Register
T0CNT
T0DATA
T0CON
TBCNT
Timer 0 Control Register
Timer B Counter Register
Timer A Counter Register
Timer B Data Register
TACNT
TBDATA
TADATA
TBCON
TACON
T2CNT
Timer A Data Register
Timer B Control Register
Timer 1/A Control Register
Timer 2 Counter Register
Timer 2 Data Register
T2DATA
T2CON
ADCON
ADDATAH
ADDATAL
LCON
Timer 2 Control Register
A/D Converter Control Register
A/D Converter Data Register (high byte)
A/D Converter Data Register (low byte)
LCD Control Register
–
0
–
0
0
1
1
0
x
–
0
–
0
0
1
1
0
x
–
–
–
0
0
1
1
0
x
–
–
–
0
0
1
1
0
x
–
0
0
0
0
1
1
0
x
–
0
0
0
0
1
1
0
x
x
x
0
0
0
0
1
1
0
x
0
0
0
0
1
1
0
x
LCD Mode Register
LMOD
Timer 3 Counter (high byte)
Timer 3 Counter (low byte)
Timer 3 Data Register (high byte)
Timer 3 Data Register (low byte)
Timer 3 Control Register
UART data register
T3CNTH
T3CNTL
T3DATAH
T3DATAL
T3CON
UDATA
UART control register
UARTCON 250
BRDATA 251
FAH
FBH
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UART Baud Rate data register
Location FCH is not mapped.
BTCNT 253 FDH
Location FEH is not mapped.
IPR 255 FFH
Basic Timer Counter
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
Interrupt Priority Register
8-3
RESET and POWER-DOWN
S3C825A/P825A
Table 8-3. S3C825A Set 1, Bank 1 Register Values after RESET
Register Name
Mnemonic
Address
Bit Values after RESET
Dec
Hex
E0H
E1H
E2H
7
0
0
0
6
0
0
0
5
0
0
0
4
0
0
0
3
0
0
0
2
0
0
0
1
0
0
0
0
0
0
0
Port 2 Control Register(High Byte)
Port 2 Control Register(Low Byte)
P2CONH
P2CONL
P2PUR
224
225
226
Port 2 Pull-up Resistors enable
Register
Port 2 Interrupt Control Register
Port 3 Control Register(High Byte)
Port 3 Control Register(Low Byte)
Port 3 Pull-up Resistors enable Register
Port 4 Interrupt Edge Selection Register
Port 4 Control Register(High Byte)
Port 4 Control Register(Low Byte)
Port 4 Interrupt Control Register
Port 4 Interrupt Pending Register
Port 5 Control Register(High Byte)
Port 5 Control Register(Low Byte)
Port 5 Pull-up Resistors enable Register
Watch timer control register
P2INT
P3CONH
P3CONL
P3PUR
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
251
252
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P4EDGE
P4CONH
P4CONL
P4INT
P4PND
P5CONH
P5CONL
P5PUR
WTCON
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
Port 7 Data Register
Port 8 Data Register
Port Group 0 Control Register
Port Group 1 Control Register
P0
P1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P3
P4
P5
P6
P7
P8
PG0CON
PG1CON
0
0
0
0
0
0
0
0
Locations FBH-FFH are not mapped.
8-4
S3C825A/P825A
RESET and POWER-DOWN
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
peripherals is halted. That is, the on-chip oscillator for system clock stops and the supply current is reduced to
less than 3 mA. All system functions stop when the clock “freezes”, but data stored in the internal register file is
retained. Stop mode can be released in one of two ways: by a reset or by external interrupts, for more details see
Figure 7-3.
NOTE
Do not use stop mode if you are using an external clock source because XIN or XTIN input must be
restricted internally to VSS to reduce current leakage.
Using RESET to Release Stop Mode
Stop mode is released when the RESET signal is released and returns to high level: all system and peripheral
control registers are reset to their default hardware values and the contents of all data registers are retained. A
reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to
'00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization
routine by fetching the program instruction stored in ROM location 0100H.
Using an External Interrupt to Release Stop Mode
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you
can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating
mode. The external interrupts in the S3C825A interrupt structure that can be used to release Stop mode are:
— External interrupts P2.4–P2.7 (INT0–INT3) and P4.0–P4.7 (INT4–INT11)
Please note the following conditions for Stop mode release:
— If you release Stop mode using an external interrupt, the current values in system and peripheral control
registers are unchanged except STPCON register.
— If you use an internal or external interrupt for stop mode release, you can also program the duration of the
oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before
entering stop mode.
— When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting
remains unchanged and the currently selected clock value is used.
— The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service
routine, the instruction immediately following the one that initiated Stop mode is executed.
How to Enter into Stop Mode
Handling STPCON register then writing Stop instruction (keep the order).
LD
STPCON, #10100101B
STOP
NOP
NOP
NOP
8-5
RESET and POWER-DOWN
S3C825A/P825A
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some
peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all
peripherals remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered.
There are two ways to release idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4
and CLKCON.3 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode.
2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle
mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock
value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction
immediately following the one that initiated idle mode is executed.
8-6
S3C825A/P825A
I/O PORTS
9
I/O PORTS
OVERVIEW
The S3C825A microcontroller has four bit-programmable and five nibble-programmable I/O ports,
P0–P8. The port 0-4, 6, and 7 are 8-bit ports, the port 5 is 7-bit port, and the port 8 is 4-bit port. This gives a total
of 67 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses
ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the
S3C825A can be configured to input or output mode and P0, P6-P8 are shared with LCD signals.
Table 9-1 gives you a general overview of the S3C825A I/O port functions.
9-1
I/O PORTS
S3C825A/P825A
Table 9-1. S3C825A Port Configuration Overview
Configuration Options
Port
0
4-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.
P0.0–P0.7 can alternately be used as outputs for LCD segment signals.
1
2
4-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.
P1.0–P1.7 can alternately be used as outputs for LCD segment signals.
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software; software
assignable pull-ups. P2.4–P2.7 can be used as input for external interrupts INT0–INT3 (with noise
filter and interrupt control, and can alternately be used as T0CLK, T1CLK, TAOUT, and TBOUT.
3
4
5
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software; software
assignable pull-ups. Alternately P3.0–P3.7 can be used as AD0-AD3, T3CLK,
T3OUT/T3PWM/T3CAP, T0OUT/T0PWM/T0CAP.
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software;
software assignable pull-ups. P4.0–P4.7 can alternately be used as inputs for external interrupts
INT4–INT11 (with noise filter and interrupt control).
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software;
software assignable pull-ups. Alternately P5.0–P5.5 can be used as SCK, SI, SO, BUZ, RXD, and
TXD.
6
7
4-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software;
software assignable pull-ups. P6.0–P6.7 can alternately be used as outputs for LCD signals.
4-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software;
software assignable pull-ups. P7.0–P7.7 can alternately be used as outputs for LCD segment
signals.
8
4-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software;
software assignable pull-ups. P8.0–P8.3 can alternately be used as outputs for LCD segment
signals.
9-2
S3C825A/P825A
I/O PORTS
PORT DATA REGISTERS
Table 9-2 gives you an overview of the register locations of all nine S3C825A I/O port data registers. Data
registers for ports 0, 1, 2, 3, 4, 5, 6, 7 and 8 have the general format shown in Figure 9-1.
Table 9-2. Port Data Register Summary
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Mnemonic
Decimal
240
Hex
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
Location
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0
P1
P2
P3
P4
P5
P6
P7
P8
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
241
242
243
244
245
246
247
248
9-3
I/O PORTS
PORT 0, 1
S3C825A/P825A
Port 0 and 1 are 8-bit I/O ports with nibble configurable pins, respectively. Port 0 and 1 pins are accessed directly
by writing or reading the Port 0 and 1 data registers, P0 at location F0H and P1 at location F1H in set 1, bank 1.
P0.0–P0.7 and P1.0–P1.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). And
they can serve as segment pins for LCD, also.
Port Group 0 Control Register (PG0CON)
Port 0 and 1 have a 8-bit control register: PG0CON.0–.3 for P0.0–P0.7 and PG0CON.4–.7 for P1.0–P1.7. A reset
clears the PG0CON register to “00H”, configuring all pins to input mode.
Port Group 0 Control Register
F9H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0.0-P0.3
/SEG16-SEG19
P1.4-P1.7
P0.4-P0.7
/SEG20-SEG23
/SEG28-SEG31
P1.0-P1.3
/SEG24-SEG27
PG0CON bit-pair pin configuration settings
00
01
10
Input mode
Input mode, pull-up
Output mode, open-drain
11
Output mode, push-pull
NOTE:
The shared I/O ports with LCD segments should
be selected as one of two by LMOD.3-.0.
Figure 9-1. Port Group 0 Control Register (PG0CON)
9-4
S3C825A/P825A
PORT 2
I/O PORTS
Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or
reading the port 2 data register, P2 at location F2H in set 1, bank 1. P2.0–P2.7 can serve as inputs, as outputs
(push-pull or open-drain) or it can be configured the following functions.
— Low-nibble pins (P2.0–P2.3): T2CLK, T2OUT
— High-nibble pins (P2.4–P2.7): T0CLK, T1CLK, TAOUT, TBOUT, INT0–INT3
Port 2 Control Registers (P2CONH, P2CONL)
Port 2 has two 8-bit control registers: P2CONH for P2.4–P2.7 and P2CONL for P2.0–P2.3. A reset clears the
P2CONH and P2CONL registers to "00H", configuring P2.4–P2.7 pins to input mode with interrupt on falling edge
and P2.0–P2.3 pins to input mode. You use control registers setting to select input or output mode(push-pull or
open-drain) and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using
the port 2 control registers must also be enabled in the associated peripheral module.
Port 2 Pull-Up Resistor Control Register (P2PUR)
Using the port2 pull-up resistor control register, P2PUR (E2H, set 1, bank 1), you can configure pull-up resistors
to individual port 2 pins.
Port 2 Interrupt Control Registers (P2INT)
To process external interrupts at the port 2 pins, a additional control register is provided: the port 2 interrupt
control register P2INT (E3H, set 1, bank 1).
The port 2 interrupt control register P2INT lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the P2INT register at regular intervals.
When the interrupt enable bit of any port 2 pin is “1”, a falling edge at that pin will generate an interrupt request.
The corresponding pending bit is then automatically set to “1” and the IRQ level goes low to signal the CPU that
an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the
clear the pending condition by writing a “0” to the corresponding P2INT bit.
9-5
I/O PORTS
S3C825A/P825A
Port 2 Control Register, High Byte (P2CONH)
E0H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.7/TBOUT
(INT3)
P2.6/TAOUT P2.5/T1CLK
(INT2) (INT1)
P2.4/T0CLK
(INT0)
P2CONH bit-pair pin configuration
00
01
10
11
Schmitt trigger input mode, interrupt on falling edge (T0CLK, T1CLK)
Output mpde, open-drain
Alternative function (TAOUT, TBOUT)
Output mode, push-pull
Figure 9-2. Port 2 High-Byte Control Register (P2CONH)
Port 2 Control Register, Low Byte (P2CONL)
E1H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.3/
T2OUT
P2.2/
T2CLK
P2.1
P2.0
P2CONL bit-pair pin configuration
00
01
10
11
Schmitt trigger input mode, interrupt on falling edge (T2CLK)
Output mode, open-drain
Alternative function (T2OUT)
Output mode, push-pull
Figure 9-3. Port 2 Low-Byte Control Register (P2CONL)
9-6
S3C825A/P825A
I/O PORTS
Port 2 Pull-up Control Register (P2PUR)
E2H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P2PUR bit configuration settings:
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
The corresponding pull-up resistor is disabled automatically
when a bit of port 2 is selected as output mode.
Figure 9-4. Port 2 Pull-up Control Register (P2PUR)
Port 2 Interrupt Control Register (P2INT)
E3H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
PND3 INT3 PND2 INT2 PND1 INT1 PND0 INT0
INTn bit configuration settings:
0
1
Disable interrupt
Enable interrupt
PNDn bit configuration settings:
0
Interrupt request is not pending,
pending bit clear when write 0
1
Interrupt request is pending
NOTE:
"n" is 0, 1, 2, and 3.
Figure 9-5. Port 2 Interrupt Control Register (P2INT)
9-7
I/O PORTS
PORT 3
S3C825A/P825A
Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or
reading the Port 3 data register, P3 at location F3H in set 1, bank 1. P3.0–P3.7 can serve as inputs, as outputs
(push pull or open-drain) or you can configure the following alternative functions:
— Low-nibble pins (P3.0-P3.3): AD0–AD3
— High-nibble pins (P3.4-P3.7): T3CLK, T3OUT/T3PWM/T3CAP, T0OUT/T0PWM/T0CAP
Port 3 Control Registers (P3CONH, P3CONL)
Port 3 has two 8-bit control registers: P3CONH for P3.4–P3.7 and P3CONL for P3.0–P3.3. A reset clears the
P3CONH and P3CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to
select input or output mode (push-pull or open drain) and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using
the port 3 control registers must also be enabled in the associated peripheral module.
Port 3 Pull-up Resistor Control Register (P3PUR)
Using the port 3 pull-up resistor control register, P3PUR (E6H, set 1, bank 1), you can configure pull-up resistors
to individual port 3 pins.
Port 3 Control Register, High Byte
E4H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.4
P3.5/T3CLK
P3.6/T3OUT/T3PWM/T3CAP
P3.7/T0OUT/T0PWM/T0CAP
P3CONH bit-pair pin configuration settings
00
01
10
11
Input mode (T3CLK, T3CAP, T0CAP)
Output mode, open-drain
Alternative function (T3OUT/T3PWM, T0OUT/T0CAP)
Output mode, push-pull
Figure 9-6. Port 3 High-Byte Control Register (P3CONH)
9-8
S3C825A/P825A
I/O PORTS
Port 3 Control Register, Low Byte
E5H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.0/AD0
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3CONL bit-pair pin configuration settings
00
01
10
11
Input mode
Output mode, open-drain
Alternative function (AD0-AD3)
Output mode, push-pull
Figure 9-7. Port 3 Low-Byte Control Register (P3CONL)
Port 3 Pull-up Control Register
E6H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P3PUR bit configuration settings:
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
The corresponding pull-up resistor is disabled
automatically, when a bit of port 3 is selected as
output mode.
Figure 9-8. Port 3 Pull-up Control Register (P3PUR)
9-9
I/O PORTS
PORT 4
S3C825A/P825A
Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or
reading the port 4 data register, P4 at location F4H in set 1, bank 1. P4.0–P4.7 can serve as inputs (with or
without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions.
— Low-nibble pins (P4.0–P4.3): INT4–INT7
— High-nibble pins (P4.4–P4.7): INT8–INT11
Port 4 Control Registers (P4CONH, P4CONL)
Port 4 has two 8-bit control registers: P4CONH for P4.4–P4.7 and P4CONL for P4.0–P4.3. A reset clears the
P4CONH and P4CONL registers to "00H", configuring pins to input mode. You use control registers setting to
select input or output mode(push-pull or open-drain).
Port 4 Interrupt Enable, Pending, and Edge Selection Registers (P4INT, P4PND, P4EDGE)
To process external interrupts at the port 4 pins, three additional control registers are provided: the port 4
interrupt enable register P4INT (EAH, set 1, bank 1), the port 4 interrupt pending register P4PND (EBH, set1,
bank 1), and the port 4 interrupt edge selection register P4EDGE (E7H, set 1, bank 1).
The port 4 interrupt pending register P4PND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the P4PND register at regular intervals.
When the interrupt enable bit of any port 4 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding P4PND bit is then automatically set to "1" and the IRQ level goes low to signal the
CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software
must the clear the pending condition by writing a "0" to the corresponding P4PND bit.
Port 4 Control Register, High Byte (P4CONH)
E8H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.7
(INT11)
P4.6
(INT10)
P4.5
(INT9)
P4.4
(INT8)
P4CONH bit-pair pin configuration
00
01
10
11
Schmitt trigger input mode
Schmitt trigger input mode, pull-up resistor
Output mode, open-drain
Output mode, push-pull
Figure 9-9. Port 4 High-Byte Control Register (P4CONH)
9-10
S3C825A/P825A
I/O PORTS
Port 4 Control Register, Low Byte (P4CONL)
E9H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.3
(INT7)
P4.2
(INT6)
P4.1
(INT5)
P4.0
(INT4)
P4CONL bit-pair pin configuration
00
01
10
11
Schmitt trigger input mode
Schmitt trigger input mode, pull-up resistor
Output mode, open-drain
Output mode, push-pull
Figure 9-10. Port 4 Low-Byte Control Register (P4CONL)
Port 4 Interrupt Control Register (P4INT)
EAH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
INT11 INT10 INT9 INT8 INT7 INT6 INT5 INT4
P4INT bit configuration settings:
0
1
Disable interrupt
Enable interrupt
Figure 9-11. Port 4 Interrupt Control Register (P4INT)
9-11
I/O PORTS
S3C825A/P825A
Port 4 Interrupt Pending Register (P4PND)
EBH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
PND11PND10 PND9 PND8 PND7 PND6 PND5 PND4
P4PND bit configuration settings:
0
Interrupt request is not pending,
pending bit clear when write 0
1
Interrupt request is pending
Figure 9-12. Port 4 Interrupt Pending Control Register (P4PND)
Port 4 Interrupt Edge Selection Register (P4EDGE)
E7H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
EDGE11 EDGE10 EDGE9 EDGE8 EDGE7 EDGE6 EDGE5 EDGE4
P4EDGE bit configuration settings:
0
1
Falling edge detection
Rising edge detection
Figure 9-13. Port 4 Interrupt Edge Selection Register (P4EDGE)
9-12
S3C825A/P825A
PORT 5
I/O PORTS
Port 5 is an 7-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or
reading the port 5 data register, P5 at location F5H in set 1, bank 1. P5.0–P5.6 can serve as inputs or as push-
pull, open-drain outputs. You can configure the following alternative functions:
— Low-nibble pins (P5.0–P5.3): SCK, SI, SO, BUZ
— High-nibble pins (P5.4–P5.6): RXD, TXD
Port 5 Control Registers (P5CONH, P5CONL)
Port 5 has two 8-bit control registers: P5CONH for P5.4–P5.6 and P5CONL for P5.0–P5.3, and P5CONH.7–.6 for
TXD/RXD output control. A reset clears the P5CONH and P5CONL registers to “00H”, configuring all pins to input
mode and TXD/RXD to output disable. You use control registers settings to select input or output mode, and
enable the alternative functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using
the port 5 control registers must also be enabled in the associated peripheral module.
Port 5 Control Register, High Byte (P5CONH)
ECH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P5.6
P5.5/TXD
P5.4/RXD
TXD output control bit
0
1
Disble TXD output at P5.5
Enable TXD output at P5.5
RXD output control bit
0
1
Disble RXD output at P5.4
Enable RXD output at P5.4
P5CONH bit-pair pin configuration settings
00
01
10
11
Input mode (RXD)
Output mode, open-drain (RXD/TXD)
Not available
Output mode, push-pull (RXD/TXD)
NOTE: The RXD and TXD outputs depend on P5CONH.6 and P5CONH.7, respectively.
Figure 9-14. Port 5 High-Byte Control Register (P5CONH)
9-13
I/O PORTS
S3C825A/P825A
Port 5 Control Register, Low Byte (P5CONL)
EDH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P5.0/SCK
P5.1/SI
P5.2/SO
P5.3/BUZ
P5CONL bit-pair pin configuration settings
Input mode (SCK, SI)
00
01
10
11
Output mode, open-drain
Alternative function (BUZ, SCK, SO)
Output mode, push-pull
Figure 9-15. Port 5 Low-Byte Control Register (P5CONL)
Port 5 Pull-up Control Register (P5PUR)
EEH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
used
P5PUR bit configuration settings:
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
The corresponding pull-up resistor is disabled
automatically, when a bit of port 5 is selected as
output mode.
Figure 9-16. Port 5 Pull-up Control Register (P5PUR)
9-14
S3C825A/P825A
PORT 6, 7, 8
I/O PORTS
Port 6 and 7 are 8-bit I/O port and port 8 is 4-bit I/O port with nibble configurable pins, respectively. Port 6, 7, and
8 pins are accessed directly by writing or reading the port 6, 7, and 8 data registers, P6 at location F6H, P7 at
location F7H, and P8 at location F8H in set 1, bank 1. P6.0–P6.7, P7.0–P7.7, and P8.0–P8.3 can serve as inputs
(with or without pull-ups), as output (open drain or push-pull). And they can serve as segment or common pins for
LCD also.
Port Group 1 Control Register (PG1CON)
Port 6, 7, and 8 have an 8-bit control register: PG1CON.0–.1 for P6.0–P6.7, PG1CON.2–.5 for P7.0–P7.7, and
PG1CON.6–.7 for P8.0–P8.3. A reset clears the PG1CON register to “00H”, configuring all pins to input mode.
Port Group 1 Control Register
FAH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P6.0-P6.7
/COM0-COM3
/SEG0-SEG3
P7.0-P7.3
/SEG4-SEG7
P7.4-P7.7
/SEG8-SEG11
P8.0-P8.3
/SEG12-SEG15
PG1CON bit-pair pin configuration settings
Input mode
00
01
10
11
Input mode, pull-up
Output mode, open-drain
Output mode, push-pull
NOTE:
Refer to LCD mode control register (LMOD).
Figure 9-17. Port Group 1 Control Register (PG1CON)
9-15
I/O PORTS
S3C825A/P825A
NOTES
9-16
S3C825A/P825A
BASIC TIMER and TIMER 0
10 BASIC TIMER and TIMER 0
OVERVIEW
The S3C825A has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit
timer/counter is called timer 0.
BASIC TIMER (BT)
You can use the basic timer (BT) in two different ways:
— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
— To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
The functional components of the basic timer block are:
— Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer
— 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only)
— Basic timer control register, BTCON (set 1, D3H, read/write)
10-1
BASIC TIMER and TIMER 0
S3C825A/P825A
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,
address D3H, and is read/write addressable using Register addressing mode.
A reset clears BTCON to “00H”. This enables the watchdog function and selects a basic timer clock frequency of
fxx/4096. To disable the watchdog function, you must write the signature code “1010B” to the basic timer register
control bits BTCON.7–BTCON.4.
The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation
by writing a "1" to BTCON.1. To clear the frequency dividers for all timers input clock, you write a "1" to
BTCON.0.
Basic TImer Control Register (BTCON)
D3H, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Divider clear bit for all timers:
0 = No effect
1= Clear divider
Watchdog timer enable bits:
1010B = Disable watchdog function
Other value = Enable watchdog function
Basic timer counter clear bit:
0 = No effect
1= Clear BTCNT
Basic timer input clock selection bits:
00 = fXX/4096
01 = fXX/1024
10 = fXX/128
11 = fXX/16
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
S3C825A/P825A
BASIC TIMER and TIMER 0
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to
“00H”, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by
the current CLKCON register setting), divided by 4096, as the BT clock.
A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must
be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always
broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
stop mode has been released by an external interrupt.
In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT
value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an
internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the
stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal
operation.
In summary, the following events occur when stop mode is released:
1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode
release and oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an
external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock
source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.
10-3
BASIC TIMER and TIMER 0
S3C825A/P825A
RESET or STOP
Bit 1
Bits 3, 2
Basic Timer Control Register
(Write '1010xxxxB' to Disable)
Data Bus
fXX/4096
Clear
fXX/1024
fXX/128
fXX/16
8-Bit Up Counter
(BTCNT, Read-Only)
fXX
DIV
MUX
OVF
RESET
Start the CPU (note)
R
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
Figure 10-2. Basic Timer Block Diagram
10-4
S3C825A/P825A
BASIC TIMER and TIMER 0
8-BIT TIMER/COUNTER 0
Timer/counter 0 has three operating modes, one of which you select using the appropriate T0CON setting:
— Interval timer mode
— Capture input mode with a rising or falling edge trigger at the P3.7 pin
— PWM mode
Timer/counter 0 has the following functional components:
— Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer
— External clock input (P2.4, T0CLK)
— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
— I/O pins for capture input, match output, or PWM output (P3.7/T0CAP, P3.7/T0OUT, P3.7/T0PWM)
— Timer 0 overflow interrupt (IRQ0, vector E2H) and match/capture interrupt (IRQ0, vector E0H) generation
— Timer 0 control register, T0CON (set 1, E5H, bank 0, read/write)
TIMER/COUNTER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter, T0CNT
— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt
— Clear timer 0 match/capture interrupt pending condition
10-5
BASIC TIMER and TIMER 0
S3C825A/P825A
T0CON is located in set 1, bank 0, at address E5H, and is read/write addressable using Register addressing
mode.
A reset clears T0CON to “00H”. This sets timer 0 to normal interval timer mode, selects an input clock frequency
of fxx/1024, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal
operation by writing a "1" to T0CON.2.
The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address E2H. When a timer 0
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware
or must be cleared by software.
To enable the timer 0 match/capture interrupt (IRQ0, vector E0H), you must write T0CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.1. When a "1" is detected, a
timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit,
INTPND.1.
Timer 0 Control Register (T0CON)
E5H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 0 input clock selection bits:
000 = fxx/1024
001 = fxx/256
Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
010 = fxx/64
011 = fxx/8
100 = fxx
Timer 0 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
101 = External clock
(P2.4/T0CLK) falling edge
110 = External clock
(P2.4/T0CLK) rising edge
111 = Counter stop
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Timer 0 operating mode selection bits:
00 = Interval mode (P3.7/T0OUT)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF and match interrupt can occur)
Figure 10-3. Timer 0 Control Register (T0CON)
10-6
S3C825A/P825A
BASIC TIMER and TIMER 0
Interrupt Pending Register (INTPND)
D0H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Timer 0 overflow interrupt pending bit
Timer 0 match/capture interrupt pending bit
Timer 3 overflow interrupt pending bit
Timer 3 match/capture interrupt pending bit
Tx interrupt pending bit (for UART)
Rx interrupt pending bit (for UART):
0 = Interrupt request is not pending, pending bit clear when write "0".
1 = Interrupt request is pending
Figure 10-4. Interrupt Pending Register (INTPND)
10-7
BASIC TIMER and TIMER 0
S3C825A/P825A
TIMER 0 FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0, Vectors E0H and E2H)
The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture
interrupt (T0INT). T0OVF is belongs to interrupt level IRQ0, vector E2H. T0INT also belongs to interrupt level
IRQ0, but is assigned the separate vector address, E0H.
A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or
should be cleared by software in the interrupt service routine by writing a “0” to the INTPND.0 interrupt pending
bit. However, the timer 0 match/capture interrupt pending condition must be cleared by the application’s interrupt
service routine by writing a "0" to the INTPND.1 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector
E0H) and clears the counter.
If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches “10H”. At this
point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each
match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-5).
Interrupt Enable/Disable
Capture Signal
T0CON.1
R (Clear)
8-Bit Up Counter
8-Bit Comparator
CLK
T0INT (IRQ0)
(Match INT)
M
U
X
INTPND.1
Pending
Match
T0OUT (P3.7)
Timer 0 Buffer Register
Timer 0 Data Register
T0CON.4-.3
Match Signal
T0CON.2
T0OVF
Figure 10-5. Simplified Timer 0 Function Diagram: Interval Timer Mode
10-8
S3C825A/P825A
BASIC TIMER and TIMER 0
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM (P3.7) pin. As in interval timer mode, a match signal is generated when the counter value is identical to
the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the
counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T0PWM (P3.7) pin is held to Low level as long as the reference
data value is less than or equal to ( £ ) the counter value and then the pulse is held to High level for as long as
the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK ´ 256 (see Figure 10-6).
T0CON.0
Interrupt Enable/Disable
Capture Signal
T0CON.1
T0OVF(IRQ0)
(Overflow INT)
CLK
8-Bit Up Counter
8-Bit Comparator
INTPND.0
T0INT (IRQ0)
(Match INT)
M
U
X
Match
INTPND.1
Pending
T0PWM
Output (P3.7)
High level when
data > counter,
Lower level when
data < counter
Timer 0 Buffer Register
Timer 0 Data Register
T0CON.4-.3
Match Signal
T0CON.2
T0OVF
Figure 10-6. Simplified Timer 0 Function Diagram: PWM Mode
10-9
BASIC TIMER and TIMER 0
Capture Mode
S3C825A/P825A
In capture mode, a signal edge that is detected at the T0CAP (P3.7) pin opens a gate and loads the current
counter value into the timer 0 data register. You can select rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source: the signal edge at the T0CAP (P3.7) pin. You select the capture
input by setting the values of the timer 0 capture input selection bits in the port 3 control register, P3CONH.7–.6,
(set 1, bank 1, E4H). When P3CONH.7–.6 is "00", the T0CAP input is selected.
Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated
whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter
value is loaded into the timer 0 data register.
By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency,
you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 10-7).
T0CON.0
T0OVF(IRQ0)
8-Bit Up Counter
INTPND.0
CLK
(Overflow INT)
Interrupt Enable/Disable
T0CON.1
T0INT (IRQ0)
(Capture INT)
M
U
X
INTPND.1
Pending
T0CAP input
(P3.7)
Match Signal
T0CON.4-.3
T0CON.4-.3
Timer 0 Data Register
Figure 10-7. Simplified Timer 0 Function Diagram: Capture Mode
10-10
S3C825A/P825A
BASIC TIMER and TIMER 0
T0CON.0
T0CON.7-.5
T0OVF
(IRQ0)
OVF
INTPND.0
Data BUS
8
fxx/1024
fxx/256
fxx/64
fxx/8
T0CON.2
Clear
fxx/1
8-Bit Up Counter
(Read-Only)
MUX
R
T0CLK
T0CON.1
T0INT
(IRQ0)
M
U
X
8-Bit Comparator
INTPND.1
Match
M
U
X
T0OUT
T0PWM
Timer 0 Buffer Register
Timer 0 Data Register
T0CAP
T0CON.4-.3
Match signal
T0CON.2
T0OVF
T0CON.4-.3
8
Data BUS
Figure 10-8. Timer 0 Block Diagram
10-11
BASIC TIMER and TIMER 0
S3C825A/P825A
NOTES
10-12
S3C825A/P825A
TIMER 1
11 TIMER 1
ONE 16-BIT TIMER MODE (TIMER 1)
The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. When TACON.7 is set to "1", it is in one
16-bit timer mode. When TACON.7 is set to "0", the timer 1 is used as two 8-bit timers.
— One 16-bit timer mode (Timer 1)
— Two 8-bit timers mode (Timer A and B)
OVERVIEW
The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 includes interval timer mode using appropriate
TACON setting.
Timer 1 has the following functional components:
— Clock frequency divider (fxx divided by 256, 64, 8, or 1 and T1CLK: External clock) with multiplexer
— 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA)
— Timer 1 match interrupt (IRQ1, vector E6H) generation
— Timer 1 control register, TACON (set 1, bank 0,EBH, read/write)
FUNCTION DESCRIPTION
Interval Timer Function
The timer 1 module can generate an interrupt, the timer 1 match interrupt (T1INT). T1INT belongs to the interrupt
level IRQ1, and is assigned a separate vector address, E6H.
The T1INT pending condition should be cleared by software after IRQ1 is serviced. The T1INT pending bit must
be cleared by the application sub-routine by writing a "0" to the TACON.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
T1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt
(T1INT, vector E6H) and clears the counter.
If, for example, you write the value 10H and 32H to TADATA and TBDATA, respectively, and 8EH to TACON,
the counter will increment until it reaches 3210H. At this point, the T1 interrupt request is generated, the counter
value is reset, and counting resumes.
11-1
TIMER 1
S3C825A/P825A
Timer 1 Control Register (TACON)
You use the timer 1 control register, TACON, to
— Enable the timer 1 operating (interval timer)
— Select the timer 1 input clock frequency
— Clear the timer 1 counter, TACNT and TBCNT
— Enable the timer 1 interrupt
— Clear timer 1 interrupt pending conditions
TACON is located in set 1, bank 0, at address EBH, and is read/write addressable using register addressing
mode.
A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency
of fxx/256, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during the normal
operation by writing a "1" to TACON.3.
To enable the timer 1 interrupt (IRQ1, vector E6H), you must write TACON.7, TACON.2, and TACON.1 to "1".
To generate the exact time interval, you should set TACON.3 and TACON.0 to “10B”, which clear counter and
interrupt pending bit. When the T1INT sub-routine is serviced, the pending condition must be cleared by software
by writing a "0" to the timer 1 interrupt pending bit, TACON.0.
Timer 1 Control Register (TACON)
EBH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 1 operation mode selection bit:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)
Timer 1 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
Timer 1 clock selection bits:
000 = fxx/256
001 = fxx/64
Timer 1 interrupt enable bit:
0 = Disable interrupt
010 = fxx/8
1 = Enable interrupt
011 = fxx
Timer 1 counter run enable bit:
0 = Disable counter running
1 = Enable counter running
111 = T1CLK
(external clock rising edge)
Timer 1 counter clear bit:
0 = No affect
1 = Clear the timer 1 counter (when write)
Figure 11-1. Timer 1 Control Register (TACON)
11-2
S3C825A/P825A
TIMER 1
BLOCK DIAGRAM
Bit 6, 5, 4
Data Bus
T1CLK
fxx/256
fxx/64
fxx/8
Bit 3
16-Bit Up-Counter
(Read Only)
<TBCNT/TACNT>
Clear
MUX
MSB
LSB
fxx/1
Pending
Bit 0
Match
16-Bit Comparator
T1INT
IRQ1
Bit 2
Bit 1
Timer 1 Buffer
Register (16-bit)
TAOUT
Counter Clear Signal
Match Signal
Timer 1 Data Register
(Read/Write)
<TBDATA/TADATA>
MSB
LSB
NOTE:
When TACON.7 is "1", 16-bit timer 1.
Figure 11-2. Timer 1 Functional Block Diagram
11-3
TIMER 1
S3C825A/P825A
TWO 8-BIT TIMERS MODE (TIMER A and B)
OVERVIEW
The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B support interval timer mode using
appropriate TACON and TBCON setting, respectively.
Timer A and B have the following functional components:
— Clock frequency divider with multiplexer
– fxx divided by 256, 64, 8, or 1 and T1CLK (External clock) for timer A
– fxx divided by 256, 64, 8, or 1 for timer B
— 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA)
— Timer A match interrupt (IRQ1, vector E6H) generation
— Timer A control register, TACON (set 1, bank 0, EBH, read/write)
— Timer B match interrupt (IRQ1, vector E4H) generation
— Timer B control register, TBCON (set 1, bank 0, EAH, read/write)
FUNCTION DESCRIPTION
Interval Timer Function
The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match
interrupt (TBINT). TAINT belongs to the interrupt level IRQ1, and is assigned a separate vector address, E6H.
TBINT belongs to the interrupt level IRQ1 and is assigned a separate vector address, E4H.
The TAINT and TBINT pending condition should be cleared by software after they are serviced.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to
the TA or TB reference data registers, TADATA or TBDATA. The match signal generates corresponding match
interrupt (TAINT, vector E6H; TBINT, vector E4H) and clears the counter.
If, for example, you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will
increment until it reaches 10H. At this point, the TB interrupt request is generated, the counter value is reset, and
counting resumes.
Timer A and B Control Register (TACON, TBCON)
You use the timer A and B control register, TACON and TBCON, to
— Enable the timer A and B operating (interval timer)
— Select the timer A and B input clock frequency
— Clear the timer A and B counter, TACNT and TBCNT
— Enable the timer A and B interrupt
— Clear timer A and B interrupt pending conditions
11-4
S3C825A/P825A
TIMER 1
TACON and TBCON are located in set 1, bank 0, at address EBH and EAH, and is read/write addressable using
register addressing mode.
A reset clears TACON and TBCON to "00H". This sets timer A and B to disable interval timer mode, selects an
input clock frequency of fxx/256, and disables timer A and B interrupt. You can clear the timer A and B counter at
any time during normal operation by writing a "1" to TACON.3 and TBCON.3.
To enable the timer A and B interrupt (IRQ1, vector E6H, E4H), you must write TACON.7 to "0", TACON.2
(TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should set TACON.3
(TBCON.3) and TACON.0 (TBCON.0) to “10B”, which clear counter and interrupt pending bit, respectively. When
the TAINT or TBINT sub-routine is serviced, the pending condition must be cleared by software by writing a "0" to
the timer A or B interrupt pending bits, TACON.0 or TBCON.0.
Timer A Control Register (TACON)
EBH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 1 operation mode selection bit:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)
Timer A interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
Timer A clock selection bits:
000 = fxx/256
001 = fxx/64
Timer A interrupt enable bit:
0 = Disable interrupt
010 = fxx/8
1 = Enable interrupt
011 = fxx
Timer A counter run enable bit:
0 = Disable counter running
1 = Enable counter running
111 = T1CLK
(external clock rising edge)
Timer A counter clear bit:
0 = No affect
1 = Clear the timer A counter (when write)
Figure 11-3. Timer A Control Register (TACON)
11-5
TIMER 1
S3C825A/P825A
Timer B Control Register (TBCON)
EAH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used the S3C825A.
Timer B interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
Timer B clock selection bits:
00 = fxx/256
01 = fxx/64
10 = fxx/8
11 = fxx
Timer B interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer B counter run enable bit:
0 = Disable counter running
1 = Enable counter running
Timer B counter clear bit:
0 = No affect
1 = Clear the timer B counter (when write)
Figure 11-4. Timer B Control Register (TBCON)
11-6
S3C825A/P825A
TIMER 1
TACON.6-.4
TACON.3
Clear
fxx/256
TACNT
R
fxx/64
fxx/8
fxx
MUX
Match
Comparator
TAOUT
TACON.2
TACON.0 Pending
T1CLK
TA Buffer Register
TACON.1
TBCON.1
TA Counter Clear Signal,
TA Match Signal
TADATA
TBDATA
IRQ1
TB Counter Clear Signal,
TB Match Signal
TB Buffer Register
Comparator
TBCON.0 Pending
fxx/256
fxx/64
fxx/8
fxx
TBCON.2
TBOUT
Match
MUX
TBCNT
R
Clear
TBCON.3
TBCON.5-.4
NOTE: When TACON.7 is "0", two 8-bit timer A/B.
Figure 11-5. Timer A and B Function Block Diagram
11-7
TIMER 1
S3C825A/P825A
NOTES
11-8
S3C825A/P825A
8-BIT TIMER 2
12 8-BIT TIMER 2
OVERVIEW
The 8-bit timer 2 is an 8-bit general-purpose timer. Timer 2 has the interval timer mode by using the appropriate
T2CON setting.
Timer 2 has the following functional components:
— Clock frequency divider (fxx divided by 256, 64, 8 or 1) with multiplexer
— External clock input (P2.2/T2CLK)
— 8-bit counter (T2CNT), 8-bit comparator, and 8-bit reference data register (T2DATA)
— Timer 2 interrupt (IRQ2, vector E8H) generation
— Timer 2 control register, T2CON (set 1, Bank 0, EEH, read/write)
FUNCTION DESCRIPTION
Interval Timer Function
The timer 2 can generate an interrupt, the timer 2 match interrupt (T2INT). T2INT belongs to interrupt level
IRQ2, and is assigned the separate vector address, E8H.
The T2INT pending condition should be cleared by software when it has been serviced. Even though T2INT is
disabled, the application’s service routine can detect a pending condition of T2INT by the software and execute
it’s sub-routine. When this case is used, the T2INT pending bit must be cleared by the application subroutine by
writing a “0” to the T2CON.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to
the Timer 2 reference data registers, T2DATA. The match signal generates a timer 2 match interrupt (T2INT,
vector E8H) and clears the counter.
If, for example, you write the value 10H to T2DATA and 0EH to T2CON, the counter will increment until it
reaches 10H. At this point, the Timer 2 interrupt request is generated, the counter value is reset, and counting
resumes.
12-1
8-BIT 2
S3C825A/P825A
TIMER 2 CONTROL REGISTER (T2CON)
You use the timer 2 control register, T2CON, to
— Enable the timer 2 operating (interval timer)
— Select the timer 2 input clock frequency
— Clear the timer 2 counter, T2CNT
— Enable the timer 2 interrupt and clear timer 2 interrupt pending condition
T2CON is located in set 1, bank 0, at address EEH, and is read/write addressable using register addressing
mode.
A reset clears T2CON to "00H". This sets timer 2 to disable interval timer mode, and disables timer 2 interrupt.
You can clear the timer 2 counter at any time during normal operation by writing a “1” to T2CON.3
To enable the timer 2 interrupt (IRQ2, vector E8H), you must write T2CON.2, and T2CON.1 to "1". To detect an
interrupt pending condition when T2INT is disabled, the application program polls pending bit, T2CON.0. When a
"1" is detected, a timer 2 interrupt is pending. When the T2INT sub-routine has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 2 interrupt pending bit, T2CON.0.
Timer 2 Control Register
EEH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 2 input clock selection bits:
000 = fxx/256
Timer 2 interrupt pending bit:
0 = No interrupt pending
001 = fxx/64
010 = fxx/8
0 = Clear pending bit (when write)
1 = Interrupt is pending
011 = fxx
111= External clock (T2CLK) input
Timer 2 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Not used
Timer 2 count enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer 2 counter clear bit:
0 = No affect
1 = Clear the timer 2 counter
(when write)
Figure 12-1. Timer 2 Control Register (T2CON)
12-2
S3C825A/P825A
8-BIT TIMER 2
BLOCK DIAGRAM
Bits 7, 6, 5
Data Bus
8
Bit 3
T2CLK
(P2.2)
fxx/256
M
U
X
8-bit up-Counter
(Read Only)
R
fxx/64
fxx/8
fxx/1
Clear
Pending
Bit 0
T2INT
IRQ2
8-bit Comparator
Match
Bit 2
Timer 2 Buffer Register
Bit 1
Counter clear signal (T2CON.3),
Match signal
Timer 2 Data Register
(Read/Write)
8
Data Bus
Figure 12-2. Timer 2 Functional Block Diagram
12-3
8-BIT 2
S3C825A/P825A
NOTES
12-4
S3C825A/P825A
16-BIT TIMER 3
13 16-BIT TIMER 3
OVERVIEW
Timer/counter 3 has three operating modes, one of which you select using the appropriate T3CON setting:
— Interval timer mode
— Capture input mode with a rising or falling edge trigger at the P3.6 pin
— PWM mode
Timer/counter 3 has the following functional components:
— Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer
— External clock input (P3.5, T3CLK)
— 16-bit counter(T3CNTH,T3CNTL), 16-bit comparator, and 16-bit reference data register(T3DATAH,T3DATAL)
— I/O pins for capture input, match output, or PWM output (P3.6/T3CAP, P3.6/T3OUT, P3.6/T3PWM)
— Timer 3 overflow interrupt (IRQ2, vector ECH) and match/capture interrupt (IRQ2, vector EAH) generation
— Timer 3 control register, T3CON (set 1, F8H, bank 0, read/write)
TIMER/COUNTER 3 CONTROL REGISTER (T3CON)
You use the timer 3 control register, T3CON, to
— Select the timer 3 operating mode (interval timer, capture mode, or PWM mode)
— Select the timer 3 input clock frequency
— Clear the timer 3 counter, T3CNTH/T3CNTL
— Enable the timer 3 overflow interrupt or timer 3 match/capture interrupt
— Clear timer 3 match/capture interrupt pending condition
13-1
16-BIT TIMER 3
S3C825A/P825A
T3CON is located in set 1, bank 0, at address F8H, and is read/write addressable using Register addressing
mode.
A reset clears T3CON to “00H”. This sets timer 3 to normal interval timer mode, selects an input clock frequency
of fxx/1024, and disables all timer 3 interrupts. You can clear the timer 3 counter at any time during normal
operation by writing a "1" to T3CON.2.
The timer 3 overflow interrupt (T3OVF) is interrupt level IRQ2 and has the vector address ECH. When a timer 3
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware
or must be cleared by software.
To enable the timer 3 match/capture interrupt (IRQ2, vector EAH), you must write T3CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.3. When a "1" is detected, a
timer 3 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 3 match/capture interrupt pending bit,
INTPND.3.
Timer 3 Control Register (T3CON)
F8H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 3 input clock selection bits:
000 = fxx/1024
001 = fxx/256
Timer 3 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
010 = fxx/64
011 = fxx/8
100 = fxx
Timer 3 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
101 = External clock
(P3.5/T3CLK) falling edge
110 = External clock
(P3.5/T3CLK) rising edge
111 = Counter stop
Timer 3 counter clear bit:
0 = No effect
1 = Clear the timer 3 counter (when write)
Timer 3 operating mode selection bits:
00 = Interval mode (P3.6/T3OUT)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF and match interrupt can occur)
Figure 13-1. Timer 3 Control Register (T3CON)
13-2
S3C825A/P825A
16-BIT TIMER 3
Interrupt Pending Register (INTPND)
D0H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Timer 0 overflow interrupt pending bit
Timer 0 match/capture interrupt pending bit
Timer 3 overflow interrupt pending bit
Timer 3 match/capture interrupt pending bit
Tx interrupt pending bit (for UART)
Rx interrupt pending bit (for UART):
0 = Interrupt request is not pending, pending bit clear when write "0".
1 = Interrupt request is pending
Figure 13-2. Interrupt Pending Register (INTPND)
13-3
16-BIT TIMER 3
S3C825A/P825A
TIMER 3 FUNCTION DESCRIPTION
Timer 3 Interrupts (IRQ2, Vectors EAH and ECH)
The timer 3 can generate two interrupts: the timer 3 overflow interrupt (T3OVF), and the timer 3 match/ capture
interrupt (T3INT). T3OVF is belongs to interrupt level IRQ2, vector ECH. T3INT also belongs to interrupt level
IRQ2, but is assigned the separate vector address, EAH.
A timer 3 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or
should be cleared by software in the interrupt service routine by writing a “0” to the INTPND.2 interrupt pending
bit. However, the timer 3 match/capture interrupt pending condition must be cleared by the application’s interrupt
service routine by writing a "0" to the INTPND.3 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
timer 3 reference data register, T3DATAH/T3DATAL. The match signal generates a timer 3 match interrupt
(T3INT, vector EAH) and clears the counter.
If, for example, you write the value "1087H" to T3DATAH/T3DATAL, the counter will increment until it reaches
“1087H”. At this point, the timer 3 interrupt request is generated, the counter value is reset, and counting
resumes. With each match, the level of the signal at the timer 3 output pin is inverted (see Figure 13-3).
Interrupt Enable/Disable
Capture Signal
T3CON.1
R (Clear)
16-Bit Up Counter
16-Bit Comparator
CLK
T3INT (IRQ2)
(Match INT)
M
U
X
INTPND.3
Pending
Match
T3OUT (P3.6)
Timer 3 Buffer Register
Timer 3 Data Register
T3CON.4-.3
Match Signal
T3CON.2
T3OVF
Figure 13-3. Simplified Timer 3 Function Diagram: Interval Timer Mode
13-4
S3C825A/P825A
16-BIT TIMER 3
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T3PWM (P3.6) pin. As in interval timer mode, a match signal is generated when the counter value is identical to
the value written to the timer 3 data register. In PWM mode, however, the match signal does not clear the
counter. Instead, it runs continuously, overflowing at "FFFFH", and then continues incrementing from "0000H".
Although you can use the match signal to generate a timer 3 overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T3PWM (P3.6) pin is held to Low level as long as the reference
data value is less than or equal to ( £ ) the counter value and then the pulse is held to High level for as long as
the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK ´ 65536 (see Figure 13-4).
T3CON.0
Interrupt Enable/Disable
Capture Signal
T3CON.1
T3OVF(IRQ2)
(Overflow INT)
CLK
16-Bit Up Counter
16-Bit Comparator
INTPND.2
T3INT (IRQ2)
(Match INT)
M
U
X
Match
INTPND.3
Pending
T3PWM
Output (P3.6)
High level when
data > counter,
Lower level when
data < counter
Timer 3 Buffer Register
Timer 3 Data Register
T3CON.4-.3
Match Signal
T3CON.2
T3OVF
Figure 13-4. Simplified Timer 3 Function Diagram: PWM Mode
13-5
16-BIT TIMER 3
Capture Mode
S3C825A/P825A
In capture mode, a signal edge that is detected at the T3CAP (P3.6) pin opens a gate and loads the current
counter value into the timer 3 data register. You can select rising or falling edges to trigger this operation.
Timer 3 also gives you capture input source: the signal edge at the T3CAP (P3.6) pin. You select the capture
input by setting the values of the timer 3 capture input selection bits in the port 3 control register, P3CONH.5–.4,
(set 1, bank 1, E4H). When P3CONH.5–.4 is "00", the T3CAP input is selected.
Both kinds of timer 3 interrupts can be used in capture mode: the timer 3 overflow interrupt is generated
whenever a counter overflow occurs; the timer 3 match/capture interrupt is generated whenever the counter
value is loaded into the timer 3 data register.
By reading the captured data value in T3DATAH/T3DATAL, and assuming a specific value for the timer 3 clock
frequency, you can calculate the pulse width (duration) of the signal that is being input at the T3CAP pin (see
Figure 13-5).
T3CON.0
T3OVF(IRQ2)
16-Bit Up Counter
INTPND.2
CLK
(Overflow INT)
Interrupt Enable/Disable
T3CON.1
T3INT (IRQ2)
(Capture INT)
M
U
X
INTPND.3
Pending
T3CAP input
(P3.6)
Match Signal
T3CON.4-.3
T3CON.4-.3
Timer 3 Data Register
Figure 13-5. Simplified Timer 3 Function Diagram: Capture Mode
13-6
S3C825A/P825A
16-BIT TIMER 3
T3CON.0
T3CON.7-.5
T3OVF
(IRQ2)
OVF
INTPND.2
Data BUS
8
fxx/1024
fxx/256
fxx/64
fxx/8
T3CON.2
Clear
fxx/1
16-Bit Up Counter
(Read-Only)
MUX
R
T3CLK
T3CON.1
T3INT
(IRQ2)
M
U
X
16-Bit Comparator
INTPND.3
Match
M
U
X
T3OUT
T3PWM
Timer 3 Buffer Register
Timer 3 Data Register
T3CAP
T3CON.4-.3
Match signal
T3CON.2
T3OVF
T3CON.4-.3
8
Data BUS
Figure 13-6. Timer 3 Block Diagram
13-7
16-BIT TIMER 3
S3C825A/P825A
NOTES
13-8
S3C825A/P825A
WATCH TIMER
14 WATCH TIMER
OVERVIEW
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock.
To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".
And if you want to service watch timer overflow interrupt (IRQ4, vector D6H), then set the WTCON.6 to “1”.
The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application’s
interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit.
After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically
set to "1", and interrupt requests commence in 3.91 ms, 0.25, 0.5 and 1-second intervals by setting Watch timer
speed selection bits (WTCON.3 – .2).
The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By
setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an
interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences.
The watch timer supplies the clock frequency for the LCD controller (fLCD). Therefore, if the watch timer is
disabled, the LCD controller does not operate.
Watch timer has the following functional components:
— Real Time and Watch-Time Measurement
— Using a Main Clock Source or Sub clock
— Clock Source Generation for LCD Controller (fLCD
)
— I/O pin for Buzzer Output Frequency Generator (P5.3, BUZ)
— Timing Tests in High-Speed Mode
— Watch timer overflow interrupt (IRQ4, vector D6H) generation
— Watch timer control register, WTCON (set 1, bank 1, EFH, read/write)
14-1
WATCH TIMER
S3C825A/P825A
WATCH TIMER CONTROL REGISTER (WTCON)
The watch timer control register, WTCON is used to select the watch timer interrupt time and Buzzer signal, to
enable or disable the watch timer function. It is located in set 1, bank 1 at address EFH, and is read/write
addressable using register addressing mode.
A reset clears WTCON to "00H". This disable the watch timer.
So, if you want to use the watch timer, you must write appropriate value to WTCON.
Watch Timer Control Register (WTCON)
EFH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Watch timer interrupt pending bit:
0 = Interrupt request is not pending
(Clear pending bit when write"0")
1 = Interrupt request is pending
Watch timer clock selection bit:
0 = Select main clock divided by 27 (fx/128)
1 = Select Sub clock (fxt)
Watch timer INT Enable/Disable bit:
0 = Disable watch timer INT
1 = Enable watch timer INT
Watch timer Enable/Disable bit:
0 = Disable watch timer
1 = Enable watch timer
Buzzer signal selection bits:
00 = 0.5 kHz
01 = 1 kHz
10 = 2 kHz
11 = 4 kHz
Watch timer speed selection bits:
00 = Set watch timer interrupt to 1 s
01 = Set watch timer interrupt to 0.5 s
10 = Set watch timer interrupt to 0.25 s
11 = Set watch timer interrupt to 3.91 ms
Figure 14-1. Watch Timer Control Register (WTCON)
14-2
S3C825A/P825A
WATCH TIMER
WATCH TIMER CIRCUIT DIAGRAM
WTCON.7
WTCON.6
WTCON.5
WT INT Enable
BUZ (P5.3)
WTINT
WTCON.6
MUX
WTCON.4
8
fW/16 (0.5 kHz)
WTCON.3
fW/8 (1 kHz)
fW/4 (2 kHz)
fW/2 (4 kHz)
WTCON.2
Enable/Disable
WTCON.1
Selector
Circuit
WTCON.0
WTCON.0
(Pending Bit)
fW/27
fW/213
fW/214
fW/215
Frequency
Dividing
Circuit
Clock
Selector
fW
(1 Hz)
32.768 kHz
fLCD = 2048 Hz
fX = Main clock (where fx = 4.19 MHz)
fxt = Sub clock (32.768 kHz)
fW = Watch timer frequency
fxt
fX/128
Figure 14-2. Watch Timer Circuit Diagram
14-3
WATCH TIMER
S3C825A/P825A
NOTES
14-4
S3C825A/P825A
LCD CONTROLLER/DRIVER
15 LCD CONTROLLER/DRIVER
OVERVIEW
The S3C825A microcontroller can directly drive an up-to-224-dot (28 segments x 8 commons) LCD panel. Its
LCD block has the following components:
— LCD controller/driver
— Display RAM for storing display data
— 4 common/segment output pins (COM4/SEG0–COM7/SEG3)
— 28 segment output pins (SEG4–SEG31)
— 4 common output pins (COM0–COM3)
— Internal resistor circuit for LCD bias
— VLC1 pin for controlling the driver and bias voltage
The LCD control register, LCON, is used to turn the LCD display on and off, switch the current to the dividing
resistors for the LCD display, and frame frequency. Data written to the LCD display RAM can be automatically
transferred to the segment signal pins without any program control.
When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even in the main clock
stop or idle mode.
VLC1
1
COM0-COM3
LCD
4
4
Controller/
Driver
8
COM4-COM7/
SEG0-SEG3
SEG4-SEG31
28
Figure 15-1. LCD Function Diagram
15-1
LCD CONTROLLER/DRIVER
LCD CIRCUIT DIAGRAM
S3C825A/P825A
SEG31/P1.7
Display
RAM
(Page 7)
Selector
32
SEG4/P7.0
fLC
COM7/SEG3/P6.7
COM6/SEG2/P6.6
COM5/SEG1/P6.5
COM4/SEG0/P6.4
COM
Control
or
Timing
Controller
Selector
COM3/P6.3
COM2/P6.2
COM1/P6.1
COM0/P6.0
COM
Control
LMOD
LCON
LCD
Voltage
Control
VLC1
Figure 15-2. LCD Circuit Diagram
15-2
S3C825A/P825A
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA
RAM addresses of page 7 are used as LCD data memory. These locations can be addressed by 1-bit or 8-bit
instructions. If the bit value of a display segment is "1", the LCD display is turned on. If the bit value is "0", the
display is turned off.
Display RAM data are sent out through the segment pins, SEG0–SEG31, using the direct memory access (DMA)
method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD
display can be allocated to general-purpose use.
COM
Bit
SEG0
700H
SEG1
701H
SEG2
702H
SEG3
703H
SEG4
704H
------
------
SEG30 SEG31
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
.0
.1
.2
.3
.4
.5
.6
.7
71EH
71FH
Figure 15-3. LCD Display Data RAM Organization
15-3
LCD CONTROLLER/DRIVER
S3C825A/P825A
LCD CONTROL REGISTER (LCON)
The LCD control register (LCON) is used to turn the LCD display on and off, LCD frame frequency, and control
the flow of the current to the dividing resistors in the LCD circuit. After a RESET, all LCON values are cleared to
"0". This turns the LCD display off and stops the flow of the current to the dividing resistors.
LCD Control Register (LCON)
F2H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
LCD clock select bits:
Not used for the S3C825A.
00 = fw/27(256 Hz at fw = 32.768 kHz)
01 = fw/26(512 Hz at fw = 32.768 kHz)
10 = fw/25(1024 Hz at fw = 32.768 kHz)
11 = fw/24(2048 Hz at fw = 32.768 kHz)
LCD display control bits:
00 = Display off, P-Tr off
01 = Normal display (Using VLC1 with
external voltage), P-Tr off
11 = Normal display (Using VLC1 with
internal voltage), P-Tr on
LCD duty and bias selection bits:
00 = 1/3 duty, 1/3 bias; COM0-2/SEG0-31
01 = 1/4 duty, 1/3 bias; COM0-3/SEG0-31
10 = 1/8 duty, 1/4 bias; COM0-7/SEG4-31
11 = 1/8 duty, 1/5 bias; COM0-7/SEG4-31
Figure 15-4. LCD Control Register (LCON)
15-4
S3C825A/P825A
LCD CONTROLLER/DRIVER
LCD MODE CONTROL REGISTER (LMOD), F3H at BANK 0 of SET 1
Table 15-1. LCD Mode Control Register (LMOD) Organization
LCON Bit
LMOD.7–.4
LMOD.3–.0
Setting
Description
Not used for the S3C825A.
0000
0001
All I/O port (P0, P1, P6–P8)
Select LCD COM0–3, COM4–7/SEG0–3.
P0, P1, P7, and P8 are I/O port.
0010
0011
0100
0101
0110
0111
1000
Select LCD COM0–3, COM4–7/SEG0–3, SEG4–7.
P0, P1, P7.4–P7.7, and P8 are I/O port.
Select LCD COM0–3, COM4–7/SEG0–3, SEG4–11.
P0, P1, and P8 are I/O port.
Select LCD COM0–3, COM4–7/SEG0–3, SEG4–15.
P0 and P1are I/O port.
Select LCD COM0–3, COM4–7/SEG0–3, SEG4–19.
P0.4–P0.7 and P1 are I/O port.
Select LCD COM0–3, COM4–7/SEG0–3, SEG4–23.
P1 is I/O port.
Select LCD COM0–3, COM4–7/SEG0–3, SEG4–27.
P1.4–P1.7 is I/O port.
Select LCD COM0–3, COM4–7/SEG0–3, SEG4–31.
NOTE: The COM4–7/SEG0–3 signals are controlled by LCON.3–.2.
15-5
LCD CONTROLLER/DRIVER
S3C825A/P825A
LCD VOLTAGE DIVIDING RESISTORS
On-chip voltage dividing resistors for the LCD drive power supply are fixed to the VLC1–VLC5 pins. Figure 15-5
shows the bias connections for the S3C825A LCD drive power supply. To cut off the flow of current through the
dividing resistor, manipulate bits 7 and 6 of the LCON register.
1/5 Bias
1/4 Bias
1/3 Bias
S3C825A
S3C825A
S3C825A
VDD
VDD
VDD
LCON.7-.6
LCON.7-.6
LCON.7-.6
VLC1
VLC2
VLC1
VLC2
VLC1
VLC2
VLC1
VLC1
VLC1
R
R
R
R
R
R
VLC3
VLC4
VLC5
VSS
VLC3
VLC4
VLC5
VSS
VLC3
VLC4
VLC5
VSS
R
R
R
R
R
R
R
R
R
R
R
R
Figure 15-5. LCD Bias Circuit Connection
15-6
S3C825A/P825A
LCD CONTROLLER/DRIVER
In Case of Internal VDD
S3C825A
VDD
LCON.7-.6
On
VLC1
VLC2
VLC1
R
R
VLC3
VLC4
VLC5
VSS
R
R
R
R
NOTE:
For power-saving and LCD-off, LCON.7-.6 must be set to 00B.
For a normal display, LCON.7-.6 must be set to 11B.
Figure 15-6. Example 1 for the Usage of LCON.7–.6
15-7
LCD CONTROLLER/DRIVER
S3C825A/P825A
In Case of Internal VDD
S3C825A
VDD
VDD
LCON.7-.6
Off
VLC1
VLC2
VLC1
R
R
VLC3
VLC4
VLC5
VSS
R
R
R
R
NOTE: For power-saving and LCD-off, LCON.7-.6 must be set to 00B.
For a normal display, LCON.7-.6 must be set to 01B.
Figure 15-7. Example 2 for the Usage of LCON.7–.6
15-8
S3C825A/P825A
LCD CONTROLLER/DRIVER
SEG2 SEG1 SEG0
0
1
2
0
1
2
V
V
LC1
SS
FR
COM0
1 FRAME
V
V
V
V
LC1
COM1
COM2
V
)
(
LC2 LC3
COM0
V
)
(
LC4 LC5
SS
V
V
V
V
LC1
V
)
(
LC2 LC3
COM1
V
)
(
LC4 LC5
SS
V
V
V
V
LC1
V
)
(
LC2 LC3
COM2
SEG0
SEG1
V
)
(
LC4 LC5
SS
V
V
V
V
LC1
V
)
(
LC2 LC3
V
)
(
LC4 LC5
SS
V
V
V
V
LC1
V
)
(
LC2 LC3
V
)
(
LC4 LC5
SS
+ V
LC1
+ 1/3 V
0 V
LC1
LC1
SEG0 COM0
-
1/3 V
-
V
-
LC1
Figure 15-8. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
15-9
LCD CONTROLLER/DRIVER
S3C825A/P825A
SEG1 SEG0
0
1
2
3
0
1
2
3
V
LC1
SS
V
FR
COM0
COM1
COM2
COM3
1 FRAME
V
V
V
V
LC1
V
)
(
LC2 LC3
COM0
V
)
(
LC4 LC5
SS
V
V
V
V
LC1
V
)
(
LC2 LC3
COM1
V
)
(
LC4 LC5
SS
V
V
LC1
V
)
(
LC2 LC3
COM2
COM3
SEG0
V
V
V
)
(
LC4 LC5
SS
V
V
V
LC1
V
)
(
LC2 LC3
V
)
(
LC4 LC5
V
V
V
V
LC1
V
)
(
LC2 LC3
V
)
(
LC4 LC5
SS
V
V
V
V
LC1
V
)
(
LC2 LC3
SEG1
V
)
(
LC4 LC5
SS
+ V
LC1
+ 1/3 V
0 V
LC1
LC1
SEG0 COM0
-
1/3 V
-
V
-
LC1
Figure 15-9. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
15-10
S3C825A/P825A
LCD CONTROLLER/DRIVER
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
0
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
V
V
LC1
SS
FR
1 FRAME
V
V
V
V
V
LC1
LC2
V
(
)
LC3 LC4
S S S S S
COM0
E E E E E
G G G G G
5 6 7 8 9
LC5
SS
V
V
V
V
V
LC1
LC2
V
(
)
LC3 LC4
COM1
COM2
SEG5
LC5
SS
V
V
V
V
V
LC1
LC2
V
(
)
LC3 LC4
LC5
SS
V
V
V
V
V
LC1
LC2
V
(
)
LC3 LC4
LC5
SS
V
V
V
V
LC1
LC2
V
(
)
LC3 LC4
LC5
0V
SEG5 COM0
-
V
V
V
V
-
-
-
-
LC5
V
(
)
-
LC3
LC4
LC2
LC1
Figure 15-10. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
15-11
LCD CONTROLLER/DRIVER
S3C825A/P825A
0
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
V
V
LC1
SS
FR
1 FRAME
V
V
V
V
V
LC1
LC2
V
(
)
LC3 LC4
SEG6
LC5
SS
V
V
V
V
LC1
LC2
V
(
)
LC3 LC4
LC5
SEG6 COM0
-
0V
V
V
V
V
-
-
-
-
LC5
V
(
)
-
LC3
LC2
LC1
LC4
Figure 15-10. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)
15-12
S3C825A/P825A
LCD CONTROLLER/DRIVER
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
0 1 2 3
7
0 1 2 3
7
V
V
LC1
SS
FR
1 FRAME
V
V
V
V
V
LC1
LC2
S S S S S
LC3
LC4
LC5
COM0
E E E E E
G G G G G
5 6 7 8 9
Vss
V
V
V
V
V
V
LC1
LC2
LC3
LC4
COM1
COM2
SEG5
LC5
SS
V
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SS
V
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SS
Figure 15-11. LCD Signal Waveforms (1/8 Duty, 1/5 Bias)
15-13
LCD CONTROLLER/DRIVER
S3C825A/P825A
0 1 2 3
7 0 1 2 3
7
V
V
LC1
SS
FR
1 FRAME
V
V
V
V
V
V
LC1
LC2
LC3
LC4
SEG6
LC5
SS
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SEG5 COM0
-
0V
V
V
V
V
V
-
-
-
-
-
LC5
LC4
LC3
LC2
LC1
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SEG6 COM0
-
0V
V
V
V
-
-
-
LC5
LC4
LC3
V
V
-
LC2
-
LC1
Figure 15-11. LCD Signal Waveforms (1/8 Duty, 1/5 Bias) (Continued)
15-14
S3C825A/P825A
A/D CONVERTER
16 10-BIT ANALOG-TO-DIGITAL CONVERTER
OVERVIEW
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at
one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the
AVREF and AVSS values. The A/D converter has the following components:
— Analog comparator with successive approximation logic
— D/A converter logic (resistor string type)
— ADC control register (ADCON)
— Four multiplexed analog data input pins (AD0–AD3)
— 10-bit A/D conversion data output register (ADDATAH/ADDATAL)
— 4-bit digital input port (Alternately, I/O port)
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input
enable at port 3, the pin set with alternative function can be used for ADC analog input. And you write the
channel selection data in the A/D converter control register ADCON.4–.5 to select one of the four analog input
pins (AD0–3) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located in
set 1, bank 0, at address EFH. The pins witch are not used for ADC can be used for normal I/O.
During a normal conversion, ADC logic initially sets the successive approximation register to 800H (the
approximate half-way point of an 10-bit register). This register is then updated automatically during each
conversion step. The successive approximation block performs 10-bit conversions for one input channel at a
time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5–
4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a
conversion is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is
dumped into the ADDATAH/ADDATAL register where it can be read. The A/D converter then enters an idle state.
Remember to read the contents of ADDATAH/ADDATAL before another conversion starts. Otherwise, the
previous result will be overwritten by the next conversion result.
NOTE
Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog
level at the AD0–AD3 input pins during a conversion procedure be kept to an absolute minimum. Any change in
the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in
conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after
ADC operation is finished.
16-1
A/D CONVERTER
S3C825A/P825A
CONVERSION TIMING
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D
conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected
for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion
requires 4 clocks, the conversion rate is calculated as follows:
4 clocks/bit ´ 10-bit + set-up time = 50 clocks, 50 clock ´ 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8)
Note that A/D converter needs at least 25ms for conversion time.
A/D CONVERTER CONTROL REGISTER (ADCON)
The A/D converter control register, ADCON, is located at address EFH in set 1, bank 0. It has three functions:
— Analog input pin selection (bits 4 and 5)
— End-of-conversion status detection (bit 3)
— ADC clock selection (bits 2 and 1)
— A/D operation start or enable (bit 0 )
After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog
input pins (AD0–AD3) can be selected dynamically by manipulating the ADCON.4–5 bits. And the pins not used
for analog input can be used for normal I/O function.
A/D Converter Control Register (ADCON)
EFH, Set 1, Bank 0, R/W (EOC bit is read-only)
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Always logic zero
Start or enable bit
0 = Disable operation
1 = Start operation
A/D input pin selection bits:
00 = AD0
01 = AD1
Clock Selection bits:
00 = fxx/16
10 = AD2
01 = fxx/8
11 = AD3
10 = fxx/4
11 = fxx/1
End-of-conversion bit
0 = Not complete Conversion
1 = complete Conversion
Figure 16-1. A/D Converter Control Register (ADCON)
16-2
S3C825A/P825A
A/D CONVERTER
Conversion Data Register ADDATAH/ADDATAL
F0H/F1H, Set 1, Bank 0, Read Only
MSB
MSB
.9
-
.8
-
.7
-
.6
-
.5
-
.4
-
.3
.1
.2
.0
LSB (ADDATAH)
LSB (ADDATAL)
Figure 16-2. A/D Converter Data Register (ADDATAH/ADDATAL)
INTERNAL REFERENCE VOLTAGE LEVELS
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input
level must remain within the range AVSS to AVREF
.
Different reference voltage levels are generated internally along the resistor tree during the analog conversion
process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AVREF
.
BLOCK DIAGRAM
ADCON.2-.1
ADCON.4-5
(Select one input pin of the assigned pins)
To ADCON.3
(EOC Flag)
Clock
Selector
ADCON.0
(AD/C Enable)
M
U
X
Analog
Comparator
Successive
Approximation
Logic & Register
-
Input Pins
AD0-AD3
(P3.0-P3.3)
.
.
.
+
ADCON.0
(AD/C Enable)
P3CONL
(Assign Pins to ADC Input)
Conversion Result
(ADDATAH/ADDATAL,
F0H/F1H, Set 1, Bank 0)
AVREF
AVSS
10-bit D/A
Converter
Figure 16-3. A/D Converter Functional Block Diagram
16-3
A/D CONVERTER
S3C825A/P825A
VDD
Reference
Voltage Input
AVREF
+
-
C
10 mF
103
(AVREF £ VDD)
VDD
Analog
Input Pin
AD0-AD3
S3C825A
C
101
AVSS
Figure 16-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
16-4
S3C825A/P825A
SERIAL I/O INTERFACE
17 SERIAL I/O INTERFACE
OVERVIEW
Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The
components of SIO function block are:
— 8-bit control register (SIOCON)
— Clock selector logic
— 8-bit data buffer (SIODATA)
— 8-bit prescaler (SIOPS)
— 3-bit serial clock counter
— Serial data I/O pins (SI, SO)
— External clock input/output pin (SCK)
The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.
PROGRAMMING PROCEDURE
To program the SIO module, follow these basic steps:
1. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P5CONL register if
necessary.
2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this
operation, SIOCON.2 must be set to "1" to enable the data shifter.
3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1".
4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift
operation starts.
5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) are set to "1" and
SIO interrupt request is generated.
17-1
SERIAL I/O INTERFACE
S3C825A/P825A
SIO CONTROL REGISTERS (SIOCON)
The control register for serial I/O interface module, SIOCON, is located at E0H in set 1, bank 0. It has the control
setting for SIO module.
— Clock source selection (internal or external) for shift clock
— Interrupt enable
— Edge selection for shift operation
— Clear 3-bit counter and start shift operation
— Shift operation (transmit) enable
— Mode selection (transmit/receive or receive-only)
— Data direction selection (MSB first or LSB first)
A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock
source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation
and the interrupt are disabled. The selected data direction is MSB-first.
Serial I/O Module Control Register (SIOCON)
E0H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
SIO interrupt pending bit:
0 = No interrupt pending
0 = Clear pending condition
(when write)
SIO shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK)
1 = Interrupt is pending
Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode
SIO interrupt enable bit:
0 = Disable SIO interrupt
1 = Enable SIO interrupt
SIO mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode
SIO shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter
Shift clock edge selection bit:
0 = tX at falling edeges, rx at rising edges.
1 = tX at rising edeges, rx at falling edges.
SIO counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting
Figure 17-1. Serial I/O Module Control Register (SIOCON)
17-2
S3C825A/P825A
SERIAL I/O INTERFACE
SIO PRE-SCALER REGISTER (SIOPS)
The prescaler register for serial I/O interface module, SIOPS, are located at E2H in set 1, bank 0.
The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as
follows:
Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.
SIO Pre-scaler Register (SIOPS)
E2H, Set 1, Bank 0 R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate = (fXX/4)/(SIOPS + 1)
Figure 17-2. SIO Prescaler Register (SIOPS)
SIO BLOCK DIAGRAM
SIO INT
3-Bit Counter
SIOCON.0
Pending
IRQ3
Clear
CLK
SIOCON.1
(Interrupt Enable)
SIOCON.3
SIOCON.7
SIOCON.4
SIOCON.2
(Edge Select)
(Shift Enable)
SIOCON.5
M
U
X
SCK
fxx/2
(Mode Select)
SIOPS (E2H, bank 0)
8-bit P.S. 1/2
CLK
8-Bit SIO Shift Buffer
SO
(SIODATA, E1H, bank 0)
SIOCON.6
(LSB/MSB First
Mode Select)
8
SI
Data Bus
Figure 17-3. SIO Functional Block Diagram
17-3
SERIAL I/O INTERFACE
S3C825A/P825A
SERIAL I/O TIMING DIAGRAM (SIO)
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQ3
Set SIOCON.3
Figure 17-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
SCK
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQ3
Set SIOCON.3
Figure 17-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
17-4
S3C825A/P825A
UART
18 UART
OVERVIEW
The UART block has a full-duplex serial port with programmable operating modes: There is one synchronous
mode and three UART (Universal Asynchronous Receiver/Transmitter) modes:
— Serial I/O with baud rate of fxx/(16 ´ (BRDATA+1))
— 8-bit UART mode; variable baud rate
— 9-bit UART mode; fxx/16
— 9-bit UART mode, variable baud rate
UART receive and transmit buffers are both accessed via the data register, UDATA, is set 1, bank 0 at address
F9H. Writing to the UART data register loads the transmit buffer; reading the UART data register accesses a
physically separate receive buffer.
When accessing a receive data buffer (shift register), reception of the next byte can begin before the previously
received byte has been read from the receive register. However, if the first byte has not been read by the time
the next byte has been completely received, one of the bytes will be lost.
In all operating modes, transmission is started when any instruction (usually a write operation) uses the UDATA
register as its destination address. In mode 0, serial data reception starts when the receive interrupt pending bit
(INTPND.5) is "0" and the receive enable bit (UARTCON.4) is "1". In mode 1, 2, and 3, reception starts whenever
an incoming start bit ("0") is received and the receive enable bit (UARTCON.4) is set to "1".
PROGRAMMING PROCEDURE
To program the UART modules, follow these basic steps:
1. Configure P5.4 and P5.5 to alternative function (RxD (P5.4), TxD (P5.5)) for UART module by setting the
P5CONH register to appropriatly value.
2. Load an 8-bit value to the UARTCON control register to properly configure the UART I/O module.
3. For interrupt generation, set the UART I/O interrupt enable bit (UARTCON.1 or UARTCON.0) to "1".
4. When you transmit data to the UART buffer, write data to UDATA, the shift operation starts.
5. When the shift operation (transmit/receive) is completed, UART pending bit (INTPND.4 or INTPND.5) is set
to "1" and an UART interrupt request is generated.
18-1
UART
S3C825A/P825A
UART CONTROL REGISTER (UARTCON)
The control register for the UART is called UARTCON in set 1, bank 0 at address FAH. It has the following
control functions:
— Operating mode and baud rate selection
— Multiprocessor communication and interrupt control
— Serial receive enable/disable control
— 9th data bit location for transmit and receive operations (modes 2 and 3 only)
— UART transmit and receive interrupt control
A reset clears the UARTCON value to "00H". So, if you want to use UART module, you must write appropriate
value to UARTCON.
UART Control Register (UARTCON)
FAH, Set 1, Bank 0, R/W
MSB MS1 MS0 MCE RE TB8 RB8 RIE
TIE LSB
Operating mode and
baud rate selection bits
(see table below)
Transmit interrupt enable bit:
0 = Disable
1 = Enable
Multiprocessor communication(1)
enable bit (for modes 2 and 3 only):
0 = Disable
Received interrupt enable bit:
0 = Disable
1 = Enable
1 = Enable
Serial data receive enable bit: Location of the 9th data bit that was
0 = Disable
1 = Enable
received in UART mode 2 or 3 ("0" or "1")
Location of the 9th data bit to be
transmitted in UART mode 2 or 3 ("0" or "1")
MS1 MS0 Mode Description(2) Baud Rate
0
0
1
1
0
1
0
1
0
1
2
3
Shift register fxx/(16 x (BRDATA + 1))
8-bit UART
9-bit UART
9-bit UART
fxx/(16 x (BRDATA + 1))
fxx/16
fxx/(16 x (BRDATA + 1))
NOTES:
1. In mode 2 or 3, if the UARTCON.5 bit is set to "1" then the receive interrupt will not be
activated if the received 9th data bit is "0". In mode 1, if UARTCON.5 = "1" then the
receive interrut will not be activated if a valid stop bit was not received.
In mode 0, the UARTCON.5 bit should be "0"
2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits
for serial data receive and transmit.
Figure 18-1. UART Control Register (UARTCON)
18-2
S3C825A/P825A
UART
UART INTERRUPT PENDING BITS
The UART interrupt pending bits, INTPND.5–.4, are located in set 1, bank 0 at address D0H, it contains the
UART data transmit interrupt pending bit (INTPND.4) and the receive interrupt pending bit (INTPND.5).
In mode 0, the receive interrupt pending bit INTPND.5 is set to "1" when the 8th receive data bit has been
shifted. In mode 1, 2, and 3, the INTPND.5 bit is set to "1" at the halfway point of the stop bit's shift time. When
the CPU has acknowledged the receive interrupt pending condition, the INTPND.5 bit must then be cleared by
software in the interrupt service routine.
In mode 0, the transmit interrupt pending bit INTPND.4 is set to "1" when the 8th transmit data bit has been
shifted. In mode 1, 2, or 3, the INTPND.4 bit is set at the start of the stop bit. When the CPU has acknowledged
the transmit interrupt pending condition, the INTPND.4 bit must then be cleared by software in the interrupt
service routine.
Interrupt Pending Register (INTPND)
D0H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Timer 0 overflow interrupt pending bit
Timer 0 match/capture interrupt pending bit
Timer 3 overflow interrupt pending bit
Timer 3 match/capture interrupt pending bit
Tx interrupt pending bit (for UART)
Rx interrupt pending bit (for UART):
0 = Interrupt request is not pending,
pending bit clear when write "0".
1 = Interrupt request is pending
Figure 18-2. UART Interrupt Pending Bits (INTPND.5–.4)
18-3
UART
S3C825A/P825A
UART DATA REGISTER (UDATA)
UART Data Register (UDATA)
F9H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Transmit or receive data
Figure 18-3. UART Data Register (UDATA)
UART BAUD RATE DATA REGISTER (BRDATA)
The value stored in the UART baud rate register, BRDATA, lets you determine the UART clock rate (baud rate).
UART Baud Rate Data Register (BRDATA)
FBH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate data
Figure 18-4. UART Baud Rate Data Register (BRDATA)
BAUD RATE CALCULATIONS
Mode 0 Baud Rate Calculation
In mode 0, the baud rate is determined by the UART baud rate data register, BRDATA in set 1, bank 0 at
address FBH: Mode 0 baud rate = fxx/(16 ´ (BRDATA + 1)).
Mode 2 Baud Rate Calculation
The baud rate in mode 2 is fixed at the fOSC clock frequency divided by 16: Mode 2 baud rate = fxx/16
Modes 1 and 3 Baud Rate Calculation
In modes 1 and 3, the baud rate is determined by the UART baud rate data register, BRDATA in set 1, bank 0 at
address FBH: Mode 1 and 3 baud rate = fxx/(16 ´ ( BRDATA + 1))
18-4
S3C825A/P825A
UART
Table 18-1. Commonly Used Baud Rates Generated by BRDATA
Mode
Baud Rate
Oscillation Clock
BRDATA
Decimal
x
Hexdecimal
Mode 2
Mode 0
Mode 1
Mode 3
0.5 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
x
38.461 Hz
19.230 Hz
9.615 Hz
4.808 Hz
19.230 Hz
9.615 Hz
4.808 Hz
12
0CH
19H
33H
67H
0CH
19H
33H
25
51
103
12
25
51
18-5
UART
S3C825A/P825A
BLOCK DIAGRAM
SAM8 Internal Data Bus
TB8
S
BRDATA
D
Q
UARTDATA
CLK
MS0
MS1
RxD (P5.4)
TxD (P5.5)
CLK
Baud Rate
Generator
fxx
Zero Detector
Write to
UDATA
Shift
Start
Tx Control
EN
Tx Clock
TIP
Send
TxD (P5.5)
Shift
Clock
TIE
RIE
IRQ3
Interrupt
RIP
Receive
Shift
Rx Clock
Start
RE
RIE
Rx Control
1-to-0
Transition
Detector
Shift
Value
Bit Detector
Shift
Register
MS0
MS1
UARTDATA
RxD (P5.4)
SAM8 Internal Data Bus
Figure 18-5. UART Functional Block Diagram
18-6
S3C825A/P825A
UART
UART MODE 0 FUNCTION DESCRIPTION
In mode 0, UART is input and output through the RxD (P5.4) pin and TxD (P5.5) pin outputs the shift clock. Data
is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first.
Mode 0 Transmit Procedure
1. Select mode 0 by setting UARTCON.6 and .7 to "00B".
2. Write transmission data to the shift register UDATA (F9H, set 1, bank 0) to start the transmission operation.
Mode 0 Receive Procedure
1. Select mode 0 by setting UARTCON.6 and .7 to "00B".
2. Clear the receive interrupt pending bit (INTPND.5) by writing a "0" to INTPND.5.
3. Set the UART receive enable bit (UARTCON.4) to "1".
4. The shift clock will now be output to the TxD (P5.5) pin and will read the data at the RxD (P5.4) pin. A UART
receive interrupt (IRQ3, vector D4H) occurs when UARTCON.1 is set to "1".
Write to Shift Register (UDATA)
Shift
RxD (Data Out)
D0
D1
D2
D3
D4
D5
D6
D7
TxD (Shift Clock)
TIP
Write to UARTPND (Clear RIP and set RE)
RIP
RE
Shift
D0
D1
D2
D3
D4
D5
D6
D7
RxD (Data In)
TxD (Shift Clock)
1
2
3
4
5
6
7
8
Figure 18-6. Timing Diagram for Serial Port Mode 0 Operation
18-7
UART
S3C825A/P825A
SERIAL PORT MODE 1 FUNCTION DESCRIPTION
In mode 1, 10-bits are transmitted (through the TxD (P5.5) pin) or received (through the RxD (P5.4) pin). Each
data frame has three components:
— Start bit ("0")
— 8 data bits (LSB first)
— Stop bit ("1")
When receiving, the stop bit is written to the RB8 bit in the UARTCON register. The baud rate for mode 1 is
variable.
Mode 1 Transmit Procedure
1. Select the baud rate generated by BRDATA.
2. Select mode 1 (8-bit UART) by setting UARTCON bits 7 and 6 to '01B'.
3. Write transmission data to the shift register UDATA (F9H, set 1, bank 0). The start and stop bits are
generated automatically by hardware.
Mode 1 Receive Procedure
1. Select the baud rate to be generated by BRDATA.
2. Select mode 1 and set the RE (Receive Enable) bit in the UARTCON register to "1".
3. The start bit low ("0") condition at the RxD (P5.4) pin will cause the UART module to start the serial data
receive operation.
Tx
Clock
Write to Shift Register (UDATA)
Shift
TxD
TIP
D0
D1
D2
D3
D4
D5
D6
D7
Stop Bit
Start Bit
Rx
Clock
RxD
D0
D1
D2
D3
D4
D5
D6
D7
Stop Bit
Start Bit
Bit Detect Sample Time
Shift
RIP
Figure 18-7. Timing Diagram for Serial Port Mode 1 Operation
18-8
S3C825A/P825A
UART
SERIAL PORT MODE 2 FUNCTION DESCRIPTION
In mode 2, 11-bits are transmitted (through the TxD pin) or received (through the RxD pin). Each data frame has
four components:
— Start bit ("0")
— 8 data bits (LSB first)
— Programmable 9th data bit
— Stop bit ("1")
The 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the TB8 bit (UARTCON.3).
When receiving, the 9th data bit that is received is written to the RB8 bit (UARTCON.2), while the stop bit is
ignored. The baud rate for mode 2 is fosc/16 clock frequency.
Mode 2 Transmit Procedure
1. Select mode 2 (9-bit UART) by setting UARTCON bits 6 and 7 to '10B'. Also, select the 9th data bit to be
transmitted by writing TB8 to "0" or "1".
2. Write transmission data to the shift register, UDATA (F9H, set 1, bank 0), to start the transmit operation.
Mode 2 Receive Procedure
1. Select mode 2 and set the receive enable bit (RE) in the UARTCON register to "1".
2. The receive operation starts when the signal at the RxD pin goes to low level.
Tx
Clock
Write to Shift Register (UARTDATA)
Shift
TxD
TIP
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Stop Bit
Start Bit
Rx
Clock
RxD
Stop
Bit
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Start Bit
Bit Detect Sample Time
Shift
RIP
Figure 18-8. Timing Diagram for Serial Port Mode 2 Operation
18-9
UART
S3C825A/P825A
SERIAL PORT MODE 3 FUNCTION DESCRIPTION
In mode 3, 11-bits are transmitted (through the TxD (P5.5) pin) or received (through the RxD (P5.4) pin). Mode 3
is identical to mode 2 except for baud rate, which is variable. Each data frame has four components:
— Start bit ("0")
— 8 data bits (LSB first)
— Programmable 9th data bit
— Stop bit ("1")
Mode 3 Transmit Procedure
1. Select the baud rate generated by BRDATA.
2. Select mode 3 operation (9-bit UART) by setting UARTCON bits 6 and 7 to '11B'. Also, select the 9th data bit
to be transmitted by writing UARTCON.3 (TB8) to "0" or "1".
3. Write transmission data to the shift register, UDATA (F9H, set 1, bank 0), to start the transmit operation.
Mode 3 Receive Procedure
1. Select the baud rate to be generated by BRDATA.
2. Select mode 3 and set the RE (Receive Enable) bit in the UARTCON register to "1".
3. The receive operation will be started when the signal at the RxD (P5.4) pin goes to low level.
Tx
Clock
Write to Shift Register (UARTDATA)
Shift
TxD
TIP
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Stop Bit
Start Bit
Rx
Clock
RxD
Stop
Bit
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Start Bit
Bit Detect Sample Time
Shift
RIP
Figure 18-9. Timing Diagram for Serial Port Mode 3 Operation
18-10
S3C825A/P825A
UART
SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS
The S3C8-series multiprocessor communication features lets a "master" S3C825A send a multiple-frame serial
message to a "slave" device in a multi-S3C825A configuration. It does this without interrupting other slave
devices that may be on the same serial line.
This feature can be used only in UART modes 2 or 3. In these modes 2 and 3, 9 data bits are received. The 9th
bit value is written to RB8 (UARTCON.2). The data receive operation is concluded with a stop bit. You can
program this function so that when the stop bit is received, the serial interrupt will be generated only if RB8 = "1".
To enable this feature, you set the MCE bit in the UARTCON register. When the MCE bit is "1", serial data
frames that are received with the 9th bit = "0" do not generate an interrupt. In this case, the 9th bit simply
separates the address from the serial data.
Sample Protocol for Master/Slave Interaction
When the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends
out an address byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In
an address byte, the 9th bit is "1" and in a data byte, it is "0".
The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being
addressed. The addressed slave then clears its MCE bit and prepares to receive incoming data bytes.
The MCE bits of slaves that were not addressed remain set, and they continue operating normally while ignoring
the incoming data bytes.
While the MCE bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit.
For mode 1 reception, if MCE is "1", the receive interrupt will be issue unless a valid stop bit is received.
18-11
UART
S3C825A/P825A
Setup Procedure for Multiprocessor Communications
Follow these steps to configure multiprocessor communications:
1. Set all S3C825A devices (masters and slaves) to UART mode 2 or 3.
2. Write the MCE bit of all the slave devices to "1".
3. The master device's transmission protocol is:
— First byte: the address
identifying the target
slave device (9th bit = "1")
— Next bytes: data
(9th bit = "0")
4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1".
The targeted slave compares the address byte to its own address and then clears its MCE bit in order to
receive incoming data. The other slaves continue operating normally.
Full-Duplex Multi-S3C825A Interconnect
TxD
RxD
TxD
RxD
TxD
RxD
TxD
RxD
Master
Slave 1
Slave 2
Slave n
. . .
S3C825A
S3C825A
S3C825A
S3C825A
Figure 18-10. Connection Example for Multiprocessor Serial Data Communications
18-12
S3C825A/P825A
ELECTRICAL DATA
19 ELECTRICAL DATA
OVERVIEW
In this chapter, S3C825A electrical characteristics are presented in tables and graphs.
The information is arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— Input/output capacitance
— Oscillation characteristics
— Oscillation stabilization time
— Data retention supply voltage in stop mode
— Serial I/O timing characteristics
— A/D converter electrical characteristics
19-1
ELECTRICAL DATA
S3C825A/P825A
Table 19-1. Absolute Maximum Ratings
°
(TA= 25 C)
Parameter
Symbol
Conditions
Rating
– 0.3 to +6.5
Unit
VDD
VI
Supply voltage
–
V
– 0.3 to VDD + 0.3
Input voltage
Ports 0–8
–
VO
IOH
– 0.3 to VDD + 0.3
– 15
Output voltage
Output current high
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 60
+ 30
IOL
Output current low
Total pin current for port
+ 100
°
C
TA
Operating temperature
Storage temperature
– 25 to + 85
TSTG
– 65 to + 150
Table 19-2. D.C. Electrical Characteristics
(TA = –25 C to + 85 C, VDD = 2.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating voltage
fx = 0.4–4 MHz, 32.8 kHz
2.0
–
5.5
V
fx = 0.4–8 MHz
Ports 0–8
2.2
–
5.5
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VOH
0.8 VDD
VDD
Input high voltage
Input low voltage
0.8 VDD
VDD–0.1
VDD
VDD
–
RESET
XIN, XOUT, XTIN, XTOUT
0.2 VDD
0.2 VDD
0.1
Ports 0–8
–
–
–
RESET
XIN, XOUT, XTIN, XTOUT
VDD = 4.5 V to 5.5 V
VDD – 1.0
VDD
Output high voltage
Output low voltage
All output ports;
IOH = –1 mA
VOL
VDD = 4.5 V to 5.5 V
–
–
2.0
All output ports;
IOL = 10 mA
19-2
S3C825A/P825A
ELECTRICAL DATA
Table 19-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = -25 C to + 85 C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
ILIH1
VIN = VDD
All input pins except
XIN, XOUT, XTIN XT
Input high leakage
current
–
–
3
uA
,
OUT
ILIH2
ILIL1
VIN = VDD, XIN
VIN = 0 V
XOUT, XTIN XT
, ,
OUT
20
-3
Input low leakage
current
–
–
All input pins except RESET, XIN
,
XOUT, XTIN XT
,
OUT
ILIL2
ILOH
VIN = 0 V, XIN
,
X
OUT, XTIN XT
-20
3
,
OUT
VOUT = VDD
All output pins
VOUT = 0 V
All output pins
VIN = 0 V
Output high leakage
current
–
–
–
–
ILOL
RL1
Output low leakage
current
-3
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
°
Pull-up resistor
25
50
50
100
150
400
700
1500
kW
kW
Port 0–8
VIN = 0 V
100
250
500
750
RL2
150
300
300
RESET
ROSC1
Oscillator feed back
resistors
VDD = 5 V, T = 25 C
A
XIN = VDD, XOUT = 0 V
°
ROSC2
1500
3000
4500
VDD = 5 V, T = 25 C
A
XTIN = VDD, XTOUT = 0 V
°
RLCD
VDC
LCD voltage
dividing resistor
40
–
60
–
80
kW
TA = 25 C
|VLCD – COMi|
VDD = 2.7 V to 5.5 V
120
mV
voltage drop
(I = 0–7)
– 15 mA per common pin
|VLCD – SEGx|
VDS
VDD = 2.7 V to 5.5 V
–
–
120
mV
V
voltage drop
(x = 0–31)
– 15 mA per common pin
0.8V –0.2 0.8V
DD
0.8V +0.2
DD
VLC2
VLC3
VLC4
VLC5
VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz
VLC1 = VDD
Middle output
voltage
DD
DD
DD
DD
0.6V –0.2 0.6V
DD
0.6V +0.2
DD
0.4V –0.2 0.4V
DD
0.4V +0.2
DD
0.2V –0.2 0.2V
DD
0.2V +0.2
DD
19-3
ELECTRICAL DATA
S3C825A/P825A
Table 19-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = -25 C to + 85 C, VDD = 2.0 V to 5.5 V)
A
Parameter
Symbol
Conditions
Run mode :
VDD = 5 V ± 10%
Min
Typ
Max
Units
IDD1
Supply
Current (1)
6.0 MHz
–
4.0
9.0
mA
Crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10%
4.19 MHz
6.0 MHz
3.0
2.0
6.0
4.0
4.19 MHz
6.0 MHz
1.5
1.0
3.4
2.5
IDD2
Idle mode :
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10%
4.19 MHz
6.0 MHz
0.9
0.6
2.0
1.2
4.19 MHz
0.4
15
0.8
30
IDD3
Run mode : VDD = 3 V ± 10%
32kHz Crystal oscillator
uA
IDD4
IDD5
Idle mode : VDD = 3 V ± 10%
32kHz Crystal oscillator
6
15
3
Stop mode : VDD = 5 V ± 10%
0.5
°
TA = 25 C
Stop mode : VDD = 3 V ± 10%
0.3
2
°
TA = 25 C
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and
ADC.
2.
3.
4.
I
I
I
and I
and I
include power consumption for subsystem clock oscillation.
DD1
DD3
DD5
DD2
DD4
are current when main system clock oscillation stops and the subsystem clock is used.
is current when main system clock and subsystem clock oscillation stops.
5. Every values in this table is measured when bits 4–3 of the system clock control register (CLKCON.4–.3) is set to “11B”.
19-4
S3C825A/P825A
ELECTRICAL DATA
Table 19-3. A.C. Electrical Characteristics
°
°
(TA = -25 C to +85 C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 5 V
Min
Typ
Max
Unit
Interrupt input high, low
width
tINTH,
tINTL
200
–
ns
(P2.4–P2.7, P4.0–P4.7)
VDD = 5 V
tRSL
10
–
–
us
RESET input low width
tTIL
tTIH
0.8 VDD
0.2 VDD
0.2 VDD
Figure 19-1. Input Timing for External Interrupts (P2.4–P2.7, P4)
t
RSL
RESET
0.2 V
DD
Figure 19-2. Input Timing for RESET
19-5
ELECTRICAL DATA
S3C825A/P825A
Table 19-4. Input/Output Capacitance
°
°
(TA = -25 C to +85 C, VDD = 0 V )
Parameter
Input
capacitance
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; unmeasured pins
are returned to VSS
–
–
10
pF
COUT
CIO
Output
capacitance
I/O capacitance
Table 19-5. Data Retention Supply Voltage in Stop Mode
°
°
(TA = -25 C to + 85 C)
Parameter
Symbol
VDDDR
Conditions
Min
Typ
–
Max
Unit
Data retention
supply voltage
2.0
5.5
V
°
IDDDR
Data retention
supply current
–
–
1
uA
VDDDR = 2 V (TA = 25 C)
Stop mode
RESET
Occurs
Oscillation
Stabilization
Time
Stop Mode
Normal
Operating Mode
Data Retention Mode
V
DD
V
DDDR
Execution of
STOP Instrction
RESET
0.2 VDD
t
WAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fxx
Figure 19-3. Stop Mode Release Timing Initiated by RESET
19-6
S3C825A/P825A
ELECTRICAL DATA
Oscillation
Stabilization Time
Idle Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
Normal
Execution of
STOP Instruction
Operating Mode
Interrupt
0.2 VDD
tWAIT
NOTE:
tWAIT is the same as 16 x 1/BT clock
Figure 19-4. Stop Mode Release Timing Initiated by Interrupts
19-7
ELECTRICAL DATA
S3C825A/P825A
Table 19-6. A/D Converter Electrical Characteristics
(T = -25 °C to +85 °C, V
A
= 2.7 V to 5.5 V, VSS = 0 V)
DD
Parameter
Resolution
Symbol
Conditions
Min
–
Typ
10
–
Max
Unit
bit
–
Total Accuracy
–
LSB
± 3
± 2
VDD = 5.12 V
Integral Linearity Error
ILE
–
–
AVREF = 5.12 V
AVSS = 0 V
Differential Linearity Error
DLE
–
–
± 1
Offset Error of Top
Offset Error of Bottom
Conversion Time (1)
EOT
EOB
TCON
CPU clock = 8 MHz
–
–
± 1
± 1
–
± 3
± 3
–
10-bit resolution
50 x fxx/4, fxx = 8 MHz
25
mS
VIAN
RAN
AVSS
2
AVREF
Analog Input Voltage
Analog Input Impedance
Analog Reference Voltage
Analog Ground
–
–
1000
–
V
MW
V
–
–
VDD
VSS + 0.3
10
AVREF
AVSS
IADIN
IADC
–
–
2.7
VSS
–
AVREF = VDD = 5V
AVREF = VDD = 5V
AVREF = VDD = 3V
Analog Input Current
Analog Block Current (2)
–
mA
–
1
3
mA
0.5
100
1.5
AVREF = VDD = 5V
500
nA
When power down mode
NOTES:
1. ‘Conversion time’ is the time required from the moment a conversion operation starts until it ends.
2. is an operating current of A/D converter.
I
ADC
19-8
S3C825A/P825A
ELECTRICAL DATA
Table 19-7. Synchronous SIO Electrical Characteristics
°
°
(TA = –25 C to +85 C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
tCKY
SCK cycle time
External SCK source
1000
–
–
ns
Internal SCK source
External SCK source
1000
500
tKH, tKL
SCK high, low width
–
–
tKCY/2–
50
Internal SCK source
tSIK
SI setup time to
External SCK source
250
–
–
–
–
–
SCK high
Internal SCK source
External SCK source
250
400
tKSI
SI hold time to
SCK high
Internal SCK source
External SCK source
400
–
tKSO
Output delay for
300
250
SCK to SO
Internal SCK source
tCKY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
Input Data
tKSO
SO
Output Data
Figure 19-5. Serial Data Transfer Timing
19-9
ELECTRICAL DATA
S3C825A/P825A
Table 19-8. Main Oscillator Characteristics
°
°
(TA = –25 C to + 85 C)
Oscillator
Crystal
Clock Circuit
Parameter
Condition (VDD
)
Min
Typ
Max
Unit
C1
Main oscillation
frequency
2.2 V – 5.5 V
0.4
–
8
MHz
XIN
XOUT
C2
C1
2.0 V – 5.5 V
2.2 V – 5.5 V
0.4
0.4
–
–
4
8
Ceramic
Main oscillation
frequency
XIN
XOUT
C2
2.0 V – 5.5 V
2.2 V – 5.5 V
0.4
0.4
–
–
4
8
XIN input
External clock
XIN
frequency
XOUT
2.0 V – 5.5 V
5.0 V
0.4
0.4
–
–
4
2
RC
Frequency
Frequency
MHz
X
X
IN
R
OUT
3.0 V
0.4
–
1
Table 19-9. Sub Oscillator Characteristics
°
°
(TA = – 25 C to + 85 C)
Oscillator
Crystal
Clock Circuit
Parameter
Condition (VDD
)
Min
Typ
Max
Unit
C1
Sub oscillation
frequency
2.0 V–5.5 V
32
32.768
35
kHz
XTIN
XTOUT
C2
XTIN input
frequency
External clock
2.0 V–5.5 V
32
–
100
kHz
XTIN
XTOUT
19-10
S3C825A/P825A
ELECTRICAL DATA
Table 19-10. Main Oscillator Stabilization Time
°
°
(TA = -25 C to + 85 C, VDD = 2.0 V to 5.5 V)
Oscillator
Crystal
Test Condition
Min
–
Typ
–
Max
40
Unit
ms
fx > 400 kHz
Oscillation stabilization occurs when VDD is equal to the
minimum oscillator voltage range.
XIN input high and low level width (tXH, tXL)
Ceramic
–
–
10
ms
External clock
62.5
–
1250
ns
1/fx
tXL
tXH
XIN
VDD-0.1V
0.1V
Figure 19-6. Clock Timing Measurement at XIN
Table 19-11. Sub Oscillator Stabilization Time
°
°
(TA = -25 C to + 85 C, VDD = 2.0 V to 5.5 V)
Oscillator
Crystal
Test Condition
Min
–
Typ
Max
10
Unit
s
–
–
–
XTIN input high and low level width (tXTL, tXTH
)
External clock
5
15
ms
1/fxt
tXTL
tXTH
XTIN
VDD-0.1V
0.1V
Figure 19-7. Clock Timing Measurement at XTIN
19-11
ELECTRICAL DATA
S3C825A/P825A
Instruction Clock
2.0 MHZ
Main Oscillator Frequency
8.0 MHZ
4.0 MHZ
8.19 kHz
400 kHz
1
2
3
4
5
6
7
2.2
Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16)
Figure 19-8. Operating Voltage Range
19-12
S3C825A/P825A
ELECTRICAL DATA
Table 19- 12. UART Timing Characteristics in Mode 0 (8 MHz)
°
°
(T = – 25 C to + 85 C, VDD = 2.0 V to 5.5 V, Load capacitance = 80 pF)
A
Parameter
Symbol
Min
Typ
Max
Unit
tSCK
Serial port clock cycle time
625
875
–
ns
t
t
CPU ´ 6
tS1
tS2
tH1
tH2
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Serial port clock High, Low level width
300
CPU ´ 5
–
tCPU
–
–
tCPU – 50
0
300
–
–
tHIGH, LOW
t
250
500
t
CPU ´ 3
NOTES:
1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.
2. The unit t
means one CPU clock period.
CPU
tSCK
tHIGH
tLOW
0.8 VDD
0.2 VDD
Figure 19-9. Waveform for UART Timing Characteristics
19-13
ELECTRICAL DATA
S3C825A/P825A
Figure 19-10. A.C. Timing Waveform for the UART Module
19-14
S3C825A/P825A
MECHANICAL DATA
20 MECHANICAL DATA
OVERVIEW
The S3C825A microcontroller is currently available in 80-pin QFP and TQFP package.
23.90 ± 0.30
0-8
20.00 ± 0.20
+ 0.10
- 0.05
0.15
0.10 MAX
80-QFP-1420C
#80
#1
0.35 + 0.10
0.15 MAX
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.80
(0.80)
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 20-1. Package Dimensions (80-QFP-1420C)
20-1
MECHANICAL DATA
S3C825A/P825A
14.00 BSC
12.00 BSC
0-7
0.09-0.20
80-TQFP-1212
#80
#1
0.17-0.27
0.05-0.15
1.00 ± 0.05
1.20 MAX
0.50
M
0. 08 MAX
(1.25)
NOTE: Dimensions are in millimeters.
Figure 20-2. Package Dimension (80-TQFP-1212)
20-2
S3C825A/P825A
S3P825A OTP
21 S3P825A OTP
OVERVIEW
The S3P825A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C825A
microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data
format.
The S3P825A is fully compatible with the S3C825A, both in function in D.C. electrical characteristics and in pin
configuration. Because of its simple programming requirements, the S3P825A is ideal as an evaluation chip for
the S3C825A.
21-1
S3P825A OTP
S3C825A/P825A
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.0/SEG4
P1.1/SEG25
P6.7/SEG3/COM7
P6.6/SEG2/COM6
P6.5/SEG1/COM5
P6.4/SEG0/COM4
P6.3/COM3
P6.2/COM2
P6.1/COM1
P6.0/COM0
VDD2
VSS2
VLC1
P5.6
P5.5/TXD
P1.2/SEG26
P1.3/SEG27
P1.4/SEG28
P1.5/SEG29
P1.6/SEG30
P1.7/SEG31
SDAT/P2.0
SCLK/P2.1
VDD/VDD1
9
S3P825A
10
11
12
13
14
15
16
17
18
19
20
VSS/VSS1
(80-TQFP-1212)
XOUT
XIN
VPP/TEST
XTIN
P5.4/RXD
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
XTOUT
RESET/RESET
P2.2/T2CLK
P2.3/T2OUT
P2.4/INT0/T0CLK
P4.7/INT11
Figure 21-1. S3P825A Pin Assignments (80-Pin TQFP Package)
21-2
S3C825A/P825A
S3P825A OTP
1
2
3
4
5
6
7
8
P0.7/SEG23
P1.0/SEG24
P1.1/SEG25
P1.2/SEG26
P1.3/SEG27
P1.4/SEG28
P1.5/SEG29
P1.6/SEG30
P1.7/SEG31
SDAT/P2.0
SCLK/P2.1
VDD/VDD1
VSS/VSS1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.2/SEG6
P7.1/SEG5
P7.0/SEG4
P6.7/SEG3/COM7
P6.6/SEG2/COM6
P6.5/SEG1/COM5
P6.4/SEG0/COM4
P6.3/COM3
P6.2/COM2
P6.1/COM1
P6.0/COM0
VDD2
VSS2
VLC1
P5.6
P5.5/TXD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3P825A
(80-QFP-1420C)
XOUT
XIN
VPP/TEST
XTIN
P5.4/RXD
P5.3/BUZ
P5.2/SO
XTOUT
RESET/RESET
P2.2/T2CLK
P5.1/SI
P2.3/T2OUT
P5.0/SCK
P4.7/INT11
P4.6/INT10
P4.5/INT9
P2.4/INT0/T0CLK
P2.5/INT1/T1CLK
P2.6/INT2/TAOUT
Figure 21-2. S3P825A Pin Assignments (80-Pin QFP Package)
21-3
S3P825A OTP
S3C825A/P825A
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P2.0
Pin Name
Pin No.
I/O
Function
SDAT
8(10)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P2.1
SCLK
VPP
9(11)
I
I
Serial clock pin. Input only pin.
TEST
14(16)
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
17(19)
I
Chip Initialization
RESET
RESET
VDD1/VSS1
VDD/VSS
10/11(12/13)
–
Logic power supply pin. VDD should be tied to
+5 V during programming.
NOTE: Parentheses indicate pin for 80-pin-QFP-1420 package.
Table 21-2. Comparison of S3P825A and S3C825A Features
Characteristic
Program Memory
Operating Voltage (VDD
S3P825A
48-Kbyte EPROM
S3C825A
48-Kbyte mask ROM
2.0 V to 5.5 V
)
2.0 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
Pin Configuration
80 TQFP, 80 QFP
80 TQFP, 80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P825A, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 21-3. Operating Mode Selection Criteria
VDD
VPP (TEST)
Address(A15–A0)
R/W
Mode
EPROM read
REG/MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
21-4
S3C825A/P825A
S3P825A OTP
Instruction Clock
2.0 MHZ
Main Oscillator Frequency
8.0 MHZ
4.0 MHZ
8.19 kHz
400 kHz
1
2
3
4
5
6
7
2.2
Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16)
Figure 21-3. Operating Voltage Range
21-5
S3P825A OTP
S3C825A/P825A
NOTES
21-6
S3C825A/P825A
DEVELOPMENT TOOLS
22 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool
including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for
S3C7, S3C6, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.
Samsung also offers support software that includes debugger, assembler, and a program for setting options.
SHINE
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked
help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be
sized, moved, scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates
object code in standard hexadecimal format. Assembled program code includes the object code that is used for
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and
an auxiliary definition (DEF) file with device specific information.
SASM88
The SASM88 is a relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a
source file containing assembly language statements and translates into a corresponding source code, object
code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating
system. It produces the relocatable object code only, so the user should link object file. Object files can be linked
with other object files and loaded into memory.
HEX2ROM
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device
automatically.
TARGET BOARDS
Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters
are included with the device-specific target board.
22-1
DEVELOPMENT TOOLS
S3C825A/P825A
IBM-PC AT or Compatible
RS-232C
SMDS2+
PROM/OTP Writer Unit
Target
Application
System
RAM Break/Display Unit
Trace/Timer Unit
Probe
Adapter
TB825A
Target
Board
POD
SAM8 Base Unit
Eva
Chip
Power Supply Unit
Figure 22-1. SMDS Product Configuration (SMDS2+)
22-2
S3C825A/P825A
DEVELOPMENT TOOLS
TB825A TARGET BOARD
The TB825A target board is used for the S3C825A microcontroller. It is supported with the SMDS2+.
TB825A
To User_VCC
Off
On
Idle
Stop
RESET
7411
Y1 (Sub-Clock)
J101
J102
25
1
2
1
2
40
1
41
160
121
144 QFP
S3E8210
EVA Chip
80
1
39
40 39
40
81
120
R6
RLCD
SMDS2
SMDS2+
SM1345A
Figure 22-2. TB825A Target Board Configuration
22-3
DEVELOPMENT TOOLS
S3C825A/P825A
Table 22-1. Power Selection Settings for TB825A
Operating Mode
"To User_VCC" Settings
Comments
The SMDS2/SMDS2+
supplies VCC to the target
To User_VCC
Target
System
TB825A
Off
On
VCC
VSS
board (evaluation chip) and
the target system.
VCC
SMDS2/SMDS2+
The SMDS2/SMDS2+
supplies VCC only to the
To User_VCC
External
VCC
Target
System
TB825A
Off
On
target board (evaluation
chip). The target system must
have its own power supply.
VSS
VCC
SMDS2/SMDS2+
NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:
SMDS2+ Selection (SAM8)
In order to write data into program memory that is available in SMDS2+, the target board should be selected to
be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
Table 22-2. The SMDS2+ Tool Selection Setting
"SW1" Setting
SMDS2 SMDS2+
Operating Mode
R/W R/W
SMDS2+
Target
Board
IDLE LED
The Yellow LED is ON when the evaluation chip (S3E8250) is in idle mode.
STOP LED
The Red LED is ON when the evaluation chip (S3E8250) is in stop mode.
22-4
S3C825A/P825A
DEVELOPMENT TOOLS
J101
1
3
5
7
2
4
6
P1.1/SEG25
P1.3/SEG27
P1.5/SEG29
P1.7/SEG31
P2.1
P1.2/SEG26
P1.4/SEG28
P1.6/SEG30
P2.0
VDD1
XOUT
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VSS1
XIN
XTIN
TEST
XTOUT
RESET
P2.2/T2CLK
P2.4/INT0/T0CLK
P2.6/INT2/TAOUT
AVREF
P3.1/AD1
P3.3/AD3
P3.4
P3.6/T3OUT/T3PWM/T3CAP
P4.0/INT4
P4.2/INT6
P2.3/T2OUT
P2.5/INT1/T1CLK
P2.7/INT3/TBOUT
P3.0/AD0
P3.2/AD2
AVSS
P3.5/T3CLK
P3.7/T0OUT/T0PWM/T0CAP
P4.1/INT5
P4.3/INT7
P4.5/INT9
P4.4/INT8
P4.6/INT10
J102
1
3
2
4
P4.7/INT11
P5.1/SI
P5.0/SCK
P5.2/SO
5
6
P5.3/BUZ
P5.4/RXD
7
8
P5.5/TXD
P5.6
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VLC1
VDD2
VSS2
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P6.0/COM0
P6.2/COM2
P6.4/SEG0/COM4
P6.6/SEG2/COM6
P7.0/SEG4
P7.2/SEG6
P7.4/SEG8
P7.6/SEG10
P8.0/SEG12
P8.2/SEG14
P0.0/SEG16
P0.2/SEG18
P0.4/SEG20
P0.6/SEG22
P1.0/SEG24
P6.1/COM1
P6.3/COM3
P6.5/SEG1/COM5
P6.7/SEG3/COM7
P7.1/SEG5
P7.3/SEG7
P7.5/SEG9
P7.7/SEG11
P8.1/SEG13
P8.3/SEG15
P0.1/SEG17
P0.3/SEG19
P0.5/SEG21
P0.7/SEG23
Figure 22-3. 40-Pin Connectors (J101, J102) for TB825A
22-5
DEVELOPMENT TOOLS
S3C825A/P825A
Target Board
Target System
J101
J102
J102
J101
1
2
41 42
41 42
1
2
Target Cable for 40-Pin Connector
Part Name: AS40D-A
Order Code: SM6306
39 40 79 80
79 80 39 40
Figure 22-4. S3C825A Cables for 80-TQFP Package
22-6
相关型号：
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