M485L1624FU0-CA2_技术文档

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

DDR SDRAM SODIMM

200pin Unbuffered SODIMM based on 256Mb F-die

64 / 72-bit (Non ECC / ECC)

66 TSOP(II) with Pb-Free

(RoHS compliant)

Revision 1.2

Oct. 2004

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Revision History

Revision 1.0 (February, 2004)

- First release

Revision 1.1 (March, 2004)

- Corrected package dimension.

Revision 1.2 (Oct, 2004)

- Corrected typo.

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

200Pin Non ECC / ECC SODIMM based on 256Mb F-die(x16)

Ordering Information

Part Number

Density

128MB

256MB

128MB

Organization

16M x 64

Component Composition

Height

1,250mil

M470L1624FU0-C(L)B3/A2/B0

M470L3224FU0-C(L)B3/A2/B0

M485L1624FU0-C(L)B3/A2/B0

16Mx16 (K4H561638F) * 4EA

16Mx16 (K4H561638F) * 8EA

16Mx16 (K4H561638F) * 5EA

32M x 64

16M x 72

Operating Frequencies

B3(DDR333@CL=2.5)

133MHz

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

100MHz

Speed @CL2

Speed @CL2.5

CL-tRCD-tRP

133MHz

2-3-3

166MHz

133MHz

2.5-3-3

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1250 (mil), single(128MB), double(256MB) sided component

• SSTL_2 Interface Pb-Free

• RoHS compliant

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Pin Configurations (Front side/back side)

Front

Back

1

3

5

7

VREF

VSS

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

DQ27

VDD

CB0

CB1

VSS

DQS8

CB2

VDD

CB3

DU

VSS

CK2

/CK2

VDD

CKE1

DU

A12

A9

VSS

A7

A5

A3

A1

VDD

A10/AP

BA0

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

DQ34

VSS

DQ35

DQ40

VDD

DQ41

DQS5

VSS

DQ42

DQ43

VDD

2

4

6

8

VREF

VSS

DQ4

DQ5

VDD

DM0

DQ6

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

DQ14

DQ15

VDD

VSS

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

136

138

140

142

144

146

148

150

152

DQ38

VSS

DQ0

DQ1

VDD

DQS0

DQ2

VSS

DQ3

DQ8

VDD

DQ9

DQS1

VSS

DQ10

DQ11

VDD

CK0

/CK0

VSS

DQ39

DQ44

VDD

DQ45

DM5

VSS

DQ46

DQ47

VDD

/CK1

CK1

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

*DU/(RESET) 154

VSS

VDD

CKE0

DU(BA2)

A11

A8

VSS

A6

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

VDD

VSS

DQ48

DQ49

VDD

DQS6

DQ50

VSS

DQ51

DQ56

VDD

DQ57

DQS7

VSS

DQ58

DQ59

VDD

SDA

SCL

DQ52

DQ53

VDD

DM6

DQ54

VSS

DQ55

DQ60

VDD

DQ61

DM7

VSS

DQ62

DQ63

VDD

SA0

SA1

SA2

KEY

A4

A2

A0

41

43

45

47

49

51

53

55

57

59

61

63

65

DQ16

DQ17

VDD

DQS2

DQ18

VSS

DQ19

DQ24

VDD

DQ25

DQS3

VSS

42

44

46

48

50

52

54

56

58

60

62

64

66

DQ20

DQ21

VDD

DM2

DQ22

VSS

DQ23

DQ28

VDD

DQ29

DM3

VDD

BA1

/RAS

/CAS

/CS1

DU

VSS

DQ36

DQ37

VDD

DM4

/WE

/CS0

*DU(A13)

VSS

DQ32

DQ33

VDD

DQS4

VDDSPD

VDDID

VSS

DQ30

DU

DQ26

Note 1. * : These pins are not used in this module.

2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64 module, & used on x72 module.

Pin 95,122 are NC for 1Row module (M470L1624FU0, M485L1624FU0) & used for 2Row module (M470L3224FU0).

Pin Description

Pin Name

Function

Address input (Multiplexed)

Bank Select Address

Data input/output

Pin Name

Function

A0 ~ A12

DM0 ~ DM7, DM8(for ECC) Data - in mask

BA0 ~ BA1

DQ0 ~ DQ63

DQS0 ~ DQS8

CK0,CK0 ~ CK2, CK2

CKE0~CKE1

CS0~CS1

RAS

VDD

Power supply (2.5V)

VDDQ

VSS

Power Supply for DQS(2.5V)

Ground

Data Strobe input/output

Clock input

VREF

VDDSPD

SDA

Power supply for reference

Serial EEPROM Power

Serial data I/O

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

SCL

Serial clock

CAS

SA0 ~ 2

NC

Address in EEPROM

No connection

WE

CB0 ~ CB7

Check bit(Data-in/data-out)

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

128MB, 16M x 64 Non ECC Module (M470L1624FU0) (Populated as 1 bank of x16 DDR SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

CS0

DQS0

DM0

DQS4

DM4

LDQS

LDM

CS

D0

LDQS

LDM

CS

D2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DQ7

I/O 7

UDQS

UDM

I/O 8

DQ39

I/O 7

UDQS

UDM

I/O 8

DQS1

DM1

DQS5

DM5

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS2

DM2

DQS6

DM6

LDQS

LDM

CS

D1

LDQS

LDM

CS

D3

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DQ23

I/O 7

UDQS

UDM

I/O 8

DQ55

I/O 7

UDQS

UDM

I/O 8

DQS3

DM3

DQS7

DM7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ60

DQ61

DQ62

DQ63

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

BA0 - BA1

BA0-BA1: DDR SDRAMs D0 - D3

A0-A12: DDR SDRAMs D0 - D3

A0 - A12

RAS

D0/D2/Cap

RAS: SDRAMs D0 - D3

Cap/Cap/Cap

CAS

CAS: SDRAMs D0 - D3

CKE: SDRAMs D0 - D3

R=120Ω

Clock Wiring

±

5%

Clock

Input

CKE0

SDRAMs

CK0/1/2

CK0/CK0

CK1/CK1

CK2/CK2

2 SDRAMs

NC

WE

WE: SDRAMs D0 - D3

Card

Edge

D1/D3/Cap

Cap/Cap/Cap

V_DDSPD

SPD

V_DD/V_DDQ

Notes:

D0 - D3

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must

be maintained as shown.

Serial PD

VREF

V_SS

D0 - D3

SCL

WP

SDA

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

A0

A1

A2

SA0 SA1 SA2

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

256MB, 32M x 64 Non ECC Module (M470L3224FU0) (Populated as 2 bank of x16 DDR SDRAM Module)

Functional Block Diagram

CS1

CS0

DQS0

DM0

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

DQS4

DM4

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

D0

D4

D2

D6

DQS1

DM1

UDQS

UDM

I/0 8

UDQS

UDM

I/0 8

DQS5

DM5

UDQS

UDM

I/0 8

UDQS

UDM

I/0 8

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

DQS2

DM2

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

DQS6

DM6

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

D1

D5

D3

D7

DQS3

DM3

UDQS

UDM

I/0 8

UDQS

UDM

I/0 8

DQS7

DM7

UDQS

UDM

I/0 8

UDQS

UDM

I/0 8

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

*Clock Net Wiring

D0/D2/Cap

BA0 - BA1

A0 - A12

RAS

BA0-BA1: DDR SDRAMs D0 - D7

A0-A12: DDR SDRAMs D0 - D7

RAS: SDRAMs D0 - D7

D1/D3/Cap

Clock Wiring

SDRAMs

R=120Ω

Clock

CK0/1/2

Input

CAS

CAS: SDRAMs D0 - D7

Card

Edge

CK0/CK0

CK1/CK1

CK2/CK2

4 SDRAMs

NC

CKE0

CKE1

CKE: SDRAMs D0 - D3

CKE: SDRAMs D4 - D7

D4/D6/Cap

D5/D7/Cap

WE

WE: SDRAMs D0 - D7

V_DDSPD

V_DD/V_DDQ

SPD

Serial PD

Notes:

D0 - D7

SCL

WP

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

SDA

2. DQ/DQS/DM/CKE/CS relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

A0

A1

A2

VREF

V_SS

D0 - D7

SA0 SA1 SA2

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

128MB, 16M x 72 ECC Module (M485L1624FU0) (Populated as 1 bank of x16 DDR SDRAM Module)

Functional Block Diagram

CS0

DQS0

DM0

DQS8

DM8

DQS4

DM4

DQS

DM

CS

D4

LDQS

LDM

CS

D0

LDQS

LDM

CS

D2

CB0

CB1

CB2

CB3

CB4

CB5

CB6

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

CB7

I/O 7

UDQS

UDM

I/O 8

DQ7

I/O 7

UDQS

UDM

I/O 8

DQ39

I/O 7

UDQS

UDM

I/O 8

DQS1

DM1

DQS5

DM5

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS2

DM2

DQS6

DM6

LDQS

LDM

CS

D1

LDQS

LDM

CS

D3

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DQ23

I/O 7

UDQS

UDM

I/O 8

DQ55

I/O 7

UDQS

UDM

I/O 8

DQS3

DM3

DQS7

DM7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ60

DQ61

DQ62

DQ63

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

BA0 - BA1

A0 - A12

BA0-BA1: DDR SDRAMs D0 - D4

A0-A12: DDR SDRAMs D0 - D4

D0/D2/D4

RAS

RAS: SDRAMs D0 - D4

CAS

CAS: SDRAMs D0 - D4

CKE: SDRAMs D0 - D4

Clock Wiring

SDRAMs

Cap/Cap/Cap

Clock

Input

CKE0

R=120

Ω

±

5%

CK0/1/2

CK0/CK0

CK1/CK1

CK2/CK2

2 SDRAMs

1 SDRAMs

WE

WE: SDRAMs D0 - D4

Card

Edge

D1/D3/Cap

V_DDSPD

SPD

Cap/Cap/Cap

V_DD/V_DDQ

D0 - D4

Serial PD

Notes:

VREF

V_SS

D0 - D4

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must

be maintained as shown.

SCL

WP

SDA

A0

A1

A2

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

SA0 SA1 SA2

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Absolute Maximum Ratings

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Voltage on VDDQ supply relative to Vss

Storage temperature

Symbol

Value

-0.5 ~ 3.6

Unit

V

VIN, VOUT

VDD

-1.0 ~ 3.6

V

VDDQ

TSTG

PD

-1.0 ~ 3.6

V

-55 ~ +150

1.5 * # of component

50

°C

W

Power dissipation

Short circuit current

IOS

mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Power & DC Operating Conditions (SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Supply voltage(for device with a nominal VDD of 2.5V)

I/O Supply voltage

Symbol

VDD

Min

2.3

Max

2.7

Unit

Note

5

1

2

VDDQ

2.3

2.7

V

I/O Reference voltage

VREF

0.49*VDDQ

VREF-0.04

VREF+0.15

-0.3

0.51*VDDQ

VREF+0.04

VDDQ+0.3

VREF-0.15

VDDQ+0.3

VDDQ+0.6

1.4

I/O Termination voltage(system)

Input logic high voltage

V_TT

V

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

VI(Ratio)

II

V

Input logic low voltage

V

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

V-I Matching: Pullup to Pulldown Current Ratio

Input leakage current

-0.3

V

0.36

V

3

4

0.71

-

-2

2

uA

Output leakage current

IOZ

-5

5

Output High Current(Normal strengh driver) ;V_OUT

_TT+ 0.84V

Output High Current(Normal strengh driver) ;V_OUT

_TT- 0.84V

=

IOH

IOL

IOH

-16.8

16.8

-9

mA

V

=

V

Output High Current(Half strengh driver) ;V_OUT= V_TT

+ 0.45V

Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled

TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.

2.V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

M470L1624FU0 (16M x 64, 128MB Module)

(VDD=2.7V, T = 10°C)

Symbol

IDD0

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Unit

mA

Notes

360

500

12

320

460

12

320

460

12

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

100

80

72

140

220

800

760

720

12

120

180

680

620

660

12

120

180

680

620

660

12

IDD6

Normal

Low power

IDD7A

6

Optional

1,400

1,200

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M470L3224FU0 (32M x 64, 256MB Module)

(VDD=2.7V, T = 10°C)

Symbol

IDD0

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Unit

mA

Notes

580

720

24

500

640

24

500

640

24

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

200

160

280

440

1,020

980

940

24

160

144

240

360

860

800

840

24

160

144

240

360

860

800

840

24

IDD6

Normal

Low power

IDD7A

12

Optional

1,620

1,380

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

M485L1624FU0 (16M x 72, 128MB Module)

(VDD=2.7V, T = 10°C)

Symbol

IDD0

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Unit

mA

Notes

810

1,035

27

720

900

27

720

900

27

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

225

180

162

270

405

1,080

1,215

1,440

27

180

162

270

405

1,080

1,215

1,440

27

180

315

495

1,260

1,440

1,530

27

IDD6

Normal

Low power

IDD7A

14

Optional

2,340

2,160

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

AC Operating Conditions

Max

Parameter/Condition

Symbol

Min

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

VREF + 0.31

V

3

1

2

VREF - 0.31

VDDQ+0.6

0.7

Input Crossing Point Voltage, CK and CK inputs

0.5*VDDQ-0.2 0.5*VDDQ+0.2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-

tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Vtt=0.5*VDDQ

RT=50Ω

Output

Z0=50Ω

VREF

=0.5*VDDQ

CLOAD=30pF

Output Load Circuit (SSTL_2)

Input/Output Capacitance

(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

Unit

M470L1624FU0

M470L3224FU0

M485L1624FU0

Parameter

Symbol

Min

41

34

25

6

Max

45

38

30

7

Min

49

42

25

6

Max

57

50

30

7

Min

41

34

25

6

Max

45

38

30

7

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )

Input capacitance(CKE0, CKE1)

CIN1

CIN2

CIN3

CIN4

CIN5

Cout1

Cout2

pF

Input capacitance( CS0, CS1)

Input capacitance( CLK0, CLK1,CLK2)

Input capacitance(DM0~DM7,DM8(for ECC))

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance (CB0~CB7)

6

7

6

7

6

7

-

6

7

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

AC Timming Parameters & Specifications

B3

(DDR333@CL=2.5))

A2

B0

(DDR266@CL=2.5))

(DDR266@CL=2.0)

Parameter

Symbol

Unit

Note

Min

60

Max

Min

65

Max

Min

65

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

ns

Refresh row cycle time

Row active time

72

75

42

70K

45

120K

45

120K

ns

RAS to CAS delay

18

20

ns

Row precharge time

18

20

ns

Row active to Row active delay

Write recovery time

tRRD

tWR

12

15

ns

15

ns

Last data in to Read command

Col. address to Col. address delay

tWTR

tCCD

1

tCK

ns

1

CL=2.0

CL=2.5

7.5

6

12

7.5

0.45

-0.75

-

12

10

12

Clock cycle time

tCK

12

7.5

0.45

-0.75

-

ns

Clock high level width

tCH

tCL

0.45

-0.6

-0.7

-

0.55

+0.6

+0.7

0.45

1.1

0.55

+0.75

0.5

0.55

+0.75

0.5

tCK

ns

Clock low level width

DQS-out access time from CK/CK

tDQSCK

tAC

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

ns

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tDSS

tDSH

tDQSH

tDQSL

tDSC

tIS

ns

12

3

0.9

0.4

0.75

0

0.9

0.4

0.75

0

1.1

0.9

0.4

0.75

0

1.1

tCK

ns

Read Postamble

0.6

CK to valid DQS-in

1.25

DQS-in setup time

DQS-in hold time

0.25

0.2

0.35

0.9

0.75

0.8

0.25

0.2

0.35

0.9

1.0

0.25

0.2

0.35

0.9

1.0

tCK

ns

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

DQS-in low level width

DQS-in cycle time

1.1

Address and Control Input setup time(fast)

Address and Control Input hold time(fast)

Address and Control Input setup time(slow)

Address and Control Input hold time(slow)

Data-out high impedence time from CK/CK

Data-out low impedence time from CK/CK

i,5.7~9

i, 6~9

1

tIH

ns

tIS

ns

tIH

ns

tHZ

+0.7

+0.75

ns

tLZ

-0.7

-0.75

ns

1

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

B3

A2

B0

(DDR266@CL=2.5))

(DDR333@CL=2.5))

(DDR266@CL=2.0)

Parameter

Symbol

Unit

Note

Min

12

Max

Min

15

Max

Min

15

Max

Mode register set cycle time

DQ & DM setup time to DQS

DQ & DM hold time to DQS

tMRD

tDS

ns

0.45

0.5

j, k

tDH

0.45

0.5

Control & Address input pulse width

DQ & DM input pulse width

Power down exit time

tIPW

tDIPW

tPDEX

2.2

1.75

6

2.2

1.75

7.5

2.2

1.75

7.5

ns

8

ns

Exit self refresh to non-Read command tXSNR

75

ns

Exit self refresh to read command

Refresh interval time

tXSRD

tREFI

200

tCK

us

7.8

-

7.8

-

7.8

-

4

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

Output DQS valid window

Clock half period

tQH

tHP

ns

11

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

-

10, 11

Data hold skew factor

tQHS

0.55

0.6

0.75

0.6

0.75

0.6

ns

11

2

DQS write postamble time

tWPST

0.4

18

0.4

20

0.4

20

tCK

Active to Read with Auto precharge

command

tRAP

tDAL

Autoprecharge write recovery +

Precharge time

(tWR/tCK)

+

(tWR/tCK)

+

(tWR/tCK)

+

tCK

13

(tRP/tCK)

System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR333 & DDR266 devices to ensure proper sys-

tem performance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

AC CHARACTERISTICS

DDR333

DDR266

PARAMETER

SYMBOL

DCSLEW

MIN

TBD

MAX

TBD

MIN

TBD

MAX

TBD

Units

V/ns

Notes

a, m

DQ/DM/DQS input slew rate measured between

VIH(DC), VIL(DC) and VIL(DC), VIH(DC)

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Input Slew Rate

0.5 V/ns

tIS

0

tIH

0

Units

ps

Notes

i

0.4 V/ns

+50

+100

0

ps

0.3 V/ns

0

ps

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

Input Slew Rate

0.5 V/ns

tDS

0

tDH

0

Units

ps

Notes

k

0.4 V/ns

+75

+150

+75

+150

ps

0.3 V/ns

ps

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Delta Slew Rate

+/- 0.0 V/ns

tDS

0

tDH

0

Units

ps

Notes

j

+/- 0.25 V/ns

+/- 0.5 V/ns

+50

+100

+50

+100

ps

Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)

Typical Range

(V/ns)

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

Notes

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

1.0

4.5

a,c,d,f,g,h

b,c,d,f,g,h

Table 6 : Output Slew Rate Characteristice (X16 Devices only)

Typical Range

(V/ns)

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

Notes

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

0.7

5.0

a,c,d,f,g,h

b,c,d,f,g,h

Table 7 : Output Slew Rate Matching Ratio Characteristics

AC CHARACTERISTICS DDR333

DDR266

PARAMETER

Output Slew Rate Matching Ratio (Pullup to Pulldown)

MIN

TBD

MAX

TBD

MIN

TBD

MAX

TBD

Notes

e,m

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Component Notes

1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a

specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).

2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys

tem performance (bus turnaround) will degrade accordingly.

3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ

ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could

be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

5. For command/address input slew rate ≥ 1.0 V/ns

6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

7. For CK & CK slew rate ≥ 1.0 V/ns

8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by

device design or tester correlation.

9. Slew Rate is measured between VOH(ac) and VOL(ac).

10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the

period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into

the clock traces.

11. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The

pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst

case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-

channel to n-channel variation of the output drivers.

12. tDQSQ

Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given

cycle.

13. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and

tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)

tDAL = 5 clocks

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

System Notes :

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Test point

Output

50Ω

VSSQ

Figure 1 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

VDDQ

50Ω

Output

Test point

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and

voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns

as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or

VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.

Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the

slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser

on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter

mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotoy.

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Command Truth Table

A0 ~ A9,

A11, A12

CKEn-1

CKEn

CS

RAS

CAS

WE

BA0,1

A10/AP

Note

COMMAND

Extended MRS

Register

H

X

H

L

OP CODE

1, 2

3

Mode Register Set

Auto Refresh

H

L

H

X

Entry

3

Refresh

Self

Refresh

L

H

L

H

X

L

H

X

H

X

H

3

Exit

L

H

X

3

Bank Active & Row Addr.

V

Row Address

L

Read &

Column Address

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

4

Column

L

H

L

H

Address

H

L

Write &

4

Column

Address

H

X

L

H

L

H

L

V

Column Address

H

4, 6

7

Burst Stop

Precharge

X

Bank Selection

All Banks

V

X

L

X

H

5

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

Active Power Down

X

H

L

Entry

H

Precharge Power Down Mode

H

L

Exit

L

H

X

DM

X

8

9

H

L

X

H

X

H

No operation (NOP) : Not defined

Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Physical Dimensions : 16M x64 (M470L1624FU0)

Units : Inches (Millimeters)

2.70

(67.60)

2.50

(63.60)

Full R 2x

0.16 ± 0.039

(4.00 ± 0.10)

1

39 41

199

0.086

2.15

0.456

11.40

1.896

(47.40)

2-φ 0.07

(1.80)

0.17

(4.20)

0.096

(2.40)

0.07

(1.8)

Z

Y

0.098

2.45

2

40 42

200

0.150 Max

(3.80 Max)

0.018 ± 0.001

(0.45 ± 0.03)

0.16 ± 0.0039

(4.00 ± 0.10)

0.01

(0.25)

0.04 ± 0.0039

(1.00 ± 0.1)

0.024 TYP

(0.60 TYP)

0.04 ± 0.0039

(1.00 ± 0.10)

Detail Z

Detail Y

Tolerances : ±.006(.15) unless otherwise specified

The used device is 16Mx16 DDR SDRAM, TSOPII

DDR SDRAM Part No. : K4H561638F-U***

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Physical Dimensions : 32M x64 (M470L3224FU0)

Units : Inches (Millimeters)

2.70

(67.60)

2.50

(63.60)

Full R 2x

0.16 ± 0.039

(4.00 ± 0.10)

1

39 41

199

0.086

2.15

0.456

11.40

1.896

(47.40)

2-φ 0.07

(1.80)

0.17

(4.20)

0.096

(2.40)

0.07

(1.8)

Z

Y

0.098

2.45

2

40 42

200

0.150 Max

(3.80 Max)

0.018 ± 0.001

(0.45 ± 0.03)

0.16 ± 0.0039

(4.00 ± 0.10)

0.01

(0.25)

0.04 ± 0.0039

(1.00 ± 0.1)

0.024 TYP

(0.60 TYP)

0.04 ± 0.0039

(1.00 ± 0.10)

Detail Z

Detail Y

Tolerances : ±.006(.15) unless otherwise specified

The used device is 16Mx16 DDR SDRAM, TSOPII

DDR SDRAM Part No. : K4H561638F-U***

Revision 1.2 Oct. 2004

DDR SDRAM

128MB, 256MB SODIMM Pb-Free

Physical Dimensions : 16M x72 (M485L1624FU0)

Units : Inches (Millimeters)

2.70

(67.60)

2.50

(63.60)

Full R 2x

0.16 ± 0.039

(4.00 ± 0.10)

1

39 41

199

0.086

2.15

0.456

11.40

1.896

(47.40)

2-φ 0.07

(1.80)

0.17

(4.20)

0.096

(2.40)

0.07

(1.8)

Z

Y

0.098

2.45

2

40 42

200

0.150 Max

(3.80 Max)

0.018 ± 0.001

(0.45 ± 0.03)

0.16 ± 0.0039

(4.00 ± 0.10)

0.01

(0.25)

0.04 ± 0.0039

(1.00 ± 0.1)

0.024 TYP

(0.60 TYP)

0.04 ± 0.0039

(1.00 ± 0.10)

Detail Z

Detail Y

Tolerances : ±.006(.15) unless otherwise specified

The used device is 16Mx16 DDR SDRAM, TSOPII

DDR SDRAM Part No. : K4H561638F-U***

Revision 1.2 Oct. 2004


型号：	M485L1624FU0-CA2
厂家：	SAMSUNG
描述：	DDR SDRAM SODIMM DDR SDRAM SODIMM 动态存储器双倍数据速率
文件：	总20页 (文件大小：265K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M485L1624FU0-CA2 [SAMSUNG]

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