M471B5173QH0-YK0 [SAMSUNG]
DDR DRAM Module, 512MX64, CMOS, HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204;
| 型号： | M471B5173QH0-YK0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 512MX64, CMOS, HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总46页 (文件大小：1016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev. 1.21, Oct. 2013
M471B5674QH0
M471B5173QH0
M471B1G73QH0
M474B5173QH0
M474B1G73QH0
204pin Unbuffered SODIMM
1.35V
based on 4Gb Q-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
(C) 2013 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
Revision History
Revision No.
History
Draft Date
Jul. 2013
Remark
Editor
S.H.Kim
S.H.Kim
1.0
1.1
- First SPEC Release
-
-
- Added to 4GB(1Rx8) ECC SODIMM from Product line-up
- Corrected Typo.
Sep. 2013
1.2
- Added 2GB(1Rx16) SODIMM IDD Value.
- Added Note 3 of Chapter #1.
Oct. 2013
Oct. 2013
-
-
S.H.Kim
S.H.Kim
1.21
- 2 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
Table Of Contents
204pin Unbuffered SODIMM based on 4Gb Q-die
1. DDR3L Unbuffered SODIMM Ordering Information......................................................................................................4
2. Key Features.................................................................................................................................................................4
3. Address Configuration ..................................................................................................................................................4
4. x64 DIMM Pin Configurations (Front side/Back Side)...................................................................................................5
5. x72 DIMM Pin Configurations (Front side/Back Side)...................................................................................................6
6. Pin Description .............................................................................................................................................................7
7. SPD and Thermal Sensor for ECC SODIMMs..............................................................................................................7
8. Input/Output Functional Description..............................................................................................................................8
9. Function Block Diagram:...............................................................................................................................................10
9.1 2GB, 256Mx64 Module (Populated as 1 rank of x16 DDR3 SDRAMs)...................................................................10
9.2 4GB, 512Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs).....................................................................11
9.3 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)........................................................................12
9.4 4GB, 512Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs).....................................................................13
9.5 8GB, 1Gx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)........................................................................14
10. Absolute Maximum Ratings ........................................................................................................................................15
10.1 Absolute Maximum DC Ratings.............................................................................................................................15
10.2 DRAM Component Operating Temperature Range ..............................................................................................15
11. AC & DC Operating Conditions...................................................................................................................................15
11.1 Recommended DC Operating Conditions ............................................................................................................15
12. AC & DC Input Measurement Levels..........................................................................................................................16
12.1 AC & DC Logic Input Levels for Single-ended Signals..........................................................................................16
12.2 VREF Tolerances....................................................................................................................................................18
12.3 AC and DC Logic Input Levels for Differential Signals ..........................................................................................19
12.3.1. Differential Signals Definition .........................................................................................................................19
12.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) .............................................19
12.3.3. Single-ended Requirements for Differential Signals ......................................................................................21
12.3.4. Differential Input Cross Point Voltage ............................................................................................................22
12.4 Slew Rate Definition for Single Ended Input Signals.............................................................................................23
12.5 Slew rate definition for Differential Input Signals...................................................................................................23
13. AC & DC Output Measurement Levels .......................................................................................................................23
13.1 Single Ended AC and DC Output Levels...............................................................................................................23
13.2 Differential AC and DC Output Levels...................................................................................................................23
13.3 Single-ended Output Slew Rate ............................................................................................................................23
13.4 Differential Output Slew Rate ................................................................................................................................25
14. IDD specification definition..........................................................................................................................................26
15. IDD SPEC Table.........................................................................................................................................................28
16. Input/Output Capacitance ...........................................................................................................................................31
17. Electrical Characteristics and AC timing.....................................................................................................................32
17.1 Refresh Parameters by Device Density.................................................................................................................32
17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................32
17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................32
17.3.1. Speed Bin Table Notes ..................................................................................................................................36
18. Timing Parameters by Speed Grade ..........................................................................................................................37
18.1 Jitter Notes ............................................................................................................................................................40
18.2 Timing Parameter Notes........................................................................................................................................41
19. Physical Dimensions :.................................................................................................................................................42
19.1 256Mbx16 based 256Mx64 Module (1 Rank) - M471B5674QH0..........................................................................42
19.2 512Mbx8 based 512Mx64 Module (1 Rank) - M471B5173QH0............................................................................43
19.3 512Mbx8 based 1Gx64 Module (2 Ranks) - M471B1G73QH0 .............................................................................44
19.4 512Mbx8 based 512Mx72 Module (1 Rank) - M474B5173QH0............................................................................45
19.5 512Mbx8 based 1Gx72 Module (2 Ranks) - M474B1G73QH0 .............................................................................46
- 3 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
1. DDR3L Unbuffered SODIMM Ordering Information
Number of
Height
2
1
Density
Organization
Part Number
Component Composition
Rank
M471B5674QH0-YH9/K0
M471B5173QH0-YH9/K0
M471B1G73QH0-YH9/K0
2GB
4GB
8GB
4GB
256Mx64
512Mx64
1Gx64
256Mx16(K4B4G1646Q-HY##)*4
512Mx8(K4B4G0846Q-HY##)*8
512Mx8(K4B4G0846Q-HY##)*16
512Mx8(K4B4G0846Q-HY##)*9
1
1
2
1
30mm
30mm
30mm
30mm
3
512Mx72
M474B5173QH0-YK0
M474B1G73QH0-YK0
8GB
1Gx72
512Mx8(K4B4G0846Q-HY##)*18
2
30mm
NOTE :
1. "##" - H9/K0
2. H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11
- DDR3L-1600(11-11-11) is backward compatible to DDR3L-1333(9-9-9)
3. Please contact Samsung for product availability.
2. Key Features
DDR3-800
6-6-6
2.5
DDR3-1066
DDR3-1333
9-9-9
1.5
DDR3-1600
Speed
Unit
7-7-7
1.875
7
11-11-11
1.25
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
ns
nCK
ns
6
9
11
15
13.125
13.125
37.5
13.5
13.5
36
13.75
13.75
35
15
ns
tRAS(min)
tRC(min)
37.5
52.5
ns
50.625
49.5
48.75
ns
•
•
JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
V
DDQ
•
400 MHz f for 800Mb/sec/pin, 533MHz f for 1066Mb/sec/pin, 667MHz f for 1333Mb/sec/pin, 800MHz f for 1600Mb/sec/pin
CK CK CK CK
•
•
•
•
•
•
8 independent internal bank
Programmable CAS Latency: 5,6,7,8,9,10,11
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
•
•
•
•
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then T
85C, 3.9us at 85C < T
95C
CASE
CASE
•
Asynchronous Reset
3. Address Configuration
Organization
Row Address
A0-A15
Column Address
A0-A9
Bank Address
BA0-BA2
Auto Precharge
A10/AP
512Mx8(4Gb) based Module
256Mx16(4Gb) based Module
A0-A14
A0-A9
BA0-BA2
A10/AP
- 4 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
4. x64 DIMM Pin Configurations (Front side/Back Side)
Pin
Front
VREFDQ
VSS
Pin
Back
Pin
Front
Pin
Back
Pin
139
141
143
145
147
Front
Pin
140
142
144
146
148
Back
DQ38
DQ39
VSS
VSS
VSS
VSS
VSS
1
2
71
72
3
4
DQ4
DQ5
VSS
KEY
DQ34
DQ35
VSS
5
DQ0
DQ1
VSS
6
73
75
77
CKE0
VDD
74
76
78
CKE1
VDD
7
8
DQ44
DQ45
VSS
A153
9
10
DQS0
NC
DQ40
DQ41
VSS
A143
VDD
149
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
DM0
VSS
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
DQS0
VSS
79
81
BA2
VDD
A12/BC
A9
80
82
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DQS5
DQS5
VSS
DQ2
DQ3
VSS
DQ6
DQ7
VSS
83
84
A11
A7
DM5
VSS
85
86
VDD
A8
VDD
A6
87
88
DQ42
DQ43
VSS
DQ46
DQ47
VSS
DQ8
DQ9
VSS
DQ12
DQ13
VSS
89
90
91
A5
92
A4
VDD
A3
VDD
A2
93
94
DQ48
DQ49
VSS
DQ52
DQ53
VSS
DQS1
DQS1
VSS
DM1
RESET
VSS
95
96
97
A1
98
A0
VDD
VDD
DQS6
DQS6
VSS
DM6
VSS
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
DQ10
DQ11
VSS
DQ14
DQ15
VSS
101
103
105
107
109
111
113
115
117
119
CK0
CK0
VDD
CK1
CK1
VDD
DQ54
DQ55
VSS
DQ50
DQ51
VSS
DQ16
DQ17
VSS
DQ20
DQ21
VSS
A10/AP
BA0
BA1
RAS
VDD
DQ60
DQ61
VSS
VDD
DQ56
DQ57
VSS
DQS2
DQS2
VSS
DM2
VSS
WE
CAS
VDD
S0
ODT0
VDD
DQS7
DQS7
VSS
DQ22
DQ23
VSS
DM7
VSS
A133
S1
DQ18
DQ19
VSS
ODT1
NC
121
123
125
127
129
DQ58
DQ59
VSS
DQ62
DQ63
VSS
VDD
VDD
DQ28
DQ29
VSS
VREFCA
VSS
DQ24
DQ25
VSS
TEST
VSS
SA0
NC
VDDSPD
DQS3
DQS3
VSS
DQ32
DQ33
VSS
DQ36
DQ37
VSS
SDA
SCL
VTT
DM3
VSS
131
133
SA1
VTT
DQ26
DQ27
DQ30
DQ31
135
137
DQS4
DQS4
DM4
VSS
NOTE :
1. NC = No Connect, NU = Not Used, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
- 5 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
5. x72 DIMM Pin Configurations (Front side/Back Side)
Pin
Front
VREFDQ
VSS
Pin
Back
Pin
Front
Pin
Back
Pin
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Front
DQS4
DQS4
VSS
Pin
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Back
DM4
VSS
1
2
71
CB1
72
CB4
3
4
DQ4
DQ5
VSS
KEY
DQ38
DQ39
VSS
VSS
5
DQ0
DQ1
VSS
6
73
75
74
76
CB5
DM8
VSS
7
8
DQS8
DQS8
VSS
DQ34
DQ35
VSS
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
DQS0
DQS0
VSS
77
78
DQ44
DQ45
VSS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
50
53
55
57
59
61
63
65
67
69
DM0
DQ2
DQ3
VSS
79
80
CB6
CB7
81
CB2
CB3
VDD
82
DQ40
DQ41
VSS
VREFCA
VDD
DQ6
DQ7
83
84
DQS5
DQS5
VSS
85
86
VSS
DQ8
DQ9
VSS
87
CKE0
CKE1
BA2
88
A15
A14
A9
DM5
DQ42
DQ43
VSS
DQ12
DQ13
VSS
89
90
DQ46
DQ47
VSS
91
92
VDD
VDD
A11
A7
DQS1
DQS1
VSS
93
94
DM1
RESET
VSS
95
A12/BC
A8
96
DQ48
DQ49
VSS
DQ52
DQ53
VSS
97
98
DQ10
DQ11
VSS
99
A5
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
A6
VDD
VDD
DQS6
DQS6
VSS
DM6
DQ14
DQ15
VSS
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
A3
A1
A4
A2
DQ54
DQ55
VSS
DQ16
DQ17
VSS
DQ20
DQ21
DM2
VSS
A0
BA1
VDD
DQ50
DQ51
VSS
VDD
DQ60
DQ61
VSS
DQS2
DQS2
VSS
CK0
CK0
Par_In, NC,CK1
Err_out, NC,CK1
VDD
DQ56
DQ57
VSS
VDD
DQ22
DQ23
VSS
DQS7
DQS7
VSS
A10/AP
DQ18
DQ19
VSS
S3
S2
BA0
WE
DM7
DQ58
DQ59
VSS
DQ28
DQ29
VSS
RAS
VDD
DQ62
DQ63
VSS
VDD
DQ24
DQ25
DM3
VSS
CAS
S0
ODT0
ODT1
A13
DQS3
DQS3
VSS
SA0
EVENT
SDA
SCL
VDDSPD
S1
VDD
VDD
DQ26
DQ27
VSS
SA1
VTT
VTT
DQ30
DQ31
VSS
DQ32
DQ33
VSS
DQ36
DQ37
VSS
CB0
NOTE :
1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
- 6 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
6. Pin Description
Pin Name
Description
Number
Pin Name
Description
Number
CK0, CK1
CK0, CK1
Clock Inputs, positive line
2
DQ0-DQ63
Data Input/Output
64
Data Masks/ Data strobes,
Termination data strobes
Clock Inputs, negative line
2
DM0-DM7
8
CKE0, CKE1 Clock Enables
2
1
1
DQS0-DQS7 Data strobes
8
8
1
RAS
CAS
Row Address Strobe
DQS0-DQS7 Data strobes complement
Column Address Strobe
Write Enable
RESET
TEST
Reset Pin
Logic Analyzer specific test pin (No connect
on SODIMM)
WE
1
2
1
V
S0, S1
Chip Selects
Core and I/O Power
Ground
18
52
DD
A0-A9, A11,
A13-A15
V
Address Inputs
14
SS
V
REFDQ
A10/AP
Address Input/Autoprecharge
1
1
Input/Output Reference
2
1
V
REFCA
V
A12/BC
Address Input/Burst chop
SDRAM Bank Addresses
SPD and Temp sensor Power
DDSPD
V
BA0-BA2
3
2
1
1
2
Termination Voltage
Reserved for future use
Total
2
3
TT
ODT0, ODT1 On-die termination control
NC
SCL
SDA
Serial Presence Detect (SPD) Clock Input
204
SPD Data Input/Output
SPD Address
SA0-SA1
NOTE:
*The VDD and VDDQ pins are tied common to a single power-plane on these designs.
7. SPD and Thermal Sensor for ECC SODIMMs
On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor.
SCL
SDA
EVENT
WP/EVENT
SA0
R1
SA1
SA1
SA2
SA2
0
R2
0
SA0
NOTE :
1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor.
2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.
When only the SPD is placed on the module, R2 is placed but R1 is not.
[ Table 1 ] Temperature Sensor Characteristics
Temperature Sensor Accuracy
Grade
Range
Units
NOTE
Min.
Typ.
+/- 0.5
+/- 1.0
+/- 2.0
0.25
Max.
+/- 1.0
+/- 2.0
+/- 3.0
75 < Ta < 95
40 < Ta < 125
-20 < Ta < 125
-
-
-
-
-
-
-
B
C
Resolution
C /LSB
- 7 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
8. Input/Output Functional Description
Symbol
Type
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock
Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM).
CK0-CK1
Input
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM Clock
Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM).
CK0-CK1
Input
Input
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and
output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank).
CKE0-CKE1
Connected to the registering clock driver on 72b-SO-RDIMMs, connected to DRAMs on 72b-SOCDIMMs
and 72b-SO-DIMMs.
Enables the command decoders for the associated rank of SDRAM when low and disables decoders
when high. When decoders are disabled, new commands are ignored and previous operations
continue. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs. For 72b-SO-RDIMMs,
other combinations of these input signals perform unique functions, including disabling all outputs
(except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register
S0-S3
Input
Input
device(s). For modules with two registers, S[3:2] operate similarly to S[1:0] for the second set of
register outputs or register control words
When sampled at the positive rising edge of the clock, CAS_n, RAS_n, and WE_n define the operation
RAS, CAS, WE
to be executed by the SDRAM. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SODIMMs,
connected to the registering clock driver on 72b-SO-RDIMMs.
On-Die Termination control signals. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SODIMMs,
connected to the registering clock driver on 72b-SO-RDIMMs.
ODT0-ODT1
VREFDQ
Input
Supply
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS_n, CAS_n, WE_n, S0_n, S1_n, CKE0, CKE1,
Par_In, ODT0 and ODT1.
VREFCA
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied.
Bank address also determines mode register is to be accessed during an MRS cycle. Connected to
BA0-BA2
Input
SDRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs, connected to the registering clock driver on
72b-SO-RDIMMs.
Provided the row address for Active commands and the column address and Auto Precharge bit for
Read/Write commands to select one location out of the memory array in the respective bank. A10 is
sampled during a Precharge command to determine whether the Precharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by
BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS command. The
address inputs also provide the op-code during Mode Register Set commands. Connected to
A[15:13,12/
BC,11,10/AP,9:0]
Input
I/O
SDRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs, connected to the registering clock driver on
72b-SO-RDIMMs.
Data and Check Bit Input/Output pins.
DQ[63:0], CB[7:0]
DM[8:0]
Input
Supply
Supply
I/O
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
VDD, VSS
VTT
DQS0-DQS17
DQS0-DQS17
I/O
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
SA0-SA1
SDA
Input
I/O
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to VDDSPD on the system planar to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDDSPD on the system planar to act as a pullup.
SCL
Input
OUT
This signal indicates that a thermal event has been detected in the thermal sensing device.The system
(open drain) should guarantee the electrical level requirement is met for the EVENT_n pin on TS/SPD part.
EVENT
- 8 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
Symbol
Type
Function
Serial EEPROM positive power supply wired to a separate power pin at the connector which supports
from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
VDDSPD
Supply
The RESET_n pin is connected to the RESET_n pin on the register (72b-SO-RDIMM) and to the
RESET_n pin on the SDRAMs (all modules). When low, all register outputs will be driven low and
the Clock Driver clocks to the DRAMs and register(s) will be set to low level (the Clock Driver will
remain synchronized with the input clock).
RESET
Input
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even). Not used on 72b-SO-DIMMs or
72b-SO-CDIMMs.
Par_In
Input
OUT
Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out_n
(open drain) bus line to VDD on the system planar to act as a pull up. Not used on 72b-SO-DIMMs or 72b-SOCDIMMs.
Err_Out
- 9 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
9. Function Block Diagram:
9.1 2GB, 256Mx64 Module (Populated as 1 rank of x16 DDR3 SDRAMs)
SCL
SA0
SA1
SCL
A0
A1
(SPD)
WP
SDA
240
DQS0
DQS0
DM0
LDQS
LDQS
LDM
A2
1%
ZQ
DQ[0:7]
DQS1
DQS1
DM1
DQ[0:7]
UDQS
UDQS
UDM
D0
DQ[8:15]
DQ[8:15]
V
V
tt
tt
V
SPD
DDSPD
V
V
D0 - D3
D0 - D3
D0 - D3
D0 - D3, SPD
D0 - D3
D0 - D3
Terminated near
card edge
NC
REFCA
240
DQS2
DQS2
DM2
LDQS
LDQS
LDM
REFDQ
1%
ZQ
V
DD
DQ[16:23]
DQS3
DQS3
DM3
DQ[24:31]
DQ[0:7]
V
UDQS
UDQS
UDM
SS
D1
CK0
CK0
DQ[8:15]
CK1
CK1
ODT1
S1
NC
240
DQS4
DQS4
DM4
LDQS
LDQS
LDM
1%
CKE1
RESET
NC
ZQ
D0 - D3
DQ[32:39]
DQS5
DQS5
DM5
DQ[40:47]
DQ[0:7]
UDQS
UDQS
UDM
D2
DQ[8:15]
D0
D1
D2
D3
240
DQS6
DQS6
DM6
LDQS
LDQS
LDM
1%
ZQ
DQ[48:55]
DQS7
DQS7
DM7
DQ[56:63]
DQ[0:7]
UDQS
UDQS
UDM
D3
Address and Controllines
DQ[8:15]
Note :
1. DQ wiring may differ from that shown
however ,DQ, DM, DQS and DQS
relationships are maintained as shown
Vtt
Vtt
V
Rank0
DD
- 10 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
9.2 4GB, 512Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
SCL
SA0
SA1
SCL
A0
A1
A2
(SPD)
WP
SDA
240
240
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS
DQS
DM
DQS
DQS
DM
1%
1%
ZQ
ZQ
DQ[0:7]
DQ[0:7]
DQ[8:15]
DQ[0:7]
D0
D4
V
V
tt
tt
V
SPD
DDSPD
V
D0 - D7
D0 - D7
D0 - D7
D0 - D7, SPD
D0 - D7
D0 - D7
REFCA
V
REFDQ
V
DD
240
240
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQS
DQS
DM
DQS
DQS
DM
1%
1%
V
SS
ZQ
ZQ
CK0
CK0
CK1
CK1
DQ[16:23]
DQ[0:7]
DQ[24:31]
DQ[0:7]
D1
D5
Terminated near
card edge
NC
S1
ODT1
NC
NC
CKE1
D0 - D7
RESET
240
240
DQS4
DQS4
DM4
DQS5
DQS5
DM5
DQS
DQS
DM
DQS
DQS
DM
1%
1%
ZQ
ZQ
DQ[32:39]
DQ[0:7]
DQ[40:47]
DQ[0:7]
D2
D6
D4
D0
D5
D6
D2
D7
D3
V1
V2
V2
V3
V3
V4
V4
V1
240
240
D1
DQS6
DQS6
DM6
DQS7
DQS7
DM7
DQS
DQS
DM
DQS
DQS
DM
1%
1%
ZQ
ZQ
DQ[48:55]
DQ[0:7]
DQ[56:63]
DQ[0:7]
D3
D7
Address and Controllines
NOTE :
1. DQ wiring may differ from that shown how-
ever ,DQ, DM, DQS and DQS relationships
are maintained as shown
Rank0
Vtt
Vtt
V
DD
- 11 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
9.3 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
V
V
DD
DD
Vtt
Vtt
Vtt
240
240
240
240
DQS3
DQS3
DM3
DQS4
DQS4
DM4
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
1%
1%
1%
1%
ZQ
ZQ
ZQ
ZQ
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[24:31]
DQ[32:39]
D11
D3
D4
D12
240
240
240
240
DQS1
DQS1
DM1
DQS6
DQS6
DM6
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
1%
1%
1%
1%
ZQ
ZQ
ZQ
ZQ
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[8:15]
DQ[48:55]
D1
D9
D14
D6
240
240
240
240
DQS0
DQS0
DM0
DQS7
DQS7
DM7
DQ[56:63]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
1%
1%
1%
1%
ZQ
ZQ
Rank0
Rank1
ZQ
ZQ
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
D0
D8
D15
D7
240
240
240
240
DQS2
DQS2
DM2
DQS5
DQS5
DM5
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
1%
1%
1%
1%
ZQ
ZQ
ZQ
ZQ
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[16:23]
DQ[40:47]
D2
D10
D13
D5
V2
V1
V1
V8
D6
D9
V3
D3
D12
D5
V9
V5
V7
V
V
tt
tt
V
SPD
D8
D10
D7
V6
DDSPD
V4
V4
V
D0 - D15
D0 - D15
D0 - D15
REFCA
REFDQ
V
SCL
SA0
SA1
SCL
A0
A1
V6
(SPD)
WP
SDA
V
D0
D2
D13
D4
D15
DD
V5
tt
V
D0 - D15, SPD
D0 - D7
SS
A2
V3
D1
V7
V
V1
V9
CK0
CK1
CK0
CK1
D11
D14
V8
V2
D8 - D15
D0 - D7
Address and Controllines
D8 - D15
D0 - D7
NOTE :
RESET
1. DQ wiring may differ from that shown how-
ever ,DQ, DM, DQS and DQS relationships
are maintained as shown
- 12 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
9.4 4GB, 512Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
SCL
SA0
SA1
SCL
A0
A1
A2
(SPD)
WP
SDA
240
240
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS
DQS
DM
DQS
DQS
DM
1%
1%
ZQ
ZQ
DQ[0:7]
DQ
DQ[8:15]
DQ
D0
D4
V
V
tt
tt
V
SPD
DDSPD
V
D0 - D8
D0 - D8
D0 - D8
D0 - D8
D0 - D8
D0 - D8
REFCA
V
REFDQ
V
DD
240
240
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQS
DQS
DM
DQS
DQS
DM
1%
1%
V
SS
ZQ
ZQ
CK0
CK0
DQ[16:23]
DQ
DQ[24:31]
DQ
D1
D5
CK1
Terminated near
card edge
CK1
NC
S1
NC
ODT1
CKE1
NC
Temp Sensor
D0 - D8
ENEVT
RESET
240
DQS4
DQS4
DM4
DQS
DQS
DM
1%
ZQ
CB[0:7]
DQ
D8
D4
D5
D6
D7
V1
V1
V2
V3
V4
V4
240
240
DQS4
DQS4
DM4
DQS5
DQS5
DM5
DQS
DQS
DM
DQS
DQS
DM
1%
1%
ZQ
ZQ
DQ[32:39]
DQ
DQ[40:47]
DQ
V2
V3
D2
D6
D0
D1
D8
D2
D3
Address and Controllines
NOTE :
1. DQ wiring may differ from that shown how-
ever ,DQ, DM, DQS and DQS relationships
are maintained as shown
240
240
DQS6
DQS6
DM6
DQS7
DQS7
DM7
DQS
DQS
DM
DQS
DQS
DM
1%
1%
ZQ
ZQ
DQ[48:55]
DQ
DQ[56:63]
DQ
D3
D7
Rank0
Vtt
Vtt
V
DD
- 13 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
9.5 8GB, 1Gx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
V
V
DD
DD
C
term
Vtt
Vtt
Vtt
240
240
240
240
1%
1%
1%
1%
DQS0
DQS0
DM0
DQS1
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQ
DQS1
DM1
DQ[8:15]
ZQ
ZQ
D10
ZQ
ZQ
D14
DQ
DQ
DQ
DQ[0:7]
D1
D5
240
240
240
240
1%
1%
1%
1%
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQ[24:31]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
ZQ
ZQ
ZQ
ZQ
D15
DQ
DQ
DQ
DQ
DQ[16:15]
D2
D3
D4
D9
D11
D6
D7
D8
240
240
240
240
1%
1%
1%
1%
DQS4
DQS4
DM4
DQS5
DQS5
DM5
DQ[40:47]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
ZQ
ZQ
Rank0
Rank1
ZQ
ZQ
DQ
DQ
DQ
DQ
DQ[32:39]
D12
D16
240
240
240
240
1%
1%
1%
1%
DQS6
DQS6
DM6
DQS7
DQS7
DM7
DQ[56:63]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
ZQ
ZQ
ZQ
ZQ
DQ
DQ
DQ
DQ
DQ[48:55]
D13
D17
240
1%
240
1%
DQS
DQS
DM
DQS8
DQS8
DM8
DQS
DQS
DM
ZQ
ZQ
DQ
DQ
CB[0:7]
D18
V2
V1
V8
D2
V
V
tt
D16
V3
D14
D4
D3
tt
V9
V
SPD
DDSPD
V7
V
D0 - D15
D0 - D15
D0 - D15
REFCA
REFDQ
D17
D6
D1
D10
SCL
SA0
SA1
SCL
A0
A1
V4
V4
V5
V5
V6
V6
V
(SPD)
WP
SDA
V
DD
V1
A2
V
D0 - D15, SPD
D0 - D7
SS
D8
D15
D5
D18
Vtt
D12
D13
D10
CK0
CK1
CK0
CK1
V3
D7
V7
D11
D8 - D15
D0 - D7
V2
V8
V9
V1
D8 - D15
D0 - D7
Address and Controllines
RESET
NOTE :
1. DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS relationships are maintained as shown
- 14 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
10. Absolute Maximum Ratings
10.1 Absolute Maximum DC Ratings
Symbol
Parameter
Voltage on V pin relative to V
SS
Rating
Units
NOTE
V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
V
1,3
DD
DD
V
Voltage on V
pin relative to V
SS
V
V
1,3
1
DDQ
DDQ
V
V
Voltage on any pin relative to V
Storage Temperature
IN, OUT
SS
T
C
1, 2
STG
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be
equal to or less than 300mV.
10.2 DRAM Component Operating Temperature Range
Symbol
Parameter
rating
Unit
NOTE
T
Operating Temperature Range
0 to 95
C
1, 2, 3
OPER
NOTE :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
11. AC & DC Operating Conditions
11.1 Recommended DC Operating Conditions
Rating
Symbol
Parameter
Operation Voltage
Units
NOTE
Min.
1.283
1.425
1.283
1.425
Typ.
1.35
1.5
Max.
1.45
1.35V
1.5V
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
V
Supply Voltage
DD
1.575
1.45
1.35V
1.5V
1.35
1.5
V
Supply Voltage for Output
DDQ
1.575
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD
.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD & VDDQ rating are determinied by operation voltage.
- 15 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
12. AC & DC Input Measurement Levels
12.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 2 ] Single Ended AC and DC input levels for Command and Address(1.35V)
DDR3L-800/1066/1333/1600
Min. Max.
Symbol
Parameter
Unit
NOTE
1.35V
V
(DC90)
V
+ 90
V
DD
DC input logic high
mV
mV
mV
mV
mV
mV
V
1
IH.CA
REF
V
(DC90)
V
V
- 90
REF
DC input logic low
1
IL.CA
SS
V
(AC160)
(AC160)
(AC135)
(AC135)
(DC)
V
+ 160
REF
AC input logic high
Note 2
1,2,5
1,2,5
1,2,5
1,2,5
3,4
IH.CA
V
V
V
- 160
AC input logic low
Note 2
IL.CA
REF
V
+135
AC input logic high
Note 2
IH.CA
REF
V
V
-135
REF
AC input logic lowM
Note 2
IL.CA
V
0.49*V
0.51*V
DD
Reference Voltage for ADD, CMD inputs
REFCA
DD
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),
VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do not
apply when the device is operated in the 1.35 voltage range.
[ Table 3 ] Single-ended AC & DC input levels for Command and Address(1.5V)
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min.
Max.
1.5V
V
(DC100)
V
+ 100
V
DC input logic high
mV
mV
mV
mV
mV
mV
V
1,5
IH.CA
REF
DD
V
V
(DC100)
(AC175)
(AC175)
(AC150)
(AC150)
(DC)
V
V
- 100
REF
DC input logic low
1,6
IL.CA
SS
V
+ 175
AC input logic high
Note 2
1,2,7
1,2,8
1,2,7
1,2,8
3,4,9
IH.CA
REF
V
V
- 175
AC input logic low
Note 2
IL.CA
IH.CA
REF
V
V
+150
AC input logic high
Note 2
REF
V
V
-150
REF
AC input logic low
Note 2
IL.CA
V
0.49*V
0.51*V
DD
Reference Voltage for ADD, CMD inputs
REFCA
DD
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is
referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is
used when Vref + 0.125V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is
referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is
used when Vref - 0.125V is referenced.
9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device
- 16 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 4 ] Single Ended AC and DC input levels for DQ and DM(1.35V)
DDR3L-800/1066
Min. Max.
DDR3L-1333/1600
Min. Max.
Symbol
Parameter
Unit
NOTE
1.35V
V
(DC90)
V
+ 90
V
V
+ 90
V
DD
DC input logic high
mV
mV
mV
mV
mV
mV
1
IH.DQ
REF
DD
REF
V
(DC90)
V
V
- 90
V
V
- 90
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
1
IL.DQ
SS
REF
SS
REF
V
(AC160)
(AC160)
(AC135)
(AC135)
V + 160
REF
Note 2
-
-
1,2,5
1,2,5
1,2,5
1,2,5
IH.DQ
V
V
V
V
- 160
REF
Note 2
-
-
IL.DQ
V
+ 135
V + 135
REF
Note 2
Note 2
IH.DQ
REF
V
- 135
V
- 135
REF
Note 2
Note 2
0.49*V
IL.DQ
REF
Reference Voltage for DQ, DM
inputs
VREF (DC)
0.49*V
0.51*V
0.51*V
DD
V
3,4
DQ
DD
DD
DD
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV.
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/
L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the
device is operated in the 1.35 voltage range.
[ Table 5 ] Single-ended AC & DC input levels for DQ and DM (1.5V)
DDR3-800/1066
Min. Max.
DDR3-1333/1600
Min. Max.
Symbol
Parameter
Unit
NOTE
1.5V
V
(DC100)
V
V
V
V
+ 100
V
V
+ 100
V
DD
DC input logic high
mV
mV
mV
mV
mV
mV
mV
mV
1,5
1,6
IH.DQ
REF
DD
REF
V
V
(DC100)
(AC175)
(AC175)
(AC150)
(AC150)
(AC135)
(AC135)
V
V
- 100
V
V
- 100
REF
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
IL.DQ
SS
REF
SS
+ 175
NOTE 2
-
-
-
1,2,7
IH.DQ
REF
V
V
- 175
REF
NOTE 2
-
1,2,8
IL.DQ
IH.DQ
V
+ 150
V
V
+ 150
NOTE 2
NOTE 2
1,2,7
REF
REF
V
V
V
- 150
V
- 150
REF
NOTE 2
NOTE 2
1,2,8
IL.DQ
REF
+ 135
+ 135
NOTE 2
NOTE 2
1,2,7,10
1,2,8,10
IH.DQ
REF
REF
V
V
- 135
V
- 135
REF
NOTE 2
NOTE 2
IL.DQ
REF
Reference Voltage for DQ, DM
inputs
VREF (DC)
0.49*V
0.51*V
0.49*V
0.51*V
DD
V
3,4,9
DQ
DD
DD
DD
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,
VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,
VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device
10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices
support this option.
- 17 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
12.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages V
and V
are illustrate in Figure 1. It shows a valid reference voltage
REFCA
REFDQ
V
V
(t) as a function of time. (V
stands for V
and V
likewise).
REFDQ
REF
REF
REF
REFCA
(DC) is the linear average of V
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V
. Fur-
REF
REF
thermore V
(t) may temporarily deviate from V
(DC) by no more than ± 1% V
.
REF
REF
DD
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements V (AC), V (DC), V (AC) and V (DC) are dependent on V
.
IH
IH
IL
IL
REF
"V
" shall be understood as V
(DC), as defined in Figure 1.
REF
REF
This clarifies, that dc-variations of V
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
REF
which setup and hold is measured. System timing and voltage budgets need to account for V
data-eye of the input signals.
(DC) deviations from the optimum position within the
REF
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
ac-noise.
REF
Timing and voltage effects due to ac-noise on V
up to the specified limit (+/-1% of V ) are included in DRAM timings and their associated deratings.
DD
REF
- 18 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
12.3 AC and DC Logic Input Levels for Differential Signals
12.3.1 Differential Signals Definition
tDVAC
V
.DIFF.AC.MIN
IH
V
.DIFF.MIN
0.0
IH
half cycle
V .DIFF.MAX
IL
V .DIFF.AC.MAX
IL
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
DDR3-800/1066/1333/1600
Symbol
Parameter
1.35V
1.5V
unit
NOTE
min
+0.18
max
NOTE 3
-0.18
min
+0.20
max
NOTE 3
-0.20
V
differential input high
differential input low
V
V
V
V
1
1
2
2
IHdiff
V
NOTE 3
NOTE 3
ILdiff
V
(AC)
(AC)
2 x (V (AC) - V
)
2 x (V (AC) - V
)
differential input high ac
differential input low ac
NOTE 3
NOTE 3
IHdiff
IH
REF
IH
REF
V
2 x (V (AC) - V
)
2 x (V (AC) - V
)
REF
NOTE 3
NOTE 3
ILdiff
IL
REF
IL
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
- 19 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 6 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)
DDR3L-800/1066/1333/1600
(AC)| = 320mV tDVAC [ps] @ |V
tDVAC [ps] @ |V
(AC)| = 270mV
IH/Ldiff
Slew Rate [V/ns]
IH/Ldiff
min
189
189
162
109
91
max
min
201
201
179
134
119
100
76
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
69
1.4
40
1.2
note
note
note
44
1.0
note
note
< 1.0
NOTE: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
[ Table 7 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)
DDR3-800 / 1066 / 1333 / 1600
tDVAC [ps] @ |V
(AC)| =
tDVAC [ps] @ |V
(AC)| =
tDVAC [ps] @ |V
(AC)| =
IH/Ldiff
IH/Ldiff
IH/Ldiff
Slew Rate [V/ns]
350mV
300mV
(DQS-DQS#) only (Optional)
min
75
max
min
175
170
167
119
102
81
max
min
214
214
191
146
131
113
88
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
57
3.0
50
2.0
38
1.8
34
1.6
29
1.4
22
54
1.2
note
note
note
19
56
1.0
note
note
11
< 1.0
note
NOTE: Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac)
level.
- 20 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
12.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach V
half-cycle.
min / V
max (approximately equal to the ac-levels ( V (AC) / V (AC) ) for ADD/CMD signals) in every
SEH
SEL IH IL
DQS have to reach V
valid transition.
min / V
max (approximately the ac-levels ( V (AC) / V (AC) ) for DQ signals) in every half-cycle proceeding and following a
SEL IH IL
SEH
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V 150(AC)/V 150(AC) is used for ADD/CMD
IH
IL
signals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to V
, the single-ended components of differential signals have a requirement
REF
with respect to V /2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
DD
ended components of differential signals the requirement to reach V
mode characteristics of these signals.
max, V
min has no bearing on timing, but adds a restriction on the common
SEL
SEH
[ Table 8 ] Single ended levels for CK, DQS, CK, DQS
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
Max
(V /2)+0.175
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
NOTE 3
NOTE 3
V
V
V
V
1, 2
1, 2
1, 2
1, 2
DD
V
SEH
(V /2)+0.175
DD
(V /2)-0.175
NOTE 3
NOTE 3
DD
V
SEL
(V /2)-0.175
DD
NOTE :
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-
nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
- 21 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
12.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V is measured from the actual
IX
cross point of true and complement signal to the mid level between of V and V
.
SS
DD
V
DD
CK, DQS
V
IX
V
/2
DD
V
V
IX
IX
CK, DQS
V
SS
Figure 4. V Definition
IX
[ Table 9 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V
DDR3L-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
-150
-150
Max
150
150
V
Differential Input Cross Point Voltage relative to V /2 for CK,CK
mV
mV
1
IX
DD
V
Differential Input Cross Point Voltage relative to V /2 for DQS,DQS
IX
DD
NOTE :
1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix(Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix(Max)) 25mV
[ Table 10 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
-150
-175
-150
Max
150
175
150
mV
mV
mV
V
V
Differential Input Cross Point Voltage relative to V /2 for CK,CK
IX
DD
1
Differential Input Cross Point Voltage relative to V /2 for DQS,DQS
IX
DD
NOTE :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
- 22 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
12.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.
12.5 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
[ Table 11 ] Differential input slew rate definition
Measured
Description
Defined by
From
To
V
V
V
[V
- V
- V
Delta TRdiff
Delta TFdiff
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
ILdiffmax
IHdiffmin
IHdiffmin
ILdiffmax] /
V
[V
IHdiffmin
IHdiffmin
ILdiffmax
ILdiffmax] /
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
VIHdiffmin
0
VILdiffmax
delta TFdiff
delta TRdiff
Differential input slew rate definition for DQS, DQS and CK, CK
13. AC & DC Output Measurement Levels
13.1 Single Ended AC and DC Output Levels
[ Table 12 ] Single Ended AC and DC output levels
Symbol Parameter
DDR3-800/1066/1333/1600
Units
NOTE
V
(DC) DC output high measurement level (for IV curve linearity)
0.8 x V
0.5 x V
0.2 x V
V
OH
DDQ
DDQ
DDQ
V
V
V
(DC) DC output mid measurement level (for IV curve linearity)
V
V
V
V
OM
(DC) DC output low measurement level (for IV curve linearity)
OL
(AC) AC output high measurement level (for output SR)
(AC) AC output low measurement level (for output SR)
V
+ 0.1 x V
1
1
OH
TT
DDQ
V
V
- 0.1 x V
TT
OL
DDQ
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test
load of 25 to VTT=VDDQ/2.
13.2 Differential AC and DC Output Levels
[ Table 13 ] Differential AC and DC output levels
Symbol
(AC)
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
V
AC differential output high measurement level (for output SR)
+0.2 x V
V
1
OHdiff
DDQ
V
(AC)
AC differential output low measurement level (for output SR)
-0.2 x V
V
1
OLdiff
DDQ
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test
load of 25 to VTT=VDDQ/2 at each of the differential outputs.
13.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) and V (AC)
OL
OH
for single ended signals as shown in below.
- 23 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 14 ] Single ended Output slew rate definition
Description
Measured
Defined by
[V (AC)-V (AC)] / Delta TRse
From
(AC)
To
(AC)
V
V
V
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
OL
OH
OH
OL
(AC)
V
(AC)
[V (AC)-V (AC)] / Delta TFse
OH OL
OH
OL
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 15 ] Single ended output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Operation
Voltage
Parameter
Symbol
Units
Min
1.75
2.5
Max
Min
1.75
2.5
Max
Min
1.75
2.5
Max
Min
1.75
2.5
Max
1)
1)
1)
1)
1.35V
1.5V
V/ns
V/ns
5
5
5
5
Single ended output slew rate SRQse
Description : SR : Slew Rate
5
5
5
5
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
VOHdiff(AC)
VTT
OLdiff(AC)
V
delta TFdiff
delta TRdiff
Figure 5. Single-ended output slew rate definition
- 24 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
13.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
(AC) and V
OH-
OLdiff
(AC) for differential signals as shown in below.
diff
[ Table 16 ] Differential Output slew rate definition
Description
Measured
Defined by
From
To
(AC)
V
V
(AC)
V
[V
(AC)-V
OLdiff
(AC)] / Delta TRdiff
(AC)]/ Delta TFdiff
Differential output slew rate for rising edge
Differential output slew rate for falling edge
OLdiff
OHdiff
OHdiff
(AC)
V
(AC)
[V
(AC)-V
OHdiff OLdiff
OHdiff
OLdiff
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Differential Output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Operation
Voltage
Parameter
Symbol
Units
Min
Max
12
Min
Max
12
Min
Max
12
Min
Max
12
1.35V
1.5V
3.5
5
3.5
5
3.5
5
3.5
5
V/ns
V/ns
Differential output slew rate
Description : SR : Slew Rate
SRQdiff
10
10
10
10
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
VOHdiff(AC)
VTT
OLdiff(AC)
V
delta TFdiff
delta TRdiff
Figure 6. Differential output slew rate definition
- 25 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
14. IDD specification definition
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between ACT and PRE;
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
IDD0
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between ACT, RD
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
IDD1
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
IDD2N
Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2)
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit3)
IDD2P0
;
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2)
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit3)
IDD2P1
IDD2Q
IDD3N
IDD3P
;
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2)
ODT Signal: stable at 0
;
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT
Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD4R
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable
at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD5B
IDD6
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
Self-Refresh Current: Extended Temperature Range (optional)6)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
IDD6ET
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: CL-1; CS: High
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
IDD7
IDD8
Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
- 26 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
7) IDD current measure method and detail patterns are described on DDR3 component datasheet
8) VDD and VDDQ are merged on module PCB.
9) DIMM IDD SPEC is measured with Qoff condition
(IDDQ values are not considered)
- 27 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
15. IDD SPEC Table
M471B5674QH0 : 2GB (256Mx64) Module
DDR3L-1333
DDR3L-1600
Symbol
Unit
NOTE
9-9-9
175
250
55
11-11-11
180
275
60
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
55
60
75
80
IDD2Q
75
80
IDD3P
70
75
IDD3N
110
465
440
570
40
120
535
500
580
40
IDD4R
IDD4W
IDD5B
IDD6
IDD7
675
25
760
25
IDD8
M471B5173QH0 : 4GB (512Mx64) Module
DDR3L-1333
9-9-9
320
DDR3L-1600
11-11-11
320
Symbol
Unit
NOTE
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
400
440
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
120
120
120
120
160
160
IDD2Q
160
160
IDD3P
160
160
IDD3N
240
240
IDD4R
680
800
IDD4W
680
840
IDD5B
1160
120
1160
120
IDD6
IDD7
1320
120
1360
120
IDD8
- 28 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
M471B1G73QH0 : 8GB (1Gx64) Module
DDR3L-1333
DDR3L-1600
Symbol
Unit
NOTE
9-9-9
480
560
240
240
320
320
320
400
840
840
1320
240
1480
240
11-11-11
480
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
600
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
240
240
320
IDD2Q
320
IDD3P
320
IDD3N
400
IDD4R
960
1
1
1
IDD4W
1000
1320
240
IDD5B
IDD6
IDD7
1520
240
1
IDD8
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
M474B5173QH0 : 4GB (512Mx72) Module
DDR3L-1600
11-11-11
TBD
Symbol
Unit
NOTE
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
TBD
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
TBD
TBD
TBD
IDD2Q
TBD
IDD3P
TBD
IDD3N
TBD
IDD4R
TBD
IDD4W
TBD
IDD5B
TBD
IDD6
TBD
IDD7
TBD
IDD8
TBD
- 29 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
M474B1G73QH0 : 8GB (1Gx72) Module
DDR3L-1600
11-11-11
540
Symbol
Unit
NOTE
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
675
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
270
270
360
IDD2Q
360
IDD3P
360
IDD3N
450
IDD4R
1080
1125
1485
270
1
1
1
IDD4W
IDD5B
IDD6
IDD7
1710
270
1
IDD8
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
- 30 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
16. Input/Output Capacitance
[ Table 18 ] Input/Output Capacitance
DDR3-800
Min Max
1.35V
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
Symbol
Units NOTE
Min
Max
Min
Max
Min
Max
Input/output capacitance
CIO
CCK
1.4
0.8
0
2.5
1.6
0.15
1.3
0.2
0.3
0.5
1.4
0.8
0
2.5
1.6
0.15
1.3
0.2
0.3
0.5
1.4
0.8
0
2.3
1.4
1.5
0.8
0
2.2
1.4
pF
pF
pF
pF
pF
pF
pF
1,2,3
2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
CDCK
0.15
1.3
0.15
1.2
2,3,4
Input capacitance
CI
0.75
0
0.75
0
0.75
0
0.75
0
2,3,6
(All other input-only pins)
Input/Output capacitance delta
(DQS and DQS)
CDDQS
CDI_CTRL
CDI_ADD_CMD
0.15
0.2
0.15
0.2
2,3,5
Input capacitance delta
-0.5
-0.5
-0.5
-0.5
-0.4
-0.4
-0.4
-0.4
2,3,7,8
2,3,9,10
(All control input-only pins)
Input capacitance delta
0.4
0.4
(all ADD and CMD input-only pins)
Input/output capacitance delta
CDIO
CZQ
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
pF
pF
2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
2, 3, 12
1.5V
Input/output capacitance
CIO
CCK
1.4
0.8
0
3.0
1.6
0.15
1.4
0.2
0.3
0.5
1.4
0.8
0
2.7
1.6
1.4
0.8
0
2.5
1.4
1.4
0.8
0
2.3
1.4
pF
pF
pF
pF
pF
pF
pF
1,2,3
2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
CDCK
0.15
1.35
0.2
0.15
1.3
0.15
1.3
2,3,4
Input capacitance
CI
0.75
0
0.75
0
0.75
0
0.75
0
2,3,6
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
CDDQS
CDI_CTRL
CDI_ADD_CMD
0.15
0.2
0.15
0.2
2,3,5
Input capacitance delta
-0.5
-0.5
-0.5
-0.5
0.3
-0.4
-0.4
-0.4
-0.4
2,3,7,8
2,3,9,10
(All control input-only pins)
Input capacitance delta
0.5
0.4
0.4
(all ADD and CMD input-only pins)
Input/output capacitance delta
CDIO
CZQ
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
pF
pF
2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
2, 3, 12
NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
DD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V or 1.35V, VBIAS=VDD/2 and on-
V
die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
- 31 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
17. Electrical Characteristics and AC timing
[0 C<TCASE 95 C, VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]
17.1 Refresh Parameters by Device Density
Parameter
Symbol
1Gb
110
7.8
2Gb
160
7.8
4Gb
260
7.8
8Gb
350
7.8
Units
ns
NOTE
All Bank Refresh to active/refresh cmd time
tRFC
0CT
85C
95C
s
CASE
Average periodic refresh interval
tREFI
85CT
3.9
3.9
3.9
3.9
s
1
CASE
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.
17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR3-800
6-6-6
min
6
DDR3-1066
7-7-7
min
DDR3-1333
9-9-9
min
9
DDR3-1600
11-11-11
min
Bin (CL - tRCD - tRP)
Units
NOTE
Parameter
CL
7
11
tCK
ns
ns
ns
ns
ns
ns
tRCD
tRP
15
13.13
13.13
37.5
13.5
13.5
36
13.75
13.75
35
15
tRAS
tRC
37.5
52.5
10
50.63
7.5
49.5
6.0
48.75
6.0
tRRD
tFAW
40
37.5
30
30
17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 19 ] DDR3-800 Speed Bins
Speed
DDR3-800
6 - 6 - 6
CL-nRCD-nRP
Units
NOTE
Parameter
Symbol
tAA
min
15
max
Internal read command to first data
ACT to internal read or write delay time
PRE command period
20
ns
ns
tRCD
15
-
tRP
15
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
52.5
37.5
3.0
2.5
ns
tRAS
9*tREFI
3.3
ns
CL = 5
CWL = 5
CWL = 5
tCK(AVG)
tCK(AVG)
ns
1,2,3,4,9,10
1,2,3
CL = 6
3.3
ns
Supported CL Settings
Supported CWL Settings
5,6
5
nCK
nCK
- 32 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 20 ] DDR3-1066 Speed Bins
Speed
DDR3-1066
CL-nRCD-nRP
7 - 7 - 7
Units
NOTE
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
Symbol
tAA
min
13.125
13.125
13.125
50.625
37.5
max
20
ns
ns
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
3.0
ns
1,2,3,4,5,9,10
CL = 5
CL = 6
CL = 7
CL = 8
Reserved
ns
4
1,2,3,5
1,2,3,4
4
2.5
3.3
ns
Reserved
Reserved
ns
ns
1.875
1.875
<2.5
<2.5
ns
1,2,3,4,8
4
Reserved
ns
ns
1,2,3
Supported CL Settings
Supported CWL Settings
5,6,7,8
5,6
nCK
nCK
- 33 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 21 ] DDR3-1333 Speed Bins
Speed
DDR3-1333
CL-nRCD-nRP
9 -9 - 9
Units
NOTE
Parameter
Symbol
min
max
13.5
(13.125)
Internal read command to first data
tAA
20
ns
ns
ns
ns
8
8
8
8
13.5
(13.125)
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
-
13.5
(13.125)
49.5
(49.125)
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS
36
9*tREFI
3.3
ns
ns
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
3.0
1,2,3,4,6,9,10
CL = 5
CWL = 6,7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
CWL = 7
Reserved
ns
4
1,2,3,6
1,2,3,4,6
4
2.5
3.3
ns
CL = 6
Reserved
Reserved
Reserved
ns
ns
ns
4
CL = 7
CL = 8
1.875
1.875
<2.5
<2.5
ns
1,2,3,4,6
1,2,3,4
4
Reserved
Reserved
ns
ns
ns
1,2,3,6
1,2,3,4
4
Reserved
Reserved
ns
ns
CL = 9
1.5
1.5
<1.875
<1.875
ns
1,2,3,4,8
4
Reserved
ns
CL = 10
ns
1,2,3
Supported CL Settings
Supported CWL Settings
5,6,7,8,9,10
5,6,7
nCK
nCK
- 34 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 22 ] DDR3-1600 Speed Bins
Speed
DDR3-1600
CL-nRCD-nRP
11-11-11
Units
NOTE
Parameter
Symbol
min
max
13.75
(13.125)
Internal read command to first data
tAA
20
ns
ns
ns
ns
8
8
8
8
13.75
(13.125)
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
-
13.75
(13.125)
48.75
(48.125)
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS
35
9*tREFI
3.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
3.0
1,2,3,4,7,9,10
CL = 5
CWL = 6,7,8
CWL = 5
CWL = 6
CWL = 7, 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6,7
CWL = 8
Reserved
4
1,2,3,7
1,2,3,4,7
4
2.5
3.3
CL = 6
Reserved
Reserved
Reserved
4
1.875
1.875
<2.5
<2.5
1,2,3,4,7
1,2,3,4,7
4
CL = 7
Reserved
Reserved
Reserved
4
1,2,3,7
1,2,3,4,7
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
1.5
1.5
<1.875
<1.875
<1.5
1,2,3,4,7
1,2,3,4
4
Reserved
Reserved
CL = 10
CL = 11
1,2,3,7
1,2,3,4
4
Reserved
Reserved
1.25
1,2,3,8
Supported CL Settings
Supported CWL Settings
5,6,7,8,9,10,11
5,6,7,8
- 35 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
17.3.1 Speed Bin Table Notes
Absolute Specification [T
; V
= V = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)];
OPER
DDQ DD
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-
anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin
+ tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
9. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
10. For CL5 support DIMM SPD include CL5 on supportable CAS Latency(Byte 14-bit1 set HIGH).
- 36 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
18. Timing Parameters by Speed Grade
[ Table 23 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
8
-
8
-
8
-
8
-
ns
6
Average Clock Period
Clock Period
tCK(avg)
tCK(abs)
See Speed Bins Table
ps
ps
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
-100
100
-90
90
-80
80
-70
70
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-90
90
-80
80
-70
70
-60
60
ps
200
180
180
160
160
140
140
120
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
147
175
194
209
222
232
241
249
257
263
269
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
103
122
136
147
155
163
169
175
180
184
188
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
tDQSQ
tQH
-
200
-
-
150
-
-
125
-
-
100
-
ps
tCK(avg)
ps
13
0.38
-800
-
0.38
-600
-
0.38
-500
-
0.38
-450
-
13, g
tLZ(DQ)
tHZ(DQ)
400
400
300
300
250
250
225
225
13,14, f
13,14, f
ps
1.35V
tDS(base)
AC160
90
40
90
-
-
-
-
-
-
ps
ps
d, 17
d, 17
d, 17
-
-
-
-
tDS(base)
AC135
140
45
25
Data setup time to DQS, DQS referenced to
V
(AC)V (AC) levels
IH
IL
1.5V
tDS(base)
AC175
75
25
75
-
-
-
-
-
-
ps
ps
-
-
-
-
tDS(base)
AC150
125
30
10
1.35V
75
1.5V
65
400
tDH(base)
DC90
160
110
-
55
-
ps
-
-
Data hold time from DQS, DQS referenced to
(DC)V (DC) levels
V
IH
IL
tDH(base)
DC100
150
600
100
490
-
45
-
ps
ps
d, 17
28
-
-
-
-
DQ and DM Input pulse width for each input
tDIPW
360
-
-
- 37 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 23 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
tRPRE
tRPST
tQSH
0.9
0.3
Note 19
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
tCK(avg) 13, 19, g
tCK(avg) 11, 13, b
Note 11
Note 11
Note 11
Note 11
0.38
0.38
0.9
-
-
-
-
0.38
0.38
0.9
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
13, g
13, g
tQSL
tWPRE
tWPST
0.3
0.3
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
tLZ(DQS)
tHZ(DQS)
-400
-800
-
400
400
400
-300
-600
-
300
300
300
-255
-500
-
255
250
250
-225
-450
-
225
225
225
ps
ps
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-
1)
13,14,f
12,13,14
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
Command and Address Timing
tDQSL
tDQSH
tDQSS
tDSS
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.27
0.18
0.18
0.55
0.55
0.27
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
29, 31
30, 31
c
c, 32
c, 32
tDSH
0.2
-
0.2
-
0.2
-
-
DLL locking time
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
512
-
-
nCK
internal READ Command to PRECHARGE Command
delay
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
e
Delay from start of internal write transaction to internal
read command
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
tWTR
-
-
-
-
e,18
e
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
(12nCK,15ns)
max
(12nCK,15ns)
max
(12nCK,15ns)
max
(12nCK,15ns)
Mode Register Set command update delay
tMOD
-
-
-
-
-
-
-
-
CAS to CAS command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
1
4
4
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
-
1
-
1
-
1
-
22
e
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin”
max
(4nCK,10ns)
max
(4nCK,7.5ns)
max
(4nCK,6ns)
max
(4nCK,6ns)
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
-
-
-
-
-
-
-
e
e
max
(4nCK,10ns)
max
(4nCK,10ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
tFAW
tFAW
40
50
-
-
37.5
50
-
-
30
45
-
-
30
40
-
-
ns
ns
e
e
1.35V
tIS(base)
AC160
215
365
140
290
80
-
-
60
-
-
ps
ps
b,16
-
-
-
-
tIS(base)
AC135
205
1.5V
65
185
b,16,27
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
tIS(base)
AC175
200
350
125
275
-
-
45
-
-
ps
ps
b,16
-
-
-
-
tIS(base)
AC150
190
1.35V
150
170
b,16,27
tIH(base)
DC90
285
210
-
130
-
ps
b,16
-
-
Command and Address hold time from CK, CK refer-
enced to V (DC) / V (DC) levels
IH
IL
1.5V
140
tIH(base)
DC100
275
900
200
780
120
560
-
-
ps
ps
b,16
28
Control & Address Input pulse width for each input
Calibration Timing
tIPW
620
-
-
-
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
nCK
nCK
nCK
23
- 38 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
[ Table 23 ] Timing Parameters by Speed Bin
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Reset Timing
max(5nCK,
tRFC +
max(5nCK,
tRFC +
max(5nCK,
tRFC +
max(5nCK,
tRFC +
Exit Reset from CKE HIGH to a valid command
tXPR
-
-
-
-
10ns)
10ns)
10ns)
10ns)
Self Refresh Timing
max(5nCK,t
RFC +
10ns)
max(5nCK,t
RFC +
10ns)
max(5nCK,t
RFC +
10ns)
Exit Self Refresh to commands not requiring a locked
DLL
max(5nCK,t
RFC + 10ns)
tXS
-
-
-
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tCKESR
tDLLK(min)
-
-
tDLLK(min)
-
-
tDLLK(min)
-
-
tDLLK(min)
-
-
nCK
Minimum CKE low width for Self refresh entry to exit
timing
tCKE(min)+
1tCK
tCKE(min)+
1tCK
tCKE(min)+
1tCK
tCKE(min) +
1tCK
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
tCKSRE
tCKSRX
-
-
-
-
-
-
-
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
(3nCK,
7.5ns)
max
(3nCK,
7.5ns)
max
(3nCK,6ns)
max
(3nCK,6ns)
tXP
tXPDLL
tCKE
-
-
-
-
-
-
-
-
-
-
-
-
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
2
max
(3nCK,
7.5ns)
max
(3nCK,
5.625ns)
max
(3nCK,
5.625ns)
max
(3nCK,5ns)
CKE minimum pulse width
Command pass disable delay
tCPDED
tPD
1
-
1
-
1
-
1
-
nCK
tCK(avg)
nCK
Power Down Entry to Exit Timing
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
15
20
20
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
nCK
RL + 4 +1
RL + 4 +1
RL + 4 +1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRAPDEN
tWRPDEN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
9
10
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4 +WR
+1
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
WL +2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
tWRAPDEN
tREFPDEN
10
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
1
-
-
1
-
-
1
-
-
1
-
-
20,21
tMRSPDEN tMOD(min)
tMOD(min)
tMOD(min)
tMOD(min)
ODT high time without write command or with write
command and BC4
ODTH4
ODTH8
tAONPD
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
nCK
nCK
ns
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
8.5
8.5
8.5
8.5
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
tAOFPD
tAON
2
8.5
400
0.7
0.7
2
8.5
300
0.7
0.7
2
8.5
250
0.7
0.7
2
8.5
225
0.7
0.7
ns
RTT turn-on
-400
0.3
0.3
-300
0.3
0.3
-250
0.3
0.3
-225
0.3
0.3
ps
7,f
8,f
f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
tCK(avg)
tCK(avg)
RTT dynamic change skew
tADC
Write Leveling Timing
First DQS/DQS rising edge after write leveling mode
is programmed
tWLMRD
tWLDQSEN
tWLS
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
tCK(avg)
tCK(avg)
ps
3
3
DQS/DQS delay after write leveling mode is pro-
grammed
Write leveling setup time from rising CK, CK crossing
to rising DQS, DQS crossing
325
325
245
245
195
195
165
165
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
ps
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
0
0
9
2
0
0
7.5
2
ns
ns
tWLOE
- 39 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
18.1 Jitter Notes
Specific Note a
Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the
input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition
edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS, DQS) crossing to its respective clock signal (CK, CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d
Specific Note e
These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal
(DQS, DQS) crossing.
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-
mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input
clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and
tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800
derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution
on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)
- 40 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
18.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions see "Device Operation & Timing Diagram Datasheet".
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by 18.1-Jitter Notes on page 40
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
(DC) = V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See "Address/Command Setup, Hold and Derating" on component datasheet.
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
(DC)= V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See "Data Setup, Hold and Slew Rate Derating" on component datasheet.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Data-
sheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
~
~
= 0.133
128ms
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
(DC) and the consecutive crossing of V
(DC)
REF
REF
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
- 41 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
19. Physical Dimensions :
19.1 256Mbx16 based 256Mx64 Module (1 Rank) - M471B5674QH0
Units : Millimeters
67.60 ± 0.13
63.60
Max 2.2
1.00 ± 0.10
A
B
39.00
21.00
0.60
0.45 ± 0.03
1.65
4.00 ± 0.10
2.55
0.25 MAX
1.00 ± 0.10
Detail A
Detail B
The used device is 256M x16 DDR3L SDRAM, BOC.
DDR3 SDRAM Part NO : K4B4G1646Q - HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 42 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
19.2 512Mbx8 based 512Mx64 Module (1 Rank) - M471B5173QH0
Units : Millimeters
67.60 ± 0.13
63.60
Max 3.8
1.00 ± 0.10
A
B
39.00
21.00
0.60
0.45 ± 0.03
1.65
4.00 ± 0.10
2.55
0.25 MAX
1.00 ± 0.10
Detail A
Detail B
The used device is 512M x8 DDR3L SDRAM, BOC.
DDR3 SDRAM Part NO : K4B4G0846Q - HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 43 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
19.3 512Mbx8 based 1Gx64 Module (2 Ranks) - M471B1G73QH0
Units : Millimeters
67.60 ± 0.13
63.60
Max 3.8
1.00 ± 0.10
A
B
39.00
21.00
0.60
1.65
0.45 ± 0.03
4.00 ± 0.10
2.55
1.00 ± 0.10
0.25 MAX
Detail A
Detail B
The used device is 512M x8 DDR3L SDRAM, BOC.
DDR3 SDRAM Part NO : K4B4G0846Q - HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 44 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
19.4 512Mbx8 based 512Mx72 Module (1 Rank) - M474B5173QH0
Units : Millimeters
67.60 ± 0.13
63.60
Max 3.8
1.00 ± 0.10
A
B
39.00
21.00
SPD
0.60
0.45 ± 0.03
1.65
4.00 ± 0.10
2.55
0.25 MAX
1.00 ± 0.10
Detail A
Detail B
The used device is 512M x8 DDR3L SDRAM, BOC.
DDR3 SDRAM Part NO : K4B4G0846Q - HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 45 -
Rev. 1.21
Unbuffered SODIMM
datasheet
DDR3L SDRAM
19.5 512Mbx8 based 1Gx72 Module (2 Ranks) - M474B1G73QH0
Units : Millimeters
67.60 ± 0.13
63.60
Max 3.8
1.00 ± 0.10
A
B
39.00
21.00
0.60
1.65
0.45 ± 0.03
4.00 ± 0.10
2.55
1.00 ± 0.10
0.25 MAX
Detail A
Detail B
The used device is 512M x8 DDR3L SDRAM, BOC.
DDR3 SDRAM Part NO : K4B4G0846Q - HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 46 -
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