M470T5669AZ0-CCC [SAMSUNG]
DDR DRAM Module, 256MX64, 0.6ns, CMOS, ROHS COMPLIANT, SODIMM-200;
| 型号： | M470T5669AZ0-CCC |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 256MX64, 0.6ns, CMOS, ROHS COMPLIANT, SODIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总23页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SODIMM
DDR2 SDRAM
DDR2 Unbuffered SODIMM
200pin Unbuffered SODIMM based on 1Gb A-die
64-bit Non-ECC
68FBGA & 84FBGA with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 March 2007
1 of 20
SODIMM
DDR2 SDRAM
Table of Contents
1.0 DDR2 Unbuffered DIMM Ordering Information ......................................................................... 4
2.0 Features ........................................................................................................................................ 4
3.0 Address Configuration ................................................................................................................ 4
4.0 Pin Configurations (Front side/Back side) ................................................................................ 5
5.0 Pin Description ............................................................................................................................ 5
6.0 Input/Output Function Description ............................................................................................ 6
7.0 Functional Block Diagram : ........................................................................................................ 7
7.1 1GB, 128Mx64 Module - M470T2864AZ3 .......................................................................................... 7
7.2 512MB, 64Mx64 Module - M470T6464AZ3 ........................................................................................ 8
7.3 2GB, 256Mx64 Module - M470T5669AZ0 .......................................................................................... 9
8.0 Absolute Maximum DC Ratings ................................................................................................ 10
9.0 AC & DC Operating Conditions ................................................................................................ 10
9.1 Recommended DC Operating Conditions (SSTL - 1.8) ..................................................................... 10
9.2 Operating Temperature Condition ................................................................................................ 11
9.3 Input DC Logic Level .................................................................................................................. 11
9.4 Input AC Logic Level .................................................................................................................. 11
9.5 AC Input Test Conditions ............................................................................................................ 11
10.0 IDD Specification Parameters Definition ............................................................................... 12
11.0 Operating Current Table ......................................................................................................... 13
........................................................................................ 13
11.1 M470T2864AZ3 : 128Mx64 1GB Module
11.2 M470T6464AZ3: 64Mx64 512MB Module ..................................................................................... 13
11.3 M470T5669AZ0: 256Mx64 1GB Module ....................................................................................... 14
12.0 Input/Output Capacitance ....................................................................................................... 15
13.0 Electrical Characteristics & AC Timing for DDR2-667/533/400 ............................................ 15
13.1 Refresh Parameters by Device Density ...................................................................................... 15
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ........................................... 15
13.3 Timing Parameters by Speed Grade .......................................................................................... 16
14.0 Physical Dimensions : ............................................................................................................. 18
14.1 64Mbx16 based 128Mx64 Module (2 Rank) - M470T2864AZ3 ......................................................... 18
14.2 64Mbx16 based 64Mx64 Module (1 Rank) - M470T6464AZ3 ........................................................... 19
14.3 st.256Mbx8 based 256Mx64 Module (2 Ranks) - M470T5669AZ0 .................................................... 20
Rev. 1.4 March 2007
2 of 20
SODIMM
DDR2 SDRAM
Revision History
Revision
Month
Year
2005
2005
2006
2006
2007
History
1.0
July
- Initial Release
1.1
1.2
August
March
- Revised IDD Current Values
- Revised Physical Dimensions for 2GB
- Added the VddSPD values
- Corrected the physical dimension
1.3
1.4
September
March
Rev. 1.4 March 2007
3 of 20
SODIMM
DDR2 SDRAM
1.0 DDR2 Unbuffered DIMM Ordering Information
Part Number
Density
512MB
1GB
Organization
64Mx64
Component Composition
Number of Rank
Height
30mm
30mm
30mm
M470T6464AZ3-C(L)E6/D5/CC
M470T2864AZ3-C(L)E6/D5/CC
M470T5669AZ0-C(L)E6/D5/CC
64Mx16 (K4T1G164QA-C(L)E6/D5/CC)*4
64Mx16 (K4T1G164QA-C(L)E6/D5/CC)*8
st.256Mx8 (K4T2G074QA-C(L)E6/D5/CC)*8
1
2
2
128Mx64
256Mx64
2GB
Note :
1. “Z” of Part number(11th digit) stand for Lead-free products.
2. “3” of Part number(12th digit) stand for Dummy Pad PCB products.
2.0 Features
• Performance range
E6 (DDR2-667)
D5 (DDR2-533)
CC (DDR2-400)
Unit
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
400
533
400
400
-
667
533
5-5-5
4-4-4
3-3-3
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- support High Temperature Self-Refresh rate enable feature
• Package: 84ball FBGA - 64Mx16, 70ball FBGA - st.256Mx8
• All of Lead-free products are compliant for RoHS
Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization
Row Address
A0-A13
Column Address
A0-A9
Bank Address
BA0-BA2
Auto Precharge
128Mx8(1Gb) based Module
64Mx16(1Gb) based Module
A10
A10
A0-A12
A0-A9
BA0-BA2
Rev. 1.4 March 2007
4 of 20
SODIMM
DDR2 SDRAM
4.0 Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
101
Front
A1
Pin
102
Back
A0
Pin
151
Front
DQ42
Pin
152
Back
DQ46
1
VREF
2
VSS
51
DQS2
52
DM2
3
5
7
9
11
VSS
DQ0
DQ1
VSS
4
6
8
10
12
DQ4
DQ5
VSS
DM0
VSS
53
55
57
59
61
VSS
DQ18
DQ19
VSS
54
56
58
60
62
VSS
DQ22
DQ23
VSS
103
105
107
109
111
VDD
A10/AP
BA0
WE
VDD
104
106
108
110
112
VDD
BA1
RAS
S0
153
155
157
159
161
DQ43
VSS
DQ48
DQ49
VSS
154
156
158
160
162
DQ47
VSS
DQ52
DQ53
VSS
DQS0
DQ24
DQ28
VDD
13
15
17
DQS0
VSS
DQ2
14
16
18
DQ6
DQ7
VSS
63
65
67
DQ25
VSS
DM3
64
66
68
DQ29
VSS
DQS3
113
115
117
CAS
NC/S1
VDD
114
116
118
ODT0
A13
VDD
163 NC, TEST 164
CK1
CK1
VSS
165
167
VSS
DQS6
166
168
19
21
23
DQ3
VSS
DQ8
20
22
24
DQ12
DQ13
VSS
69
71
73
NC
VSS
DQ26
70
72
74
DQS3
VSS
DQ30
119 NC/ODT1 120
NC
VSS
DQ36
169
171
173
DQS6
VSS
DQ50
170
172
174
DM6
VSS
DQ54
121
123
VSS
DQ32
122
124
25
27
DQ9
VSS
26
28
DM1
VSS
75
77
DQ27
VSS
76
78
DQ31
VSS
125
127
DQ33
VSS
126
128
DQ37
VSS
175
177
DQ51
VSS
176
178
DQ55
VSS
29
31
33
DQS1
DQS1
VSS
30
32
34
CK0
CK0
VSS
79
81
83
CKE0
VDD
NC
80 NC/CKE1 129
DQS4
DQS4
VSS
130
132
134
DM4
VSS
DQ38
179
181
183
DQ56
DQ57
VSS
180
182
184
DQ60
DQ61
VSS
82
84
VDD
NC
131
133
35
37
DQ10
DQ11
36
38
DQ14
DQ15
85
87
BA2
VDD
86
88
NC
VDD
135
137
DQ34
DQ35
136
138
DQ39
VSS
185
187
DM7
VSS
186
188
DQS7
DQS7
39
41
43
45
47
49
VSS
VSS
DQ16
DQ17
VSS
40
42
44
46
48
50
VSS
VSS
DQ20
DQ21
VSS
89
91
93
95
97
99
A12
A9
A8
VDD
A5
A3
90
92
94
96
98
A11
A7
A6
VDD
A4
A2
139
141
143
145
147
149
VSS
DQ40
DQ41
VSS
DM5
VSS
140
142
144
146
148
150
DQ44
DQ45
VSS
DQS5
DQS5
VSS
189
191
193
195
197
DQ58
DQ59
VSS
SDA
SCL
190
192
194
196
198
VSS
DQ62
DQ63
VSS
SA0
SA1
DQS2
NC
100
199 VDDSPD 200
Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.
5.0 Pin Description
Pin Name
Description
Clock Inputs, positive line
Pin Name
SDA
Description
SPD Data Input/Output
CK0,CK1
CK0,CK1
CKE0,CKE1
RAS
Clock Inputs, negative line
Clock Enables
SA1,SA0
SPD address
DQ0~DQ63
DM0~DM7
DQS0~DQS7
DQS0~DQS7
Data Input/Output
Data Masks
Row Address Strobe
Column Address Strobe
Write Enable
CAS
Data strobes
WE
Data strobes complement
Logic Analyzer specific test pin
(No connect on So-DIMM)
S0,S1
Chip Selects
TEST
VDD
A0~A9, A11~A13 Address Inputs
Core and I/O Power
Ground
VSS
A10/AP
Address Input/Autoprecharge
VREF
VDDSPD
BA0~BA2
SDRAM Bank Address
Input/Output Reference
ODT0,ODT1
SCL
On-die termination control
SPD Power
Serial Presence Detect(SPD) Clock Input
Clock Inputs, positive line
NC
Spare pins, No connect
SPD Data Input/Output
CK0,CK1
SDA
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.4 March 2007
5 of 20
SODIMM
DDR2 SDRAM
6.0 Input/Output Function Description
Symbol
Type
Description
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge
of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output
timing for read operations is synchronized to the input clock.
CK0-CK1
CK0-CK1
Input
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating
the clocks, CKE low initiates the Power Down mode or the Self Refesh mode.
CKE0-CKE1
S0-S1
Input
Input
Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but previous operations
continue. Rank 0 is selected by S0, Rank 1 is selected by S1. Ranks are also called “Physical banks”.
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE
define the operation to be executed by the SDRAM.
RAS, CAS, WE
BA0~BA2
Input
Input
Input
Selects which DDR2 SDRAM internal bank is activated.
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended
Mode Register Set (EMRS).
ODT0~ODT1
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the
rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column
address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the
column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If
AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, auto-
precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to con-
trol which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA0-
BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
A0~A9,
A10/AP,
A11~A13
Input
DQ0~DQ63
DM0~DM7
In/Out
Input
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high. In
Read mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read mode,
the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data
window. DQS signals are complements, and timing is relative to the crosspoint of respective
DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals
must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately.
DQS0~DQS7
DQS0~DQS7
In/Out
V
DD,VDD SPD,VSS
SDA
Supply
In/Out
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be con-
nected to VDD to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL
to VDD to act as a pull up.
SCL
SA0~SA1
TEST
Input
Input
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-
DIMMs).
In/Out
Rev. 1.4 March 2007
6 of 20
SODIMM
DDR2 SDRAM
7.0 Functional Block Diagram :
7.1 1GB, 128Mx64 Module - M470T2864AZ3
(Populated as 2 rank of x16 DDR2 SDRAMs)
3Ω + 5%
ODT1
ODT0
CKE1
CKE0
S1
S0
CS
CS
CS
CS
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
DQS0
DQS4
DQS4
DM4
LDQS
LDQS
LDM
LDQS
LDQS
LDM
LDQS
LDQS
LDM
LDQS
LDQS
LDM
DQS0
DM0
DQ0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D4
D2
D6
DQS1
DQS1
DM1
DQS5
DQS5
DM5
UDQS
UDQS
UDM
UDQS
UDQS
UDM
UDQS
UDQS
UDM
UDQS
UDQS
UDM
DQ8
I/O 8
I/O 8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
CS
CS
CS
CS
DQS2
DQS2
DM2
DQS6
DQS6
DM6
LDQS
LDQS
LDM
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
LDQS
LDQS
LDM
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D5
D3
D7
DQS3
DQS3
DM3
DQS7
DQS7
DM7
UDQS
UDQS
UDM
UDQS
UDQS
UDM
UDQS
UDQS
UDM
UDQS
UDQS
UDM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
I/O 8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 8
I/O 9
I/O 9
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
3Ω + 5%
BA0 - BA2
A0 - A13
RAS
DDR2 SDRAMs D0 - D7
DDR2 SDRAMs D0 - D7
DDR2 SDRAMs D0 - D7
DDR2 SDRAMs D0 - D7
DDR2 SDRAMs D0 - D7
SCL
SA0
SA1
SCL
A0
A1
SPD
WP
SDA
A2
CAS
WE
* Clock Wiring
Clock Input DDR2 SDRAMs
V
V
V
V
SPD
Serial PD
DD
*CK0/CK0 4 DDR2 SDRAMs
*CK1/CK1 4 DDR2 SDRAMs
DDR2 SDRAMs D0 - D7
REF
DD
DDR2 SDRAMs D0 - D7, V and V
DD
Q
DD
* Wire per Clock Loading
Table/Wiring Diagrams
DDR2 SDRAMs D0 - D7, SPD
SS
Note :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms ± 5%.
Rev. 1.4 March 2007
7 of 20
SODIMM
DDR2 SDRAM
7.2 512MB, 64Mx64 Module - M470T6464AZ3
(Populated as 1 rank of x16 DDR2 SDRAMs)
3Ω + 5%
CKE0
ODT0
S0
CS
CS
O
D
T
C
K
E
O
D
T
C
K
E
DQS0
DQS4
DQS4
DM4
LDQS
LDQS
LDM
LDQS
LDQS
LDM
DQS0
DM0
DQ0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D2
DQS1
DQS1
DM1
DQS5
DQS5
DM5
UDQS
UDQS
UDM
UDQS
UDQS
UDM
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
O
D
T
C
K
E
CS
O
D
T
C
K
E
DQS2
DQS2
DM2
LDQS
LDQS
LDM
DQS6
DQS6
DM6
LDQS
LDQS
LDM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D3
DQS3
DQS3
DM3
UDQS
UDQS
UDM
DQS7
DQS7
DM7
UDQS
UDQS
UDM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
3Ω + 5%
SCL
SA0
SA1
SCL
A0
A1
A2
BA0 - BA2
A0 - A13
RAS
DDR2 SDRAMs D0 - D3
DDR2 SDRAMs D0 - D3
DDR2 SDRAMs D0 - D3
DDR2 SDRAMs D0 - D3
DDR2 SDRAMs D0 - D3
SPD
WP
SDA
CAS
WE
* Clock Wiring
Clock Input DDR2 SDRAMs
V
V
V
V
SPD
Serial PD
DD
DDR2 SDRAMs D0 - D3
REF
DD
SS
*CK0/CK0 2 DDR2 SDRAMs
*CK1/CK1 2 DDR2 SDRAMs
DDR2 SDRAMs D0 - D3, V and V
DD
Q
DD
* Wire per Clock Loading
Table/Wiring Diagrams
DDR2 SDRAMs D0 - D3, SPD
Note :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms ± 5%.
Rev. 1.4 March 2007
8 of 20
SODIMM
DDR2 SDRAM
7.3 2GB, 256Mx64 Module - M470T5669AZ0
(Populated as 2 ranks of x8 DDR2 SDRAMs)
3Ω + 5%
CKE1
ODT1
S1
CKE0
ODT0
S0
CS0
CS1
CS0
CS1
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
DQS0
DQS4
DQS4
DM4
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS0
DM0
DQ0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D8
D4
D12
DQS1
DQS1
DM1
DQS5
DQS5
DM5
CS0
CS1
CS0
CS1
DQS
DQS
DM
O
D
T
0
C
K
E
0
DQS
DQS
DM
O
D
T
1
C
K
E
1
DQS
DQS
DM
O
D
T
0
C
K
E
0
DQS
DQS
DM
O
D
T
1
C
K
E
1
DQ8
I/O 8
I/O 8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
I/O 9
I/O 9
D1
D9
D5
D13
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS0
CS1
CS0
CS1
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D10
D6
D14
CS0
CS1
CS0
CS1
DQS3
DQS3
DM3
DQS
DQS
DM
O
D
T
0
C
K
E
0
DQS
DQS
DM
O
D
T
1
C
K
E
1
DQS7
DQS7
DM7
DQS
DQS
DM
O
D
T
0
C
K
E
0
DQS
DQS
DM
O
D
T
1
C
K
E
1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
I/O 8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 8
I/O 9
I/O 9
I/O 9
I/O 9
D3
D11
D7
D15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
10Ω + 5%
* Clock Wiring
Clock Input DDR2 SDRAMs
BA0 - BA2
A0 - A13
RAS
DDR2 SDRAMs D0 - D15
DDR2 SDRAMs D0 - D15
DDR2 SDRAMs D0 - D15
DDR2 SDRAMs D0 - D15
DDR2 SDRAMs D0 - D15
SCL
SA0
SA1
SCL
A0
SPD
A1
SDA
*CK0/CK0 8 DDR2 SDRAMs
*CK1/CK1 8 DDR2 SDRAMs
A2
WP
CAS
* Wire per Clock Loading
Table/Wiring Diagrams
WE
V
V
V
V
SPD
Serial PD
DD
Note :
DDR2 SDRAMs D0 - D15
REF
DD
SS
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 10.0 Ohms ± 5%.
DDR2 SDRAMs D0 - D15, V and V
DD
Q
DD
DDR2 SDRAMs D0 - D15, SPD
Rev. 1.4 March 2007
9 of 20
SODIMM
DDR2 SDRAM
8.0 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on VDD pin relative to VSS
VDD
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VDDQ
VDDL
V
V
1
V
IN, VOUT
TSTG
Note :
V
1
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
9.0 AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Typ.
1.8
Symbol
Parameter
Units
Notes
Min.
1.7
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
Supply Voltage
V
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
1.7
1.8
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Rating
Symbol
Parameter
Core Supply Voltage
Units
Notes
Min.
1.7
Max.
3.6
VDDSPD
V
5
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD
.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
5. SO-DIMMs that include an optional temperature sensor may require a restricted VDDSPD operating voltage range for proper operation of the temperature
sensor. Refer to the thermal sensor specification for details regarding the supported voltage range. All other functions of the SO-DIMM SPD are
supported across the full VDDSPD range.
Rev. 1.4 March 2007
10 of 20
SODIMM
DDR2 SDRAM
9.2 Operating Temperature Condition
Symbol
TOPER
Parameter
Operating Temperature
Rating
0 to 95
Units
°C
Notes
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
9.3 Input DC Logic Level
Symbol
IH(DC)
Parameter
DC input logic high
Min.
VREF + 0.125
Max.
VDDQ + 0.3
Units
V
Notes
V
VIL(DC)
DC input logic low
- 0.3
VREF - 0.125
V
9.4 Input AC Logic Level
DDR2-400, DDR2-533
DDR2-667
Min.
VREF + 0.200
Symbol
Parameter
Units
Min.
Max.
Max.
VIH(AC)
VIL(AC)
AC input logic high
AC input logic low
VREF + 0.250
-
V
V
-
VREF - 0.250
VREF - 0.200
9.5 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
VSWING(MAX)
SLEW
Input reference voltage
0.5 * VDDQ
1.0
V
V
1
1
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
V/ns
2, 3
Note :
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
(DC) min
IH
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
Rising Slew =
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.4 March 2007
11 of 20
SODIMM
DDR2 SDRAM
10.0 IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Units
Note
t
t
t
t
t
t
IDD0
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
IDD1
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
mA
mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
mA
RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
Rev. 1.4 March 2007
12 of 20
SODIMM
DDR2 SDRAM
11.0 Operating Current Table :
(TA=0oC, VDD= 1.9V)
11.1 M470T2864AZ3 : 128Mx64 1GB Module
667@CL=5
533@CL=4
400@CL=3
Symbol
Unit
Notes
CE6
LE6
CD5
LD5
CCC
LCC
IDD0
IDD1
660
740
620
700
580
660
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
120
64
120
64
120
64
360
360
320
144
440
960
980
1,060
360
360
280
144
440
860
860
1,040
320
320
280
144
400
740
720
1,000
IDD6
120
48
120
48
120
48
IDD7
1,580
1,540
1,480
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.2 M470T6464AZ3: 64Mx64 512MB Module
(TA=0oC, VDD= 1.9V)
Unit Notes
667@CL=5
533@CL=4
400@CL=3
Symbol
CE6
LE6
CD5
LD5
CCC
LCC
IDD0
IDD1
480
560
440
520
420
500
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
60
32
60
32
60
32
180
180
160
72
260
780
800
880
180
180
140
72
260
680
680
860
160
160
140
72
240
580
560
840
IDD6
IDD7
60
24
60
24
60
24
1,400
1,360
1,320
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.4 March 2007
13 of 20
SODIMM
DDR2 SDRAM
(TA=0oC, VDD= 1.9V)
11.3 M470T5669AZ0: 256Mx64 1GB Module
667@CL=5
533@CL=4
400@CL=3
Symbol
Unit
Notes
CE6
LE6
CD5
LD5
CCC
LCC
IDD0
IDD1
1,080
1,160
1,040
1,120
1,000
1,080
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
240
128
240
128
240
128
720
720
720
720
640
640
640
560
560
288
288
288
840
840
760
1,600
1,600
2,120
1,400
1,400
2,080
1,240
1,240
2,000
IDD6
240
96
240
96
240
96
IDD7
2,760
2,600
2,400
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.4 March 2007
14 of 20
SODIMM
DDR2 SDRAM
(VDD=1.8V, VDDQ=1.8V, TA=25oC)
12.0 Input/Output Capacitance
Parameter
Non-ECC
Min
Max
Min
Max
Min
Max
Symbol
Units
M470T2864AZ3
M470T6464AZ3
M470T5669AZ0
Input capacitance, CK and CK
Input capacitance, CKE , CS, Addr, RAS, CAS, WE
CCK
CI
-
-
-
-
32
34
10
9
-
-
-
-
24
34
6
-
-
-
-
48
42
10
9
pF
CIO(400/533)
CIO(667)
Input/output capacitance, DQ, DM, DQS, DQS
5.5
* DM is internally loaded to match DQ and DQS identically.
13.0 Electrical Characteristics & AC Timing for DDR2-667/533/400
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
Parameter
Refresh to active/Refresh command time
Symbol
256Mb
75
512Mb
105
1Gb
127.5
7.8
2Gb
195
7.8
4Gb
327.5
7.8
Units
ns
tRFC
tREFI
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
7.8
7.8
µs
Average periodic refresh interval
3.9
3.9
3.9
3.9
3.9
µs
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-667(E6)
5 - 5 - 5
DDR2-533(D5)
4 - 4 - 4
DDR2-400(CC)
3 - 3 - 3
Units
min
max
min
max
min
max
5
3.75
3
8
5
3.75
3.75
15
8
5
5
8
ns
ns
ns
ns
ns
ns
ns
8
8
8
8
8
-
-
15
15
54
39
-
-
15
15
55
40
-
tRP
-
-
15
-
-
-
-
tRC
55
tRAS
70000
40
70000
70000
Rev. 1.4 March 2007
15 of 20
SODIMM
DDR2 SDRAM
13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-667
DDR2-533
min
-500
-450
0.45
0.45
DDR2-400
Parameter
Symbol
Units Note
min
-450
-400
0.45
0.45
max
+450
+400
0.55
0.55
max
+500
+450
0.55
0.55
min
-600
-500
0.45
0.45
max
+600
+500
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
x
x
x
ps
Clock cycle time, CL=x
tCK
3000
175
8000
3750
225
8000
5000
275
8000
ps
ps
ps
DQ and DM input hold time
DQ and DM input setup time
tDH(base)
tDS(base)
x
x
x
x
x
x
100
100
150
Control & Address input pulse width for
each input
tIPW
0.6
x
0.6
x
0.6
x
tCK
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK/CK tHZ
0.35
x
x
0.35
x
x
0.35
x
x
tCK
ps
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tLZ(DQS)
tAC min
2*tACmin
tAC min
2* tACmin
tAC min
2* tACmin
ps
tLZ(DQ)
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
x
240
x
300
x
350
ps
DQ hold skew factor
tQHS
tQH
x
340
x
x
400
x
x
450
x
ps
ps
DQ/DQS output hold time from DQS
tHP - tQHS
tHP - tQHS
tHP - tQHS
First DQS latching transition to associated
clock edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
x
x
x
tDSH
x
x
x
tMRD
x
x
x
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
0.4
0.35
275
200
0.9
0.4
0.6
x
0.4
0.35
375
250
0.9
0.4
0.6
x
0.4
0.35
475
350
0.9
0.4
0.6
x
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
x
x
x
x
x
x
ps
1.1
0.6
1.1
0.6
1.1
0.6
tCK
tCK
Read postamble
Active to active command period for 1KB
page size products
tRRD
tRRD
tFAW
tFAW
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
ns
ns
ns
ns
Active to active command period for 2KB
page size products
Four Activate Window for 1KB page size
products
37.5
50
37.5
50
37.5
50
Four Activate Window for 2KB page size
products
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
2
2
tCK
ns
15
x
x
x
15
x
x
x
15
x
x
x
Auto precharge write recovery + precharge
time
tDAL
WR+tRP
WR+tRP
WR+tRP
tCK
Internal write to read command delay
tWTR
7.5
7.5
7.5
7.5
10
7.5
ns
ns
Internal read to precharge command delay tRTP
Exit self refresh to a non-read command
Exit self refresh to a read command
tXSNR
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
ns
tXSRD
tCK
Exit precharge power down to any non-
read command
tXP
2
x
2
x
2
x
tCK
Rev. 1.4 March 2007
16 of 20
SODIMM
DDR2 SDRAM
DDR2-667
DDR2-533
DDR2-400
Parameter
Symbol
Units Note
min
max
min
max
min
max
Exit active power down to read command tXARD
2
x
2
x
2
x
tCK
tCK
Exit active power down to read command
tXARDS
7 - AL
6 - AL
6 - AL
(slow exit, lower power)
CKE minimum pulse width
tCKE
3
2
3
2
3
2
tCK
tCK
ns
(high and low pulse width)
tAOND
tAON
ODT turn-on delay
2
2
2
tAC(max)+
0.7
tAC(max)+
1
ODT turn-on
tAC(min)
tAC(min)
tAC(min) tAC(max)+1
2tCK+tAC(
max)+1
2tCK+tAC(
max)+1
2tCK+tAC
tAC(min)+2
tAONPD
tAOFD
tAOF
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
(max)+1
2.5
2.5
2.5
2.5
tAC(max)+
0.6
tAC(max)+
0.6
tAC(max)+
0.6
ODT turn-off
tAC(min)
tAC(min)
tAC(min)
2.5tCK+
2.5tCK+tAC
(max)+1
2.5tCK+
tAC(max)+1
tAOFPD
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2 tAC(max)+ tAC(min)+2
1
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
Minimum time clocks remains ON after
CKE asynchronously drops LOW
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tDelay
ns
Rev. 1.4 March 2007
17 of 20
SODIMM
DDR2 SDRAM
14.0 Physical Dimensions :
14.1 64Mbx16 based 128Mx64 Module (2 Rank)
- M470T2864AZ3
Units : Millimeters
3.8 mm
max
67.60 mm
2.00
a
b
199
200
1
2
1.1mm
max
11.40
16.25
47.40
63.00
a
67.60 mm
DETAIL a
DETAIL b
BACK SIDE
FRONT SIDE
4.00 ± 0.10
4.20
1.0 ± 0.05
1.50 ± 0.10
2.70 ± 0.10
1.80 ± 0.10
2.40 ± 0.10
0.60
1.0 ± 0.05
4.20
4.00 ± 0.10
0.45 ± 0.03
The used device is 64M x16 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G164QA
Rev. 1.4 March 2007
18 of 20
SODIMM
DDR2 SDRAM
14.2 64Mbx16 based 64Mx64 Module (1 Rank)
- M470T6464AZ3
Units : Millimeters
3.8 mm
max
67.60 mm
2.00
a
b
199
200
1
2
1.1mm
max
11.40
16.25
47.40
63.00
a
67.60 mm
DETAIL a
DETAIL b
BACK SIDE
FRONT SIDE
4.00 ± 0.10
4.20
1.0 ± 0.05
1.50 ± 0.10
2.70 ± 0.10
1.80 ± 0.10
2.40 ± 0.10
0.60
1.0 ± 0.05
4.20
4.00 ± 0.10
0.45 ± 0.03
The used device is 64M x16 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G164QA
Rev. 1.4 March 2007
19 of 20
SODIMM
DDR2 SDRAM
14.3 st.256Mbx8 based 256Mx64 Module (2 Ranks)
- M470T5669AZ0
Units : Millimeters
3.8 mm
max
67.60 mm
2.00
199
1
a
b
11.40
16.25
47.40
1.1mm
max
63.00
2
200
a
67.60 mm
DETAIL a
DETAIL b
BACK SIDE
FRONT SIDE
4.00 ± 0.10
4.20
1.0 ± 0.05
1.50 ± 0.10
2.70 ± 0.10
1.80 ± 0.10
2.40 ± 0.10
0.60
1.0 ± 0.05
4.20
4.00 ± 0.10
0.45 ± 0.03
The used device is st.256M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T2G074QA
Rev. 1.4 March 2007
20 of 20
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http://www.samsung.com/ privacy legal sitemap contact us
Copyright© 2007 SAMSUNG. All right
part number
M470T5669AZ0-CD5
M470T5669AZ0-CE6
Density of Comp.
Organization of Comp.
Number Of Comp.
Part Number of Comp.
1G
1G
x8 Stack(70-mono)
x8 Stack(70-mono)
K4T1GA84QA-ZCD5000
8
K4T1GA84QA-ZCE6000
8
production & availability
part number
M470T5669AZ0-CD5
M470T5669AZ0-CE6
life cycle
PRODUCTION
PRODUCTION
die revision
MASS PRODUCTION
MASS PRODUCTION
MOQ (small box)
MOQ (large box)
qual sample
150
150
450
450
Q1/2006
Q1/2006
N/A
Q1/2006
Q1/2006
N/A
mass production
last time buy
last time ship
N/A
N/A
replacement part number
Technical File Download
- specification data
file
rev #
size
21KB
updated date
SPD
(CE6,CD5,CCC)
2007/08/13
2007/08/13
2007/08/13
Data Sheet
1.4
396KB
19KB
SPD
(LE6,LD5,LCC)
- simulation models
file
rev #
size
updated date
Electrical Board Description
214KB
2007/08/13
RoHS information
For more information, please click the button next to the product name.
material declaration sheet
declaration letter
does not contain hazardous materials defined in China RoHS
contains hazardous materials defined in China RoHS
is Lead-free and RoHS-compliant.
M470T5669AZ0-CD5
M470T5669AZ0-CE6
is Lead-free and RoHS-compliant.
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