M393T5660MZ3-CD5 [SAMSUNG]
DDR DRAM Module, 256MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240;![M393T5660MZ3-CD5](http://pdffile.icpdf.com/pdf2/p00237/img/icpdf/M393T5660MZ3_1390169_icpdf.jpg)
型号: | M393T5660MZ3-CD5 |
厂家: | ![]() |
描述: | DDR DRAM Module, 256MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240 时钟 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总16页 (文件大小:354K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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2GB, 4GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 1Gb M-die
72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered DIMM Ordering Information
Part Number
Density
Organization
Component Composition
256Mx4(K4T1G044QM)*18EA
256Mx4(K4T1G044QM)*18EA
st.512Mx4(K4T2G064QM)*18EA
Number of Rank
Height
30mm
30mm
30mm
M393T5660MZ3-CD5/CC
M393T5660MZ0-CD5/CC
M393T5168MZ0-CD5/CC
2GB
256Mx72
1
1
2
2GB
256Mx72
4GB
512Mx72
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Features
• Performance range
D5(DDR2-533)
CC(DDR2-400)
Unit
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
-
400
400
-
Mbps
Mbps
Mbps
CK
4-4-4
3-3-3
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/pin
CK
CK
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than T
• Serial presence detect with EEPROM
85°C, 3.9us at 85°C < T
< 95°C
CASE
CASE
• DDR2 SDRAM Package: 68ball FBGA - 256Mx4, 56ball BGA - st.512Mbx4
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
A10
256Mx4(1Gb) based Module
A0-A13
A0-A9,A11
BA0-BA2
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Pin Configurations (Front side/Back side)
Pin
1
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Pin
61
62
63
64
Front
Pin
181
182
183
184
Back
Pin
91
92
93
94
95
96
97
98
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
V
V
V
V
V
V
DQ19
A4
DM5/DQS14
NC/DQS14
REF
SS
SS
DDQ
SS
V
V
2
3
4
5
6
7
8
9
DQ4
DQ5
V
DQ28
DQ29
A3
A1
DQS5
DQS5
SS
SS
DDQ
V
DQ0
DQ1
V
DQ24
DQ25
A2
SS
V
V
V
V
DQ46
DQ47
SS
SS
DD
DD
SS
V
DM0/DQS9
NC/DQS9
DM3/DQS12
NC/DQS12
KEY
DQ42
DQ43
SS
SS
V
V
DQS0
DQS0
V
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0
SS
SS
V
V
V
V
DQ52
DQ53
SS
SS
SS
SS
V
V
V
DQ6
DQ7
V
DQ30
DQ31
DQ48
DQ49
SS
SS
DD
DD
V
DQ2
DQ3
V
DQ26
DQ27
NC/Par_In
A0
99
SS
V
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
RFU
RFU
SS
SS
DD
DD
SS
V
DQ12
DQ13
V
CB4
CB5
A10/AP
BA0
BA1
SA2
NC(TEST)
SS
SS
V
V
DQ8
DQ9
V
CB0
CB1
DDQ
SS
V
V
V
RAS
S0
DM6/DQS15
NC/DQS15
SS
SS
DDQ
SS
V
DM1/DQS10
NC/DQS10
DM8/DQS17
NC/DQS17
WE
CAS
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
V
DQS8
DQS8
DDQ
SS
V
V
V
V
ODT0
A13
DQ54
DQ55
SS
SS
DDQ
SS
4
V
RFU
RFU
V
CB6
CB7
DQ50
DQ51
S1
SS
SS
V
V
RESET
NC
V
CB2
CB3
ODT1
DD
SS
V
V
V
V
DQ60
DQ61
SS
SS
DDQ
SS
SS
V
V
V
DQ14
DQ15
V
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
4
V
V
DQ10
DQ11
V
DQ32
DQ33
CKE1
DDQ
SS
V
V
V
CKE0
DM7/DQS16
NC/DQS16
SS
DD
SS
SS
V
V
DQ20
DQ21
V
NC
NC
DM4/DQS13
NC/DQS13
DQS7
DQS7
SS
DD
SS
V
DQ16
DQ17
V
BA2
NC/Err_Out
DQS4
DQS4
SS
V
V
V
DQ62
DQ63
SS
DDQ
SS
SS
V
V
DM2/DQS11
NC/DQS11
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
V
A11
A7
DQ34
DQ35
SS
V
V
V
V
VDDSPD
SA0
SA1
SS
DD
SS
SS
V
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
SS
DQ18
A5
DQ40
DQ41
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
Pin Description
Pin Name
Description
Pin Name
Description
CK0
Clock Inputs, positive line
Clock inputs, negative line
Clock Enables
ODT0~ODT1
DQ0~DQ63
CB0~CB7
On die termination
Data Input/Output
CK0
CKE0, CKE1
RAS
Data check bits Input/Output
Data strobes
Row Address Strobe
Column Address Strobe
Write Enable
DQS0~DQS8
DQS0~DQS8
CAS
Data strobes, negative line
WE
DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)
S0, S1
Chip Selects
DQS9~DQS17
Data strobes (Read), negative line
Reserved for Future Use
No Connect
A0~A9, A11~A13
A10/AP
Address Inputs
RFU
NC
Address Input/Autoprecharge
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
BA0, BA2
DDR2 SDRAM Bank Address
TEST
SCL
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
V
V
V
V
V
Core Power
I/O Power
DD
SDA
DDQ
SS
SA0~SA2
Par_In
Err_Out
RESET
SPD address
Ground
Parity bit for the Address and Control bus
Parity error found in the Address and Control bus
Register and PLL control pin
Input/Output Reference
SPD Power
REF
DDSPD
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
CK0
Type
Input
Input
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CK0
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
Input
CKE0~CKE1
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-
abled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
Input
S0~S1
Input
Input
ODT0~ODT1
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
RAS, CAS, WE
V
Supply
Reference voltage for SSTL_18 inputs
REF
V
Supply
Input
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of eight is activated.
DDQ
BA0~BA2
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Pre-
charge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are
used to define which bank to precharge.
A0~A9,A10/AP
A11~A13
Input
DQ0~63,
In/Out
Input
Data and Check Bit Input/Output pins
CB0~CB7
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
DM0~DM8
V
, V
SS
Supply
In/Out
In/Out
Power and ground for the DDR SDRAM input buffers and core logic
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
DD
DQS0~DQS17
DQS0~DQS17
SA0~SA2
These signals are tied at the system planar to either V or V
to configure the serial SPD EEPROM address range.
DDSPD
Input
SS
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to V to act as a pullup.
SDA
SCL
In/Out
DDSPD
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to V to act as a pullup.
Input
DDSPD
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to
3.6 Volt operation).
V
Supply
DDSPD
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
RESET
Input
Par_In
Err_Out
TEST
Input
Input
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
In/Out
Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 2GB, 256Mx72 Module(populated as 1 rank of x4 DDR2 SDRAMs)
(M393T5660MZ3/M393T5660MZ0)
VSS
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D9
DQS1
DM1/DQS10
DQS1
NC/DQS10
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
D1
D10
DQ10
DQ11
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D11
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D12
DQS4
DM4/DQS13
DQS4
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D13
DQS5
DM5/DQS14
DQS5
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D14
Serial PD
DQS6
DM6/DQS15
SCL
SDA
DQS6
NC/DQS15
WP A0 A1 A2
SA0 SA1 SA2
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D15
DQS7
DM7DQS16
DQS7
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DQ56
DQ60
DDSPD
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D16
/V
DD DDQ
DQS8
DM8/DQS17
VREF
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
V
SS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D17
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L
1:2
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D17
CK0
BA0-BA2
A0-A13
RAS
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
PCK7 -> CK : Register
OE
RESET
PCK7 -> CK : Register
CAS
S
T
E
R
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
WE
2. Unless otherwise noted, resister values are 22 Ohms
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RST
RESET**
* S0 connects to DCS of Register1, CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
PCK7**
PCK7**
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 4GB, 512Mx72 Module(populated as 2 rank of x4 DDR2 SDRAMs)
(M393T5168MZ0)
VSS
RS1
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
CS DQS DQS
DM/
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D18
D9
D27
DQS1
DM1/DQS10
DQS1
NC/DQS10
DM
CS DQS DQS
DM/
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
D1
D19
D10
D28
DQ10
DQ11
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM/
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D20
D11
D29
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D21
D12
D30
DQS4
DM4/DQS13
DQS4
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D22
D13
D31
DQS5
DM5/DQS14
DQS5
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D23
D14
D32
DQS6
DM6/DQS15
DQS6
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D24
D15
D33
DQS7
DM7DQS16
DQS7
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS8
DM8/DQS17
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D26
D17
D35
Serial PD
V
V
Serial PD
D0 - D35
D0 - D35
D0 - D35
DDSPD
S0*
S1*
BA0-BA2
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RSO-> CS : DDR2 SDRAMs D0-D17
RS1-> CS : DDR2 SDRAMs D18-D35
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
RRAS -> RAS : DDR2 SDRAMs D0-D35
RCAS -> CAS : DDR2 SDRAMs D0-D35
RWE -> WE : DDR2 SDRAMs D0-D35
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
SCL
SDA
1:2
R
E
G
I
/V
DD DDQ
WP A0 A1 A2
SA0 SA1 SA2
VREF
V
SS
S
T
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
P
L
L
E
R
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
PCK7 -> CK : Register
PCK7 -> CK : Register
OE
RESET
RST
RESET**
PCK7**
* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
PCK7**
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on V pin relative to V
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
DD
SS
DD
Voltage on V
Voltage on V
pin relative to V
V
V
DDQ
DDL
SS
DDQ
pin relative to V
V
V
1
SS
DDL
Voltage on any pin relative to V
Storage Temperature
V
V
V
1
SS
IN, OUT
T
°C
1, 2
STG
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
V
Supply Voltage
V
V
DD
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
DDL
V
1.7
1.8
1.9
V
DDQ
V
0.49*V
0.50*V
0.51*V
DDQ
mV
V
1,2
3
REF
DDQ
DDQ
V
V
-0.04
V
V
+0.04
REF
TT
REF
REF
Note : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
must be less than or equal
DDQ
DD
to V
.
DD
1. The value of V
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
is expected to be about 0.5
REF
REF
x V
of the transmitting device and V
is expected to track variations in V
.
DDQ
DDQ
REF
2. Peak to peak AC noise on V
may not exceed +/-2% V
(DC).
REF
REF
3. V of transmitting device must track V
of receiving device.
REF
TT
4. AC parameters are measured with V , V
and V
tied together.
DDL
DD
DDQ
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2
standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
(DC)
Parameter
Min.
+ 0.125
Max.
V + 0.3
DDQ
Units
Notes
Notes
V
DC input logic high
DC input logic low
V
V
V
V
IH
REF
V (DC)
- 0.3
V
- 0.125
IL
REF
Input AC Logic Level
Symbol
Parameter
Min.
Max.
Units
V
(AC)
AC input logic high
AC input logic low
+ 0.250
REF
-
V
V
IH
V (AC)
-
V
- 0.250
IL
REF
AC Input Test Conditions
Symbol
Condition
Value
0.5 * V
Units
V
Notes
1
1
V
Input reference voltage
REF
DDQ
V
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
SWING(MAX)
SLEW
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
(AC) level applied to the device under test.
IH/IL
2. The input signal minimum slew rate is to be maintained over the range from V
to V (AC) min for rising edges and the range from V
to V (AC)
REF IL
REF
IH
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative
IL
IH
IH
IL
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
Rising Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol Proposed Conditions
Units
Notes
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
IDD0
IDD1
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
mA
is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
t
t
mA
mA
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
mA
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
Operating Current Table (TA=0oC, VDD= 1.9V)
DDR2 SDRAM
M393T5660MZ3/M393T5660MZ0 : 2GB(256Mx4 *18) Module
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
2,330
2,550
856
1,200
1,180
1,190
690
1,660
3,802
3,662
5,608
216
2,160
2,400
796
1,130
1,150
1,130
660
1,640
3,170
3,090
5,410
216
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
Normal
IDD7
7,808
7,100
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T5168MZ0 : 4GB(st.512Mx4 *18) Module
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
3,170
3,420
1,372
2,060
2,000
2,060
1,210
2,330
4,712
4,562
6,468
432
3,040
3,370
1,272
1,960
2,030
1,960
1,160
2,410
4,080
3,980
6,220
432
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
Normal
IDD7
9,158
8,160
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter
Min
M393T5660MZ3
M393T5660MZ0
Max
Min
Max
Symbol
Units
Part-Number
M393T5168MZ0
Input capacitance, CK and CK
CCK
CI1
-
-
-
-
11
-
-
-
-
11
12
12
10
Input capacitance, CKE and CS
12
12
10
pF
Input capacitance, Addr,RAS,CAS,WE
CI2
Input/output capacitance, DQ, DM, DQS, DQS
CIO
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
DDQ DD
CASE
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
195
327.5
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
Average periodic refresh interval
85 °C < T
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR2-533(D5)
DDR2-400(CC)
3 - 3 - 3
Bin (CL - tRCD - tRP)
4 - 4 - 4
Units
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
min
5
max
min
5
max
8
8
-
8
8
-
ns
ns
ns
ns
ns
ns
ns
3.75
-
5
-
15
15
55
40
15
15
55
40
tRP
tRC
70000
70000
tRAS
Timing Parameters by Speed Grade
(Refer to notes for information related to this table at the bottom)
DDR2-533
min max
DDR2-400
max
Symbol
Units
Notes
Parameter
min
-600
DQ output access time from CK/CK
tAC
-500
+500
+600
ps
ps
DQS output access time from CK/CK
CK high-level width
tDQSCK
tCH
-450
+450
-500
+500
0.45
0.55
0.45
0.55
tCK
tCK
ps
CK low-level width
tCL
0.45
0.55
0.45
0.55
CK half period
tHP
min(tCL, tCH)
3750
x
min(tCL, tCH)
5000
x
Clock cycle time, CL=x
tCK
8000
8000
ps
DQ and DM input hold time
tDH
225
x
275
x
ps
DQ and DM input setup time
tDS
100
x
150
x
ps
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tIPW
0.6
x
0.6
x
tCK
tCK
ps
tDIPW
tHZ
0.35
x
tAC max
tAC max
tAC max
300
0.35
x
tAC max
tAC max
tAC max
350
x
x
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tAC min
2* tACmin
x
tAC min
2* tACmin
x
ps
ps
ps
x
400
x
450
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tHP - tQHS
WL-0.25
0.35
x
tHP - tQHS
WL-0.25
0.35
x
ps
tDQSS
tDQSH
tDQSL
WL+0.25
x
WL+0.25
x
tCK
tCK
tCK
DQS input low pulse width
0.35
x
0.35
x
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
DDR2-533
DDR2-400
Symbol
tDSS
Units
Notes
Parameter
min
max
min
max
DQS falling edge to CK setup time
0.2
x
0.2
x
tCK
tCK
tCK
tCK
tCK
ps
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDSH
tMRD
tWPST
tWPRE
tIH
0.2
x
0.2
x
2
x
2
x
0.4
0.6
x
0.4
0.6
x
Write preamble
0.35
375
250
0.9
0.35
475
350
0.9
Address and control input hold time
Address and control input setup time
Read preamble
x
x
tIS
x
x
ps
tRPRE
tRPST
tRRD
1.1
0.6
x
1.1
0.6
x
tCK
tCK
ns
Read postamble
0.4
0.4
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
7.5
7.5
tRRD
tFAW
10
x
10
x
ns
37.5
50
37.5
50
ns
tFAW
ns
tCCD
tWR
2
2
tCK
ns
Write recovery time
15
x
x
x
15
x
x
x
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read command
Exit active power down to read command
Exit active power down to read command (Slow exit, Lower power)
CKE minimum pulse width (high and low pulse width)
tDAL
tWR+tRP
7.5
tWR+tRP
10
tCK
ns
tWTR
tRTP
7.5
7.5
ns
tXSNR
tXSRD
tXP
tRFC + 10
200
2
tRFC + 10
200
2
ns
tCK
tCK
tCK
tCK
x
x
x
x
tXARD
tXARDS
2
2
6 - AL
3
6 - AL
3
t
tCK
CKE
t
ODT turn-on delay
ODT turn-on
2
2
2
2
tCK
ns
AOND
t
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
AON
2tCK+tAC(ma
x)+1
2tCK+tAC
(max)+1
t
ODT turn-on(Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AONPD
t
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
AOFD
t
tAC(min)
tAC(max)+ 0.6
tAC(max)+ 0.6
tAC(min)
AOF
2.5tCK+
2.5tCK+
t
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AOFPD
tAC(max)+1
tAC(max)+1
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE asynchronously drops
LOW
tDelay
tIS+tCK +tIH
tIS+tCK +tIH
ns
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Physical Dimensions: 256Mbx4 based 256Mx72 Module(1 Rank)
(M393T5660MZ3/M393T5660MZ0)
Units : Millimeters
133.35
4.0
30.00
PLL
1.0 max
1.2 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 256M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G044QM
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Physical Dimensions: st.512Mbx4 based 512Mx72 Module(2 Ranks)
(M393T5168MZ0)
Units : Millimeters
133.35
6.75 max
30.00
PLL
4.05 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is st.512M x4 DDR2 SDRAM.
DDR2 SDRAM Part NO : K4T2G064QM
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
240 Pin DDR2 Registered DIMM Clock Topology
0ns (nominal)
PLL
DDR2 SDRAM
120 ohms
OUT1
CK0
120 ohms
IN
DDR2 SDRAM
Reg.A
CK0
120 ohms
OUTN
120 ohms
C
C
Feedback In
Feedback Out
Reg.B
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.4 Aug. 2005
2GB, 4GB Registered DIMMs
DDR2 SDRAM
Revision History
Revision 0.1 (Mar. 2004)
- Initial Release
Revision 0.2 (May 2004)
- Corrected the Ordering Information
Revision 1.0 (Dec. 2004)
- Added DDR2-400(CC) current data (2GB Only)
Revision 1.1 (Mar. 2005)
- Added DDR2-400(CC) current data (4GB Only)
Revision 1.2 (May 2005)
- Revised the physical dimensions
Revision 1.3 (Jul. 2005)
- Revised the Ordering Information
Revision 1.4 (Aug. 2005)
- Added DDR2-533(D5) current data
Rev. 1.4 Aug. 2005
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