M391T6553EZ3-CE6 [SAMSUNG]
DDR DRAM Module, 64MX72, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240;![M391T6553EZ3-CE6](http://pdffile.icpdf.com/pdf2/p00292/img/icpdf/M391T6553EZ3_1769972_icpdf.jpg)
型号: | M391T6553EZ3-CE6 |
厂家: | ![]() |
描述: | DDR DRAM Module, 64MX72, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240 时钟 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总27页 (文件大小:847K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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UDIMM
DDR2 SDRAM
DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 512Mb E-die
64/72-bit Non-ECC/ECC
60FBGA & 84FBGA with Lead-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 July 2008
1 of 27
UDIMM
DDR2 SDRAM
Table of Contents
1.0 DDR2 Unbuffered DIMM Ordering Information ..........................................................................4
2.0 Features .........................................................................................................................................4
3.0 Address Configuration .................................................................................................................4
4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................5
5.0 x72 DIMM Pin Configurations (Front side/Back side) ................................................................6
6.0 Pin Description ..............................................................................................................................6
7.0 Input/Output Functional Description ..........................................................................................7
8.0 Functional Block Diagram : .........................................................................................................8
8.1 512MB, 64Mx64 Module - M378T6553EZS .........................................................................................8
8.2 512MB, 64Mx72 ECC Module - M391T6553EZ3 ..................................................................................9
8.3 1GB, 128Mx64 Module - M378T2953EZ3 .........................................................................................10
8.4 1GB, 128Mx72 ECC Module - M391T2953EZ3 ..................................................................................11
8.5 256MB, 32Mx64 Module - M378T3354EZ3 ........................................................................................12
9.0 Absolute Maximum DC Ratings .................................................................................................13
10.0 AC & DC Operating Conditions ...............................................................................................13
10.1 Recommended DC Operating Conditions (SSTL - 1.8) ..................................................................13
10.2 Operating Temperature Condition ..............................................................................................14
10.3 Input DC Logic Level ................................................................................................................14
10.4 Input AC Logic Level ................................................................................................................14
10.5 AC Input Test Conditions ..........................................................................................................14
11.0 IDD Specification Parameters Definition ................................................................................15
12.0 Operating Current Table ...........................................................................................................16
13.0 Input/Output Capacitance ........................................................................................................19
14.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................19
14.1 Refresh Parameters by Device Density .......................................................................................19
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ............................................19
14.3 Timing parameters by speed grade (DDR2-800 and DDR2-667) ......................................................20
14.4 Timing parameters by speed grade (DDR2-533 and DDR2-400) ......................................................22
15.0 Physical Dimensions : ..............................................................................................................24
15.1 64Mbx8 based 64Mx64 Module (1 Rank) - M378T6553EZS ..............................................................24
15.2 64Mbx8 based 64Mx72 Module (1 Rank) - M391T6553EZ3 ..............................................................25
15.3 64Mbx8 based 128Mx64/x72 Module (2 Ranks) - M378T2953EZ3, M391T2953EZ3 .............................26
15.4 32Mbx16 based 32Mx64 Module (1 Rank) - M378T3354EZ3 ............................................................27
Rev. 1.3 July 2008
2 of 27
UDIMM
DDR2 SDRAM
Revision History
Revision
0.1
Month
March
Year
2006
2006
History
- Initial Release
- Revised the IDD values
1.0
September
- Added DDR2-800 CL=6
- Changed the Feature
1.1
September
2006
1.2
1.3
June
July
2007
2008
- Corrected Typo
- Applied JEDEC update(JESD79-2E) on AC timing table
Rev. 1.3 July 2008
3 of 27
UDIMM
DDR2 SDRAM
1.0 DDR2 Unbuffered DIMM Ordering Information
Part Number
Density
Organization
Component Composition
Number of Rank
Height
x64 Non ECC
M378T3354EZ3-CE7/F7/E6/D5/CC
M378T6553EZS-CE7/F7/E6/D5/CC
M378T2953EZ3-CE7/F7/E6/D5/CC
256MB
512MB
1GB
32Mx64
64Mx64
128Mx64
32Mx16(K4T51163QE)*4
64Mx8(K4T51083QE)*8
64Mx8(K4T51083QE)*16
1
1
2
30mm
30mm
30mm
x72 ECC
M391T6553EZ3-CE7/F7/E6/D5/CC
M391T2953EZ3-CE7/F7/E6/D5/CC
512MB
1GB
64Mx72
64Mx8(K4T51083QE)*9
64Mx8(K4T51083QE)*18
1
2
30mm
30mm
128Mx72
Note :
1. “Z” of Part number(11th digit) stands for Lead-Free products.
2. “3” of Part number(12th digit) stands for Dummy Pad PCB products.
2.0 Features
• Performance range
E7 (DDR2-800)
F7 (DDR2-800)
E6 (DDR2-667)
D5 (DDR2-533)
CC (DDR2-400)
Unit
Mbps
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
400
533
800
-
-
400
533
667
-
400
533
533
-
400
400
-
533
667
800
6-6-6
-
5-5-5
5-5-5
4-4-4
3-3-3
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- Support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-Free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization
64Mx8(512Mb) based Module
32Mx16(512Mb) based Module
Row Address
A0-A13
Column Address
A0-A9
Bank Address
BA0-BA1
Auto Precharge
A10
A10
A0-A12
A0-A9
BA0-BA1
Rev. 1.3 July 2008
4 of 27
UDIMM
DDR2 SDRAM
4.0 x64 DIMM Pin Configurations (Front side/Back side)
Pin
1
Front
VREF
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ19
VSS
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Pin
61
Front
A4
Pin
181
182
183
184
Back
Pin
91
92
93
94
95
96
97
98
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
VSS
VSS
VDDQ
VSS
VDDQ
2
3
4
5
6
7
8
9
DQ4
DQ5
VSS
DQ28
DQ29
VSS
62
63
64
A3
A1
VDD
DQS5
DQS5
VSS
VSS
DQ0
DQ1
VSS
DQ24
DQ25
VSS
A2
VDD
DQ46
DQ47
VSS
DM0
NC
VSS
DM3
NC
VSS
KEY
DQ42
DQ43
VSS
VSS
VSS
VDD
DQS0
DQS0
VSS
DQS3
DQS3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0
VDD
DQ52
DQ53
VSS
DQ6
DQ7
VSS
DQ30
DQ31
VSS
DQ48
DQ49
VSS
DQ2
DQ3
VSS
DQ26
DQ27
VSS
NC
VDD
A0
VDD
99
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2
VSS
DQ12
DQ13
VSS
NC
NC
VSS
A10/AP
BA0
VDDQ
BA1
VDDQ
SA2
NC, TEST2
VSS
DQ8
DQ9
VSS
NC
NC
VSS
RAS
S0
VDDQ
DM6
NC
VSS
DM1
NC
VSS
NC
NC
VSS
WE
CAS
VDDQ
DQS6
DQS6
VSS
DQS1
DQS1
VSS
NC
NC
VSS
ODT0
A131
VDD
DQ54
DQ55
VSS
CK1
CK1
VSS
NC
NC
VSS
VDDQ
S1
DQ50
DQ51
VSS
NC
NC
VSS
NC
NC
VSS
VDDQ
ODT1
VDDQ
VSS
VSS
DQ60
DQ61
VSS
DQ14
DQ15
VSS
DQ36
DQ37
VSS
DQ56
DQ57
VSS
DQ10
DQ11
VSS
CKE1
VDD
DQ32
DQ33
VSS
CKE0
VDD
DM7
NC
VSS
DQ20
DQ21
VSS
NC
NC
VDDQ
DM4
NC
VSS
DQS7
DQS7
VSS
DQ16
DQ17
VSS
NC
NC
VDDQ
DQS4
DQS4
VSS
DQ62
DQ63
VSS
DM2
NC
VSS
A12
A9
VDD
DQ38
DQ39
VSS
DQ58
DQ59
VSS
DQS2
DQS2
VSS
A11
A7
VDD
A5
DQ34
DQ35
VSS
DQ40
DQ41
VDDSPD
DQ22
DQ23
A8
A6
DQ44
DQ45
VSS
SDA
SCL
SA0
SA1
DQ18
NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Rev. 1.3 July 2008
5 of 27
UDIMM
DDR2 SDRAM
5.0 x72 DIMM Pin Configurations (Front side/Back side)
Pin
1
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Pin
61
Front
Pin
181
182
183
184
Back
DDQ
Pin
91
92
93
94
95
96
97
98
Front
SS
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
V
V
V
V
V
V
DQ19
A4
REF
SS
SS
V
V
2
3
4
5
6
7
8
9
DQ4
DQ5
V
DQ28
DQ29
V
62
63
64
A3
A1
DQS5
DQS5
SS
SS
DDQ
V
DQ0
DQ1
V
DQ24
DQ25
A2
SS
V
V
V
DQ46
DQ47
SS
SS
DD
DD
SS
V
DM0
NC
V
DM3
NC
V
KEY
DQ42
DQ43
SS
SS
V
V
DQS0
DQS0
V
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0
SS
SS
V
V
DQ52
DQ53
SS
SS
SS
SS
V
V
V
DQ6
DQ7
V
DQ30
DQ31
V
DQ48
DQ49
SS
SS
DD
DD
V
DQ2
DQ3
V
DQ26
DQ27
NC
A0
99
SS
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2
SS
SS
DD
DD
SS
V
DQ12
DQ13
V
CB4
CB5
V
A10/AP
BA0
BA1
SA2
SS
SS
2
V
V
DQ8
DQ9
V
CB0
CB1
NC, TEST
DDQ
SS
V
V
RAS
S0
DM6
NC
SS
SS
DDQ
SS
V
DM1
NC
V
DM8
NC
V
WE
CAS
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
V
DQS8
DQS8
DDQ
SS
V
V
ODT0
A13
DQ54
DQ55
SS
SS
DDQ
SS
V
CK1
CK1
V
CB6
CB7
V
S1
ODT1
DQ50
DQ51
SS
SS
V
V
NC
NC
V
CB2
CB3
DD
SS
V
V
V
DQ60
DQ61
VSS
DM7
NC
SS
SS
DDQ
SS
SS
V
V
V
DQ14
DQ15
V
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
V
DQ10
DQ11
V
CKE1
DQ32
DQ33
DDQ
V
V
V
CKE0
SS
DD
SS
SS
V
V
DQ20
DQ21
V
NC
NC
DM4
NC
DQS7
DQS7
SS
DD
SS
V
DQ16
DQ17
V
NC
NC
DQS4
DQS4
SS
V
V
V
DQ62
DQ63
SS
DDQ
SS
SS
V
V
DM2
NC
V
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
V
A11
A7
DQ34
DQ35
SS
V
V
V
V
SS
DD
SS
SS
DDSPD
V
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SA0
SA1
SS
DD
SS
DQ18
A5
DQ40
DQ41
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
6.0 Pin Description
Pin Name
A0-A13
Description
DDR2 SDRAM address bus
Pin Name
CK0, CK1, CK2
CK0, CK1, CK2
SCL
Description
DDR2 SDRAM clocks (positive line of differential pair)
DDR2 SDRAM clocks (negative line of differential pair)
I2C serial bus clock for EEPROM
I2C serial bus data line for EEPROM
I2C serial address select for EEPROM
DDR2 SDRAM core power supply
DDR2 SDRAM I/O Driver power supply
DDR2 SDRAM I/O reference supply
Power supply return (ground)
BA0, BA1
RAS
DDR2 SDRAM bank select
DDR2 SDRAM row address strobe
DDR2 SDRAM column address strobe
DDR2 SDRAM wirte enable
DIMM Rank Select Lines
CAS
SDA
WE
SA0-SA2
S0, S1
VDD*
CKE0,CKE1
ODT0, ODT1
DQ0 - DQ63
CB0 - CB7
DQS0 - DQS8
DM(0-8)
DDR2 SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
VDDQ
VREF
VSS
*
DIMM ECC check bits
VDDSPD
NC
Serial EEPROM positive power supply
Spare Pins(no connect)
DDR2 SDRAM data strobes
DDR2 SDRAM data masks
RESET
Not used on UDIMM
Used by memory bus analysis tools
(unused on memory DIMMs)
DQS0-DQS8
DDR2 SDRAM differential data strobes
TEST
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.3 July 2008
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UDIMM
DDR2 SDRAM
7.0 Input/Output Functional Description
Symbol
Type
Function
CK0-CK2
CK0-CK2
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of
CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing)
Input
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE
low initiates the Powe Down mode, or the Self-Refresh mode
CKE0-CKE1
Input
Input
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disbled, new command are ignored but previous operations continue. This signal provides for exter-
nal rank selection on systems with multiple ranks
S0-S1
RAS, CAS, WE
ODT0-ODT1
VREF
Input
Input
RAS, CAS, and WE (ALONG WITH CS) define the command being entered.
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
Supply Reference voltage for SSTL 18 inputs.
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered
VDDQ
Supply
DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA1
Input
Selects which SDRAM BANK of four is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-
charge.
A0-A13
Input
DQ0-DQ63
CB0-CB7
In/Out
Input
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
DM0-DM8
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on
these modules.
V
DD,VSS
Supply
DQS0-DQS8
DQS0-DQS8
Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the
DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
In/Out
Input
SA0-SA2
These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the
SDA bus line to VDD to act as a pullup on the system board.
SDA
In/Out
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDD to act as a pullup onthe system board.
SCL
Input
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable
from 1.7V to 3.6V.
VDDSPD
Supply
Rev. 1.3 July 2008
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UDIMM
DDR2 SDRAM
8.0 Functional Block Diagram :
8.1 512MB, 64Mx64 Module - M378T6553EZS
(Populated as 1 rank of x8 DDR2 SDRAMs)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
NU/ CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
V
V
V
V
Serial PD
DDSPD
Serial PD
SCL
WP
* Clock Wiring
Clock Input DDR2 SDRAMs
/V
D0 - D7
D0 - D7
D0 - D7
DD DDQ
SDA
A0
A1
A2
REF
SS
*CK0/CK0 2 DDR2 SDRAMs
*CK1/CK1 3 DDR2 SDRAMs
*CK2/CK2 3 DDR2 SDRAMs
SA0 SA1 SA2
BA0 - BA1
A0 - A13
RAS
BA0-BA1 : DDR2 SDRAMs D0 - D7
A0-A13 : DDR2 SDRAMs D0 - D7
RAS : DDR2 SDRAMs D0 - D7
CAS : DDR2 SDRAMs D0 - D7
CKE : DDR2 SDRAMs D0 - D7
WE : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D0 - D7
*Wire per Clock Loading
Table/Wiring Diagrams
CAS
Note :
CKE0
WE
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.
ODT0
Rev. 1.3 July 2008
8 of 27
UDIMM
DDR2 SDRAM
8.2 512MB, 64Mx72 ECC Module - M391T6553EZ3
(Populated as 1 rank of x8 DDR2 SDRAMs)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
DQS8
DQS8
DM8
Serial PD
SCL
WP
DM
CS DQS DQS
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
D8
SA0 SA1 SA2
* Clock Wiring
Clock Input DDR2 SDRAMs
V
V
V
V
Serial PD
D0 - D8
D0 - D8
D0 - D8
DDSPD
/V
DD DDQ
*CK0/CK0 3 DDR2 SDRAMs
*CK1/CK1 3 DDR2 SDRAMs
*CK2/CK2 3 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
BA0 - BA1
A0 - A13
RAS
BA0-BA1 : DDR2 SDRAMs D0 - D8
A0-A13 : DDR2 SDRAMs D0 - D8
RAS : DDR2 SDRAMs D0 - D8
CAS : DDR2 SDRAMs D0 - D8
CKE : DDR2 SDRAMs D0 - D8
WE : DDR2 SDRAMs D0 - D8
ODT : DDR2 SDRAMs D0 - D8
REF
SS
CAS
Note :
CKE0
WE
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.
ODT0
Rev. 1.3 July 2008
9 of 27
UDIMM
DDR2 SDRAM
8.3 1GB, 128Mx64 Module - M378T2953EZ3
(Populated as 2 ranks of x8 DDR2 SDRAMs)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D8
D4
D12
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D9
D5
D13
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D10
D6
D14
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D11
D7
D15
V
V
V
V
Serial PD
DDSPD
Serial PD
/V
D0 - D15
D0 - D15
D0 - D15
DD DDQ
SCL
WP
SDA
REF
SS
A0
A1
A2
* Clock Wiring
Clock Input DDR2 SDRAMs
SA0 SA1 SA2
BA0 - BA1
A0 - A13
CKE0
BA0-BA1 : DDR2 SDRAMs D0 - D15
A0-A13 : DDR2 SDRAMs D0 - D15
CKE : DDR2 SDRAMs D0 - D7
*CK0/CK0 4 DDR2 SDRAMs
*CK1/CK1 6 DDR2 SDRAMs
*CK2/CK2 6 DDR2 SDRAMs
CKE1
RAS
CAS
CKE : DDR2 SDRAMs D8 - D15
RAS : DDR2 SDRAMs D0 - D15
CAS : DDR2 SDRAMs D0 - D15
*Wire per Clock Loading
Table/Wiring Diagrams
Note :
WE
ODT0
ODT1
WE : DDR2 SDRAMs D0 - D15
ODT : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D8 - D15
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.
Rev. 1.3 July 2008
10 of 27
UDIMM
DDR2 SDRAM
8.4 1GB, 128Mx72 ECC Module - M391T2953EZ3
(Populated as 2 ranks of x8 DDR2 SDRAMs)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D9
D4
D13
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
DQS8
DQS8
DM8
Serial PD
SCL
WP
DM
CS DQS DQS
DM
CS DQS DQS
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
D8
D17
SA0 SA1
SA2
* Clock Wiring
Clock Input
DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
BA0 - BA1
A0 - A13
CKE0
BA0-BA1 : DDR2 SDRAMs D0 - D17
A0-A13 : DDR2 SDRAMs D0 - D17
CKE : DDR2 SDRAMs D0 - D8
V
V
V
/V
DD DDQ
*Wire per Clock Loading
Table/Wiring Diagrams
REF
SS
CKE1
RAS
CAS
CKE : DDR2 SDRAMs D9 - D17
RAS : DDR2 SDRAMs D0 - D17
CAS : DDR2 SDRAMs D0 - D17
Note :
WE
ODT0
ODT1
WE : DDR2 SDRAMs D0 - D17
ODT : DDR2 SDRAMs D0 - D8
ODT : DDR2 SDRAMs D9 - D17
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.
Rev. 1.3 July 2008
11 of 27
UDIMM
DDR2 SDRAM
8.5 256MB, 32Mx64 Module - M378T3354EZ3
(Populated as 1 rank of x16 DDR2 SDRAMs)
S0
CS
CS
DQS1
DQS1
DM1
DQS5
DQS5
DM5
LDQS
LDOS
LDM
LDQS
LDOS
LDM
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D0
D2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DQS0
DM0
DQS4
DQS4
DM4
UDQS
UDOS
UDM
UDQS
UDOS
UDM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 8
I/O 8
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
CS
DQS3
DQS3
DM3
DQS7
DQS7
DM7
LDQS
LDOS
LDM
LDQS
LDOS
LDM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D3
DQS2
DQS2
DM2
DQS6
DQS6
DM6
UDQS
UDOS
UDM
UDQS
UDOS
UDM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 8
I/O 8
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
* Clock Wiring
DDR2 SDRAMs
V
Serial PD
DDSPD
Clock Input
V
V
V
/V
D0 - D3
D0 - D3
D0 - D3
DD DDQ
Serial PD
*CK0/CK0
*CK1/CK1
*CK2/CK2
NC
SCL
WP
2 DDR2 SDRAMs
2 DDR2 SDRAMs
REF
SS
SDA
A0
A1
A2
*Wire per Clock Loading
Table/Wiring Diagrams
SA0 SA1 SA2
BA0 - BA1
A0 - A12
CKE0
BA0-BA1 : DDR2 SDRAMs D0 - D3
A0-A12 : DDR2 SDRAMs D0 - D3
CKE : DDR2 SDRAMs D0 - D3
RAS : DDR2 SDRAMs D0 - D3
CAS : DDR2 SDRAMs D0 - D3
Notes :
RAS
CAS
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.
WE
ODT0
WE : DDR2 SDRAMs D0 - D3
ODT : DDR2 SDRAMs D0 - D3
Rev. 1.3 July 2008
12 of 27
UDIMM
DDR2 SDRAM
9.0 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
Voltage on VDD pin relative to VSS
- 1.0 V ~ 2.3 V
V
1
VDD
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
VDDQ
VDDL
V
1
VIN, VOUT
TSTG
°C
1, 2
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
10.0 AC & DC Operating Conditions
10.1 Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Typ.
1.8
Symbol
Parameter
Units
Notes
Min.
1.7
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
Supply Voltage
V
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
1.7
1.8
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD
.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Rev. 1.3 July 2008
13 of 27
UDIMM
DDR2 SDRAM
10.2 Operating Temperature Condition
Symbol
TOPER
Parameter
Operating Temperature
Rating
0 to 95
Units
°C
Notes
1, 2
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2
standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
10.3 Input DC Logic Level
Symbol
VIH(DC)
VIL(DC)
Parameter
DC input logic high
DC input logic low
Min.
VREF + 0.125
- 0.3
Max.
VDDQ + 0.3
VREF - 0.125
Units
V
V
Notes
10.4 Input AC Logic Level
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Symbol
Parameter
Units
Notes
Min.
Max.
Min.
Max.
V
IH(AC)
AC input logic high
AC input logic low
VREF + 0.250
-
-
VREF + 0.200
V
V
VIL(AC)
VREF - 0.250
VREF - 0.200
10.5 AC Input Test Conditions
Symbol
Condition
Value
0.5 * VDDQ
1.0
Units
V
Notes
1
1
VREF
VSWING(MAX)
SLEW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
V
1.0
V/ns
2, 3
Note :
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
V (DC) max
IL
V (AC) max
IL
V
SS
delta TF
V
delta TR
Rising Slew =
V
(AC) min - V
delta TR
- V (AC) max
IL
REF
IH
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.3 July 2008
14 of 27
UDIMM
DDR2 SDRAM
11.0 IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
Units
Notes
Operating one bank active-precharge current;
IDD0
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
IDD1
mA
Precharge power-down current;
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD4W
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
mA
mA
Burst auto refresh current;
IDD5B
IDD6
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
IDD7
mA
Rev. 1.3 July 2008
15 of 27
UDIMM
DDR2 SDRAM
12.0 Operating Current Table :
(TA=0oC, VDD= 1.9V)
12.1 M378T6553EZS : 512MB(64Mx8 *8) Module
Symbol
IDD0
IDD1
E7(800@CL=5)
F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
680
760
64
280
320
240
96
480
920
1,160
920
64
680
760
64
280
320
240
96
480
920
1,160
920
64
600
720
64
280
320
240
96
440
840
1,080
880
64
600
680
64
240
280
240
96
400
720
880
880
64
560
680
64
240
280
240
96
400
680
800
840
64
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
1,720
1,720
1,440
1,440
1,440
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
(TA=0oC, VDD= 1.9V)
12.2 M378T2953EZ3 : 1GB(64Mx8 *16) Module
Symbol
IDD0
IDD1
E7(800@CL=5)
1,000
1,080
128
F7(800@CL=6)
1,000
1,080
128
E6(667@CL=5)
920
D5(533@CL=4)
880
CC(400@CL=3)
840
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,040
128
560
640
480
192
760
1,160
1,400
1,200
128
960
128
480
560
480
192
680
1,000
1,160
1,160
128
960
128
480
560
480
192
680
960
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
560
640
480
192
560
640
480
192
800
800
1,240
1,480
1,240
128
1,240
1,480
1,240
128
1,080
1,120
128
IDD7
2,200
2,200
1,760
1,720
1,720
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 July 2008
16 of 27
UDIMM
DDR2 SDRAM
(TA=0oC, VDD= 1.9V)
12.3 M378T3354EZ3 : 256MB(32Mx16 *4) Module
Symbol
IDD0
IDD1
E7(800@CL=5)
F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
380
460
32
140
160
120
48
240
540
760
460
32
380
460
32
140
160
120
48
240
540
760
460
32
360
440
32
140
160
120
48
220
480
680
440
32
360
420
32
120
140
120
48
200
420
560
440
32
360
420
32
120
140
120
48
200
400
540
440
32
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
1,120
1,120
960
960
860
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
(TA=0oC, VDD= 1.9V)
12.4 M391T6553EZ3 : 512MB(64Mx8 *9) ECC Module
Symbol
IDD0
IDD1
E7(800@CL=5)
765
F7(800@CL=6)
765
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
675
810
72
675
765
72
630
765
72
855
72
315
360
270
108
540
1,035
1,305
1,035
72
855
72
315
360
270
108
540
1,035
1,305
1,035
72
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
315
360
270
108
495
945
1,215
990
72
270
315
270
108
450
810
990
990
72
270
315
270
108
450
765
900
945
72
IDD7
1,935
1,935
1,620
1,620
1,620
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 July 2008
17 of 27
UDIMM
DDR2 SDRAM
(TA=0oC, VDD= 1.9V)
12.5 M391T2953EZ3 : 1GB(64Mx8 *18) ECC Module
Symbol
IDD0
IDD1
E7(800@CL=5)
1,125
1,215
144
F7(800@CL=6)
1,125
1,215
144
E6(667@CL=5)
1,035
1,170
144
D5(533@CL=4)
990
CC(400@CL=3)
945
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,080
144
540
630
540
216
765
1,125
1,305
1,305
144
1,080
144
540
630
540
216
765
1,080
1,215
1,260
144
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
630
720
540
216
630
720
540
216
630
720
540
216
900
900
855
1,395
1,665
1,395
144
1,395
1,665
1,395
144
1,305
1,575
1,350
144
IDD7
2,475
2,475
1,980
1,935
1,935
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 July 2008
18 of 27
UDIMM
DDR2 SDRAM
(VDD=1.8V, VDDQ=1.8V, TA=25oC)
13.0 Input/Output Capacitance
Parameter
Min
Max
Min
Max
Min
Max
Symbol
CCK0
Units
Non-ECC
M378T6553EZS
M378T2953EZ3
M378T3354EZ3
-
-
-
-
-
-
-
24
25
25
42
42
6
-
-
26
28
28
42
42
10
9
-
-
22
24
24
34
34
6
Input capacitance, CK and CK
CCK1
CCK2
Input capacitance, CKE and CS
CI1
-
-
-
-
-
-
-
-
pF
Input capacitance, Addr, RAS, CAS, WE
CI2
CIO(400/533)
CIO(667/800)
Symbol
CCK0
Input/output capacitance, DQ, DM, DQS, DQS
5.5
5.5
ECC
M391T6553EZ3
M391T2953EZ3
Units
-
-
25
25
25
44
-
-
28
28
28
44
Input capacitance, CK and CK
CCK1
CCK2
CI1
Input capacitance, CKE and CS
-
-
pF
CI2
Input capacitance, Addr, RAS, CAS, WE
-
-
-
44
6
-
-
-
44
10
9
CIO(400/533)
CIO(667/800)
Input/output capacitance, DQ, DM, DQS, DQS
5.5
Note : DM is internally loaded to match DQ and DQS identically.
14.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
14.1 Refresh Parameters by Device Density
Parameter
Refresh to active/Refresh command time
Symbol
tRFC
256Mb
75
512Mb
105
1Gb
127.5
7.8
2Gb
195
7.8
4Gb
327.5
7.8
Units
ns
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
7.8
7.8
µs
Average periodic refresh interval
tREFI
3.9
3.9
3.9
3.9
3.9
µs
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tCK, CL=6
tRCD
DDR2-800(E7)
DDR2-800(F7)
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
3 - 3 - 3
5 - 5 - 5
6 - 6 - 6
5 - 5 - 5
4 - 4 - 4
Units
min
5
max
min
-
max
min
5
max
min
5
max
min
5
max
8
-
8
8
8
8
-
8
ns
ns
ns
ns
ns
ns
ns
ns
3.75
2.5
-
8
3.75
3
8
3.75
3
8
3.75
3.75
-
5
8
8
8
8
-
-
-
2.5
15
15
60
45
8
-
-
-
-
12.5
12.5
57.5
45
-
-
15
15
60
45
-
15
-
15
15
55
40
-
tRP
-
-
-
-
-
-
15
-
-
-
tRC
60
-
70000
70000
70000
70000
70000
tRAS
45
Rev. 1.3 July 2008
19 of 27
UDIMM
DDR2 SDRAM
14.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)
(Refer to notes for informations related to this table at the component datasheet)
DDR2-800
DDR2-667
Notes
Parameter
Symbol
Units
min
-400
-350
0.48
0.48
max
400
min
max
450
DQ output access time from CK/CK
DQS output access time from CK/CK
Average clock HIGH pulse width
Average clock LOW pulse width
tAC
-450
-400
0.48
0.48
ps
40
40
tDQSCK
tCH(avg)
tCL(avg)
350
400
ps
0.52
0.52
0.52
0.52
tCK(avg)
tCK(avg)
35,36
35,36
Min(tCL(abs),
tCH(abs))
Min(tCL(abs),
tCH(abs))
CK half pulse period
tHP
x
x
ps
37
Average clock period
tCK(avg)
tDH(base)
tDS(base)
tIPW
2500
8000
3000
8000
ps
ps
35,36
DQ and DM input hold time
125
x
175
x
6,7,8,21,28,31
6,7,8,20,28,31
DQ and DM input setup time
50
x
100
x
ps
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS/DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
0.6
x
0.6
x
tCK(avg)
tCK(avg)
ps
tDIPW
tHZ
0.35
x
0.35
x
x
tAC(max)
x
tAC(max)
18,40
18,40
18,40
13
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC(min)
tAC(max)
tAC(min)
tAC(max)
ps
2* tAC(min)
tAC(max)
2* tAC(min)
tAC(max)
ps
x
x
200
300
x
x
x
240
340
x
ps
ps
38
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
tQH
tHP - tQHS
- 0.25
0.35
0.35
0.2
tHP - tQHS
-0.25
0.35
0.35
0.2
ps
39
tDQSS
tDQSH
tDQSL
tDSS
0.25
x
0.25
x
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
nCK
30
DQS input LOW pulse width
x
x
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
MRS command to ODT update delay
Write postamble
x
x
30
30
tDSH
0.2
x
0.2
x
tMRD
2
x
2
x
tMOD
0
12
0.6
x
0
12
0.6
x
ns
32
10
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
0.4
0.4
tCK(avg)
tCK(avg)
ps
Write preamble
0.35
250
175
0.9
0.35
275
200
0.9
Address and control input hold time
Address and control input setup time
Read preamble
x
x
5,7,9,23,29
5,7,9,22,29
19,41
x
x
ps
1.1
0.6
x
1.1
0.6
x
tCK(avg)
tCK(avg)
ns
Read postamble
0.4
0.4
19,42
Activate to activate command period for 1KB page size products tRRD
Activate to activate command period for 2KB page size products tRRD
7.5
7.5
4,32
10
x
10
x
ns
4,32
Rev. 1.3 July 2008
20 of 27
UDIMM
DDR2 SDRAM
DDR2-800
DDR2-667
Notes
Parameter
Symbol
Units
min
max
min
max
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
35
x
x
x
x
x
x
x
x
x
x
x
37.5
x
x
x
x
x
x
x
x
x
x
x
ns
ns
32
32
45
50
2
2
nCK
ns
Write recovery time
15
15
32
33
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
WR + tnRP
WR + tnRP
nCK
ns
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
7.5
24,32
3,32
32
7.5
7.5
ns
tRFC + 10
tRFC + 10
ns
200
2
200
2
nCK
nCK
nCK
Exit precharge power down to any command
Exit active power down to read command
tXARD
2
2
1
Exit active power down to read command
(slow exit, lower power)
tXARDS
8 - AL
x
7 - AL
x
nCK
1,2
CKE minimum pulse width (HIGH and LOW pulse width)
tCKE
3
2
x
3
2
x
nCK
nCK
ns
27
16
ODT turn-on delay
ODT turn-on
tAOND
tAON
2
2
tAC(min)
tAC(max)+0.7
tAC(min)
tAC(max)+0.7
6,16,40
2*tCK(avg)
2*tCK(avg)
ODT turn-on (Power-Down mode)
tAONPD
tAC(min)+2
tAC(min)+2
ns
+tAC(max)+1
+tAC(max)+1
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
nCK
ns
17,45
tAC(min)
tAC(max)+0.6
tAC(min)
tAC(max)+0.6
17,43,45
2.5*tCK(avg)
+tAC(max)+1
2.5*tCK(avg)
+tAC(max)+1
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
x
x
3
8
0
x
x
nCK
nCK
ns
12
12
32
15
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tIS+tCK(avg)
+tIH
tIS+tCK(avg)
+tIH
tDelay
x
x
ns
Rev. 1.3 July 2008
21 of 27
UDIMM
DDR2 SDRAM
14.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)
(Refer to notes for informations related to this table at the component datasheet)
DDR2-533
DDR2-400
Parameter
Symbol
Units
Notes
min
max
min
-600
-500
0.45
0.45
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK HIGH pulse width
tAC
-500
500
600
ps
ps
tDQSCK
tCH
-450
450
500
0.45
0.55
0.55
tCK
tCK
ps
CK LOW pulse width
tCL
0.45
0.55
0.55
CK half pulse period
tHP
Min(tCL, tCH)
x
Min(tCL, tCH)
x
11,12
15
Clock cycle time, CL=x
tCK
3750
8000
5000
275
8000
ps
DQ and DM input hold time (differential strobe)
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input setup time (single-ended strobe)
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS(/DQS) low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDH(base)
tDS(base)
tDH1(base)
tDS1(base)
tIPW
225
x
x
ps
6,7,8,21,28
6,7,8,20,28
6,7,8,26
6,7,8,25
100
x
150
x
ps
-25
x
25
x
ps
-25
x
25
x
ps
0.6
x
0.6
x
tCK
tCK
ps
tDIPW
tHZ
0.35
x
0.35
x14
x
x
tAC(max)
tAC(max)
18
18
18
13
12
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC(min)
tAC(max)
tAC(min)
2* tAC(min)
x
tAC(max)
ps
2* tAC(min)
tAC(max)
tAC(max)
ps
x
x
300
400
x
350
450
x
ps
x
ps
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
tQH
tHP - tQHS
-0.25
0.35
0.35
0.2
tHP - tQHS
-0.25
0.35
0.35
0.2
ps
tDQSS
tDQSH
tDQSL
tDSS
0.25
x
0.25
x
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS input LOW pulse width
x
x
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
MRS command to ODT update delay
Write postamble
x
x
tDSH
0.2
x
0.2
x
tMRD
2
x
2
x
tMOD
0
12
0.6
x
0
12
0.6
x
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
0.4
0.4
tCK
tCK
ps
10
Write preamble
0.35
375
250
0.9
0.35
475
Address and control input hold time
Address and control input setup time
Read preamble
x
x
5,7,9,23
x
350
x
ps
5,7,9,22
1.1
0.6
x
0.9
1.1
0.6
x
tCK
tCK
ns
19
19
4
Read postamble
0.4
0.4
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
7.5
7.5
tRRD
10
x
10
x
ns
4
Rev. 1.3 July 2008
22 of 27
UDIMM
DDR2 SDRAM
DDR2-533
DDR2-400
Parameter
Symbol
tFAW
Units
Notes
min
37.5
50
max
min
37.5
50
max
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ns
ns
tFAW
tCCD
tWR
2
2
tCK
ns
Write recovery time
15
15
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
WR+tRP
WR+tRP
tCK
ns
14
24
3
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
10
7.5
7.5
ns
tRFC + 10
tRFC + 10
ns
200
2
200
2
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
tXARD
2
2
1
Exit active power down to read command
(slow exit, lower power)
tXARDS
6 - AL
x
6 - AL
x
tCK
1,2
CKE minimum pulse width (HIGH and LOW pulse width)
tCKE
3
2
x
3
2
x
tCK
tCK
ns
27
16
16
ODT turn-on delay
ODT turn-on
tAOND
tAON
2
2
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
2tCK+
2tCK+
ODT turn-on (Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
tAC(max)+1
tAC(max)+1
2.5
2.5
17,44
17,44
tAC(max)
+ 0.6
tAC(max)
+ 0.6
ODT turn-off
tAC(min)
tAC(min)
2.5tCK+
2.5tCK+
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
tAC(min)+2
ns
tAC(max)+1
tAC(max)+1
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
x
x
3
8
0
x
x
tCK
tCK
ns
12
12
32
15
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
tIS+tCK+tIH
x
tIS+tCK+tIH
x
ns
Rev. 1.3 July 2008
23 of 27
UDIMM
DDR2 SDRAM
15.0 Physical Dimensions :
15.1 64Mbx8 based 64Mx64 Module (1 Rank)
- M378T6553EZS
Units : Millimeters
133.35
131.35
128.95
SPD
30.00
(2)
2.50
B
A
2.7
63.00
55.00
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QE
Rev. 1.3 July 2008
24 of 27
UDIMM
DDR2 SDRAM
15.2 64Mbx8 based 64Mx72 Module (1 Rank)
- M391T6553EZ3
Units : Millimeters
133.35
131.35
128.95
ECC
SPD
(for x72)
30.00
(2)
2.50
B
A
2.7
63.00
55.00
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QE
Rev. 1.3 July 2008
25 of 27
UDIMM
DDR2 SDRAM
15.3 64Mbx8 based 128Mx64/x72 Module (2 Ranks)
Units : Millimeters
- M378T2953EZ3/M391T2953EZ3
133.35
131.35
128.95
N/A
(for x64)
SPD
ECC
30.00
(for x72)
(2)
2.50
B
A
4.00
63.00
55.00
N/A
(for x64)
ECC
(for x72)
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QE
Rev. 1.3 July 2008
26 of 27
UDIMM
DDR2 SDRAM
15.4 32Mbx16 based 32Mx64 Module (1 Rank)
- M378T3354EZ3
Units : Millimeters
133.35
131.35
128.95
SPD
30.00
(2)
2.50
B
A
2.7
63.00
55.00
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 32M x16 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51163QE
Rev. 1.3 July 2008
27 of 27
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