M391T5663MZ0-CCC [SAMSUNG]
DRAM, 256MX72, 0.6ns, CMOS, PDMA240;
| 型号： | M391T5663MZ0-CCC |
| 厂家： | 
SAMSUNG |
| 描述： | DRAM, 256MX72, 0.6ns, CMOS, PDMA240 时钟 动态存储器 光电二极管 |
| 文件： | 总21页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 1Gb M-die
64/72-bit Non-ECC/ECC
Revision 0.2
May 2004
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
DDR2 Unbuffered DIMM Ordering Information
Number of
Rank
Part Number
Density Organization
Component Composition
Height Pakage
x64 Non ECC
M378T2863MZ0-CD5/CC
M378T5663MZ0-CD5/CC
1GB
2GB
128Mx64
256Mx64
128Mx8(K4T1G084QM)*8
128Mx8(K4T1G084QM)*16
1
2
30mm
30mm
Lead-Free
Lead-Free
x72 ECC
M391T2863MZ0-CD5/CC
M391T5663MZ0-CD5/CC
1GB
2GB
128Mx72
256Mx72
128Mx8(K4T1G084QM)*9
128Mx8(K4T1G084QM)*18
1
2
30mm
30mm
Lead-Free
Lead-Free
Features
•
Performance range
D5(DDR2-533)
CC(DDR2-400)
Unit
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
-
400
400
-
4-4-4
3-3-3
•
•
•
JEDEC standard 1.8V ± 0.1V Power Supply
VDDQ = 1.8V ± 0.1V
200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
•
•
•
•
•
•
•
•
•
•
•
8 Bank
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination
Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C
•
•
•
Serial presence detect with EEPROM
DDR2 SDRAM Package: 68ball FBGA - 128Mx8
All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
128Mx8(1Gb) based Module
A0-A13
A0-A9
BA0-BA2
A10
x64 DIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Pin
Front
A4
Pin
181
182
183
184
Back
Pin
91
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
V
V
V
V
V
1
DQ19
61
REF
SS
SS
DDQ
SS
V
V
V
2
DQ4
DQ5
DQ28
DQ29
62
A3
A1
92
DQS5
DQS5
SS
SS
DDQ
V
3
DQ0
DQ1
DQ24
DQ25
63
A2
93
SS
V
V
V
V
V
4
64
94
DQ46
DQ47
SS
SS
DD
DD
SS
V
V
5
DM0
NC
DM3
NC
KEY
95
DQ42
DQ43
SS
SS
V
V
6
DQS0
DQS0
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0
96
SS
SS
V
V
V
V
7
97
DQ52
DQ53
SS
SS
SS
SS
V
V
V
V
8
DQ6
DQ7
DQ30
DQ31
98
DQ48
DQ49
SS
SS
DD
DD
V
9
DQ2
DQ3
DQ26
DQ27
NC
A0
99
SS
V
V
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2
SS
SS
DD
DD
SS
V
V
DQ12
DQ13
NC
NC
A10/AP
BA0
BA1
SA2
SS
SS
2
V
V
DQ8
DQ9
NC
NC
NC, TEST
DDQ
SS
V
V
V
V
RAS
S0
DM6
NC
SS
SS
DDQ
SS
V
V
DM1
NC
NC
NC
WE
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
NC
NC
CAS
DDQ
SS
V
V
V
V
ODT0
DQ54
DQ55
SS
SS
DDQ
SS
1
V
V
CK1
CK1
NC
NC
S1
DQ50
DQ51
A13
SS
SS
V
V
NC
NC
NC
NC
ODT1
DD
SS
V
V
V
V
V
DQ60
DQ61
SS
SS
DDQ
SS
SS
V
V
V
V
DQ14
DQ15
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
V
V
DQ10
DQ11
CKE1
DQ32
DQ33
DDQ
SS
V
V
V
V
CKE0
DM7
NC
SS
DD
SS
SS
V
V
V
DQ20
DQ21
DM4
NC
DQS7
DQS7
SS
DD
NC
NC
SS
V
DQ16
DQ17
BA2
NC
DQS4
DQS4
SS
V
V
V
V
DQ62
DQ63
SS
DDQ
SS
SS
V
V
V
DM2
NC
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
A11
A7
DQ34
DQ35
SS
V
V
V
V
VDDSPD
SA0
SS
DD
SS
SS
V
V
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
SS
DQ18
A5
DQ40
DQ41
SA1
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
x72 DIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Pin
Front
Pin
181
182
183
184
Back
Pin
91
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
V
V
V
V
V
1
DQ19
61
A4
REF
SS
SS
DDQ
SS
V
V
V
2
DQ4
DQ5
DQ28
DQ29
62
A3
A1
92
DQS5
DQS5
SS
SS
DDQ
V
3
DQ0
DQ1
DQ24
DQ25
63
A2
93
SS
V
V
V
V
V
4
64
94
DQ46
DQ47
SS
SS
DD
DD
SS
V
V
5
DM0
NC
DM3
NC
KEY
95
DQ42
DQ43
SS
SS
V
V
6
DQS0
DQS0
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0
96
SS
SS
V
V
V
V
7
97
DQ52
DQ53
SS
SS
SS
SS
V
V
V
V
8
DQ6
DQ7
DQ30
DQ31
98
DQ48
DQ49
SS
SS
DD
DD
V
9
DQ2
DQ3
DQ26
DQ27
NC
A0
99
SS
V
V
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2
SS
SS
DD
DD
SS
V
V
DQ12
DQ13
CB4
CB5
A10/AP
BA0
BA1
SA2
SS
SS
2
V
V
DQ8
DQ9
CB0
CB1
DDQ
NC, TEST
SS
V
V
V
V
RAS
S0
DM6
NC
SS
SS
DDQ
SS
V
V
DM1
NC
DM8
NC
WE
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
DQS8
DQS8
CAS
DDQ
SS
V
V
V
V
ODT0
A13
DQ54
DQ55
SS
SS
DDQ
SS
V
V
CK1
CK1
CB6
CB7
S1
DQ50
DQ51
SS
SS
V
V
NC
NC
CB2
CB3
ODT1
DD
SS
V
V
V
V
V
DQ60
DQ61
SS
SS
DDQ
SS
SS
V
V
V
V
DQ14
DQ15
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
V
V
DQ10
DQ11
CKE1
DQ32
DQ33
DDQ
SS
V
V
V
V
CKE0
DM7
NC
SS
DD
SS
SS
V
V
V
DQ20
DQ21
NC
NC
DM4
NC
DQS7
DQS7
SS
DD
SS
V
DQ16
DQ17
BA2
NC
DQS4
DQS4
SS
V
V
V
V
DQ62
DQ63
SS
DDQ
SS
SS
V
V
V
DM2
NC
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
A11
A7
DQ34
DQ35
SS
V
V
V
V
VDDSPD
SA0
SS
DD
SS
SS
V
V
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
SS
DQ18
A5
DQ40
DQ41
SA1
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Description
Pin Name
Description
Pin Name
Description
A0-A13
BA0, BA2
RAS
DDR2 SDRAM address bus
CK0, CK1, CK2
CK0, CK1, CK2
SCL
DDR2 SDRAM clocks (positive line of differential pair)
DDR2 SDRAM clocks (negative line of differential pair)
DDR2 SDRAM bank select
2
DDR2 SDRAM row address strobe
DDR2 SDRAM column address strobe
DDR2 SDRAM wirte enable
DIMM Rank Select Lines
I C serial bus clock for EEPROM
2
CAS
WE
SDA
I C serial bus data line for EEPROM
2
SA0-SA2
I C serial address select for EEPROM
V
*
S0, S1
DDR2 SDRAM core power supply
DDR2 SDRAM I/O Driver power supply
DDR2 SDRAM I/O reference supply
Power supply return (ground)
DD
V
*
CKE0,CKE1
ODT0, ODT1
DQ0 - DQ63
DDR2 SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
DDQ
V
REF
V
SS
V
SPD
CB0 - CB7
DQS0 - DQS8
DM(0-8)
DIMM ECC check bits
Serial EEPROM positive power supply
Spare Pins(no connect)
DD
DDR2 SDRAM data strobes
DDR2 SDRAM data masks
NC
RESET
TEST
Not used on UDIMM
Used by memory bus analysis tools (unused on memory
DIMMs)
DQS0-DQS8
DDR2 SDRAM differential data strobes
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Input/Output Functional Description
Symbol
Type
Function
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing
of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of
CK and CK (Both directions of crossing)
CK0-CK2
CK0-CK2
Input
Activates the SDRAM CK signal when high and deactivates the CK Signal when low. By deactivat-
ing the clocks, CKE low initiates the Power Down mode, or the Self-Refresh mode
CKE0-CKE1
S0-S1
Input
Input
Enables the associated SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but previous oper-
ations continue. This signal provides for external rank selection on systems with multiple ranks
RAS, CAS, WE
ODT0-ODT1
Input
Input
RAS, CAS, and WE (ALONG WITH CS) define the command being entered.
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is
enabled in the Extended Mode Register Set (EMRS).
V
Supply Reference voltage for SSTL 18 inputs.
REF
Power supply for the DDR2 SDRAM output buffers to provide improved noise immunity. For all cur-
Supply
V
DDQ
rent DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA2
A0-A13
Input
Input
Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the column address, In addition to
the column address, AP is used to invoke autoprecharge operation at the end of the burst read or
write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-
charged. If AP is low, autoprecharge is disabled. During a precharge command cycle, AP is used in
conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be
precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to
define which bank to precharge.
DQ0-DQ63
CB0-CB7
In/Out
Input
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident
with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins
are input only, the DM loading matches the DQ and DQS loading.
DM0-DM8
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to
V
,V
Supply
In/Out
Input
DD SS
V
/V
planes on these modules.
DD DDQ
DQS0-DQS8
DQS0-DQS8
Data strobe for input and output data.
These signals and tied at the system planar to either V or V to configure the serial SPD EER-
SS
DD
SA0-SA2
SDA
POM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to VDD to act as a pullup on the system board.
In/Out
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDD to act as a pullup onthe system board.
SCL
Power supply for SPD EEPROM. This supply is separate from the V /V
EEPROM supply is operable from 1.7V to 3.6V.
power plane.
DD DDQ
V
SPD
Supply
DD
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs)
(M378T2863MZ0)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D4
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
NU/ CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
V
V
Serial PD
DDSPD
Serial PD
SCL
* Clock Wiring
/V
D0 - D7
D0 - D7
D0 - D7
DD DDQ
SDA
WP
Clock
Input
DDR2 SDRAMs
VREF
A0
A1
A2
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
V
SA0 SA1 SA2
SS
BA0 - BA2
A0 - A13
RAS
BA0-BA2 : DDR2 SDRAMs D0 - D7
A0-A13 : DDR2 SDRAMs D0 - D7
RAS : DDR2 SDRAMs D0 - D7
CAS : DDR2 SDRAMs D0 - D7
CKE : DDR2 SDRAMs D0 - D7
WE : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D0 - D7
*Wire per Clock Loading
Table/Wiring Diagrams
CAS
Notes :
CKE0
WE
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.
ODT0
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Functional Block Diagram: 1GB, 128Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs)
(M391T2863MZ0)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D4
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
DQS8
DQS8
DM8
Serial PD
SCL
WP
DM
CS DQS DQS
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
D8
SA0 SA1 SA2
* Clock Wiring
V
V
Serial PD
D0 - D8
D0 - D8
D0 - D8
DDSPD
Clock
Input
DDR2 SDRAMs
/V
DD DDQ
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
VREF
BA0 - BA2
A0 - A13
RAS
BA0-BA2 : DDR2 SDRAMs D0 - D8
A0-A13 : DDR2 SDRAMs D0 - D8
RAS : DDR2 SDRAMs D0 - D8
CAS : DDR2 SDRAMs D0 - D8
CKE : DDR2 SDRAMs D0 - D8
WE : DDR2 SDRAMs D0 - D8
ODT : DDR2 SDRAMs D0 - D8
V
SS
*Wire per Clock Loading
Table/Wiring Diagrams
CAS
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.
CKE0
WE
ODT0
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Functional Block Diagram: 2GB, 256Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs)
(M378T5663MZ0)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D8
D4
D12
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D9
D5
D13
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D10
D6
D14
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D11
D7
D15
V
V
Serial PD
DDSPD
Serial PD
/V
D0 - D15
D0 - D15
D0 - D15
DD DDQ
SCL
WP
SDA
VREF
A0
A1
A2
V
* Clock Wiring
SS
SA0 SA1 SA2
Clock
Input
DDR2 SDRAMs
BA0 - BA2
A0 - A13
CKE0
BA0-BA2 : DDR2 SDRAMs D0 - D15
A0-A13 : DDR2 SDRAMs D0 - D15
CKE : DDR2 SDRAMs D0 - D7
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
CKE1
RAS
CAS
CKE : DDR2 SDRAMs D8 - D15
RAS : DDR2 SDRAMs D0 - D15
CAS : DDR2 SDRAMs D0 - D15
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.
WE
ODT0
ODT1
WE : DDR2 SDRAMs D0 - D15
ODT : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D8 - D15
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Functional Block Diagram: 2GB, 256Mx72 ECC Module(Populated as 2 ranks of x8 DDR2 SDRAMs)
(M391T5663MZ0)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D9
D4
D13
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
DQS8
DQS8
DM8
Serial PD
SCL
WP
DM
CS DQS DQS
DM
CS DQS DQS
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
D8
D17
SA0 SA1 SA2
* Clock Wiring
Clock
Input
DDR2 SDRAMs
V
Serial PD
DDSPD
BA0 - BA2
A0 - A13
CKE0
BA0-BA2 : DDR2 SDRAMs D0 - D17
A0-A13 : DDR2 SDRAMs D0 - D17
CKE : DDR2 SDRAMs D0 - D8
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
V
/V
D0 - D17
D0 - D17
D0 - D17
DD DDQ
VREF
CKE1
RAS
CAS
CKE : DDR2 SDRAMs D9 - D17
RAS : DDR2 SDRAMs D0 - D17
CAS : DDR2 SDRAMs D0 - D17
*Wire per Clock Loading
Table/Wiring Diagrams
V
SS
Notes :
WE
ODT0
ODT1
WE : DDR2 SDRAMs D0 - D17
ODT : DDR2 SDRAMs D0 - D8
ODT : DDR2 SDRAMs D9 - D17
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
Notes
1
- 1.0 V ~ 2.3 V
V
V
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
V
VIN VOUT
,
V
1
TSTG
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please
refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
V
V
Supply Voltage
1.7
1.8
1.8
1.9
4
4
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must
be less than or equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Operating Temperature Condition
Symbol
TOPER
Parameter
Rating
0 to 95
Units
Notes
1, 2, 3
Operating Temperature
°C
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to
enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
VIH(DC)
Parameter
Min.
Max.
Units
V
Notes
VREF + 0.125
VDDQ + 0.3
DC input logic high
DC input logic low
VIL(DC)
- 0.3
VREF - 0.125
V
Input AC Logic Level
Symbol
VIH(AC)
Parameter
Min.
Max.
-
Units
V
Notes
VREF + 0.250
AC input logic high
AC input logic low
VIL(AC)
-
VREF - 0.250
V
AC Input Test Conditions
Symbol
Condition
Input reference voltage
Value
Units
Notes
V
V
0.5 * V
1.0
V
V
1
1
REF
DDQ
Input signal maximum peak to peak swing
Input signal minimum slew rate
SWING(MAX)
SLEW
1.0
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
2. The input signal minimum slew rate is to be maintained over the range from V
(AC) level applied to the device under test.
IH/IL
to V (AC) min for rising edges and the range from V
REF
IH
REF
to V (AC) max for falling edges as shown in the below figure.
IL
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on
IL
IH
IH
IL
the negative transitions.
VDDQ
VIH(AC) min
VIH(DC) min
VREF
VSWING(MAX)
VIL(DC) max
VIL(AC) max
VSS
delta TF
V
delta TR
REF - VIL(AC) max
delta TF
VIH(AC) min - VREF
delta TR
Falling Slew =
Rising Slew =
< AC Input Test Signal Waveform >
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
Units
Notes
IDD0
Operating one bank active-precharge current;
t
t
t
t
t
t
mA
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid com-
mands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD
mA
t
= RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
Precharge power-down current;
t
mA
mA
mA
t
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STA-
BLE; Data bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD4W
IDD4R
IDD5B
Operating burst write current;
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
t
t
t
mA
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS
t
t
t
= RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD6
IDD7
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
mA
mA
Low Power
Operating bank interleave read current;
t
t
t
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK =
mA
t
t
t
t
t
t
t
CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;
Refer to the following page for detailed timing conditions
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M378T2863MZ0 : 1GB(128Mx8 *8) Module
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4) (DDR2-400@CL=3)
IDD0
IDD1
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
Normal
IDD7
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M378T5663MZ0 : 2GB(128Mx8 *16) Module
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4) (DDR2-400@CL=3)
IDD0
IDD1
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
Normal
IDD7
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M391T2863MZ0 : 1GB(128Mx8 *9) ECC Module
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4) (DDR2-400@CL=3)
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
IDD6
Normal
IDD7
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M391T2863MZ0 : 2GB(128Mx8 *18) ECC Module
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4) (DDR2-400@CL=3)
IDD0
IDD1
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
Normal
IDD7
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter
Symbol
Min
Max
Min
Max
Units
Non-ECC
M378T2863MZ0
M378T5663MZ0
CCK0
CCK1
CCK2
CI1
-
-
-
-
24
25
25
42
-
-
26
28
28
42
Input capacitance, CK and CK
pF
Input capacitance, CKE and CS
-
-
-
Input capacitance, Addr, RAS, CAS, WE
CI2
-
-
42
6
42
10
Input/output capacitance, DQ, DM, DQS, DQS CIO
ECC
M391T2863MZ0
M391T5663MZ0
CCK0
-
-
25
25
25
44
-
-
28
28
28
44
Input capacitance, CK and CK
CCK1
CCK2
pF
Input capacitance, CKE and CS
CI
-
-
-
-
-
-
1
2
Input capacitance, Addr, RAS, CAS, WE
CI
44
6
44
10
Input/output capacitance, DQ, DM, DQS, DQS CIO
Note: DM is internally loaded to match DQ and DQS identically.
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
195
327.5
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
Average periodic refresh interval
85 °C < T
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-533(D5)
DDR2-400(CC)
Units
4 - 4 - 4
3 - 3 - 3
min
5
max
min
5
max
8
8
-
8
8
-
ns
ns
ns
ns
ns
ns
ns
3.75
-
5
-
15
15
55
40
15
15
55
40
tRP
tRC
70000
70000
tRAS
Timing Parameters by Speed Grade
(Refer to notes for information related to this table at the bottom)
Symbol
Units
Notes
Parameter
DDR2-533
DDR2-400
min
max
min
max
DQ output access time from
CK/CK
tAC
-500
+500
-600
+600
ps
ps
DQS output access time
from CK/CK
tDQSCK
-450
+450
-500
+500
CK high-level width
CK low-level width
CK half period
tCH
tCL
tHP
0.45
0.45
0.55
0.55
x
0.45
0.45
0.55
0.55
x
tCK
tCK
ps
min(tCL,
tCH)
min(tCL,
tCH)
Clock cycle time, CL=x
tCK
tDH
tDS
3750
225
8000
5000
275
8000
ps
ps
ps
DQ and DM input hold time
x
x
x
x
DQ and DM input setup
time
100
150
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Symbol
Units
Parameter
DDR2-533
DDR2-400
min
max
min
max
Control & Address input
pulse width for each input
tIPW
0.6
x
0.6
x
tCK
tCK
ps
DQ and DM input pulse
width for each input
tDIPW
tHZ
0.35
x
0.35
x
Data-out high-impedance
time from CK/CK
x
tAC max
tAC max
tAC max
300
x
tAC max
tAC max
tAC max
350
DQS low-impedance time
from CK/CK
tLZ(DQS)
tLZ(DQ)
tDQSQ
tAC min
2* tACmin
x
tAC min
2* tACmin
x
ps
DQ low-impedance time
from CK/CK
ps
DQS-DQ skew for DQS and
associated DQ signals
ps
DQ hold skew factor
tQHS
tQH
x
400
x
x
450
x
ps
ps
DQ/DQS output hold time
from DQS
tHP - tQHS
tHP - tQHS
Write command to first DQS
latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
x
x
x
0.35
0.35
0.2
x
x
x
tCK
tCK
tCK
DQS falling edge to CK
setup time
DQS falling edge hold time
from CK
tDSH
tMRD
0.2
2
x
x
0.2
2
x
x
tCK
tCK
Mode register set command
cycle time
Write postamble
Write preamble
tWPST
tWPRE
tIH
0.4
0.6
x
0.4
0.6
x
tCK
tCK
ps
0.35
375
0.35
475
Address and control input
hold time
x
x
Address and control input
setup time
tIS
250
x
350
x
ps
Read preamble
Read postamble
tRPRE
tRPST
tRRD
0.9
0.4
7.5
1.1
0.6
x
0.9
0.4
7.5
1.1
0.6
x
tCK
tCK
ns
Active to active command
period for 1KB page size
products
Active to active command
period for 2KB page size
products
tRRD
10
x
10
x
ns
tFAW
tFAW
Four Activate Window for
1KB page size products
37.5
50
2
37.5
50
2
ns
ns
Four Activate Window for
2KB page size products
CAS to CAS command
delay
tCCD
tCK
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Symbol
Units
Parameter
DDR2-533
DDR2-400
min
max
min
max
Write recovery time
tWR
15
x
x
15
x
x
ns
Auto precharge write
tDAL
tWR+tRP
tWR+tRP
tCK
recovery + precharge time
Internal write to read
command delay
tWTR
tRTP
7.5
x
10
x
ns
ns
Internal read to precharge
command delay
7.5
7.5
Exit self refresh to a non-
read command
tXSNR
tXSRD
tXP
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read
command
200
2
200
2
tCK
tCK
tCK
tCK
Exit precharge power down
to any non-read command
x
x
x
x
Exit active power down to
read command
tXARD
tXARDS
2
2
Exit active power down to
read command
6 - AL
6 - AL
(Slow exit, Lower power)
tCKE
CKE minimum pulse width
(high and low pulse width)
tCK
3
3
tAOND
tAON
ODT turn-on delay
ODT turn-on
2
2
2
2
tCK
ns
tAC(min)
tAC(max)
+1
tAC(min)
tAC(max)+
1
tAONPD
ODT turn-on(Power-Down
mode)
tAC(min)+
2
2tCK+tAC
(max)+1
tAC(min)+
2
2tCK+tAC
(max)+1
ns
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
tAC(min)
tAC(max)+
0.6
tAC(max)+
0.6
tAC(min)
tAOFPD
ODT turn-off (Power-Down
mode)
tAC(min)+
2
2.5tCK+
tAC(max)
+1
tAC(min)+
2
2.5tCK+
tAC(max)+
1
ns
ODT to power down entry
latency
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
ODT power down exit
latency
OCD drive mode output
delay
12
12
Minimum time clocks
remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Physical Dimensions: 128Mbx8 based 128Mx64/x72 Module(1 Rank)
(M378/91T2863MZ0)
Units : Millimeters
133.35
131.35
128.95
N/A
(for x64)
SPD
ECC
(for x72)
30.00
(2)
2.50
B
A
2.7
63.00
55.00
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 128M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QM
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Physical Dimensions: 128Mbx8 based 256Mx64/x72 Module(2 Ranks)
(M378/91T5663MZ0)
Units : Millimeters
133.35
131.35
128.95
N/A
(for x64)
SPD
ECC
30.00
(for x72)
(2)
2.50
B
A
4.00
63.00
55.00
N/A
(for x64)
ECC
(for x72)
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 128M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QM
Rev. 0.2 May 2004
Preliminary
DDR2 SDRAM
1GB,2GB Unbuffered DIMMs
Revision History
Revision 0.1 (Mar. 2004)
- Initial Release
Revision 0.2 (May 2004)
- Corrected the Ordering Information
Rev. 0.2 May 2004
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