M390S5658BTU-C7A [SAMSUNG]
Synchronous DRAM Module, 256MX72, 5.4ns, CMOS, DIMM-168;型号: | M390S5658BTU-C7A |
厂家: | SAMSUNG |
描述: | Synchronous DRAM Module, 256MX72, 5.4ns, CMOS, DIMM-168 时钟 动态存储器 内存集成电路 |
文件: | 总26页 (文件大小:659K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
512MB, 1GB, 2GB Registered DIMM
SDRAM
SDRAM Registered Module
168pin Registered Module based on 512Mb B-die
with 72-bit ECC
Revision 1.0
January 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
Revision History
Revision 1.0 (January, 2004)
- First release
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
168Pin Registered DIMM based on 512Mb B-die (x4, x8)
Ordering Information
Component
Package
Part Number
Density
Organization
Component Composition
Height
M390S6553BT1-C7A
M390S6553BTU-C7A
M390S2950BT1-C7A
M390S2950BTU-C7A
M390S2953BT1-C7A
M390S5658BT1-C7A
M390S5658BTU-C7A
512MB
512MB
1GB
64Mx72
64Mx72
64Mx8(K4S510832B) * 9EA
64Mx8(K4S510832B) * 9EA
1,500mil
1,200mil
1,700mil
1,200mil
1,700mil
1,700mil
1,200mil
128Mx4(K4S510432B) * 18EA
128Mx4(K4S510432B) * 18EA
64Mx8(K4S510832B) * 18EA
st.256Mx4(K4S1G0632B) * 18EA
st.256Mx4(K4S1G0632B) * 18EA
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
1GB
54-TSOP(II)
1GB
2GB
2GB
Operating Frequencies
7A
@CL3
133MHz(7.5ns)
3 - 3 - 3
@CL2
Maximum Clock Frequency
CL-tRCD-tRP(clock)
100MHz(10ns)
2 - 2 - 2
Feature
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PIN CONFIGURATIONS (Front side/back side)
Pin
Pin
Front
Pin
Front
Front
Pin
Back
Pin
Back
Pin
Back
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
**CS0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
**CLK0
VSS
DU
**CS2
DQM2
DQM3
DU
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
*VREF
**CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
**CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
**CLK1
A12
VSS
**CKE0
**CS3
DQM6
DQM7
*A13
VDD
NC
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
VDD
DQ52
NC
*VREF
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CB1
VSS
NC
NC
VDD
WE
CB5
VSS
NC
NC
VDD
CAS
DQM4
**CLK2
NC
NC
SDA
SCL
NC
**CLK3
NC
SA0
SA1
SA2
CB6
CB7
VSS
DQ48
DQ49
DQM0
VDD
VDD
Note : 1. * These pins are not used in this module.
2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD.
3. ** About these pins, Refer to the Block Diagram of each.
Pin Description
Pin Name
Function
Address input (Multiplexed)
Select bank
Pin Name
DQM0 ~ 7
Function
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0 ~ 3
CKE0, CKE1
CS0 ~ CS3
RAS
DQM
VDD
Power supply (3.3V)
Ground
Data input/output
VSS
Check bit (Data-in/data-out)
Clock input
*VREF
REGE
SDA
SCL
Power supply for reference
Register enable
Serial data I/O
Serial clock
Clock enable input
Chip select input
Row address strobe
Colume address strobe
Write enable
SA0 ~ 2
DU
Address in EEPROM
Don′t use
CAS
WE
NC
No connection
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
A0 ~ A12
Address
Column address : (x4 : CA0 ~ CA9, CA11, CA12), (x8 : CA0 ~ CA9, CA11)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
REGE
Register enable
DQ0 ~ 63
CB0 ~ 7
VDD/VSS
Data input/output
Check bit
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power supply/ground
Power and ground for the input buffers and the core logic.
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
512MB, 64Mx72 ECC Module (M390S6553BT1) (Populated as 1 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
BCKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
•
D0
D1
D2
D3
•
•
•
•
•
•
•
B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE
BDQM0
DQ0~7
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
DQ8~15
CB0~7
10Ω
PCLK1
•
•
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM1
•
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BCS2
•
•
BDQM2
DQ16~23
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
PCLK3
•
D4
D5
•
BDQM3
DQ24~31
DQ32~39
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
•
BDQM4
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
D7
D8
•
BDQM5
DQ40~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
•
•
BDQM6
DQ48~55
DQ56~63
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM7
10Ω
VSS
VDD
B0A0~B0A9
10
Ω
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
A0~A9
74ALVCF162835
CLK1,2,3
CLK0
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
12pF
RAS,CAS,WE
DQM0,1,4,5
CS0
CDCF2509
PCLK0
PCLK1
PCLK2
PCLK3
10
Ω
LE
REGE
CLK
OE
FBOUT
FIBIN
12pF
PCLK2
10kΩ
Cb*1
VDD
Note
1. The actual values of Cb will depend upon the PLL chosen.
74ALVCF162835
A10,A11,A12,BA0~1
CS2
B0A10,B0A11,B0A12,BBA0~1
BCS2
BCKE0
BDQM2,3,6,7
Serial PD
SCL
CKE0
DQM2,3,6,7
WP
SDA
A0 A1 A2
47K
Ω
LE
OE
SA0 SA1 SA2
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
512MB, 64Mx72 ECC Module (M390S6553BTU) (Populated as 1 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
D0
D1
D2
D3
•
•
•
BCKE0
B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE
BDQM0
•
•
•
•
DQ0~7
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
PCLK1
DQ8~15
10Ω
PCLK2
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM1
•
CB0~7
10Ω
PCLK3
BCS2
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
•
•
BDQM2
DQ16~23
10Ω
PCLK4
•
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D4
D5
•
•
BDQM3
DQ24~31
DQ32~39
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
BDQM4
10
Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
D7
D8
•
•
BDQM5
DQ40~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
BDQM6
DQ48~55
DQ56~63
10
Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM7
10
Ω
VSS
VDD
B0A0~B0A6
10
Ω
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
A0~A6
74ALVCF162835
PCLK4
PCLK5
CLK1,2,3
CLK0
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
12pF
RAS,CAS,WE
DQM0,1,4,5
CS0
CDCF2509
PCLK0
PCLK1
PCLK2
PCLK3
10
Ω
LE
REGE
CLK
OE
FBOUT
FIBIN
12pF
PCLK2
10kΩ
Cb*1
Note
1. The actual values of Cb will depend upon the PLL chosen.
VDD
74ALVCF162835
A7~A12,BA0~1
CS2
B0A7~B0A12,BBA0~BBA1
BCS2
Serial PD
SCL
CKE0
DQM2,3,6,7
BCKE0
BDQM2,3,6,7
WP
SDA
A0 A1 A2
47KΩ
LE
OE
SA0 SA1 SA2
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
1GB 128Mx72 ECC Module (M390S2950BT1) (Populated as 1 bank of x4 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
B0CKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0
D1
D2
D3
D9
D10
D11
D12
D13
D14
D15
D16
D17
B1CKE0
BDQM4
B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE
BDQM0
DQ0~3
DQ32~35
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
DQ4~7
DQ36~39
DQ40~43
10Ω
PCLK1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM1
BDQM5
10
DQ8~11
10Ω
Ω
PCLK2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
DQ12~15
DQ44~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4
10Ω
CB4~7
CB0~3
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK3
BCS2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5
D6
D7
D8
DQ48~51
DQ16~19
DQ20~23
DQ24~27
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM6
DQ52~55
DQ56~59
DQ60~63
BDQM2
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK5
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM7
10
B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE
BDQM3
DQ28~31
Ω
10Ω
VSS
VDD
A3~A10,BA0
B0A3~B0A10,B0BA0
B1A3~B1A10,B1BA0
10
Ω
IY0
IY1
IY2
IY3
IY4
2Y0
2Y1
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
74ALVCF162835
CLK1,2,3
CLK0
V
DD
12pF
CDCF2510
10k
Ω
PCLK6
REGE
10
Ω
OE
LE
LE
LE
CLK
FIBIN
FBOUT
12pF
B0A11.B0A12.B0BA1
B1A11.B1A12.B1BA1
BCS2
B0CKE0
B1CKE0
A11,A12,BA1
74ALVCF162835
Cb*1
CS2
CKE0
Note
DQM2,3,6,7
BDQM2,3,6,7
1. The actual values of Cb will depend upon the PLL chosen.
OE
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0
A0,A1,A2
Serial PD
SCL
74ALVCF162835
RAS,CAS,WE
WP
SDA
A0 A1 A2
CS0
DQM0,1,4,5
47K
Ω
BDQM0,1,4,5
SA0 SA1 SA2
OE
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
1GB 128Mx72 ECC Module (M390S2950BTU) (Populated as 1 bank of x4 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
B0CKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0
D1
D2
D3
D9
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE
BDQM0
DQ0~3
BDQM4
DQ32~35
10Ω
10Ω
PCLK1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D10
D11
D12
10Ω
DQ4~7
DQ36~39
DQ40~43
10Ω
PCLK2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM1
BDQM5
10Ω
DQ8~11
DQ12~15
CB0~3
10Ω
PCLK3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
DQ44~47
CB4~7
10Ω
PCLK4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4
D13
10Ω
10Ω
PCLK5
BCS2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5
D6
D7
D8
D14
D15
D16
D17
BDQM6
BDQM2
DQ48~51
DQ52~55
DQ16~19
DQ20~23
DQ24~27
10Ω
10Ω
PCLK6
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
10Ω
PCLK7
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM3
BDQM7
DQ56~59
DQ60~63
10Ω
10Ω
PCLK8
BCS2
B1CKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE
DQ28~31
10Ω
10Ω
VSS
VDD
A0~A12,BA0~1, RAS, CAS
CKE0
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS
B0CKE0
74ALVCF162835
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9
PCLK9
PCLK5
PCLK6
PCLK7
PCLK8
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
10
Ω
V
DD
B1CKE0
CLK1,2,3
10k
Ω
12pF
PCLK9
REGE
CDCF2510
OE
LE
LE
LE
10
Ω
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS
CLK
FIBIN
CLK0
74ALVCF162835
FBOUT
12pF
Cb*1
Note
OE
1. The actual values of Cb will depend upon the PLL chosen.
Serial PD
SCL
74ALVCF162835
B0WE
B1WE
WE
WP
SDA
A0 A1 A2
47KΩ
DQM0~7,CS0,CS2
BDQM0~7, BCS0,BCS2
OE
SA0 SA1 SA2
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
1GB, 128Mx72 ECC Module (M390S2953BT1) (Populated as 2 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
B0CKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0
D1
D2
D3
D9
D10
D11
D12
D13
D14
D15
D16
D17
B1CKE0
BDQM4
B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE
BDQM0
DQ0~3
DQ32~35
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
DQ4~7
DQ8~11
DQ36~39
DQ40~43
10Ω
PCLK1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM5
10
BDQM1
10Ω
Ω
PCLK2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
DQ12~15
DQ44~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4
10Ω
CB4~7
CB0~3
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK3
BCS2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5
D6
D7
D8
DQ48~51
DQ52~55
DQ16~19
DQ20~23
DQ24~27
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM6
BDQM2
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
DQ56~59
DQ60~63
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK5
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM7
10
B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE
BDQM3
DQ28~31
Ω
10Ω
VSS
VDD
A3~A10,BA0
B0A3~B0A10,B0BA0
B1A3~B1A10,B1BA0
10
Ω
IY0
IY1
IY2
IY3
IY4
2Y0
2Y1
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
74ALVCF162835
CLK1,2,3
CLK0
V
DD
12pF
CDCF2510
10k
Ω
PCLK6
REGE
10
Ω
OE
LE
LE
LE
CLK
FIBIN
FBOUT
12pF
B0A11.B0A12.B0BA1
B1A11.B1A12.B1BA1
BCS2
B0CKE0
B1CKE0
A11,A12,BA1
74ALVCF162835
Cb*1
CS2
CKE0
Note
DQM2,3,6,7
BDQM2,3,6,7
1. The actual values of Cb will depend upon the PLL chosen.
OE
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0
A0,A1,A2
Serial PD
SCL
74ALVCF162835
RAS,CAS,WE
WP
SDA
A0 A1 A2
CS0
DQM0,1,4,5
47K
Ω
BDQM0,1,4,5
SA0 SA1 SA2
OE
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
2GB, 256Mx72 ECC Module (M390S5658BT1) (Populated as 2 bank of x4 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
BCS1,B2CKE0
BCS0,B0CKE0
PCLK0
CLK
CLK
CLK
CLK
CS1,CKED0L
CS0,CKED0U
CS0,CKE D9L
CS1,CKED9U
B0RAS,B0CAS,B0WE,B0BA0,B0BA1
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
B0A0~B0A12
BDQM0
BDQM4
DQ32~35
DQ0~3
10Ω
10Ω
10Ω
PCLK1
CLK
CLK
CLK
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
CS1,CKED1L
CS0,CKED1U
CS0,CKED10L
D10U
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
DQ4~7
DQ36~39
10Ω
PCLK2
CLK
CLK
CLK
CLK
CS1,CKE
CS0,CKED11L
D11U
CS1,CKED2L
CS0,CKED2U
CTL
CTL
CTL
CTL
Add
DQM
DQ0~3
Add
DQM
DQ0~3
Add
DQM
DQ0~3
Add
DQM
DQ0~3
BDQM5
DQ40~43
BDQM1
DQ8~11
DQ12~15
CB0~3
10Ω
PCLK3
10Ω
10Ω
10Ω
CLK
CLK
CLK
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
CS0,CKED12L
D12U
CS1,CKED3L
CS0,CKED3U
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
DQ44~47
CB4~7
10Ω
PCLK4
CLK
CLK
CLK
CLK
CS1,CKED4L
CS0,CKED4U
CS0,CKED13L
CS1,CKED13U
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
10Ω
BCS3,B3CKE0
BCS2,B1CKE0
PCLK5
CLK
CLK
CLK
CLK
CS1,CKE
CS1,CKED5L
CS0,CKED5U
CS0,CKED14L
D14U
CTL
CTL
CTL
CTL
Add
DQM
DQ0~3
Add
DQM
DQ0~3
Add
DQM
DQ0~3
Add
DQM
DQ0~3
BDQM2
BDQM6
DQ48~51
DQ16~19
10Ω
10Ω
10Ω
PCLK6
CLK
CS1
CTL
Add
DQM
DQ0~3
CLK
CLK
CLK
D6L
CS0,CKED6U
CS0,CKE D15L
CS1,CKED15U
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
DQ20~23
DQ24~27
DQ52~55
10Ω
PCLK7
CLK
CLK
CS1,CKE
CLK
CLK
CS0,CKED16L
D16U
CS1,CKED7L
CS0,CKED7U
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
CTL
Add
DQM
DQ0~3
BDQM7
DQ56~59
BDQM3
10Ω
PCLK8
10Ω
CLK
CLK
CS1,CKE
CLK
CLK
CS0,CKED17L
D17U
CS1,CKED8L
CS0,CKED8U
B1RAS,B1CAS,B1WE,B1BA0,B1BA1
B1A0~B1A12
CTL
Add
CTL
Add
CTL
Add
CTL
Add
DQM
DQ0~3
DQM
DQ0~3
DQM
DQ0~3
DQM
DQ0~3
DQ28~31
DQ60~63
10Ω
10Ω
VSS
VDD
B0A3~B0A10,B0BA0
B1A3~B1A10,B1BA0
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
PCLK8
PCLK9
A3~A10,BA0
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
10Ω
74ALVCF162835
CLK1,2,3
VDD
10kΩ
12pF
CDCF2510
10Ω
PCLK9
REGE
OE
LE
CLK
CLK0
FBOU
FBIN
B0A11,B0A12.B0BA1
B1A11,B1A12.B1BA1
12pF
A11,A12,BA1
74ALVCF162835
BCS2,BCS3
Cb*1
CS2,CS3
CKE0
B0CKE0,B1CKE0
B2CKE0,B3CKE0
BDQM2,3,6,7
Note
DQM2,3,6,7
1. The actual values of Cb will depend upon the PLL chosen.
OE
LE
Serial PD
SCL
A0,A1,A2
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0,BCS1
74ALVCF162835
WP
SDA
RAS,CAS,WE
A0 A1 A2
47KΩ
CS0,CS1
DQM0,1,4,5
SA0 SA1 SA2
BDQM0,1,4,5
OE
LE
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
2GB, 256Mx72 ECC Module (M390S5658BTU) (Populated as 2 bank of x4 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
BCS1
PCLK0
BCS0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0L
D1L
D2L
D3L
D0U
D9L
D9
B0CKE0
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE
BDQM4
BDQM0
DQ0~3
DQ32~35
10Ω
10Ω
PCLK1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D1U
D10L
D11L
D12L
D10
D11
D12
10Ω
DQ4~7
DQ8~11
DQ12~15
CB0~3
DQ36~39
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK2
D2U
BDQM1
BDQM5
DQ40~43
10Ω
10Ω
D3U
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK3
10Ω
DQ44~47
10
Ω
PCLK4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4L
D4U
D13L
D13
10Ω
CB4~7
10Ω
PCLK5
BCS2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5L
D6L
D7L
D8L
D14L
D15L
D16L
D17L
D5U
D14
D15
D16
D17
BDQM2
BDQM6
DQ48~51
DQ16~19
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK6
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D6U
DQ52~55
DQ20~23
DQ24~27
10
Ω
10Ω
PCLK7
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D7U
BDQM3
BDQM7
DQ56~59
10Ω
10Ω
PCLK8
BCS2
B1CKE0
CLK
CS
CKE
CLK
CS
CKE
CLK
CS
CKE
CLK
CS
CKE
D8U
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE
Add,CTL
DQM
DQ0~3
Add,CTL
DQM
DQ0~3
Add,CTL
DQM
DQ0~3
Add,CTL
DQM
DQ0~3
BDQM7
BDQM0
DQ60~63
DQ28~31
10Ω
10
Ω
BCS3
VSS
VDD
A0~A12,BA0~1, RAS, CAS
CKE0
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS
B0CKE0
74ALVCF162835
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9
PCLK9
10
Ω
V
DD
PCLK5
PCLK6
PCLK7
PCLK8
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
B1CKE0
CLK1,2,3
10k
Ω
12pF
PCLK9
REGE
CDCF2510
OE
LE
LE
LE
10
Ω
CLK
CLK0
Note
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS
74ALVCF162835
FIBIN
FBOUT
12pF
Cb*1
OE
1. The actual values of Cb will depend upon the PLL chosen.
Serial PD
SCL
74ALVCF162835
B0WE,B0CKE1
B1WE,B1CKE1
WE
WP
SDA
A0 A1 A2
47K
Ω
DQM0~7,CS0~3
BDQM0~7, BCS0~3
OE
SA0 SA1 SA2
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
REG
*1
DOUT
Control Signal(RAS,CAS,WE)
*3
*1. Register Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
1CLK
tSAC
tRAC(refer to *1)
tRAC(refer to *2)
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
DQ
CAS latency(refer to *2)
=2CLK
tRDL
Row Active
Precharge
Command
Write
Command
Row Active
Read
Command
Precharge
Command
td, tr = Delay of register
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register. Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don′t care
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
Unit
V
-1.0 ~ 4.6
V
-55 ~ +150
1.0 * # of component
50
°C
W
Power dissipation
PD
Short circuit current
IOS
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input high voltage
Input low voltage
3.0
VDDQ+0.3
V
1
VIL
0
-
0.8
-
V
2
Output high voltage
Output low voltage
Input leakage current
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE(Max.) (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
M390S6553BT1 M390S2950BT1
M390S6553BTU M390S2950BTU
M390S5658BT1
M390S5658BTU
Parameter
Symbol
M390S2953BT1
Unit
Input capacitance (A0 ~ A11)
CIN1
CIN2
15
15
15
23
15
15
15
16
16
15
15
15
20
15
15
15
16
16
19
19
33
12
12
12
12
19
19
15
15
15
20
15
15
15
22
22
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0)
CIN3
Input capacitance (CLK0)
CIN4
Input capacitance (CS0, CS2)
CIN5
Input capacitance (DQM0 ~ DQM7)
Input capacitance (BA0 ~ BA1)
Data input/output capacitance(DQ0~DQ63)
Data input/ouput capacitance (CB0~CB7)
CIN6
CIN7
COUT1
COUT2
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
DC CHARACTERISTICS
M390S6453BTU(1) (64M x 72, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
Operating current
(One bank active)
ICC1
1,310
mA
mA
1
ICC2P
ICC2PS
370
20
Precharge standby current
in power-down mode
ICC2N
530
95
Precharge standby current
in non power-down mode
mA
ICC2NS
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
405
60
Active standby current in
power-down mode
mA
mA
mA
ICC3N
620
230
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
tRC ≥ tRC(min)
ICC4
1,400
mA
1
2
Refresh current
Self refresh current
ICC5
ICC6
2,300
405
mA
mA
CKE ≤ 0.2V
M390S2950BTU(1) (256M x 72, 2GB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
mA
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
2,030
1
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
490
40
Precharge standby current
in power-down mode
mA
ICC2N
710
190
Precharge standby current
in non power-down mode
mA
ICC2NS
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
460
110
Active standby current in
power-down mode
mA
mA
mA
ICC3N
890
455
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
tRC ≥ tRC(min)
ICC4
2,120
mA
1
2
Refresh current
Self refresh current
ICC5
ICC6
4,100
460
mA
mA
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
DC CHARACTERISTICS
M390S2953BT1 (128M x 72, 1GB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
Operating current
(One bank active)
ICC1
1,445
mA
mA
1
ICC2P
ICC2PS
390
40
Precharge standby current
in power-down mode
ICC2N
710
185
Precharge standby current
in non power-down mode
mA
ICC2NS
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
460
110
Active standby current in
power-down mode
mA
mA
mA
ICC3N
800
455
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
tRC ≥ tRC(min)
ICC4
1,625
mA
1
2
Refresh current
Self refresh current
ICC5
ICC6
2,345
405
mA
mA
CKE ≤ 0.2V
M390S5658BTU(1) (128M x 72, 1GB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
mA
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
2,570
1
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
425
75
Precharge standby current
in power-down mode
mA
ICC2N
1,070
365
Precharge standby current
in non power-down mode
mA
ICC2NS
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
570
220
Active standby current in
power-down mode
mA
mA
mA
ICC3N
1,430
905
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
tRC ≥ tRC(min)
ICC4
2,660
mA
1
2
Refresh current
Self refresh current
ICC5
ICC6
4,640
570
mA
mA
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
7A
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
15
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
45
ns
Row active time
100
us
Row cycle time
65
ns
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + tRP
1
1
1
2
1
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
7A
Parameter
Symbol
Unit
ns
Note
1
Min
7.5
10
Max
CAS latency=3
CLK cycle
time
tCC
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5.4
6
CLK to valid
output delay
tSAC
ns
1,2
2
3
Output data
hold time
tOH
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
A0 ~ A9,
A11, A12
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
Mode register set
Register
Refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
Auto refresh
H
L
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
L
Read &
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
4
4,5
4
Column
L
L
H
H
L
L
H
L
column address
address
H
L
Write &
Column
address
H
X
X
V
column address
H
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 64Mx72 (M390S6553BT1)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
PLL
REG
REG
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
0.123 ± 0.005
0.008 ± 0.006
(3.125 ± 0.125)
(3.125 ± 0.125)
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S510832B
This module is based on JEDEC PC133 Specification
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 64Mx72 (M390S6553BTU)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
R 0.079
(1.372)
5.014
0.118
(3.000)
(R 2.000)
(127.350)
0.157 ± 0.004
(4.000 ± 0.100)
PLL
REG
REG
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
0.123 ± 0.005
0.008 ± 0.006
(3.125 ± 0.125)
(3.125 ± 0.125)
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S510832B
This module is based on JEDEC PC133 Specification
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 128Mx72 (M390S2950BT1)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
REG
REG
PLL
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 SDRAM, TSOPII
SDRAM Part No. : K4S510432B
This module is based on JEDEC PC133 Specification
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 128Mx72 (M390S2950BTU)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
R 0.079
5.014
0.118
(R 2.000)
(127.350)
(3.000)
0.157 ± 0.004
PLL
(4.000 ± 0.100)
REG
REG
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 SDRAM, TSOPII
SDRAM Part No. : K4S510432B
This module is based on JEDEC PC133 Specification
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 128Mx72 (M390S2953BT1)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
REG
REG
PLL
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ±0.006
(0.200 ±0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances :± 0.005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S510832B
This module is based on JEDEC PC133 Specification
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 256Mx72 (M390S5658BT1)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
REG
REG
PLL
B
C
A
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.254 Max
(6.452 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
SDRAM Part No. : K4S1G0632B
- The used device is stacked 256Mx4 SDRAM, TSOPII
- Staktek’s stacking technology is Samsung’s stacking technology of choice
This module is based on JEDEC PC133 Specification
Rev. 1.0 January 2004
512MB, 1GB, 2GB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 256Mx72 (M390S5658BTU)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
R 0.079
5.014
0.118
(R 2.000)
(127.350)
(3.000)
0.157 ± 0.004
PLL
(4.000 ± 0.100)
REG
REG
B
C
A
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.254 Max
(6.452 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
SDRAM Part No. : K4S1G0632B
- The used device is stacked 256Mx4 SDRAM, TSOPII
- Staktek’s stacking technology is Samsung’s stacking technology of choice
This module is based on JEDEC PC133 Specification
Rev. 1.0 January 2004
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