M366S3253BTS [SAMSUNG]

32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD; 基于32Mx8 ， 4Banks ， 8K刷新， 3.3V同步DRAM与SPD 32Mx64 SDRAM DIMM


型号：	M366S3253BTS
厂家：	SAMSUNG
描述：	32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD 基于32Mx8 ， 4Banks ， 8K刷新， 3.3V同步DRAM与SPD 32Mx64 SDRAM DIMM 光电二极管动态存储器
文件：	总10页 (文件大小：157K)
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M366S3253BTS

PC133 Unbuffered DIMM

Revision History

Revision 0.0 (May, 2000)

• PC133 first published.

Revision 0.1 (July, 2000)

• Added PC100@CL3 data on DC Characteristics, Operating AC Parameter, AC Characteristics.

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

M366S3253BTS SDRAM DIMM

32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

GENERAL DESCRIPTION

FEATURE

The Samsung M366S3253BTS is a 32M bit x 64 Synchronous

Dynamic RAM high density memory module. The Samsung

M366S3253BTS consists of eight CMOS 32M x 8 bit with 4banks

Synchronous DRAMs in TSOP-II 400mil package and a 2K

EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy sub-

strate. Two 0.1uF decoupling capacitors are mounted on the

printed circuit board in parallel for each SDRAM.

• Performance range

Part No.

Max Freq. (Speed)

M366S3253BTS-C75

PC133@CL3 & PC100@CL3

• Burst mode operation

• Auto & self refresh capability (8192 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V ± 0.3V power supply

The M366S3253BTS is a Dual In-line Memory Module and is

intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of

system clock. I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable latencies allows

the same device to be useful for a variety of high bandwidth, high

performance memory system applications.

• MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB : Height (1,375mil), single sided component

PIN CONFIGURATIONS (Front side/back side)

PIN NAMES

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

Pin Name

A0 ~ A12

BA0 ~ BA1

DQ0 ~ DQ63

CLK0, CLK2

CKE0

Function

Address input (Multiplexed)

Select bank

VSS

29 DQM1 57 DQ18 85

VSS 113 DQM5 141 DQ50

DQ0 30

DQ1 31

DQ2 32

DQ3 33

CS0

VSS

DQ19 86 DQ32 114 *CS1 142 DQ51

Data input/output

Clock input

VDD

87 DQ33 115 RAS 143 VDD

DQ20 88 DQ34 116 VSS 144 DQ52

*VREF 90

89 DQ35 117

VDD 118

145 NC

146 *VREF

147 NC

148 VSS

149 DQ53

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

VDD

CS0, CS2

RAS

DQ4 35

DQ5 36

DQ6 37

63 *CKE1 91 DQ36 119

65 DQ21 93 DQ38 121

VSS

92 DQ37 120

CAS

10 DQ7 38 A10/AP

DQ22 94 DQ39 122 BA0 150 DQ54

67 DQ23 95 DQ40 123 A11 151 DQ55

69 DQ24 97 DQ41 125 *CLK1 153 DQ56

71 DQ26 99 DQ43 127 VSS 155 DQ58

11 DQ8 39

12 40

13 DQ9 41

BA1

VDD

DQM0 ~ 7

VDD

DQM

VSS

VSS 124 VDD 152 VSS

Power supply (3.3V)

Ground

14 DQ10 42 CLK0

DQ25 98 DQ42 126 A12 154 DQ57

VSS

15 DQ11 43

16 DQ12 44

17 DQ13 45

VSS

CS2

*VREF

Power supply for reference

Serial data I/O

DQ27 100 DQ44 128 CKE0 156 DQ59

VDD 101 DQ45 129 *CS3 157 VDD

DQ28 102 VDD 130 DQM6 158 DQ60

SDA

VDD

46 DQM2

SCL

Serial clock

19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61

SA0 ~ 2

Address in EEPROM

Write protection

Don¢t use

77 DQ31 105 *CB4 133 VDD 161 DQ63

79 CLK2 107 VSS 135 NC 163 *CLK3

20 DQ15 48

21 *CB0 49

22 *CB1 50

VDD

DQ30 104 DQ47 132 *A13 160 DQ62

VSS 106 *CB5 134 NC 162 VSS

VSS

VDD

No connection

53 *CB3 81

52 *CB2

NC 108 NC 136 *CB6 164 NC

WP 109 NC 137 *CB7 165 **SA0

**SDA 110 VDD 138 VSS 166 **SA1

These pins are not used in this module.

** These pins should be NC in the system

VSS

55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2

which does not support SPD.

28 DQM0 56 DQ17

VDD 112 DQM4 140 DQ49 168 VDD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

PIN CONFIGURATION DESCRIPTION

Name

System clock

Input Function

CLK

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock enable

CKE should be enabled 1CLK+tSS prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9

A0 ~ A12

BA0 ~ BA1

RAS

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

DQM0 ~ 7

DQ0 ~ 63

Data input/output mask

Data input/output

Data inputs/outputs are multiplexed on the same pins.

WP pin is connected to VSS through 47KW Resistor.

When WP is "high", EEPROM Programming will be inhibited and the entire memory will

be write-protected.

Write protection

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

FUNCTIONAL BLOCK DIAGRAM

CS0

DQM0

DQM4

DQM CS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQM5

DQM CS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ0

DQ1

DQ8

DQ9

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS2

DQM2

DQM6

DQM CS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ0

DQ1

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM3

DQM7

DQM CS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ0

DQ1

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Serial PD

SDA

SDRAM U0 ~ U7

A0 ~ An, BA0 & 1

SCL

A0 A1 A2

RAS

CAS

47KW

SA0 SA1 SA2

U0/U2

U4/U6

U1/U3

U5/U7

10W

CKE0

CLK0/2

10W

DQn

Every DQpin of SDRAM

3.3pF

VDD

CLK1/3

Two 0.1uF Capacitors

per each SDRAM

10pF

To all SDRAMs

Vss

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

Unit

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

Typ

Max

Unit

Note

3.3

3.6

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

3.0

VDDQ+0.3

VIL

0.8

VOH

IOH = -2mA

IOL = 2mA

VOL

0.4

ILI

-10

Notes :

1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Symbol

Min

Max

Unit

Address (A0 ~ A12, BA0 ~ BA1)

RAS, CAS, WE

CADD

CIN

CKE (CKE0)

CCKE

CCLK

CCS

Clock (CLK0, CLK2)

CS (CS0, CS2)

DQM (DQM0 ~ DQM7)

DQ (DQ0 ~ DQ63)

CDQM

COUT

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Version

Parameter

Symbol

Test Condition

Unit Note

-75

tCC=7.5ns

tCC=10ns

Burst length =1

tRC ³ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

960

880

ICC2P

CKE £ VIL(max), tCC = 10ns

Precharge standby current in

power-down mode

ICC2PS CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

ICC2N

128

112

Input signals are changed one time during 20ns

Precharge standby current

in non power-down mode

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

ICC2NS

Input signals are stable

ICC3P

CKE £ VIL(max), tCC = 10ns

Active standby current

in power-down mode

ICC3PS CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

ICC3N

240

200

Active standby current

in non power-down mode

(One bank active)

Input signals are changed one time during 20ns

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

ICC3NS

Input signals are stable

IO = 0 mA

Operating current

(Burst mode)

Page burst

4Banks activated

tCCD = 2CLKs

ICC4

1,120

1,760

920

Refresh current

ICC5

ICC6

tRC ³ tRC(min)

CKE £ 0.2V

1,680

Self refresh current

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

Input timing measurement reference level

Input rise and fall time

tr/tf = 1/1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200W

50W

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50W

50pF

870W

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-75

tCC=7.5ns

tCC=10ns

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

Row precharge time

tRAS(min)

tRAS(max)

tRC(min)

Row active time

100

Row cycle time

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

tRDL(min)

tDAL(min)

tCDL(min)

tBDL(min)

tCCD(min)

CLK

2 CLK + 20 ns

CLK

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

-75

Parameter

Symbol

Unit

Note

tCC=7.5ns

tCC=10ns

Max

Min

Max

Min

CLK cycle time

CAS latency=3

tCC

7.5

1000

6.0

CLK to valid

output delay

CAS latency=3

tSAC

5.4

1,2

Output data

hold time

tOH

3.0

1,2

CLK high pulse width

CLK low pulse width

Input setup time

tCH

tCL

2.5

1.5

0.8

3.0

tSS

tSH

tSLZ

Input hold time

CLK to output in Low-Z

CLK to output

in Hi-Z

CAS latency=3

tSLZ

5.4

6.0

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

SIMPLIFIED TRUTH TABLE

A12, A11,

A9 ~ A0

CKEn-1 CKEn

RAS

CAS

DQM BA0,1

A10/AP

Note

Command

Refresh

Mode register set

Auto refresh

OP code

1,2

Entry

Self

refresh

Exit

Bank active & row addr.

Row address

Column

address

(A0 ~ A9)

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

4,5

Column

address

(A0 ~ A9)

Write &

column address

4,5

Burst stop

Precharge

Bank selection

All banks

Entry

Clock suspend or

active power down

Exit

Entry

Precharge power down mode

Exit

DQM

No operation command

(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

REV. 0.1 July. 2000

M366S3253BTS

PC133 Unbuffered DIMM

PACKAGE DIMENSIONS

Units : Inches (Millimeters)

5.250

(133.350)

0.089

(2.26)

R 0.050+0.04

(R 1.27+0.1)

R 0.079

5.014

0.118

(3.000)

(127.350)

0.125

(3.175)

0.375

(R 2.000)

(9.525)

0.157 ± 0.004

(4.000 ± 0.100)

0.096

(2.44)

.118DIA ± 0.004

(3.000DIA ± 0.100)

0.250

(6.350)

0.250

(6.350)

0.350

(8.890)

1.450

(36.830)

2.150

(54.61)

.450

(11.430)

4.550

(115.57)

0.100 Max

(2.54 Max)

0.050 ± 0.0039

(1.270 ± 0.10)

0.250

(6.350)

0.250

(6.350)

0.039 ± 0.002

(1.000 ± 0.050)

0.123 ± 0.005

(3.125 ± 0.125)

0.123 ± 0.005

(3.125 ± 0.125)

0.008 ± 0.006

(0.200 ± 0.150)

0.050

(1.270)

0.079 ± 0.004

(2.000 ± 0.100)

0.079 ± 0.004

(2.000 ± 0.100)

Detail A

Detail B

Detail C

Tolerances : ± .005(.13) unless otherwise specified

The used device is 32Mx8 SDRAM, TSOP

SDRAM Part No. : K4S560832B-TC75

REV. 0.1 July. 2000

M366S3253BTS [SAMSUNG]

相关型号：

M366S3253BTS-C75

M366S3253CTS

M366S3253CTS-C1H

M366S3253CTS-C1L

M366S3253CTS-C7A

M366S3253CTS-C7C

M366S3253CTS-L1H

M366S3253CTS-L1L

M366S3253CTS-L7A

M366S3253CTS-L7C

M366S3253DTS

M366S3253DTS-C7A