KM732V589A [SAMSUNG]
32Kx32 Synchronous SRAM; 32Kx32同步SRAM
| 型号： | KM732V589A |
| 厂家： | 
SAMSUNG |
| 描述： | 32Kx32 Synchronous SRAM |
| 文件： | 总15页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
KM732V589A/L
32Kx32 Synchronous SRAM
Document Title
32Kx32-Bit Synchronous Pipelined Burst SRAM, 3.3V Power
Datasheets for 100 QFP/TQFP
Revision History
Rev.No.
History
Draft Data
Remark
Rev.0.0
Rev.1.0
Initial draft
Oct. 28.1996
Preliminary
Final spec release
May.13. 1997
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
May 1997
Rev 1.0
- 1 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
32Kx32-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
The KM732V589A/L is a 1,048,576-bit Synchronous Static
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD = 3.3V-5%/+10% Power Supply
• 5V Tolerant Inputs except I/O Pins
• Byte Writable Function.
Random Access Memory designed for high performance sec-
ond level cache of Pentium and Power PC based System.
It is organized as 32K words of 32bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP disable to support address pipelining.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-QFP-1420C
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
• 100-TQFP-1420A
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
FAST ACCESS TIMES
The KM732V589A/L is fabricated using SAMSUNG¢s high per-
formance CMOS technology and is available in a 100pin QFP/
TQFP package. Multiple power and ground pins are utilized to
minimize ground bounce.
Parameter
Cycle Time
Symbol -13
-15
15
Unit
ns
tCYC
tCD
13
7.0
6.0
Clock Access Time
8.0
7.0
ns
Output Enable Access Time
tOE
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
32Kx32
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0 ~ A1
A2~A14
ADDRESS
REGISTER
A0~A14
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
GW
BW
WEa
WEb
WEc
WEd
OUTPUT
REGISTER
CONTROL
LOGIC
BUFFER
OE
ZZ
DQa0 ~ DQd7
May 1997
Rev 1.0
- 2 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
1
2
3
4
5
6
7
8
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin
(T)QFP
VDD
N.C.
VSS
N.C.
VDD
ZZ
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
N.C.
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
N.C.
(20mm x 14mm)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A14
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,81,
82,99,100
83
84
85
89
98
VDD
VSS
N.C.
Power Supply(+3.3V)
Ground
No Connect
15,41,65,91
17,40,67,90
1,14,16,30,38,39,42,43,
49,50,51,66,80
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
Data Inputs/Outputs
18,19,22,23,24,25,28,29
97
92
VDDQ
VSSQ
Output Power Supply
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
93,94,95,96
86
88
87
64
31
May 1997
Rev 1.0
- 3 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
FUNCTION DESCRIPTION
The KM732V589A/L is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC
based microprocessor. All inputs (with the exception of OE and ZZ) are sampled on rising clock edges. The start and duration of the
burst access is controlled by CS1, ADSC, ADSP and ADV. The accesses are enabled with the chip select signals and output enabled
signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time.
Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regardless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa controls DQa0 ~ DQa7, WEb controls DQb0 ~ DQb7, WEc
controls DQc0 ~ DQc7, and WEd controls DQd0 ~ DQd7. Read or write cycle may also be initiated with ADSC, instead of ADSP. The
differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BURST SEQUENCE TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
NOTE : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
May 1997
Rev 1.0
- 4 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
Address Accessed
N/A
Operation
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Not Selected
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
NOTE : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
X
Operation
READ
H
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
NOTE : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
Operation
ZZ
H
L
OE
X
I/O Status
High-Z
NOTE
Sleep Mode
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
L
DQ
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
May 1997
Rev 1.0
- 5 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
PASS-THROUGH TRUTH TABLE
Previous Cycle
Present Cycle
CS1
Next Cycle
Operation
WRITE
Operation
WRITE
OE
Initiate Read Cycle
Address=An
Data=Qn-1 for all bytes
Write Cycle, All bytes
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
All L
L
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for all bytes
No carryover from
previous cycle
All L
All L
H
H
H
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=High-Z
No carryover from
previous cycle
H
Initiate Read Cycle
One L Address=An
Data=Qn-1 for one byte
Write Cycle, One byte
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
L
H
H
L
L
Write Cycle, One byte
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for one byte
No carryover from
previous cycle
One L
H
NOTE : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
Symbol
VDD
Rating
-0.3 to 4.6
VDD
Unit
V
VDDQ
VIN
V
-0.3 to 6.0
-0.3 to VDDQ + 0.5
1.2
V
VIO
V
PD
W
°C
°C
°C
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS (0°C£ TA£70°C)
Parameter
Supply Voltage
Ground
Symbol
Min
3.13
3.13
0
Typ.
3.3
3.3
0
Max
3.6
3.6
0
Unit
V
VDD
VDDQ
VSS
V
V
CAPACITANCE*(TA=25°C, f=1MHz)
Parameter
Symbol
Test Condition
VIN=0V
Min
Max
5
Unit
pF
Input Capacitance
CIN
-
-
Output Capacitance
COUT
VOUT=0V
7
pF
*NOTE : Sampled not 100% tested.
May 1997
Rev 1.0
- 6 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
DC ELECTRICAL CHARACTERISTICS
(VDD=3.3V-5%+10%, TA=0 to 70°C)
Parameter
Symbol
IIL
Test Conditions
VDD= Max, VIN=VSS to VDD
Min
-2
-2
-
Max
+2
Unit
mA
Input Leakage Current(except ZZ)
Output Leakage Current
IOL
+2
mA
Output Disabled, VOUT=VSSQ to VDDQ
-13
-15
200
180
Device Selected, IOUT=0mA, ZZ£VIL,
All Inputs=VIL or VIH
Operating Current
ICC
-
mA
mA
Cycle Time ³ tCYC min
Device deselected, IOUT=0mA, ZZ£VIL,
f=Max, All Inputs£0.2V or³ VDD-0.2V
ISB
-
40
Device deselected, IOUT=0mA,
ZZ£0.2V, f = 0,
-
-
-
-
5
1
mA
mA
mA
mA
ISB1
Standby Current
L-Ver.
L-Ver.
All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA,
ZZ³ VDD-0.2V, f = Max,
All Inputs£VIL or³ VIH
5
ISB2
500
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
-
0.4
-
V
V
V
V
2.4
-0.5*
2.2
0.8
5.5**
VIH
* VIL(Min) = -3.0V(Pulse Width£20ns)
** In Case of I/O Pins, the Max. VIH = VDDQ + 0.5V
TEST CONDITIONS
unless otherwise specified)
(TA=0 to 70°C, VDD=3.3V-5%/+10%
Parameter
Value
0 to 3V
2ns
Input Pulse Level
Input Rise and Fall Time(Measured at 0.3V and 2.7V)
Input and Output Timing Reference Levels
Output Load
1.5V
See Fig. 1
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V
RL=50W
319W
Dout
Dout
VL=1.5V
353W
Z0=50W
30pF*
5pF*
* Capacitive Load consists of all components of
the test environment.
* Including Scope and Jig Capacitance
Fig. 1
May 1997
Rev 1.0
- 7 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
AC TIMING CHARACTERISTICS
(VDD=3.3V-5%/+10%, TA=0 to 70°C)
KM732V589A-13
KM732V589A-15
Parameter
Symbol
Unit
Min
13
-
Max
Min
15
-
Max
Cycle Time
tCYC
tCD
-
-
ns
ns
Clock Access Time
7.0
8.0
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
6.0
-
7.0
ns
tLZC
tOH
0
-
0
-
ns
2.5
0
-
2.5
0
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
ns
-
4.0
-
4.0
ns
1.5
4.5
4.5
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
2
5.0
-
2.0
6.0
6.0
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
2
6.0
-
ns
ns
Clock Low Pulse Width
tCL
-
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
-
-
ns
tSS
-
-
ns
tDS
-
-
ns
Write Setup to Clock High(GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
-
-
ns
tADVS
tCSS
tAH
-
-
ns
-
-
ns
-
-
ns
tSH
-
-
ns
tDH
-
-
ns
Write Hold from Clock High(GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
-
-
ns
-
-
ns
-
-
ns
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
NOTE : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
May 1997
Rev 1.0
- 8 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
May 1997
Rev 1.0
- 9 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
May 1997
Rev 1.0
- 10 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
May 1997
Rev 1.0
- 11 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
May 1997
Rev 1.0
- 12 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
May 1997
Rev 1.0
- 13 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 32Kx32 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 32K depth to 64K depth without extra logic.
Data
I/O[0:63]
A[0:14]
Address
A[0:15]
A[15]
A[0:14]
A[15]
Address Data
CS2
Address Data
CS2
CLK
CS2
CLK
ADSC
WEx
OE
CS2
CLK
ADSC
WEx
OE
64-Bits
Microprocessor
32Kx32
SPB
SRAM
32Kx32
SPB
SRAM
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS1
ADV
ADSP
ADV
ADSP
ADS
* Please refer to attached timing diagram 2
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Clock
tSS
tSH
ADSP
tAS
tAH
A2
A1
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*NOTES n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Don¢t Care
Undefined
May 1997
Rev 1.0
- 14 -
PRELIMINARY
32Kx32 Synchronous SRAM
KM732V589A/L
PACKAGE DIMENSIONS
100-QFP-1420C
Units:millimeters/inches
23.90 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.15
17.90 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.80 ±0.20
#1
(0.58)
0.65
0.30 ±0.10
0.15 MAX
2.65 ±0.10
3.00 Max.
0.05 MIN.
0.80 ±0.20
Units:millimeters/inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
May 1997
Rev 1.0
- 15 -
相关型号：
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