KM6161002CLF-120 [SAMSUNG]
Standard SRAM, 64KX16, 12ns, CMOS, PBGA48, 0.75 MM PITCH, FBGA-48;
| 型号： | KM6161002CLF-120 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 64KX16, 12ns, CMOS, PBGA48, 0.75 MM PITCH, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No.
Rev. 0.0
Rev. 1.0
History
Remark
Draft Data
Aug. 5. 1998
Sep. 7. 1998
Initial release with preliminary.
Preliminary
Preliminary
Relax DC characteristics.
Item
Previous
90mA
88mA
Changed
95mA
93mA
ICC
12ns
15ns
20ns
85mA
90mA
Rev. 2.0
Rev. 2.1
Add 48-fine pitch BGA.
Changed device part name for FP-BGA.
Sep. 17. 1998
Nov. 5. 1998
Preliminary
Final
Item
Previous
Changed
F
Symbol
Z
ex) KM6161002CZ -> KM6161002CF
Rev. 2.2
Rev. 3.0
Changed device ball name for FP-BGA.
Previous
Dec. 10. 1998
Mar. 3. 1999
Final
Final
Changed
I/O9 ~ I/O16
I/O1 ~ I/O8
I/O1 ~ I/O8
I/O9 ~ I/O16
Added Data Retention Characteristics.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 3.0
March 1999
- 1 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
64K x 16 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 12,15,20ns(Max.)
• Low Power Dissipation
GENERAL DESCRIPTION
The KM6161002C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
KM6161002C uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG¢s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
KM6161002C is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-Fine pitch BGA.
Standby (TTL)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating KM6161002C/CL - 12: 95mA(Max.)
KM6161002C/CL - 15: 93mA(Max.)
KM6161002C/CL - 20: 90mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
: 30mA(Max.)
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16
• Standard Pin Configuration:
KM6161002CJ: 44-SOJ-400
KM6161002CT: 44-TSOP2-400F
KM6161002CF: 48-Fine pitch BGA with 0.75 Ball pitch
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
KM6161002C/CL -12/15/20
Commercial Temp.
Clk Gen.
Pre-Charge Circuit
KM6161002CI/CLI -12/15/20
Industrial Temp.
A0
A1
A2
A3
A4
Memory Array
512 Rows
128x16 Columns
A5
A6
A7
A8
PIN FUNCTION
Pin Name
Pin Function
Data
Cont.
I/O Circuit &
Column Select
I/O1~I/O8
A0 - A15
WE
Address Inputs
Write Enable
Chip Select
Data
Cont.
I/O9~I/O16
CS
Gen.
CLK
OE
Output Enable
A9 A10 A11 A12 A13 A14 A15
LB
Lower-byte Control(I/O1~I/O8)
Upper-byte Control(I/O9~I/O16)
Data Inputs/Outputs
Power(+5.0V)
UB
I/O1 ~ I/O16
VCC
WE
OE
VSS
Ground
UB
LB
N.C
No Connection
CS
Revision 3.0
March 1999
- 2 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
A0
A1
1
2
3
4
5
6
7
8
9
44 A15
43 A14
42 A13
41 OE
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
N.C
I/O9
I/O10
Vcc
A2
A3
I/O1
CS
A4
40 UB
CS
I/O1
I/O2
I/O3
39 LB
I/O2
Vss
I/O3
I/O4
I/O5
I/O6
N.C
A8
A5
A6
I/O11
I/O12
I/O13
I/O14
WE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 N.C
27 A12
26 A11
25 A10
24 A9
N.C
N.C
A14
A12
A9
A7
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A5 18
SOJ/
Vcc
I/O7
I/O8
N.C
N.C
A15
A13
A10
Vss
TSOP2
I/O15
I/O16
N.C
G
H
A11
A6 19
A7 20
48-CSP
A8 21
N.C 22
23 N.C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
Unit
-0.5 to VCC+0.5
-0.5 to 7.0
1
V
V
Pd
W
°C
°C
°C
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
Commercial
Operating Temperature
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA= to 70°C)
Parameter
Supply Voltage
Symbol
Min
4.5
Typ
Max
Unit
V
VCC
5.0
5.5
Ground
VSS
0
0
-
0
V
Input High Voltage
Input Low Voltage
VIH
2.2
VCC+0.5***
0.8
V
VIL
-0.5**
-
V
*
The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
*** VIH(Max) = VCC + 2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
Revision 3.0
March 1999
- 3 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Parameter
Symbol
Test Conditions
VIN=VSS to VCC
Unit
Input Leakage Current
ILI
-2
2
mA
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
Output Leakage Current
Operating Current
ILO
ICC
-2
2
mA
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA
12ns
15ns
20ns
-
95
93
90
30
5
mA
-
-
Standby Current
ISB
Min. Cycle, CS=VIH
-
mA
mA
ISB1
Normal
L-Ver.
-
f=0MHz, CS ³ VCC-0.2V,
VIN³ VCC-0.2V or VIN £0.2V
-
-
0.5
0.4
-
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
V
V
V
IOH=-4mA
IOH1=-0.1mA
2.4
-
VOH1**
3.95
* The above parameters are also guaranteed at industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
CI/O
Test Conditions
VI/O=0V
MIN
Max
8
Unit
Input/Output Capacitance
Input Capacitance
-
-
pF
pF
VIN=0V
CIN
6
* Capacitance is sampled and not 100% tested.
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
Output Loads(A)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
RL = 50W
DOUT
480W
VL = 1.5V
30pF*
DOUT
ZO = 50W
255W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
Revision 3.0
March 1999
- 4 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
READ CYCLE*
KM6161002C/CL-12 KM6161002C/CL-15 KM6161002C/CL-20
Parameter
Symbol
Unit
Min
12
-
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tAA
-
12
12
6
6
-
15
-
-
15
15
7
7
-
20
-
-
20
20
9
9
-
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tBA
-
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
-
-
-
-
Chip Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
tLZ
3
0
0
0
0
0
3
0
-
3
0
0
-
3
0
0
-
tBLZ
tOLZ
tHZ
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
6
6
6
-
7
7
7
-
9
9
9
-
tOHZ
tBHZ
tOH
tPU
-
-
-
-
3
0
-
3
0
-
-
-
-
tPD
12
15
20
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
KM6161002C/CL-12
KM6161002C/CL-15
KM6161002C/CL-20
Parameter
Symbol
Unit
Min
12
8
Max
Min
15
9
Max
Min
20
10
0
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB, LB Valid to End of Write
Write Recovery Time
tAW
tWP
tWP1
tBW
tWR
tWHZ
tDW
tDH
8
9
10
10
20
10
0
8
9
12
8
15
9
0
0
Write to Output High-Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
6
7
8
0
0
0
tOW
3
3
3
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
Revision 3.0
March 1999
- 5 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tBHZ(3,4,5)
tBA
UB, LB
tBLZ(4,5)
tOHZ
tOH
tOE
OE
tOLZ
tLZ(4,5)
Data out
High-Z
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)
tWC
tAW
Address
tWR(5)
OE
CS
tCW(3)
tBW
UB, LB
tAS(4)
WE
tWP(2)
tDW
tDH
High-Z
High-Z
Data in
Valid Data
tOHZ(6)
Data out
Revision 3.0
March 1999
- 6 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
tBW
CS
UB, LB
tWP1(2)
tAS(4)
WE
tDW
tDH
High-Z
Valid Data
Data in
(9)
(10)
tWHZ(6)
tOW
High-Z
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
CS
tAW
tWR(5)
tCW(3)
tBW
UB, LB
tAS(4)
WE
tWP(2)
tDH
tDW
High-Z
High-Z
Data in
Valid Data
tLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
Revision 3.0
March 1999
- 7 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
CS
tAW
tCW(3)
tWR(5)
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDH
tDW
High-Z
Data in
Valid Data
tBLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE
going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
I/O Pin
CS
WE
OE
LB
UB
Mode
Supply Current
I/O1~I/O8
High-Z
I/O9~I/O16
High-Z
H
L
L
L
X
H
X
H
X*
H
X
X
X
H
L
X
X
H
H
L
Not Select
ISB, ISB1
ICC
Output Disable
High-Z
High-Z
L
Read
Write
DOUT
High-Z
DOUT
DIN
High-Z
DOUT
DOUT
High-Z
DIN
ICC
ICC
H
L
L
L
L
X
L
H
L
H
L
High-Z
DIN
L
DIN
* X means Don¢t Care.
Revision 3.0
March 1999
- 8 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
VCC for Data Retention
Data Retention Current
Symbol
VDR
Test Condition
CS³ VCC-0.2V
Min.
2.0
-
Typ.
Max.
5.5
Unit
V
-
-
IDR
VCC=3.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
0.4
mA
VCC=2.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
-
-
0.3
Data Retention Set-Up Time
Recovery Time
tSDR
tRDR
See Data Retention
Wave form(below)
0
5
-
-
-
-
ns
ms
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Revision 3.0
March 1999
- 9 -
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
Units:millimeters/Inches
PACKAGE DIMENSIONS
44-SOJ-400
#44
#23
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
0.20
-0.05
0.008 +0.004
-0.002
#1
#22
28.98
MAX
1.141
0.69
MIN
0.027
25.58 ±0.12
1.125 ±0.005
1.19
)
(
0.047
3.76
1.27
MAX
0.148
(
)
0.050
0.10
0.004
MAX
+0.10
-0.05
0.43
+0.10
-0.05
0.71
0.017 +0.004
0.95
0.0375
1.27
0.050
-0.002
(
)
0.028+0.004
-0.002
44-TSOP2-400F
0~8°
0.25
0.010
(
)
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76 ±0.20
0.463 ±0.008
0.50
0.020
(
)
#1
#22
18.81
0.741
MAX.
18.41 ±0.10
0.725 ±0.004
1.00 ±0.10
0.039 ±0.004
1.20
0.047
0.10
0.004
MAX.
MAX
0.05
MIN.
0.002
0.35 ±0.10
0.014 ±0.004
0.80
0.0315
0.805
0.032
(
)
Revision 3.0
March 1999
- 10
CMOS SRAM
KM6161002C/CL, KM6161002CI/CLI
PACKAGE OUTLINE
(Units : millimeter)
Top View
Bottom View
B
A1 INDEX MARK
0.50
B1
B
0.50
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.35
1.05
0.80
0.25
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
B1
C
-
6.90
7.10
-
C1
D
-
4. Typ : Typical
0.30
0.40
1.20
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.20
-
0.30
0.08
Revision 3.0
March 1999
- 11
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