KM4132G112Q-8/F8_技术文档

KM4132G112

CMOS SGRAM

32Mbit SGRAM

512K x 32bit x 2 Banks

Synchronous Graphic RAM

LVTTL

Revision 1.4

June 1999

Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.4 (Jun. 1999)

- 1 -

KM4132G112

CMOS SGRAM

Revision History

Revision 1.4 (June 10th, 1999)

• AC values of tRCD/tRP/tRAS/tRC are returned to the number of clock cycles. Those can be also converted to ns unit

based values by multiplying the number of clock cycles and clock cycle time of each part together. Accordingly,

- Changed tRCD and tRP of KM4132G112-5/7/8 each from 18ns to 20ns/21ns/20ns

- Changed tRC of KM4132G112-7/8 each from 67ns/68ns to 70ns

- Changed tRC of KM4132G112-5 from 65ns(13CLK) to 60ns (12CLK)

- Changed tRC of KM4132G112-6 from 66ns(11CLK) to 60ns (10CLK)

• Add KM4132G112-C(183MHz@CL3) part .For -C part, tRDL=1CLK can be supported within restricted amounts and it will

be distingusihed by bucket code "NV"

Revision 1.3 (April 1999)

• Modified power-up sequence.

• Changed ILI and ILO from +/- 5uA to +/-10uA.

• Changed tSAC and tSHZ of KM4132G112-8@CL2 from 7ns to 6ns.

Revision 1.2 (March 1999)

• Removed KM4132G112-Z(125MHz@CL2) and KM4132G112-10.

• Changed tRDL of KM4132G112-7/8 from 1CLK to 2CLK. For -6/7/8, tRDL=1CLK product can be supported within

restricted amounts and it will be distingusihed by bucket code "NV"

Revision 1.1 (February 1999)

• Removed KM4132G112-7@CL2 (115MHz@CL2) part

• Changed VDD Condition of KM4132G112-8@CL2 from 3.135V~3.6V to 3.0V~3.6V.

• Changed AC characteristics table format.

Revision 1.0 (February 1999) : Final Spec.

• Changed AC Parameters based on next generation spec.

• Add KM4132G112-5/F5 and KM4132G112-Z/FZ products.

Revision 0.3 (January 1999) : Preliminary Spec.

Revision 0.2 (September 1998)

• Added the Low Power Products in all speed grade.

- KM4132G112-F*

• Changed the clock cycle time of KM4132G112 -7/F7 @ CL2 from 12ns to 8.7ns, accordingly, the AC and DC parameters

of KM4132G112 -7/F7 @ CL2 are changed in AC/DC CHARACTERISTICS.

• Changed the clock cycle time of KM4132G112 -8/F8 @ CL2 from 12ns to 10ns, accordingly, the AC and DC parameters

of KM4132G112 -8/F8 @ CL2 are changed in AC/DC CHARACTERISTICS.

• Added KM4132G112-10/F10 products.

• AC Operating Condition is changed as defined :

- VIH(max) = 5.6V AC. The overshoot voltage duration is £ 3ns.

- VIL(min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

• Added DC Characteristics

- Estimated Current Data

Revision 0.1 (June 1998)

• Initial Industry Release.

Revision 0.0 (April 1998)

• Initial Release for Internal Review.

Rev. 1.4 (Jun. 1999)

- 2 -

KM4132G112

CMOS SGRAM

512K x 32Bit x 2 Banks Synchronous Graphic RAM

FEATURES

GENERAL DESCRIPTION

• 3.3V power supply

The KM4132G112 is 33,554,432 bits synchronous high data

rate Dynamic RAM organized as 2 x 524,288 words by 32 bits,

fabricated with SAMSUNG¢s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock. I/O transactions are possible on every

clock cycle. Range of operating frequencies, programmable

burst length, and programmable latencies allows the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

• LVTTL compatible with multiplexed address

• Dual bank operation

• MRS cycle with address key programs

-. CAS Latency (2, 3)

-. Burst Length (1, 2, 4, 8 & full page)

-. Burst Type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

Write per bit and 8 columns block write improves performance in

graphics systems.

• Burst Read Single-bit Write operation

• DQM 0-3 for byte masking

ORDERING INFORMATION

• Auto & self refresh

Part NO.

Max Freq.

200MHz

183MHz

166MHz

143MHz

125MHz

200MHz

183MHz

166MHz

143MHz

125MHz

Interface Package

• 32ms refresh period (2K cycle)

• 100 Pin PQFP, TQFP (14 x 20 mm)

KM4132G112Q-5/F5

KM4132G112Q-C/FC

KM4132G112Q-6/F6

KM4132G112Q-7/F7

KM4132G112Q-8/F8

KM4132G112TQ-5/F5

KM4132G112TQ-C/FC

KM4132G112TQ-6/F6

KM4132G112TQ-7/F7

KM4132G112TQ-8/F8

LVTTL 100 PQFP

Graphics Features

• SMRS cycle.

-. Load mask register

-. Load color register

• Write Per Bit(Old Mask)

• Block Write(8 Columns)

LVTTL 100 TQFP

FUNCTIONAL BLOCK DIAGRAM

MASK

REGISTER

DQMi

BLOCK

COLOR

REGISTER

WRITE

CONTROL

LOGIC

MUX

·

CLK

CKE

CS

COLUMN

MASK

DQi

(i=0~31)

DQMi

RAS

CAS

WE

512Kx32

CELL

512Kx32

CELL

·

ARRAY

DSF

DQMi

ROW DECORDER

BANK SELECTION

·

SERIAL

COUNTER

COLUMN ADDRESS

BUFFER

ROW ADDRESS

BUFFER

REFRESH

COUNTER

ADDRESS REGISTER

Samsung Electronics reserves the right to

change products or specification without

notice.

*

CLOCK ADDRESS(A0~A10,BA)

Rev. 1.4 (Jun. 1999)

- 3 -

KM4132G112

CMOS SGRAM

PIN CONFIGURATION (TOP VIEW)

DQ29

VSSQ

DQ30

DQ31

VSS

N.C

VDD

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

A7

A6

A5

A4

VSS

A10

N.C

VDD

A3

100 Pin QFP

Forward Type

2

20 x 14 mm

0.65mm pin Pitch

DQ0

DQ1

VSSQ

DQ2

A2

A1

A0

*PQFP (Height = 3.0mmMAX)

TQFP (Height = 1.2mmMAX)

PIN CONFIGURATION DESCRIPTION

CLK

NAME

System Clock

INPUT FUNCTION

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQMi

CS

Chip Select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one clock + tSS prior to new command.

Disable input buffers for power down in standby.

CKE

Clock Enable

Row / Column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, Column address : CA0 ~ CA7

A0 ~ A10

BA

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank Select Address

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

RAS

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

WE

Column Address Strobe

Write Enable

Enables write operation and Row precharge.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.(Byte Masking)

DQMi

Data Input/Output Mask

DQi

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

Enables write per bit, block write and special mode register set.

Power Supply : +3.3V±0.3V/Ground

DSF

Define Special Function

Power Supply /Ground

Data Output Power /Ground

No Connection

VDD/VSS

VDDQ/VSSQ

N.C

Provide isolated Power/Ground to DQs for improved noise immunity.

Rev. 1.4 (Jun. 1999)

- 4 -

KM4132G112

CMOS SGRAM

ABSOLUTE MAXIMUM RATINGS(Voltage referenced to VSS)

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

1

Unit

V

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

-

Typ

Max

Unit

V

Note

3.3

3.6

5

Input high voltage

3.0

VDDQ+0.3

V

1

Input low voltage

VIL

0

-

0.8

-

V

2

Output high voltage

Output low voltage

Input leakage current

Output leakage current

Output Loading Condition

VOH

V

IOH = -2mA

VOL

-

0.4

10

V

IOL = 2mA

ILI

-10

-

uA

3

4

ILO

-

uA

see figure 1

Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. Dout is disabled, 0V £ VOUT £ VDD.

5. The VDD condition of KM4132G112-5/C/6 is 3.135V~3.6V.

CAPACITANCE (VDD/VDDQ = 3.3V, TA = 23°C, f = 1MHz)

Symbol

CCLK

CIN

Min

Max

4.0

5.0

Unit

pF

Clock

-

RAS, CAS, WE, CS, CKE, DQMi,DSF

pF

Address

DQi

CADD

COUT

pF

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

uF

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

CDC1

CDC2

0.1 + 0.01

uF

Note :

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

Rev. 1.4 (Jun. 1999)

- 5 -

KM4132G112

CMOS SGRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)

Speed

-6

200 190 180 160 150

CAS

Latency

Parameter

Symbol

Test Condition

Unit Note

-5

-C

-7

-8

3

2

Operating Current

(One Bank Active)

Burst Length =1

tRC ³ tRC(min), tCC ³ tCC(min), Io = 0mA

ICC1

mA

2

-

150

ICC2P

CKE £ VIL(max), tCC = 15ns

2

Precharge Standby Current

in power-down mode

ICC2PS CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

ICC2N

30

15

Precharge Standby Current

in non power-down mode

mA

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC2NS

ICC3P

CKE £ VIL(max), tCC = 15ns

3

Active Standby Current

in power-down mode

ICC3PS CKE £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

ICC3N

50

30

Active Standby Current

in non power-down mode

(One Bank Active)

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC3NS

3

2

3

2

290 270 260 230 200

160

200 190 180 160 150

Operating Current

(Burst Mode)

Io = 0 mA, Page Burst

All bank Activated, tCCD = tCCD(min)

ICC4

ICC5

mA

2

3

-

Refresh Current

tRC ³ tRC(min)

-

2

-

150

mA

uA

4

5

Self Refresh Current

ICC6

ICC7

CKE £ 0.2V

450

Operating Current

(One Bank Block Write)

tCC ³ tCC(min), Io=0mA, tBWC(min)

230 210 200 170 150 mA

Note :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

4. KM4132G112*

5. KM4132G112-F* ; Low Power version

Rev. 1.4 (Jun. 1999)

- 6 -

KM4132G112

CMOS SGRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)

Parameter

Input levels (Vih/Vil)

Value

2.4 / 0.4

1.4

Unit

V

Input timing measurement reference level

Input rise and fall time

V

ns

V

tr/tf =1 / 1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200W

50W

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

·

Output

Z0=50W

30pF

870W

(Fig. 1) DC Output Load Circuit

1. The VDD condition of KM4132G112-5/C/6 is 3.135V~3.6V.

(Fig. 2) AC Output Load Circuit

Note :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

-6

Parameter

Symbol

Unit

Note

-5

-C

-7

-8

CAS Latency

CLK cycle time

CL

3

5

2

-

3

2

-

3

6

2

-

3

7

2

-

3

8

2

CLK

ns

tCC(min)

tRRD(min)

tRCD(min)

tRP(min)

tRAS(min)

tRAS(max)

5.5

10

Row active to row active delay

RAS to CAS delay

2

CLK

us

1

4

8

-

3

7

-

3

7

-

3

7

-

3

6

2

5

Row precharge time

Row active time

Row cycle time

100

tRC(min)

12

-

10

-

10

-

10

-

9

7

CLK

1

Last data in to row precharge

Last data in to new col.address delay

Last data in to burst stop

tRDL(min)

tCDL(min)

tBDL(min)

tCCD(min)

tBPL(min)

tBWC(min)

tMRS(min)

2

1

2

1

2

1

CLK

2, 5

2

Col. address to col. address delay

Block Write data-in to PRE command

Block write cycle time

3

4

Mode Register Set cycle time

CAS Latency=3

CAS Latency=2

Number of valid output data

ea

Note :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following ns-unit based AC table.

Rev. 1.4 (Jun. 1999)

- 7 -

KM4132G112

CMOS SGRAM

Version

-6

Parameter

Symbol

Unit

-8

-5

5

-C

5.5

-7

7

CLK cycle time

tCC(min)

6

8

ns

us

ns

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

10

20

40

11

12

14

21

49

16

20

48

16.5

38.5

18

Row precharge time

18

tRAS(min)

tRAS(max)

tRC(min)

42

Row active time

Row cycle time

100

60

55

70

2. Minimum delay is required to complete write.

3. This parameter means minimum CAS to CAS delay at block write cycle only.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. For -C/6/7/8, tRDL =1CLK product can be supported within restricted amounts and it will be distinguished by bucket code

"NV". From the next generation, tRDL will be only 2CLK for every clock frequency.

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

-5

-C

-6

-7

-8

Parameter

Symbol

tCC

Unit Note

Min Max Min Max Min Max Min Max Min Max

CAS Latency=3

5

-

5.5

-

6

7

8

10

-

CLK cycle time

1000

1000 ns

1

CAS Latency=2

CAS Latency=3

CAS Latency=2

-

4.5

-

5

-

5.5

-

5.5

6

-

CLK to valid

output delay

tSAC

ns

1, 2

-

Output data hold time

CLK high pulse width

tOH

tCH

2

-

2

-

2.5

-

2.5

ns

2

3

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

-

3

-

3

-

2

-

2

-

2.5

-

3

CLK low

pulse width

ns

3

tCL

tSS

-

1.5

-

1.5

-

1.5

-

1.75

2

2.5

1

Input setup time

-

1

-

Input hold time

tSH

1

-

1

-

1

-

ns

3

2

CLK to output in Low-Z

tSLZ

-

1

CAS latency=3

CAS latency=2

4.5

-

5

-

5.5

-

5.5

-

6

CLK to output

in Hi-Z

tSHZ

ns

-

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev. 1.4 (Jun. 1999)

- 8 -

KM4132G112

CMOS SGRAM

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1 CKEn CS RAS CAS WE DSF DQM BA A8 A10,A9,A7~A0

Note

1, 2

1,2,7

3

Register

Refresh

Mode Register Set

Special Mode Register Set

Auto Refresh

L

H

L

X

L

X

OP CODE

H

L

H

L

X

Entry

3

Self

Refresh

L

H

X

H

X

H

X

3

Exit

H

X

H

3

Bank Active Write Per Bit Disable

L

4, 5

4,5,9

4

H

L

H

L

H

V

Row Address

& Row Addr.

Write Per Bit Enable

H

Read &

Column

Address

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

Column

Address

(A0~A7)

H

X

H

L

X

H

L

4, 6

4, 5

Write &

Column

Address

Column

Address

(A0~A7)

L

H

L

V

H

L

4,5,6,9

4, 5

Block Write Auto Precharge Disable

&

Auto Precharge Enable

Column

Address

(A0~A7)

H

4,5,6,9

7

H

Burst Stop

H

X

L

H

L

H

L

X

Bank Selection

Precharge

V

X

L

X

Both Banks

H

L

H

X

L

H

X

H

X

V

X

H

X

H

X

V

X

H

X

H

X

V

X

Entry

H

L

X

Clock Suspend or

Active Power Down

X

Exit

L

H

L

X

Entry

H

L

Precharge Power Down

Mode

V

X

Exit

L

H

X

H

DQM

H

X

V

X

8

L

H

X

H

X

H

X

No Operation Command

X

H

(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)

Note :1. OP Code : Operand Code

A0 ~ A10, BA : Program keys. (@MRS)

A5, A6 : LMR or LCR select. (@SMRS)

Color register exists only one per DQi which both banks share.

So dose Mask Register.

Color or mask is loaded into chip through DQ pin.

2. MRS can be issued only at both banks precharge state.

SMRS can be issued only if DQ¢s are idle.

A new command can be issued at the next clock of MRS/SMRS.

Rev. 1.4 (Jun. 1999)

- 9 -

KM4132G112

CMOS SGRAM

SIMPLIFIED TRUTH TABLE

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by "Auto".

Auto/Self refresh can be issued only at both precharge state.

4. BA : Bank select address.

If "Low" at read, (block) write, Row active and precharge, bank A is selected.

If "High" at read, (block) write, Row active and precharge, bank B is selected.

If A8 is "High" at Row precharge, BA is ignored and both banks are selected.

5. It is determined at Row active cycle.

whether Normal/Block write operates in write per bit mode or not.

For A bank write, at A bank Row active, for B bank write, at B bank Row active.

Terminology : Write per bit =I/O mask

(Block) Write with write per bit mode=Masked(Block) Write

6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.

Another bank read/(block) write command can be issued at tRP after the end of burst.

7. Burst stop command is valid only at full page burst length.

8. DQM sampled at positive going edge of a CLK.

masks the data-in at the very CLK(Write DQM latency is 0)

but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)

9. Graphic features added to SDRAM¢s original features.

If DSF is tied to low, graphic functions are disabled and chip operates as a 32M SDRAM with 32 DQ¢s.

SGRAM vs SDRAM

Function

MRS

Bank Active

Write

DSF

L

H

L

H

L

H

Bank Active

with

Write per bit

Disable

Bank Active

with

Write per bit

Enable

SGRAM

Function

Normal

Write

Block

Write

MRS

SMRS

If DSF is low, SGRAM functionality is identical to SDRAM functionality.

SGRAM can be used as an unified memory by the appropriate DSF control

--> SGRAM=Graphic Memory + Main Memory

Rev. 1.4 (Jun. 1999)

- 10

KM4132G112

CMOS SGRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address

BA

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Function

RFU

W.B.L

TM

CAS Latency

BT

Burst Length

(Note 1)

(Note 2)

Test Mode

Type

CAS Latency

Burst Type

Type

Burst Length

A8

A7

0

A6

0

A5

A4

0

Latency

Reserved

-

A3

A2

A1

A0

0

BT=0

BT=1

Reserved

4

0

1

Mode Register Set

0

1

0

1

0

1

Sequential

Interleave

0

1

0

1

0

1

2

1

Vendor

Use

Only

0

1

0

2

0

4

1

0

1

3

1

8

Write Burst Length

Length

1

0

Reserved

0

Reserved

256(Full)

Reserved

A9

0

1

Burst

1

0

1

Single Bit

1

(Note 3)

Special Mode Register Programmed with SMRS

Address

BA

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Function

X

LC

LM

X

Load Color

Load Mask

A6

0

Function

Disable

Enable

A5

0

Function

Disable

1

Enable

(Note 4)

POWER UP SEQUENCE

SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for Future Use) should stay "0" during MRS cycle.

2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

3. The full column burst(256bit) is available only at Sequential mode of burst type.

4. If LC and LM both high(1), data of mask and color register will be unknown.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial address

Sequential

Interleave

A1

A0

0

1

2

3

1

2

3

0

2

3

0

1

3

0

1

2

0

1

2

3

1

0

3

2

3

0

1

3

2

1

0

1

0

1

BURST SEQUENCE (BURST LENGTH = 8)

Initial address

Sequential

Interleave

A2

0

A1

0

A0

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

0

2

3

4

5

6

7

0

1

3

4

5

6

7

0

1

2

4

5

6

7

0

1

2

3

5

6

7

0

1

2

3

4

5

7

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

1

2

3

0

1

6

7

4

5

3

2

1

0

7

6

5

4

5

6

7

0

1

2

3

5

4

7

6

1

0

3

2

6

7

4

5

2

3

0

1

7

6

5

4

3

2

1

0

1

6

7

0

1

2

3

4

0

3

2

5

4

7

6

0

1

0

1

0

1

0

1

0

1

PIXEL to DQ MAPPING(at BLOCK WRITE)

Column address

3 Byte

I/O31 - I/O24

DQ24

2 Byte

1 Byte

0 Byte

A2

0

A1

0

A0

0

I/O23 - I/O16

DQ16

I/O15 - I/O8

DQ8

I/O7 - I/O0

DQ0

0

1

DQ25

DQ17

DQ9

DQ1

0

1

0

DQ26

DQ18

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ2

0

1

DQ27

DQ19

DQ3

1

0

DQ28

DQ20

DQ4

1

0

1

DQ29

DQ21

DQ5

1

0

DQ30

DQ22

DQ6

1

DQ31

DQ23

DQ7

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

DEVICE OPERATIONS

CLOCK (CLK)

POWER-UP

SGRAMs must be powered up and initialized in a pre-

defined manner to prevent undefined operations.

The clock input is used as the reference for all SGRAM opera-

tions. All operations are synchronized to the positive going edge

of the clock. The clock transitions must be monotonic between

VIL and VIH. During operation with CKE high all inputs are

assumed to be in a valid state (low or high) for the duration of

set-up and hold time around positive edge of the clock for proper

functionality and ICC specifications.

1. Power must be applied to both CKE and DQM inputs to pull

them high and other pins are NOP condition at the inputs

before or along with VDD(and VDDQ) supply.

The clock signal must also be asserted at the same time.

2. After VDD reaches the desired voltage, a minimum pause of

200 microseconds is required with inputs in NOP condition.

3. Both banks must be precharged now.

CLOCK ENABLE (CKE)

4. Perform a minimum of 2 Auto refresh cycles to stabilize the

internal circuitry.

5. Perform a MODE REGISTER SET cycle to program the CAS

latency, burst length and burst type as the default value of

mode register is undefined.

At the end of one clock cycle from the mode register set cycle,

the device is ready for operation.

When the above sequence is used for Power-up, all the outputs

will be in high impedance state. The high impedance of outputs

is not guaranteed in any other power-up sequence.

cf.) Sequence of 4 & 5 may be changed.

The clock enable(CKE) gates the clock onto SGRAM. If CKE

goes low synchronously with clock (set-up and hold time are the

same as other inputs), the internal clock is suspended from the

next clock cycle and the state of output and burst address is fro-

zen as long as the CKE remains low. All other inputs are ignored

from the next clock cycle after CKE goes low. When both banks

are in the idle state and CKE goes low synchronously with clock,

the SGRAM enters the power down mode from the next clock

cycle. The SGRAM remains in the power down mode ignoring

the other inputs as long as CKE remains low. The power down

exit is synchronous as the internal clock is suspended. When

CKE goes high at least "tSS + 1CLOCK" before the high going

edge of the clock, then the SGRAM becomes active from the

same clock edge accepting all the input commands.

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various

operating modes of SGRAM. It programs the CAS latency,

addressing mode, burst length, test mode and various vendor

specific options to make SGRAM useful for variety of different

applications. The default value of the mode register is not

defined, therefore the mode register must be written after power

up to operate the SGRAM. The mode register is written by

asserting low on CS, RAS, CAS, WE and DSF (The SGRAM

should be in active mode with CKE already high prior to writing

the mode register). The state of address pins A0 ~ A10 and BA in

the same cycle as CS, RAS, CAS, WE and DSF going low is the

data written in the mode register. One clock cycle is required to

complete the write in the mode register. The mode register con-

tents can be changed using the same command and clock cycle

requirements during operation as long as both banks are in the

idle state. The mode register is divided into various fields

depending on functionality. The burst length field uses A0 ~ A2,

burst type uses A3, addressing mode uses A4 ~ A6, A7 ~ A8 , A10

and BA are used for vendor specific options or test mode. And

the write burst length is programmed using A9. A7 ~ A8 , A10 and

BA must be set to low for normal SGRAM operation. Refer to

table for specific codes for various burst length, addressing

modes and CAS latencies.

BANK SELECT (BA)

This SGRAM is organized as two independent banks of 524,288

words x 32 bits memory arrays. The BA inputs is latched at the

time of assertion of RAS and CAS to select the bank to be used

for the operation. When BA is asserted low, bank A is selected.

When BA is asserted high, bank B is selected. The bank select

BA is latched at bank activate, read, write mode register set and

precharge operations.

ADDRESS INPUT (A0 ~ A10)

The 19 address bits required to decode the 524,288 word loca-

tions are multiplexed into 11 address input pins(A0~A10). The 11

bit row address is latched along with RAS and BA during bank

activate command. The 8 bit column address is latched along

with CAS, WE and BA during read or write command.

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SGRAM performs no

operation (NOP). NOP does not initiate any new operation, but

is needed to complete operations which require more than sin-

gle clock cycle like bank activate, burst read, auto refresh, etc.

The device deselect is also a NOP and is entered by asserting

CS high. CS high disables the command decoder so that RAS,

CAS, WE, DSF and all the address inputs are ignored.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

DEVICE OPERATIONS

cycles in adjacent addresses depending on burst length and

BANK ACTIVATE

burst sequence. By asserting low on CS, CAS and WE with valid

column address, a write burst is initiated. The data inputs are

provided for the initial address in the same clock cycle as the

burst write command. The input buffer is deselected at the end

of the burst length, even though the internal writing may not

have been completed yet. The writing can not complete to burst

length. The burst write can be terminated by issuing a burst

read and DQM for blocking data inputs or burst write in the same

or the other active bank. The burst stop command is valid only at

full page burst length where the writing continues at the end of

burst and the burst is wrapped around. The write burst can also

be terminated by using DQM for blocking data and precharging

the bank "tRDL" after the last data input to be written into the

active row. See DQM OPERATION also.

The bank activate command is used to select a random row in

an idle bank. By asserting low on RAS and CS with desired row

and bank addresses, a row access is initiated. The read or write

operation can occur after a time delay of tRCD(min) from the time

of bank activation. tRCD(min) is an internal timing parameter of

SGRAM, therefore it is dependent on operating clock frequency.

The minimum number of clock cycles required between bank

activate and read or write command should be calculated by

dividing tRCD(min) with cycle time of the clock and then rounding

off the result to the next higher integer. The SGRAM has two

internal banks on the same chip and shares part of the internal

circuitry to reduce chip area, therefore it restricts the activation

of both banks immediately. Also the noise generated during

sensing of each bank of SGRAM is high requiring some time for

power supplies to recover before the other bank can be sensed

reliably. tRRD(min) specifies the minimum time required between

activating different banks. The number of clock cycles required

between different bank activation must be calculated similar to

tRCD specification. The minimum time required for the bank to be

active to initiate sensing and restoring the complete row of

dynamic cells is determined by tRAS(min) specification before a

precharge command to that active bank can be asserted. The

maximum time any bank can be in the active state is determined

by tRAS(max). The number of cycles for both tRAS(min) and

tRAS(max) can be calculated similar to tRCD specification.

DQM OPERATION

The DQM is used to mask input and output operations. It works

similar to OE during read operation and inhibits writing during

write operation. The read latency is two cycles from DQM and

zero cycle for write, which means DQM masking occurs two

cycles later in the read cycle and occurs in the same cycle dur-

ing write cycle. DQM operation is synchronous with the clock,

therefore the masking occurs for a complete cycle. The DQM

signal is important during burst interrupts of write with read or

precharge in the SGRAM. Due to asynchronous nature of the

internal write, the DQM operation is critical to avoid unwanted or

incomplete writes when the complete burst write is not required.

DQM is also used for device selection, byte selection and bus

control in a memory system. DQM0 controls DQ0 to DQ7,

DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,

DQM3 controls DQ24 to DQ31. DQM masks the DQ¢s by a byte

regardless that the corresponding DQ¢s are in a state of WPB

masking or Pixel masking. Please refer to DQM timing diagram

also.

BURST READ

The burst read command is used to access burst of data on con-

secutive clock cycles from an active row in an active bank. The

burst read command is issued by asserting low on CS and CAS

with WE being high on the positive edge of the clock. The bank

must be active for at least tRCD(min) before the burst read com-

mand is issued. The first output appears CAS latency number of

clock cycles after the issue of burst read command. The burst

length, burst sequence and latency from the burst read com-

mand is determined by the mode register which is already pro-

grammed. The burst read can be initiated on any column

address of the active row. The address wraps around if the initial

address does not start from a boundary such that number of out-

puts from each I/O are equal to the burst length programmed in

the mode register. The output goes into high-impedance at the

end of the burst, unless a new burst read was initiated to keep

the data output gapless. The burst read can be terminated by

issuing another burst read or burst write in the same bank or the

other active bank or a precharge command to the same bank.

The burst stop command is valid only at full page burst length

where the output does not go into high impedance at the end of

burst and the burst is wrapped around..

PRECHARGE

The precharge operation is performed on an active bank by

asserting low on CS, RAS, WE and A8/AP with valid BA of the

bank to be precharged. The precharge command can be

asserted anytime after tRAS(min) is satisfied from the bank acti-

vate command in the desired bank. "tRP" is defined as the mini-

mum time required to precharge a bank. The minimum number

of clock cycles required to complete row precharge is calculated

by dividing "tRP" with clock cycle time and rounding up to the

next higher integer. Care should be taken to make sure that

burst write is completed or DQM is used to inhibit writing before

precharge command is asserted. The maximum time any bank

can be active is specified by tRAS(max). Therefore, each bank

has to be precharged within tRAS(max) from the bank activate

command. At the end of precharge, the bank enters the idle

state and is ready to be activated again.

BURST WRITE

The burst write command is similar to burst read command, and

is used to write data into the SGRAM on consecutive clock

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

DEVICE OPERATIONS (Continued)

Entry to Power Down, Auto refresh, Self refresh and Mode reg-

ister Set etc. is possible only when both banks are in idle state.

SELF REFRESH

The self refresh is another refresh mode available in the

SGRAM. The self refresh is the preferred refresh mode for data

retention and low power operation of SGRAM. In self refresh

mode, the SGRAM disables the internal clock and all the input

buffers except CKE. The refresh addressing and timing are

internally generated to reduce power consumption.

The self refresh mode is entered from all banks idle state by

asserting low on CS, RAS, CAS and CKE with high on WE.

Once the self refresh mode is entered, only CKE state being low

matters, all the other inputs including the clock are ignored in

order to remain in the self refresh mode.

The self refresh is exited by restarting the external clock and

then asserting high on CKE. This must be followed by NOP¢s

for a minimum time of "tRC" before the SGRAM reaches idle

state to begin normal operation. If the system uses burst auto

refresh during normal operation, it is recommended to use burst

2048 auto refresh cycles immediately after exiting self refresh.

AUTO PRECHARGE

The precharge operation can also be performed by using auto

precharge. The SGRAM internally generates the timing to satisfy

tRAS(min) and "tRP" for the programmed burst length and CAS

latency. The auto precharge command is issued at the same

time as burst read or burst write by asserting high on A8/AP. If

burst read or burst write command is issued with low on A8/AP,

the bank is left active until a new command is asserted. Once

auto precharge command is given, no new commands are pos-

sible to that particular bank until the bank achieves idle state.

BOTH BANKS PRECHARGE

Both banks can be precharged at the same time by using Pre-

charge all command. Asserting low on CS, RAS, and WE with

high on A8/AP after both banks have satisfied tRAS(min) require-

ment, performs precharge on both banks. At the end of tRP after

performing precharge all, both banks are in idle state.

DEFINE SPECIAL FUNCTION(DSF)

The DSF controls the graphic applications of SGRAM. If DSF is

tied to low, SGRAM functions as 512K x 32 x2 Bank SDRAM.

SGRAM can be used as an unified memory by the appropriate

DSF command. All the graphic function modes can be entered

only by setting DSF high when issuing commands which other-

wise would be normal SDRAM commands. SDRAM functions

such as RAS Active, Write, and WCBR change to SGRAM func-

tions such as RAS Active with WPB, Block Write and SWCBR

respectively. See the section below for the graphic functions that

DSF controls.

AUTO REFRESH

The storage cells of SGRAM need to be refreshed every 32ms

to maintain data. An auto refresh cycle accomplishes refresh of

a single row of storage cells. The internal counter increments

automatically on every auto refresh cycle to refresh all the rows.

An auto refresh command is issued by asserting low on CS,RAS

and CAS with high on CKE and WE. The auto refresh command

can only be asserted with both banks being in idle state and the

device is not in power down mode (CKE is high in the previous

cycle). The time required to complete the auto refresh operation

is specified by "tRC(min)". The minimum number of clock cycles

required can be calculated by driving "tRC" with clock cycle time

and them rounding up to the next higher integer. The auto

refresh command must be followed by NOP¢s until the auto

refresh operation is completed. Both banks will be in the idle

state at the end of auto refresh operation. The auto refresh is the

preferred refresh mode when the SGRAM is being used for nor-

mal data transactions. The auto refresh cycle can be performed

once in 15.6us or a burst of 2048 auto refresh cycles once in

32ms.

SPECIAL MODE REGISTER SET(SMRS)

There are two kinds of special mode registers in SGRAM.One is

color register and the other is mask register. Those usage will be

explained in the "WRITE PER BIT" and "BLOCK WRITE" sec-

tions. When A5 and DSF goes high in the same cycle as CS,

RAS, CAS and WE going low, Load Mask Register(LMR) pro-

cess is executed and the mask registers are filled with the

masks for associated DQ¢s through DQ pins. And when A6 and

DSF goes high in the same cycle as CS, RAS, CAS and WE

going low, Load Color Register(LCR) process is executed and

the color register is filled with color data for associated DQ¢s

through the DQ pins. If both A5 and A6 are high at SMRS, data

of mask and color cycle are required to complete the write in the

mask register and the color register at LMR and LCR respec-

tively. A new command can be issued in the next clock of LMR

or LCR. SMRS, compared with MRS, can be issued at the active

state under the condition that DQ¢s are idle. As in write opera-

tion, SMRS accepts the data needed through DQ pins. There-

fore bus contention must be avoided. The more detailed

materials can be obtained by referring corresponding timing dia-

gram.

Rev. 1.4 (Jun. 1999)

- 15

KM4132G112

CMOS SGRAM

DEVICE OPERATIONS (Continued)

Timing Diagram to lllustrate tBWC

WRITE PER BIT

Write per bit(i.e. I/O mask mode) for SGRAM is a function that

selectively masks bits of data being written to the devices. The

mask is stored in an internal register and applied to each bit of

data written when the mask is enabled. Bank active command

with DSF=High enables write per bit for associated bank. Bank

active command with DSF=Low disables write per bit for the

associated bank. The mask used for write per bit operations is

stored in the mask register accessed by SWCBR(Special Mode

Register Set Command). When a mask bit=1, the associated

data bit is written when a write command is executed and write

per bit has been enabled for the bank being written. When a

mask bit=0, the associated data bit is unaltered when a write

command is executed and the write per bit has been enabled for

the bank being written. No additional timing conditions are

required for write per bit operations. Write per bit writes can be

either single write, burst writes or block writes. DQM masking is

the same for write per bit and non-WPB write.

0

1

2

CLOCK

CKE

CS

HIGH

RAS

CAS

WE

DSF

1 CLK BW

BLOCK WRITE

Block write is a feature allowing the simultaneous writing of

consecutive 8 columns of data within a RAM device during a sin-

gle access cycle. During block write the data to be written comes

from an internal "color" register and DQ I/O pins are used for

independent column selection. The block of column to be written

is aligned on 8 column boundaries and is defined by the column

address with the 3 LSB¢s ignored. Write command with DSF=1

enables block write for the associated bank. A write command

with DSF=0 enables normal write for the associated bank. The

block width is 8 column where column="n" bits for by "n" part.

The color register is the same width as the data port of the

chip.It is written via a SWCBR where data present on the DQ pin

is to be coupled into the internal color register. The color register

provides the data masked by the DQ column select, WPB

mask(If enabled), and DQM byte mask. Column data mask-

ing(Pixel masking) is provided on an individual column basis for

each byte of data. The column mask is driven on the DQ pins

during a block write command. The DQ column mask function is

segmented on a per bit basis(i.e. DQ[0:7] provides the column

mask for data bits[0:7], DQ[8:15] provides the column mask for

data bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9

masks column [1] for data bits [8:15], etc). Block writes are

always non-burst, independent of the burst length that has been

programmed into the mode register. Back to back block writes

are allowed provided that the specified block write cycle

time(tBWC) is satisfied. If write per bit was enabled by the bank

active command with DSF=1, then write per bit masking of the

color register data is enabled.

If write per bit was disabled by a bank active command with

DSF=0, the write per bit masking of the color register data is dis-

abled. DQM masking provides independent data byte masking

during block write exactly the same as it does during normal

write operations, except that the control is extended to the con-

secutive 8 columns of the block write.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

SUMMARY OF 4M Byte SGRAM BASIC FEATURES AND BENEFITS

Features

512K x 32 x 2 SGRAM

Benefits

Better interaction between memory and system without wait-state of

asynchronous DRAM.

Interface

Synchronous

High speed vertical and horizontal drawing.

High operating frequency allows performance gain for SCROLL, FILL,

and BitBLT.

Pseudo-infinite row length by on-chip interleaving operation.

Hidden row activation and precharge.

Bank

2 ea

Page Depth / 1 Row

Total Page Depth

256 bit

High speed vertical and horizontal drawing.

2048 bytes

Programmable burst of 1, 2, ,4, 8 and full page transfer per column

addresses.

Burst Length(Read)

1, 2, 4, 8 Full Page

Programmable burst of 1, 2, ,4, 8 and full page transfer per column

addresses.

Burst Length(Write)

BRSW

Sequential & Interleave

2, 3

Switch to burst length of 1 at write without MRS.

Compatible with Intel and Motorola CPU based system.

Programmable CAS latency.

Burst Type

CAS Latency

High speed FILL, CLEAR, Text with color registers.

Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and

byte masking functions.

Block Write

8 Columns

Color Register

Mask Register

1 ea.

A and B bank share.

Write-per-bit capability(bit plane masking). A and B banks share.

Byte masking(pixel masking for 8bpp system) for data-out/in

Each bit of the mask register directly controls a corresponding bit plane.

Byte masking(pixel masking for 8bpp system) for color by DQi

DQM0-3

Mask function

Write per bit

Pixel Mask at Block Write

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

1) Clock Suspended During Write (BL=4)

2) Clock Suspended During Read (BL=4)

CLK

CMD

CKE

WR

RD

Masked by CKE

Internal

CLK

D0

Q1

DQ(CL2)

DQ(CL3)

D0

D1

D2

D3

Q0

Q2

Q1

Q3

Q2

Q3

D2

Q0

Not Written

SuspendedDout

Note : CKE to CLK disable/enable=1 clock

2. DQM Operation

1) Write Mask (BL=4)

2) Read Mask (BL=4)

CLK

WR

RD

CMD

DQMi

Note 1

Masked by DQM

D3

Masked by DQM

Hi-Z

DQ(CL2)

DQ(CL3)

D0

D1

Q0

Q2

Q1

Q3

Q2

Hi-Z

D3

Q3

DQM to Data-in Mask = 0CLK

DQM to Data-out Mask = 2CLK

3) DQM with Clock Suspended (Full Page Read) ^{Note 2}

CLK

CMD

RD

CKE

DQM

Hi-Z

DQ(CL2)

DQ(CL3)

Q6

Q5

Q0

Q2

Q1

Q4

Q3

Q7

Q6

Q8

Q7

*Note : 1. There are 4 DQMi(i=0~3).

Each DQMi masks 8 DQi¢s.(1 Byte, 1 Pixel for 8 bpp)

2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE " L".

Rev. 1.4 (Jun. 1999)

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KM4132G112

3. CAS Interrupt (I)

1) Read interrupted by Read (BL=4)^{Note 1}

CLK

CMOS SGRAM

CMD

RD

A

RD

B

ADD

DQ(CL2)

QA0 QB0 QB1 QB2 QB3

DQ(CL3)

tCCD

Note 2

2) Write interrupted by(Block) Write (BL=2)

CLK

3) Write interrupted by Read (BL=2)

WR RD

CMD

WR WR

tCCD

WR BW

tCCD

Note 2

tCCD

Note 2

A

B

C

D

A

B

ADD

DQ

Note 4

DQ(CL2)

DQ(CL3)

DA0 DB0 DB1

DC0 Pixel

DA0

QB0 QB1

tCDL

Note 3

tCDL

Note 3

4) Block Write to Block Write

CLK

CMD

ADD

BW BW

A

B

Note 4

DQ

Pixel Pixel

tBWC

Note 5

*Note :

1. By " Interrupt ", It is possible to stop burst read/write by external command before the end of burst.

By "CAS Interrupt" , to stop burst read/write by CAS access ; read, write and block write.

2. tCCD : CAS to CAS delay. (=1CLK)

3. tCDL : Last data in to new column address delay. (=1CLK)

4. Pixel :Pixel mask.

5. tBWC : Block write minimum cycle time.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

4. CAS Interrupt (II) : Read Interrupted by Write & DQM

(1) CL=2, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

RD WR

D0

D1

D2

D3

D2

RD

WR

DQM

DQ

Hi-Z

D0

D1

D3

D2

iii) CMD

RD

WR

DQM

DQ

Hi-Z

D0

D1

D3

D2

iv) CMD

RD

WR

DQM

DQ

Hi-Z

Q0

D0

D1

D3

Note 1

(2) CL=3, BL=4

CLK

i) CMD

DQM

RD WR

D0

D1

D2

D3

D2

DQ

ii) CMD

DQM

RD

WR

DQ

iii) CMD

DQM

D0

D1

D3

D2

RD

WR

D0

D1

D3

D2

D1

DQ

iv) CMD

DQM

WR

Hi-Z

DQ

v) CMD

DQM

D0

D1

D3

D2

WR

Hi-Z

Q0

D0

D3

DQ

Note 2

*Note :

1. To prevent bus contention, there should be at least one gap between data in and data out.

2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

5. Write Interrupted by Precharge & DQM

CLK

Note 2,3

CMD

DQM

DQ

WR

D0

PRE

Note 1

D1

D2

D3

Masked by DQM

*Note : 1. To inhibit invalid write, DQM should be issued.

2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge

interrupt but only another bank precharge of dual banks operation.

3. For -C/6/7/8, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency.

6. Precharge

1) Normal Write (BL=4)

2) Block Write

CLK

CMD

WR

D0

PRE

BW

PRE

DQ

D1

D2

D3

Pixel

tRDL

tBPL

Note 1,4

Note 1

3) Read (BL=4)

CLK

CMD

RD

PRE

Q2

Note 2

Q3

1

DQ(CL2)

Q0

Q1

Q0

Q3

Q2

2

DQ(CL3)

Q1

7. Auto Precharge

1) Normal Write (BL=4)

2) Block Write

CLK

CMD

WR

D0

BW

DQ

(CL 2, 3)

D1

D2

D3

Pixel

tBPL

tRP

Note 3,4

Auto Precharge Starts

3) Read (BL=4)

Note 3

Auto Precharge Starts

CLK

CMD

RD

DQ(CL2)

Q0

Q1

Q0

Q2

Q1

Q3

Q2

DQ(CL3)

Q3

Note 3

Auto Precharge Starts

*Note :1. tBPL : Block write data-in to PRE command delay

2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated

bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

4. For -C/6/7/8, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency.

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KM4132G112

CMOS SGRAM

8. Burst Stop & Precharge Interrupt

1) Write Interrupted by Precharge (BL=4)

CLK

2) Write Burst Stop (Full Page Only)

CLK

WR

PRE

WR

STOP

CMD

DQM

DQ

CMD

D3

DQ

D0

D1

D2

D0

D1

D2

tBDL

tRDL Note 1,5

3) Read Interrupted by Precharge (BL=4)

CLK

4) Read Burst Stop (Full Page Only)

CLK

CMD

DQ(CL2)

DQ(CL3)

RD

PRE

Q0

CMD

DQ(CL2)

DQ(CL3)

RD

STOP

Note 3

Q1

1

Q1

Q0

Q1

Q0

2

Q0

Q1

9. MRS & SMRS

2) Special Mode Register Set

CLK

1) Mode Register Set

CLK

Note 4

CMD

PRE

MRS ACT

CMD

SMRS ACT SMRS SMRS BW

tRP

1CLK

1CLK 1CLK

*Note :

1. tRDL : 1 CLK, Last Data in to Row Precharge.

2. tBDL : 1 CLK, Last Data in to Burst Stop Delay.

3. Number of valid output data after Row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.

4. PRE : Both banks precharge if necessary.

MRS can be issued only at all bank precharge state.

5. For -C/6/7/8, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency.

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KM4132G112

CMOS SGRAM

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit

CLK

2) Power Down (=Precharge Power Down) Exit

CLK

CKE

tSS

Internal

CLK

Note 1

Note 2

CLK

CMD

ACT

NOP

RD

11. Auto Refresh & Self Refresh

Note 3

1) Auto Refresh

CLK

Note 4

Note 5

CMD

CKE

PRE

AR

CMD

tRP

tRC

Note 6

2) Self Refresh

CLK

Note 4

CMD

CKE

SR

PRE

CMD

tRP

tRC

*Note :

1. Active power down : one or more bank active state.

2. Precharge power down : both bank precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.

No precharge commands are required after Auto Refresh command.

During tRC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, both banks must be idle state.

5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are perfomed internally.

After self refresh entry, self refresh mode is kept while CKE is LOW.

During self refresh mode, all inputs expect CKE will be don¢t cared, and outputs will be in Hi-Z state.

During tRC from self refresh exit command, any other command can not be accepted.

Before/After self refresh mode, burst auto refresh cycle (2K cycles) is recommended.

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CMOS SGRAM

12. About Burst Type Control

At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)

BL=1, 2, 4, 8 and full page wrap around.

Sequential Counting

Basic

MODE

At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)

BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting

Interleave Counting

At MRS A3 = "1".(See to Interleave Counting Mode)

Starting Address LSB 3 bits A0-2 should be "000" or "111".@BL=8.

-- if LSB="000" : Increment Counting.

-- if LSB="111" : Decrement Counting.

Pseudo-

Decrement Sequential

Counting

For Example,(Assume Addresses except LSB 3 bits are all 0, BL=8)

-- @ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7

-- @ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0

At BL=4, same applications are possible. As above example, at Interleave Counting mode,

by confining starting address to some values, Pseudo-Decrement Counting Mode can be

realized. See the BURST SEQUENCE TABLE carefully.

Pseudo-

MODE

At MRS A3 = "0".(See to Sequential Counting Mode)

A0-2 = "111".(See to Full Page Mode)

Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized.

-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3(BL=8)

-- @ Pseudo-Binary Counting,

Pseudo-

Binary Counting

Accessed Column in order 3-4-5-6-7-8-9-10(Burst Stop command)

Note. The next column address of 256 is 0.

Every cycle Read/Write Command with random column address can realize

Random Column Access.

That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

Random column Access

tCCD = 1 CLK

Random

MODE

13. About Burst Length Control

At MRS A2,1,0 = "000".

At auto precharge, tRAS should not be violated.

1

At MRS A2,1,0 = "001".

At auto precharge, tRAS should not be violated.

2

Basic

MODE

At MRS A2,1,0 = "010".

At MRS A2,1,0 = "011".

4

8

At MRS A2,1,0 = "111".

Full Page

Wrap around mode(Infinite burst length)should be stopped by burst stop,

RAS interrupt or CAS interrupt.

At MRS A9 = "1".

BRSW

Read burst =1, 2, 4, 8, full page/write Burst =1

At auto precharge of write, tRAS should not be violated.

Special

MODE

8 Column Block Write. LSB A0-2 are ignored. Burst length=1.

tBWC should not be violated.

At auto precharge, tRAS should not be violated.

Block Write

Burst Stop

Random

MODE

tBDL= 1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively

Using burst stop command, it is possible only at full page burst length.

Before the end of burst, Row precharge command of the same bank

stops read/write burst with Row precharge.

tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CL= 2, 3 respectively

During read/write burst with auto precharge, RAS interrupt cannot be issued.

RAS Interrupt

(Interrupted by Precharge)

Interrupt

MODE

Before the end of burst, new read/write stops read/write burst and starts new

read/write burst or block write.

CAS Interrupt

During read/write burst with auto precharge, CAS interrupt can not be issued.

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KM4132G112

CMOS SGRAM

14. Mask Functions

1) Normal Write

I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.

If bit plane 0, 3, 7, 9, 15, 22, 24, and 31 keep the original value.

i) STEP

- SMRS(LMR) :Load mask[31-0]="0111, 1110, 1011,1111, 0111, 1101, 0111, 0110"

- Row Active with DSF "H" :Write Per Bit Mode Enable

- Perform Normal Write.

i) ILLUSTRATION

I/O(=DQ)

External Data-in

DQMi

31

24

23

16

15

8

7

0

1 1 1 1 1 1 1 1

DQM3=0

1 1 1 1 1 1 1 1

DQM2=0

0 0 0 0 0 0 0 0

DQM1=0

0 0 0 0 0 0 0 0

DQM0=1

Mask Register

Before Write

After Write

0 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 0

1 0 1 1 1 1 1 1

0 0 0 0 0 0 0 0

1 0 1 1 1 1 1 1

0 1 1 1 1 1 0 1

1 1 1 1 1 1 1 1

1 0 0 0 0 0 1 0

0 1 1 1 0 1 1 0

1 1 1 1 1 1 1 1

Note 1

2) Block Write

Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.

See PIXEL TO DQ MAPPING TABLE.

If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color.

Assume 8bpp,

White = "0000,0000", Red="1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011"

i) STEP

- SMRS(LCR) :Load color(for 8bpp, through x32 DQ color0-3 are loaded into color registers)

Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)

= "1100,0011, 1110, 0001, 0000, 1111, 1010, 0011"

- Row Active with DSF "L" : I/O Mask by Write Per Bit Mode Disable

- Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110"

i) ILLUSTRATION

I/O(=DQ)

DQMi

31

24

23

16

15

8

7

0

DQM3=0

DQM2=0

DQM1=0

DQM0=1

Color Register

Color3=Blue

White DQ24=H

White DQ25=H

White DQ26=H

White DQ27=L

White DQ28=H

White DQ29=H

White DQ30=H

White DQ31=L

Blue

Color2=Green

White DQ16=H

White DQ17=H

White DQ18=L

White DQ19=H

White DQ20=H

White DQ21=H

White DQ22=L

White DQ23=H

Green

Color1=Yellow

White DQ8=H

White DQ9=L

White DQ10=H

White DQ11=H

White DQ12=H

White DQ13=L

White DQ14=H

White DQ15=H

Yellow

Color0=Red

White DQ0=L

White DQ1=H

White DQ2=H

White DQ3=H

White DQ4=L

White DQ5=H

White DQ6=H

White DQ7=H

White

000

Before

Block

Write

&

DQ

(Pixel

data)

001

010

011

100

101

110

111

000

001

010

011

100

101

110

Blue

Green

White

Blue

White

Yellow

White

After

Block

Write

White

Green

Yellow

White

Blue

Green

Yellow

White

Blue

Green

White

Blue

White

Yellow

White

111

White

Green

Yellow

White

Note 2

*Note :

1. DQM byte masking.

2. At normal write, ONE column is selected among columns decorded by A2-0(000-111).

At block write, instead of ignored address A2-0, DQ0-31 control each pixel.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

(Continued)

Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.

By Pixel Data issued through DQ pin, the selected pixels keep the original data.

See PIXEL TO DQ MAPPING TABLE.

Assume 8bpp,

White = "0000,0000", Red="1010,0011", Green ="1110,0001", Yellow ="0000,1111", Blue ="1100,0011"

i) STEP

- SMRS(LCR) : Load color(for 8bpp, through x 32 DQ color0-3 are loaded into color registers)

Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)

= "1100,0011,1110,0001,0000,1111,1010,0011"

- SMRS(LMR ): Load mask. Mask[31-0] ="1111,1111,1101,1101, 0100,0010,0111,0110"

--> Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Masking

- Row Active with DSF "H" : I/O Mask by Write Per Bit Mode Enable

- Block Write with DQ[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110"

(Pixel Mask)

i) ILLUSTRATION

I/O(=DQ)

31

24

23

16

15

8

7

0

Blue

1 1 0 0 0 0 1 1

Green

1 1 1 0 0 0 0 1

Yellow

0 0 0 0 1 1 1 1

Red

1 0 1 0 0 0 1 1

Color Register

DQMi

DQM3=0

DQM2=0

DQM1=0

DQM0=1

Mask Register

1 1 1 1 1 1 1 1

1 1 0 1 1 1 0 1

0 1 0 0 0 0 1 0

0 1 1 1 0 1 1 0

Yellow

0 0 0 0 1 1 1 1

Yellow

0 0 0 0 1 1 1 1

Green

1 1 1 0 0 0 0 1

White

0 0 0 0 0 0 0 0

Before Write

Blue

1 1 0 0 0 0 1 1

Blue

1 1 0 0 0 0 1 1

Red

1 0 1 0 0 0 1 1

White

0 0 0 0 0 0 0 0

After Write

Note 1

I/O(=DQ)

DQMi

31

24

23

16

15

8

7

0

DQM3=0

DQM2=0

DQM1=0

DQM0=1

Color Register

Color3=Blue

Yellow DQ24=H

Yellow DQ25=H

Yellow DQ26=H

Yellow DQ27=L

Yellow DQ28=H

Yellow DQ29=H

Yellow DQ30=H

Yellow DQ31=L

Blue

Color2=Green

Yellow DQ16=H

Yellow DQ17=H

Yellow DQ18=H

Yellow DQ19=H

Yellow DQ20=H

Yellow DQ21=H

Yellow DQ22=H

Yellow DQ23=H

Blue

Color1=Yellow

Green DQ8=H

Green DQ9=L

Green DQ10=H

Green DQ11=L

Green DQ12=H

Green DQ13=L

Green DQ14=H

Green DQ15=L

Red

Color0=Red

White DQ0=L

White DQ1=H

White DQ2=H

White DQ3=H

White DQ4=L

White DQ5=H

White DQ6=H

White DQ7=H

White

000

Before

Block

Write

&

DQ

(Pixel

data)

001

010

011

100

101

110

111

000

001

010

011

100

101

110

Blue

Green

White

Blue

Red

White

After

Block

Write

Yellow

Blue

Green

White

Blue

Red

White

Blue

Green

White

Blue

Red

White

111

Note 2

Yellow

Blue

Green

White

Note 1

PIXEL MASK

I/O MASK

PIXEL & I/O MASK

BYTE MASK

*Note :

1. DQM byte masking.

2. At normal write, ONE column is selected among columns decorded by A2-0(000-111).

At block write, instead of ignored address A2-0, DQ0-31 control each pixel.

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KM4132G112

CMOS SGRAM

Power On Sequence & Auto Refresh

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

High level is necessary

CKE

CS

tRP

tRC

RAS

CAS

Ra

KEY

ADDR

BA

KEY

BS

Ra

A8/AP

WE

DSF

DQM

DQ

High level is necessary

High-Z

Precharge

(All Banks)

Auto Refresh

Mode Register Set

Row Active

(Write per Bit

Enable or Disable)

: Don¢t care

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1

tCH

4

0

1

2

3

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

tCL

tRAS

tCC

HIGH

CKE

CS

tRC

*Note 1

tSH

tRP

tRCD

tSS

tSH

RAS

CAS

ADDR

BA

tCCD

tSS

tSH

tSS

Ca

tSS

tSH

Ra

Cb

tSH

Cc

Rb

tSS

*Note 2

*Note 2,3

*Note 2,3 *Note 4

*Note 2

BS

*Note 3

*Note 3 *Note 4

Ra

A8/AP

Rb

tSH

WE

tSS

*Note 6

*Note 5

*Note 3

DSF

tSS

tSH

tSS

tSH

DQM

DQ

tRAC

tSAC

tSLZ

Qa

tOH

Db

Qc

tSS

tSHZ

Row Active

(Write per Bit

Enable or Disable)

Read

Write

or

Block Write

Read

Row Active

(Write per Bit

Enable or

Disable)

Precharge

: Don¢t care

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

*Note :

1. All input can be don't care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA.

BA

0

Active & Read/Write

Bank A

1

Bank B

3. Enable and disable auto precharge function are controlled by A8/AP in read/write command.

A8/AP

0

BA

0

Operation

Disable auto precharge, leave bank A active at end of burst.

Disable auto precharge, leave bank B active at end of burst.

Enable auto precharge, precharge bank A at end of burst.

Enable auto precharge, precharge bank B at end of burst.

1

0

1

4. A8/AP and BA control bank precharge when precharge command is asserted.

A8/AP

BA

0

Precharge

Bank A

0

1

Bank B

X

Both Bank

5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.

BA

0

DSF

L

Operation

Bank A row active, disable write per bit function for bank A

Bank A row active, enable write per bit function for bank A

Bank B row active, disable write per bit function for bank B

Bank B row active, enable write per bit function for bank B

H

L

1

H

6. Block write/normal write is controlled by DSF.

Operation

Normal write

Block write

DSF

L

Minimum cycle time

tCCD

tBWC

H

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

Read & Write Cycle at Same Bank @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

*Note 1

tRC

CS

tRCD

RAS

CAS

*Note 2

Ra

Ca0

Rb

Cb0

ADDR

BA

Ra

Rb

A8/AP

WE

DSF

DQM

tOH

DQ

(CL=2)

Qa0 Qa1 Qa2 Qa3

Db0 Db1 Db2 Db3

tRAC

tRDL

*Note 4

*Note 3

tSAC

tSHZ

*Note 5

tOH

Qa0 Qa1 Qa2 Qa3

DQ

(CL=3)

Db0 Db1 Db2 Db3

tRAC

tRDL

*Note 3

tSAC

*Note 4

tSHZ

*Note 5

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don¢t care

1. Minimum row cycle times is required to complete internal DRAM operation.

*Note :

2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row

enters precharge. Last valid output will be Hi-Z after tSHZ from the clcok.

3. Access time from Row address. tCC *(tRCD + CAS latency - 1) + tSAC

4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8). At Full page bit burst, burst is wrap-around.

5. For -C/6/7/8, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

Page Read & Write Cycle at Same Bank @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

tRCD

RAS

CAS

*Note 2

Ra

Ca0

Cb0

Cc0

Cd0

ADDR

BA

Ra

A8/AP

*Note 4

tRDL

tCDL

WE

*Note 2

DSF

*Note 1

*Note 3

DQM

DQ

Qa0 Qa1 Qb0 Qb1

Qa0 Qa1 Qb0

Dc0 Dc1 Dd0 Dd1

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Read

(A-Bank)

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don¢t care

*Note :

1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

4. For -C/6/7/8, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency.

Rev. 1.4 (Jun. 1999)

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KM4132G112

CMOS SGRAM

Block Write cycle(with Auto Precharge)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

*Note 2

CBb

CBa

RAa

CAa CAb

RBa

ADDR

BA

RBa

A8/AP

WE

DSF

tBWC

DQM

DQ

*Note 1

Pixel Pixel

Mask Mask

Pixel Pixel

Mask Mask

Block Write with

Auto Precharge

(B-Bank)

Row Active with

Write-per-Bit

Enable

Masked

Block Write

(A-Bank)

Row Active

(B-Bank)

(A-Bank)

Block Write

(B-Bank)

Masked

Block Write with

Auto Precharge

(A-Bank)

: Don¢t care

*Note :

1. Column Mask(DQi=L : Mask, DQi=H :Non Mask)

2. At Block Write, CA0~2 are ignored.

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KM4132G112

CMOS SGRAM

SMRS and Block/Normal Write @ Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

*Note 1

CBa

RAa

RBa

A0-2

A3,4,7,8

CBa

RAa

CAa

RBa

A5

A6

A8/AP

BA

WE

DSF

DQM

DQ

I/O

Mask

Pixel

Mask

I/O

Mask

Color

DBa0 DBa1 DBa2 DBa3

Load Color Load Mask

Register Register

Row Active Load Color

with WPB*

Enable

Register

WPB* : Write-Per-Bit

Row Active

with WPB*

Enable

Masked

Block Write

(A-Bank)

Masked Write

with Auto

Precharge

(B-Bank)

Load Mask Register

(A-Bank)

: Don¢t care

*Note : 1. At the next clock of special mode set command, new command is possible.

Rev. 1.4 (Jun. 1999)

- 33

KM4132G112

CMOS SGRAM

Page Read Cycle at Different Bank @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

*Note 1

CS

RAS

CAS

ADDR

BA

*Note 2

RAa

CAa RBb

CBb

CAc

CBd

CAe

RBb

A8/AP

WE

LOW

DSF

DQM

DQ

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Row Active

(B-Bank)

Read

(B-Bank)

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Read

(A-Bank)

: Don¢t care

*Note :

1. CS can be don¢t care when RAS, CAS and WE are high at the clock high going edge.

2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

Rev. 1.4 (Jun. 1999)

- 34

KM4132G112

CMOS SGRAM

Page Write Cycle at Different Bank @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

ADDR

BA

RAa Key

CAa RBb

CBb

CAc

CBd

RAa

RBb

A8/AP

tCDL

WE

DSF

DQM

DQ

Mask

DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3 DBd0 DBd1 DBd2 DBd3

Load Mask

Register

Row Active

(B-Bank)

Write

(B-Bank)

Masked Write

with auto

precharge

(A-Bank)

Write with auto

Precharge

(B-Bank)

Row Active with

Write-Per-Bit

enable

Masked Write

(A-Bank)

: Don¢t care

Rev. 1.4 (Jun. 1999)

- 35

KM4132G112

CMOS SGRAM

Read & Write Cycle at Different Bank @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

RAa

CAa

RBb

CBb RAc

CAc

ADDR

BA

RAc

A8/AP

tCDL

*Note 1

WE

DSF

DQM

DQ

DBb0 DBb1 DBb2 DBb3

QAc0 QAc1 QAc2

QAa0 QAa1 QAa2 QAa3

(CL=2)

DQ

(CL=3)

QAa0 QAa1 QAa2 QAa3

QAc0 QAc1

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Write

(B-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

Row Active

(A-Bank)

: Don¢t care

*Note : 1. tCDL should be met to complete write.

Rev. 1.4 (Jun. 1999)

- 36

KM4132G112

CMOS SGRAM

Read & Write Cycle with Auto Precharge I @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

ADDR

BA

RAa

CBb

RBb CAa

RBb

A8/AP

WE

DSF

DQMi

DQ

DBb0 DBb1 DBb2 DBb3

QAa0 QAa1 QAa2 QAa3

(CL=2)

DQ

(CL=3)

QAa0 QAa1 QAa2 QAa3

Read with

Auto Precharge

(A-Bank)

Auto Precharge

Start Point

Auto Precharge

Start Point

Row Active

(A-Bank)

Write with

Auto Precharge

(B-Bank)

(A-Bank)

(B-Bank)

Row Active

(B-Bank)

: Don¢t care

*Note :

1. tRCD should be controlled to meet minimum tRAS before internal precharge start.

(In the case of Burst Length=1 & 2, BRSW mode and Block write)

Rev. 1.4 (Jun. 1999)

- 37

KM4132G112

CMOS SGRAM

Read & Write Cycle with Auto Precharge II @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

Ra

Rb

Ca

Cb

Ra

Ca

ADDR

BA

A8/AP

Ra

Rb

Ra

WE

DSF

DQM

DQ

Qb3

Da0

Da1

Qa0

Qa1

Qb0

Qb1

Qb0

Qb2

(CL=2)

Qa0

Qa1

Qb1 Qb2

Qb3

DQ

(CL=3)

Read without Auto

precharge(B-Bank)

Auto Precharge

Start Point

Read with

Auto Pre

charge

Write with

Auto Precharge

(A-Bank)

Row Active

(A-Bank)

Precharge

(B-Bank)

Row Active

(A-Bank)

*Note 1

(A-Bank)

Row Active

(B-Bank)

: Don¢t care

*Note:

1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.

- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank

auto precharge will start at B Bank read command input point .

- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.

Rev. 1.4 (Jun. 1999)

- 38

KM4132G112

CMOS SGRAM

Read & Write Cycle with Auto Precharge III @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

Ra

Ca

Rb

Cb

ADDR

BA

A8/AP

Rb

Ra

WE

DSF

DQM

DQ

Qa0

Qa1

Qa2

Qa1

Qa3

Qa2

Qb0

Qb1

Qb2

Qb3

(CL=2)

DQ

(CL=3)

Qa0

Qa3

Qb0

Qb1

Qb2

Qb3

*Note 1

Read with

Auto Precharge

(A-Bank)

Auto Precharge

Start Point

(A-Bank)

Row Active

(A-Bank)

Read with

Auto Precharge

(B-Bank)

Auto Precharge

Start Point

(B-Bank)

Row Active

(B-Bank)

: Don¢t care

*Note :

1. Any command to A-bank is not allowed in this period.

tRP is determined from at auto precharge start point

Rev. 1.4 (Jun. 1999)

- 39

KM4132G112

CMOS SGRAM

Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full page Only)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

RAa

CAa

CAb

ADDR

BA

*Note 1

A8/AP

WE

DSF

DQM

1

*Note 2

DQ

(CL=2)

QAa0 QAa1 QAa2 QAa3 QAa4

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

2

QAa0 QAa1 QAa2 QAa3 QAa4

2

DQ

(CL=3)

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

Row Active

(A-Bank)

Read

(A-Bank)

Burst Stop

Read

(A-Bank)

Precharge

(A-Bank)

: Don¢t care

*Note :

1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. About the valid DQ¢s after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the label 1, 2 on them.

But at burst write, Burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of "Full page write burst stop cycle".

Rev. 1.4 (Jun. 1999)

- 40

KM4132G112

CMOS SGRAM

Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

HIGH

CKE

CS

RAS

CAS

ADDR

BA

RAa

CAa

CAb

*Note 1

RAa

A8/AP

tBDL

*Note 5

tRDL

WE

DSF

*Note 3

DQM

DQ

*Note 2

DAa0 DAa1 DAa2 DAa3 DAa4

DAb0 DAb1 DAb2 DAb3 DAb4 DAb5

Row Active

(A-Bank)

Write

(A-Bank)

Burst Stop

Write

(A-Bank)

Precharge

(A-Bank)

: Don¢t care

*Note :

1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell.

It is defined by AC parameter of tBDL(=1CLK).

3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.

It is defined by AC parameter of tRDL(=2CLK).

DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.

DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.

Input data after Row precharge cycle will be masked internally.

4. Burst stop is valid only at full page burst length.

5. For -C/6/7/8, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency.

Rev. 1.4 (Jun. 1999)

- 41

KM4132G112

CMOS SGRAM

Burst Read Single bit Write Cycle @Burst Length=2, BRSW

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

*Note 1

HIGH

CS

RAS

*Note 2

CAS

RAa

CAa RBb CAb

RAc CBc

CAd

ADDR

BA

RBb

RAc

A8/AP

WE

DSF

DQMi

QAb0 QAb1

QAd0 QAd1

DQ

DBc0

DAa0

(CL=2)

QAb0 QAb1

QAd0 QAd1

DQ

(CL=3)

Row Active

(A-Bank)

Row Active

(B-Bank)

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Write

Write with

(A-Bank)

Auto Precharge

(B-Bank)

Read with

Auto Precharge

(A-Bank)

: Don¢t care

*Note :

1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.

Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,

the next cycle starts the precharge.

3. WPB function is also possible at BRSW mode.

Rev. 1.4 (Jun. 1999)

- 42

KM4132G112

CMOS SGRAM

Clock suspension & DQM operation cycle @CAS Latency=2, Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

CS

RAS

CAS

ADDR

Ra

Ca

Cb

Cc

BA

Ra

A8/AP

WE

DSF

DQM

DQ

*Note 1

Qb0 Qb1

tSHZ

Dc0

Dc2

Qa0 Qa1

Qa2

Qa3

tSHZ

Row Active

Read

Clock

Suspension

Write

DQM

Read DQM

Write

Clock

Suspension

: Don¢t care

*Note : 1. DQM needed to prevent bus contention.

Rev. 1.4 (Jun. 1999)

- 43

KM4132G112

CMOS SGRAM

Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

*Note 2

tSS

*Note 1

*Note 3

CS

RAS

CAS

Ra

Ca

ADDR

BA

A8/AP

WE

Ra

DSF

DQM

DQ

Qa0 Qa1 Qa2

Precharge

Power-down

Entry

Precharge

Power-down

Exit

Read

Row Active

Active

Power-down

Entry

Active

Power-down

Exit

: Don¢t care

*Note :

1. All banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least "1CLK + tSS" prior to Row active command.

3. Cannot violate minimum refresh specification. (32ms)

Rev. 1.4 (Jun. 1999)

- 44

KM4132G112

CMOS SGRAM

Self Refresh Entry & Exit Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

*Note 4

*Note 2

tRCmin.

*Note 6

*Note 1

tSS

*Note 3

tSS

*Note 5

CS

RAS

CAS

*Note 7

ADDR

BA

A8/AP

WE

DSF

DQM

Hi-Z

DQ

Hi-Z

Self Refresh Exit

Self Refresh Entry

*Note :

Auto Refresh

TO ENTER SELF REFRESH MODE

1. CS, RAS & CAS with CKE should be low at the same clock cycle.

: Don¢t care

2. After 1 clock cycle, all the inputs including the system clock can be don¢t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays "Low".

cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS starts from high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit

if the system uses burst refresh.

Rev. 1.4 (Jun. 1999)

- 45

KM4132G112

CMOS SGRAM

Mode Register Set Cycle

Auto Refresh Cycle

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

8

9

10

CLOCK

CKE

HIGH

CS

*Note 2

tRC

RAS

CAS

*Note 1

*Note 3

ADDR

Key Ra

WE

DSF

DQM

DQ

Hi-Z

MRS New

Command

New Command

Auto Refresh

: Don¢t care

* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE

*Note :

1. CS, RAS, CAS, & WE activation and DSF of low at the same clock cycle with address key will set internal

mode register.

2. Minimum 1 clock cycles should be met before new RAS activation.

3. Please refer to Mode Register Set table.

Rev. 1.4 (Jun. 1999)

- 46

KM4132G112

CMOS SGRAM

FUNCTION TRUTH TABLE(TABLE 1)

Current

State

CS

RAS

CAS

WE

DSF

BA

ADDR

ACTION

NOTE

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

L

X

NOP

X

ILLEGAL

2

X

H

L

BA

X

CA

RA

PA

X

H

L

Row Active ; Latch Row Address ; Non-IO Mask

L

H

L

Row Active ; Latch Row Address ; IO Mask

IDLE

L

NOP

4

5

L

H

L

ILLEGAL

L

H

L

X

Auto Refresh or Self Refresh

L

H

L

X

ILLEGAL

L

OP Code

Mode Register Access

5

6

L

H

X

L

Special Mode Register Access

X

H

L

X

H

L

X

H

L

X

NOP

X

NOP

ILLEGAL

2

6

3

H

L

BA

X

CA,AP

X

Begin Read ; Latch CA ; Determine AP

ILLEGAL

L

H

L

BA

X

CA,AP

RA

Begin Write ;Latch CA ; Determine AP

Block Write ;Latch CA ; Determine AP

ILLEGAL

Row

Active

L

H

X

L

H

L

H

L

PA

Precharge

L

H

X

L

X

ILLEGAL

L

H

L

X

ILLEGAL

L

X

ILLEGAL

L

H

X

L

OP Code

Special Mode Register Access

NOP(Continue Burst to End --> Row Active)

Term burst --> Row active

ILLEGAL

X

H

L

X

H

L

X

H

L

X

L

H

L

X

CA,AP

X

H

L

BA

X

Term burst ; Begin Read ; Latch CA ; Determine AP

ILLEGAL

L

H

L

Read

L

BA

X

CA,AP

CA.AP

RA

Term burst ; Begin Write ; Latch CA ; Determine AP

Term burst ; Block Write ; Latch CA ; Determine AP

ILLEGAL

3

2

3

L

H

X

L

H

L

H

L

PA

Term Burst ; Precharge timing for Reads

ILLEGAL

L

H

X

L

X

L

X

H

L

X

ILLEGAL

X

H

X

H

L

X

NOP(Continue Burst to End --> Row Active)

Term burst --> Row active

ILLEGAL

X

L

H

L

X

Write

H

L

BA

X

CA,AP

X

Term burst ; Begin Read ; Latch CA ; Determine AP

ILLEGAL

3

L

H

L

BA

CA,AP

Term burst ; Begin Write ; Latch CA ; Determine AP

Term burst ; Block Write ; Latch CA ; Determine AP

3

L

H

Rev. 1.4 (Jun. 1999)

- 47

KM4132G112

CMOS SGRAM

FUNCTION TRUTH TABLE(TABLE 1, Continued)

Current

State

CS

RAS

CAS

WE

DSF

BA

ADDR

ACTION

NOTE

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

L

BA

X

RA

ILLEGAL

2

PA

Term Burst : Precharge timing for Writes

3

Write

L

H

X

ILLEGAL

L

X

H

L

X

ILLEGAL

X

H

L

X

H

L

X

NOP(Continue Burst to End --> Precharge)

X

NOP(Continue Burst to End --> Precharge)

Read with

Auto

Precharge

X

ILLEGAL

H

L

BA

X

CA,AP

ILLEGAL

2

L

CA,AP

ILLEGAL

H

L

X

H

L

RA,PA

ILLEGAL

L

X

ILLEGAL

2

X

H

L

X

H

L

X

NOP(Continue Burst to End --> Precharge)

X

NOP(Continue Burst to End --> Precharge)

Write with

Auto

Precharge

X

ILLEGAL

H

L

BA

X

CA,AP

2

L

CA,AP

H

L

X

H

L

RA,PA

L

X

2

X

H

L

X

H

L

X

NOP --> Idle after tRP

ILLEGAL

X

Precharging

X

H

L

BA

X

CA,AP

ILLEGAL

2

4

H

L

RA

L

PA

NOP --> Idle after tRP

ILLEGAL

L

X

H

L

X

H

L

X

H

L

X

NOP --> Row Active after tBWC

ILLEGAL

X

Block

Write

Recovering

X

CA,AP

RA

PA

X

H

L

BA

X

ILLEGAL

2

H

L

ILLEGAL

L

Term Block Write : Precharge timing for Block Write

ILLEGAL

L

X

H

L

X

H

L

X

H

L

X

NOP --> Row Active after tRCD

ILLEGAL

X

Row

Activating

X

H

L

BA

X

CA,AP

RA

PA

X

ILLEGAL

2

H

L

X

H

L

X

H

L

X

NOP --> Idle after tRC

ILLEGAL

X

Refreshing

X

H

L

X

ILLEGAL

L

X

Rev. 1.4 (Jun. 1999)

- 48

KM4132G112

CMOS SGRAM

FUNCTION TRUTH TABLE (TABLE 1, Continued)

ABBREVIATIONS

RA = Row Address(A0~A10)

NOP = No Operation Command

BA = Bank Address

CA = Column Address(A0~A7)

PA = Precharge All(A8)

AP = Auto Precharge(A8)

*Note :

1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle.

2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA).

5. Illegal if any banks is not idle.

6. Legal only if all banks are in idle or row active state.

FUNCTION TRUTH TABLE for CKE(TABLE 2)

Current

State

CKE

n-1

CKE

n

CS

RAS

CAS

WE

DSF

ADDR

ACTION

NOTE

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

L

X

INVALID

X

7

Exit Self Refresh --> ABI after tRC

ILLEGAL

L

X

Self

Refresh

L

X

L

X

H

L

X

ILLEGAL

L

X

H

L

X

ILLEGAL

L

X

H

L

X

H

L

X

NOP(Maintain Self Refresh)

INVALID

H

L

X

H

L

X

Exit Power Down --> ABI

ILLEGAL

8

Both

Bank

Precharge

Power

L

X

L

X

L

X

H

L

X

ILLEGAL

Down

L

X

H

L

X

ILLEGAL

L

X

H

L

X

H

L

X

NOP(Maintain Power Down Mode)

Refer to Table 1

H

L

H

L

X

Enter Power Down

ILLEGAL

9

L

X

L

X

All

Banks

Idle

L

X

H

L

X

ILLEGAL

L

H

L

RA

Row (& Bank) Active

Enter Self Refresh

Mode Register Access

Special Mode Register Access

NOP

L

X

9

L

OP Code

L

H

X

OP Code

L

X

H

L

H

L

Refer to Operations in Table 1

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

Maintain clock Suspend

Any State

other than

Listed

10

H

L

Above

L

ABBREVIATIONS : ABI = All Banks Idle

*Note :

7. After CKE¢s low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE¢s low to high

transition to issue a new command.

8. CKE low to high transition is asynchronous as if restarts internal clock.

A minimum setup time "tSS + one clock" must be satisfied before any command other than exit.

9. Power-down and self refresh can be entered only from the all banks idle state.

10. Must be a legal command.

Rev. 1.4 (Jun. 1999)

- 49

KM4132G112

CMOS SGRAM

PACKAGE DIMENSIONS (TQFP)

Dimensions in Millimeters

0 ~ 7°

17.20 ± 0.20

14.00 ± 0.10

#100

#1

23.20 ± 0.20

20.00 ± 0.10

0.825

0.09~0.20

0.30 ± 0.08

0.65

0.13 MAX

1.00 ± 0.10

1.20 MAX *

0.10 MAX

0.05 MIN

0.80 ± 0.20

* All Package Dimensions of PQFP & TQFP are same except Height.

- PQFP (Height = 3.0mmMAX)

- TQFP (Height = 1.2mmMAX)

Rev. 1.4 (Jun. 1999)

- 50


型号：	KM4132G112Q-8/F8
厂家：	SAMSUNG
描述：	Video DRAM, 1MX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 3 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 动态存储器
文件：	总50页 (文件大小：1203K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KM4132G112Q-8/F8 [SAMSUNG]

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