KM29W32000AT [SAMSUNG]
Flash, 4MX8, 35ns, PDSO40, 0.400 INCH, 0.80 MM PITCH, TSOP2-44/40;
| 型号： | KM29W32000AT |
| 厂家： | 
SAMSUNG |
| 描述： | Flash, 4MX8, 35ns, PDSO40, 0.400 INCH, 0.80 MM PITCH, TSOP2-44/40 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
Document Title
4M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
0.1
Initial issue.
April 10th 1998
Advanced
Information
Final
Data Sheet, 1999
April 10th 1999
1) Added CE dont’ care mode during the data-loading and reading
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
KM29W32000AT, KM29W32000AIT
4M x 8 Bit NAND Flash Memory
FEATURES
FLASH MEMORY
GENERAL DESCRIPTION
· Voltage Supply : 2.7V ~ 5.5V
· Organization
- Memory Cell Array : (4M + 128K)bit x 8bit
The KM29W32000A is a 4M(4,194,304)x8bit NAND Flash
Memory with a spare 128K(131,072)x8bit. Its NAND cell pro-
vides the most cost-effective solution for the solid state mass
storage market. A program operation programs the 528-byte
page in typically 250ms and an erase operation can be per-
formed in typically 2ms on an 8K-byte block.
- Data Register
: (512 + 16)bit x8bit
· Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
- Status Register
Data in the page can be read out at 50ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out-
put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verify and margin-
ing of data. Even the write-intensive systems can take advan-
tage of the KM29W32000A extended reliability of one million
program/erase cycles by providing either ECC(Error Correction
Code) or real time mapping-out algorithm. These algorithms
have been implemented in many mass storage applications
and also the spare 16 bytes of a page combined with the other
512 bytes can be utilized by system-level ECC.
· 528-Byte Page Read Operation
- Random Access
: 10ms(Max.)
- Serial Page Access : 50ns(Min.)
· Fast Write Cycle Time
- Program time
: 250ms(typ.)
- Block Erase time : 2ms(typ.)
· Command/Address/Data Multiplexed I/O port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
The KM29W32000A is an optimum solution for large nonvola-
tile storage application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.
· Command Register Operation
· 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
- Forward Type
PIN CONFIGURATION
PIN DESCRIPTION
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
RE
R/B
SE
N.C
N.C
N.C
N.C
N.C
Pin Name
I/O0 ~ I/O7
CLE
Pin Function
Data Inputs/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
ALE
CE
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RE
Read Enable
WE
Write Enable
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCCQ
WP
Write Protect
SE
Spare area Enable
Ready/Busy output
Power(2.7V ~ 5.5V)
Output Butter Power(2.7V ~ 5.5V)
Ground
R/B
VCC
VCCQ
VSS
44(40) TSOP (II)
STANDARD TYPE
N.C
No Connection
NOTE : Connect all VCC, VCCQ and VSS pins of each device to power supply outputs.
Do not leave VCC or VSS disconnected.
2
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
Y-Gating
2nd half Page Register & S/A
X-Buffers
A9 - A21
Latches
& Decoders
32M + 1M Bit
NAND Flash
ARRAY
Y-Buffers
A0 - A7
Latches
& Decoders
(512 + 16)Byte x 8192
1st half Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCCQ
VSS
I/O Buffers & Latches
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
I/0 7
Output
Driver
Global Buffers
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block(=16 Row)
(8K + 256) Byte
1 Page = 528 Bytes
1 Block = 528 B x 16 Pages
= (8K + 256) Bytes
1 Device = 528B x 16Pages x 512 Blocks
= 33 Mbits
32M : 8K Row
(=512 Block)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512B Column
16B Column
16Byte
I/O 0 ~ I/O 7
Page Register
512Byte
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
Column Address
Row Address
1st Cycle
A3
2nd Cycle
3rd Cycle
A9
A10
A18
A11
A19
A12
A20
A13
A21
A14
*X
A15
*X
A16
*X
(Page Address)
A17
NOTE : Column Address : Starting Address of the Register.
00H Command(Read) : Defines the starting Address of the 1st half of the Register.
01H Command(Read) : Defines the sarting Address of the 2nd half of the Register.
* A8 is initially set to "Low" or "High" by the 00H or 01H Command.
* X can be High or Low.
3
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
PRODUCT INTRODUCTION
The KM29W32000A is a 33Mbit(34,603,008 bit) memory organized as 8192 rows by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16
pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 512 separately or grouped erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29W32000A.
The KM29W32000A has addresses multiplexed into 8 I/O¢s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O¢s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 4M byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29W32000A.
Table 1. COMMAND SETS
Function
Sequential Data Input
Read 1
1st. Cycle
80h
2nd. Cycle
Acceptable Command during Busy
-
00h/01h(1)
50h(2)
90h
-
Read 2
-
Read ID
-
Reset
FFh
-
O
Page Program
Block Erase
Erase Suspend
Erase Resume
Read Status
10h
-
60h
D0h
B0h
-
-
-
O
O
D0h
70h
NOTE : 1. The 00H command defines starting address of the 1st half of registers.
The 01H command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01H command, the status pointer is
automatically moved to the 1st half register(00H) on the next cycle.
2. The 50H command is valid only when the SE(pin 40) is low level.
4
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
Spare Area Enable(SE)
The SE input controls the spare area selection when SE is high, the device is deselected the spare area during Read1, Sequential
data input and page Program.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
Power Line(VCC & VCCQ)
The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at VCCQ.
5
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
-0.6 to +7.0
-10 to +125
-40 to +125
-65 to +150
5
Unit
Voltage on any pin relative to VSS
VIN
V
KM29W32000AT
KM29W32000AIT
Temperature Under Bias
TBIAS
°C
Storage Temperature
Short Circuit Output Current
NOTE :
TSTG
IOS
°C
mA
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, KM29W32000AT:TA=0 to 70°C, KM29W32000AIT:TA=-40 to 85°C)
Parameter
Supply Voltage
Symbol
VCC
Min
2.7
2.7
0
Typ.
Max
5.5
5.5
0
Unit
V
-
-
Supply Voltage
Supply Voltage
VCCQ
VSS
V
0
V
NOTE : 1. Vcc and VccQ pins are separated each other.
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Vcc=2.7V ~ 3.6V
Vcc=3.6V ~ 5.5V
Parameter
Symbol
Test Conditions
Unit
Min Typ
Max
20
Min Typ
Max
Sequential Read
ICC1
ICC2
ICC3
ISB1
ISB2
ILI
tcycle=80ns, CE=VIL, IOUT=0mA
-
10
10
10
-
-
-
-
-
-
-
-
15
15
25
-
30
Operating
Program
Erase
-
-
-
20
30
Current
mA
-
-
20
40
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
CE=VIH, WP=SE=0V/VCC
CE=VCC-0.2, WP=SE=0V/VCC
VIN=0 to 5.5V
VOUT=0 to 5.5V
I/O pins
1
1
-
10
-
50
10
-
50
-
±10
±10
±10
mA
ILO
-
-
-
±10
2.0
2.0
-0.3
2.4
-
-
VCCQ+0.3 3.0
-
VCCQ+0.5
Input High Voltage
VIH
Except I/O pins
-
-
VCC+0.3
3.0
-0.3
2.4
-
-
VCC+0.5
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
VIL
VOH
VOL
-
0.6
-
-
0.8
-
V
IOH=-400mA
-
-
IOL=2.1mA
-
0.4
-
-
0.4
-
IOL(R/B) VOL=0.4V
8
10
8
10
mA
6
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
502
508
512
Blocks
NOTE :
1. The KM29W32000A may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these
invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are
guaranteed though its initial number could be reduced. (Refer to the attached technical notes)
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(KM29W32000AT:TA=0 to 70°C, KM29W32000AIT:TA=-40 to 85°C, VCC=2.7V ~ 5.5V unless otherwise noted)
Value
Parameter
Vcc=2.7V ~ 3.6V
Vcc=3.6V ~ 5.5V
Input Pulse Levels
0.4V to 2.4V
0.4V to 3.4V
Input Rise and Fall Times
Input and Output Timing Levels
5ns
0.8V and 2.0V
1 TTL GATE and
Output Load
1 TTL GATE and CL=100pF
CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V)
CAPACITANCE(TA=25°C, Vcc=5.0V f=1.0MHz)
Item
Symbol
CI/O
Test Condition
VIL=0V
Min
Max
10
Unit
Input/Output Capacitance
Input Capacitance
-
-
pF
pF
CIN
VIN=0V
10
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
CE
WE
RE
H
SE
X
WP
Mode
L
L
X
Command Input
Read Mode
Write Mode
H
L
H
X
X
Address Input(3clock)
Command Input
H
L
L
L
H
X
H
H
L
H
X
H
Address Input(3clock)
L/H(3)
L/H(3)
L/H(3)
L/H(3)
X
L
L
L
H
H
Data Input
L
L
L
H
H
X
X
X
X
X
Sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
L
L
L
H
X
X
X
X
X
X
X
X
X
X
H
H
X
X
H
L
X
X(1)
X
X
(2)
(2)
X
Stand-by
0V/VCC
0V/VCC
NOTE : 1. X can be VIL or VIH
2. WP should be biased to CMOS high or CMOS low for standby.
3. When SE is high, spare area is deselected.
Program/Erase Characteristics
Parameter
Symbol
tPROG
Nop
Min
Typ
0.25
-
Max
1.5
10
Unit
ms
Program Time
-
-
-
Number of Partial Program Cycles in the Same Page
Block Erase Time
cycles
ms
tBERS
2
10
7
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE Set-up Time
CLE Hold Time
CE Setup Time
CE Hold Time
0
-
-
-
-
-
-
-
-
-
-
-
10
0
tCH
10
25
0
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
tWP
tALS
tALH
tDS
10
20
10
50
15
tDH
tWC
WE High Hold Time
tWH
AC Characteristics for Operation
Parameter
Symbol
tR
Min
-
Max
Unit
Data Transfer from Cell to Register
ALE to RE Delay(read ID)
ALE to RE Delay(Read cycle)
CE to RE Delay(ID read)
Ready to RE Low
10
ms
ns
ns
ns
tAR1
tAR2
tCR
150
50
100
20
30
-
-
-
-
tRR
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
-
Read Cycle Time
tRC
50
-
RE Access Time
tREA
tRHZ
tCHZ
tREH
tIR
35
30
20
-
RE High to Output Hi-Z
CE High to Output Hi-Z
RE High Hold Time
15
-
15
0
Output Hi-Z to RE Low
Last RE High to Busy(at sequential read)
-
tRB
-
100
CE High to Ready(in case of interception by CE at read)(1)
CE High Hold Time(at the last serial read)(3)
RE Low to Status Output
50 +tr(R/B)(2)
tCRY
tCEH
tRSTO
tCSTO
tRHW
tWHR
tSR
-
100
-
-
35
CE Low to Status Output
-
45
RE High to WE Low
0
-
WE High to RE Low
60
-
-
500
Erase Suspend Input to Ready
RE access time(Read ID)
ms
tREADID
tRST
-
35
ns
Device Resetting Time(Read/Program/Erase/after erase suspend)
-
5/10/500/5
ms
NOTE : 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to VOL.
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
3. To break the sequential read cycle, CE must be held high for longer time than tCEH.
8
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically,
an invalid block will contain a single bad bit. The information regarding the invalid block(s) is so called as the invalid block informa-
tion. The invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data. Devices with invalid
block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND
Flash, however, is fully guaranteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block information is written prior to shipping. Since the
invalid block information is also erasable in most cases, it is impossible to recover the information once it has been
erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block
information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional era-
sure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFH" on the 1st and 2nd page
*
No
Create (or update)
Check "FFH" ?
Invalid Block(s) Table
Yes
No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
9
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Over its life time, the additional invalid blocks may occur. Though the tight process control and intensive testing, Samsung minimizes
the additional block failure rate, which is projected far below 0.1% up until 1million program/erase cycles. Refer to the qualification
report for the actual data.The following possible failure modes should be considered to implement a highly reliable system.
Failure Mode
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Erase Failure
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> Block Replacement or ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00H
Write 80H
Write Address
Wait for tR Time
Write Address
Write Data
Write 10H
*
No
Program Error
Verify Data
Write 70H
Yes
Program Completed
No
SR. 6 = 1 ?
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
SR. 0 = 0 ?
Yes
10
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60H
Write 00H
Write Block Address
Write Address
Read Data
Write D0H
Write 70H
ECC Generation
No
No
SR. 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
SR. 0 = 0 ?
*
Block Replacement
Yes
: copy the corrected whole block data to another
block (recommended for high reliability system)
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Buffer
memory
error occurs
When the error happens in Block "A", try to write the
data into another Block "B" by reloading from an exter-
nal buffer. Then, prevent further system access to
Block "A"(by creating a "invalid block" table or other
appropriate scheme.)
Block A
Block B
11
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
Pointer Operation of KM29W32000A
The KM29W32000A has three read modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command,
to "B" area by the "01" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2
shows the block diagram of its operations.
"A" area
(00h plane)
"B" area
(01h plane) (50h plane)
"C" area
Table 1. Destination of the pointer
256 Byte
256 Byte
16 Byte
Command
Pointer position
Area
00H
01H
50H
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A"
"B"
"C"
Internal
Page Buffer
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block diagram of pointer Operation
Example of Pointer Operation programming
(1) "A" area program
Address / Data input
10h
"A" area program
Address / Data input
10h
50h
00h
01h
50h
80h
80h
80h
80h
80h
80h
"C" area
"A" area
"A" area
"A" area
"B" area
"C" area
"A" area program
"A" area program
"C" area program
(2) "B" area program
Address / Data input
10h
Address / Data input
10h
00h
"B" area program
(3) "C" area program
Address / Data input
10h
Address / Data input
10h
00h
"C" area program
Table 2. Pointer Status after each operation
Operation
Pointer status after operation
With previous 00H, Device is set to 00H Plane
Program/Erase
With previous 01H, Device is set to 00H Plane*
With previous 50H, Device is set to 50H Plane
Reset
"00h" Plane("A" area)
"00h" Plane("A" area)
Power up
* 01H command is valid just one time when it is used as a pointer for program/erase.
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
System Interface Using CE don’t-care.
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE dont’-care
CE
WE
ALE
80H
Start Add.(3Cycle)
Data Input
Data Input
10H
I/O0~7
CE
(Min. 10ns)
tCS
(Max. 45ns)
tCEA
tCH
CE
RE
tREA
tWP
WE
I/O0~7
out
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
Figure 4. Read Operation with CE don’t-care.
CLE
CE
CE dont’-care
RE
ALE
tR
R/B
WE
Data Output(sequential)
00H
Start Add.(3Cycle)
I/O0~7
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
* Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
tDS
tDH
Command
I/O0~7
* Address Latch Cycle
tCLS
tCS
CLE
CE
tWC
tWC
tWP
tWP
tWP
WE
tWH
tWH
tALH
tALS
ALE
tDH
tDH
tDS
tDH
tDS
tDS
A17~A21
I/O0~7
A0~A7
A9~A16
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
* Input Data Latch Cycle
tCLH
CLE
CE
tCH
tALS
tWC
ALE
WE
tWP
tWP
tWP
tWH
tDH
tDH
tDH
tDS
tDS
tDS
DIN 511
I/O0~7
DIN 1
DIN 0
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tRP
tREA
tREH
tCHZ*
tREA
tREA
RE
tRHZ*
tRHZ*
tRHZ
Dout
I/O0~7
R/B
Dout
Dout
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
* Status Read Cycle
tCLS
CLE
tCLH
tCLS
tCS
CE
tCH
tWP
WE
tCSTO
tCHZ*
tWHR
RE
tDH
tDS
tIR
tRHZ*
tRSTO
I/O0~7
Status Output
70H
READ1 OPERATION(READ ONE PAGE)
CLE
tCEH
CE
tCHZ
tWC
WE
tWB
tAR2
tCRY
ALE
tRHZ
tR
tRC
RE
tRR
Dout 527
tRB
00h or 01h
A0 ~ A7
A9 ~ A16
Dout N+2 Dout N+3
Dout N
Dout N+1
A17 ~ A21
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
READ1 OPERATION(INTERCEPTED BY CE)
CLE
CE
WE
tWB
tAR2
tCHZ
ALE
tR
tRC
RE
tRR
Dout N
A17 ~ A21
Dout N+3
Dout N+1 Dout N+2
A0 ~ A7
A9 ~ A16
00h or 01h
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE
ALE
RE
tR
tWB
tAR2
tRR
Dout
511+M+1
Dout
50H
A9 ~ A16 A17 ~ A21
Dout 527
A0 ~ A7
I/O0~7
R/B
511+M
Selected
Row
M Address
A0 ~ A3 :Valid Address
A4 ~ A7 :Don't care
512
16
Start
address M
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
SEQUENTIAL ROW READ OPERATION
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
N+2
Dout
527
Dout
0
Dout
1
Dout
2
Dout
527
00H
A0 ~ A7 A9 ~ A16
A17 ~ A21
I/O0~7
R/B
Busy
Busy
M
M+1
Output
N
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tWB
tPROG
Din
527
Din
N
Din
N+1
10H
80H
A0 ~ A7 A9 ~ A16 A17 ~ A21
70H
I/O0
I/O0~7
R/B
Sequential Data
Input Command Address
Read Status
Command
Column
Program
Command
1 up to 528 Byte Data
Sequential Input
Page(Row)
Address
I/O0=0 Successful Program
I/O0=1 Error in Program
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
CLE
CE
tWC
tWC
WE
tWB
tBERS
ALE
RE
60H
A9 ~ A16 A17 ~ A21
DOH
70H
I/O0
I/O0~7
R/B
Block
Address
Busy
I/O0=0 Successful Erase
I/O0=1 Error in Erase
Auto Block Erase Setup Command
Erase Command
Read Status
Command
SUSPEND & RESUME OPERATION DURING BLOCK ERASE
CLE
CE
WE
tWB
ALE
RE
Block Address
tRHW
B0H
60H
D0H
D0H
tWB
I/O0
70H
I/O0~7
R/B
A9 ~ A16 A17 ~ A21
tSR
Busy
Suspend
I/O0=0 Successful Erase
I/O0=1 Error in Erase
Resume
Program/Read
Function are
Acceptable
Auto Block Erase Setup Command
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
RE
tREAID
90H
00H
ECH
E3H
I/O0~7
Read ID Command
Maker Code
Device Code
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10ms(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output
of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE
with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last
column address(column 511 or 527 depending on state of SE pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential read.
Waiting 10ms again allows for reading of the selected page. The sequential read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Addresses A0 to A3 set the starting address
of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incre-
mented for sequential read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00H/01H) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each
read operation.
Figure 3. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
00H
01H
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A21
Data Output(Sequential)
(01H Command)*
I/O0~7
(00H Command)
1st half array 2nd half array
1st half array
2nd half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00H) at next cycle.
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
Figure 4. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
Data Output(Sequential)
Spare Field
50H
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A21
I/O0~7
(A4 ~ A7 :
Don't Care)
1st half array
2nd half array
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation
tR
tR
tR
R/B
I/O0~7
00H
01H
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A21
Data Output
1st
Data Output
Data Output
2nd
(528 Byte)
Nth
(528 Byte)
(SE=L, 01H Command)
(SE=H, 00H Command)
(SE=L, 00H Command)
1st half array
2nd half array
1st half array
2nd half array
1st half array
2nd half array
1st
1st
1st
2nd
2nd
2nd
Nth
Nth
Nth
Data Field
Spare Field
Data Field
Spare Field
Data Field
Spare Field
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
Figure 6. Sequential Read2 Operation(SE=fixed low)
tR
tR
tR
R/B
I/O0~7
50H
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A21
Data Output
1st
Data Output
Data Output
2nd
(16 Byte)
Nth
(16 Byte)
(A4 ~ A7 :
Don't Care)
1st half array
2nd half array
1st
2nd
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, fol-
lowed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can
be started from 2nd half array. About the pointer operation, please refer to the attached technical notes.The serial data loading period
begins by inputting the Serial Data Input command(80H), followed by the three cycle address input and then serial data loading. The
bytes other than those to be programmed do not need to be loaded.
The Page Program confirm command(10H) initiates the programming process. Writing 10H alone without perviously entering the
serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Regis-
ter command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program
cycle by monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command and Reset com-
mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O0) may be
checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation
tPROG
R/B
I/O0~7
Pass
80H
Address & Data Input
I/O 0
Fail
10H
70H
A0 ~ A7 & A9 ~ A21
528 Byte Data
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
BLOCK ERASE
The Erase operation can erase on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60H). Only address A13 to A21 is valid while A9 to A12 is ignored. The addresses of the block to be erased to FFH.
The Erase Confirm command(D0H) following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse
repetition where required. If an erase operation error is detected, the internal verify is halted and erase operation is terminated. When
the erase operation is completed, the Write Status Bit(I/O0) may be checked.
Figure 8 details the sequence.
Figure 8. Block Erase Operation
tBERS
R/B
Pass
I/O0~7
60H
I/O 0
Fail
70H
Address Input(2Cycle)
Block Add. : A9 ~ A21
D0H
ERASE SUSPEND/ERASE RESUME
The Erase Suspend allows interruption during any erase operation in order to read or program data to or from another block of
memory. Once an erase process begins, writing the Erase Suspend command (B0H) to the command register suspends the internal
erase process, and the R/B signal return to "1". Erase Suspend Status bit will be also set to "1" when the Status Register is read. At
this time, blocks other than the suspended block can be read or programmed. The Status Register and R/B operation will function as
usual. After the Erase Resume command is written to it, the erase process is restarted from the beginning of the erasing period. The
Erase Suspend Status bit and R/B will return to "0". Refer to Figure 9 for operation sequence.
Figure 9. Erase Suspend & Erase Resume Operation
R/B
I/O0~7
60H
Block Address input
D0H
B0H
D0H
Erase Function
Start
Erase Function
Suspend
Erase Function
Resume
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KM29W32000AT, KM29W32000AIT
FLASH MEMORY
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether
the program or erase operation completed successfully. After writing 70H command to the command register, a read cycle outputs
the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00H or 50H) should be given before sequential page read cycle.
Table2. Status Register Definition
SR
Status
Definition
"0" : Successful Program / Erase
I/O0
Program / Erase
"1" : Error in Program / Erase
I/O1
I/O2
I/O3
I/O4
"0"
"0"
Reserved for Future
Use
"0"
"0"
"0" : Erase in Progress / Completed
"1" : Suspended
I/O5
Erase Suspend
I/O6
I/O7
Device Operation
Write Protect
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
READ ID
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of
00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (E3H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE
tCR
CE
WE
tAR1
ALE
RE
tREADID
I/O0~7
00
E3H
90H
ECH
Address. 1 cycle
Maker code
Device code
25
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
RESET
The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during random
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0H when WP is
high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is
not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation
tRST
R/B
I/O0~7
FFH
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 8. The two step command sequence for program/erase provides additional
software protection.
Figure 8. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
High
26
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by following equation.
VCC
Note*
VCC(Max.) - VOL(Max.)
Rp =
=
IOL + å IL
8mA + å IL
R/B
open drain output
where IL is the sum of the input currents of all devices tied to the
R/B pin.
Note* KM29W32000 : 5.1V When Vcc=3.6~5.5V
3.2V When Vcc=2.7~3.6V
GND
Device
27
KM29W32000AT, KM29W32000AIT
FLASH MEMORY
PACKAGE DIMENSIONS
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)
44(40) - TSOP2 - 400F
Unit :mm/Inch
0~8°
0.25
TYP
0.010
#44(40)
#23(21)
0.50
0.020
#1
#22(20)
+0.10
0.15
-0.05
+0.004
-0.002
0.006
18.81
0.741
Max.
18.41±0.10
0.725±0.004
0.10
MAX
0.004
0.805
0.032
0.80
0.35±0.10
0.014±0.004
(
)
0.0315
28
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