KBE00D002M-F407_技术文档

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KBE00D002M-F407

Document Title

Multi-Chip Package MEMORY

256M Bit (16Mx16) Nand Flash*2 / 128M Bit (2Mx16x4Banks) Mobile SDRAM*2

Revision No. History

Draft Date

Remark

0.0

Initial issue.

June , 25, 2003

Preliminary

- 512M NAND DDP C-Die_ ver 1.0

- 256M MSDRAM DDP E-Die_ver 0.4

0.1

August, 22 , 2003 Preliminary

- Changed errata for odering information : page 4

406 --> 407

<NAND Flash> .... ver 2.6

- Added the new definition of the number of invalid blocks : page 10

(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb

memory space.)

- Changed value of tR & tREA : page 11

tR : 12us --> 10us

tREA : 30ns --> 35ns

<M-SDR> .... ver 0.5

- Changing DC Current of ICC3P/3PS : page 32

10mA/2mA --> 8mA/8mA

- Added the word of "Internal: : page 38

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.

http://samsungelectronics.com/semiconductors/products/products_index.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

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Multi-Chip Package MEMORY

256M Bit (16Mx16) Nand Flash*2 / 128M Bit (2Mx16x4Banks) Mobile SDRAM*2

FEATURES

<SDRAM>

· Operating Temperature : -25°C ~ 85°C

· Package : 137-ball FBGA Type - 10.5x13mm, 0.8mm pitch

· Power Supply Voltage : 1.65~1.95V

• LVCMOS compatible with multiplexed address.

• Four banks operation.

<NAND>

· Power Supply Voltage : 1.7~1.95V

· Organization

• MRS cycle with address key programs.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

• EMRS cycle with address key programs.

• All inputs are sampled at the positive going edge of the system

clock.

- Memory Cell Array : (32M + 1024K)bit x 16bit

- Data Register : (256 + 8)bit x16bit

· Automatic Program and Erase

- Page Program : (256 + 8)Word

- Block Erase : (8K + 256)Word

· Page Read Operation

• Burst read single-bit write operation.

• Special Function Support.

- Page Size : (256 + 8)Word

- Random Access : 10ms(Max.)

- Serial Page Access : 50ns(Min.)

· Fast Write Cycle Time

- Program time : 200ms(Typ.)

- Block Erase Time : 2ms(Typ.)

· Command/Address/Data Multiplexed I/O Port

· Hardware Data Protection

- Program/Erase Lockout During Power Transitions

· Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

-. DS (Driver Strength)

• DQM for masking.

• Auto refresh.

• 64ms refresh period (4K cycle).

• Commercial Temperature Operation (-25°C ~ 70°C).

Extended Temperature Operation (-25°C ~ 85°C).

· Command Register Operation

· Intelligent Copy-Back

· Unique ID for Copyright Protection

· Safe Lock Mechanism

GENERAL DESCRIPTION

The KBE00D002M is a Multi Chip Package Memory which combines 512Mbit Nand Flash Memory(organized with two pieces of

256Mbit Nand Flash Memory) and 256Mbit synchronous high data rate Dynamic RAM(organized with two pieces of 128Mbit Mobile

SDRAM)

512Mbit NAND Flash memory is organized as 32M x16 bits and 256Mbit SDRAM is organized as 2M x32 bits x4 banks.

In 256Mbit NAND Flash, a 264-word page program can be typically achieved within 200us and an 8K-word block erase can be typi-

cally achieved within 2ms. In serial read operation, a word can be read by 50ns. IO pins serve as the ports for address and data

input/output as well as command inputs. Even the write-intensive systems can take advantage of flash¢s extended reliability of 100K

program/erase cycles with real time mapping-out algorithm. These algorithms have been implemented in many mass storage appli-

cations.

256Mbit Mobile SDRAM is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits,

fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of

system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths

and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory sys-

tem applications.

The KBE00D002M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power

consumption. This device is available in 137-ball FBGA Type.

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PIN CONFIGURATION

9

10

1

2

3

4

5

6

7

8

A

B

C

D

E

F

DNU

NC

DNU

Vdd

A4

DNU

NC

Vss

A2

A0

A11

BA1

Vdd

WEd

NC

Vss

CLK

CAS

CKE

DQ10

DQ25

DQ9

DQ24

DQ8

NC

RAS

CS

A3

A7

Vdd

A1

A10

Vss

IO15

IO6

BA0

DQM1

DQM2

DQ19

DQ3

A9

A6

IO7

NC

R/B

DQM0

WEn

DQ17

DQ1

DQM3

NC

A8

A5

IO14

IO13

IO3

NC

CE

IO4

IO12

IO10

IO1

IO5

G

H

J

DQ6

DQ23

DQ7

NC

Vcc

Vss

RE

CLE

ALE

WP

IO8

Vcc

Vss

IO11

NC

DQ4

DQ13

DQ28

DQ12

DQ11

DQ26

DQ27

Vss

IO2

DQ18

DQ20

DQ0

DQ21

DQ5

DQ14

DQ30

DQ31

DQ15

DQ29

Vddq

IO9

K

L

Vssq

Vss

Vddq

Vssq

NC

DQ16

Vdd

Vddq

Vssq

Vddq

DNU

IO0

DQ22

NC

Vddq

Vssq

DNU

Vddq

Vss

Vdd

NC

M

DQ2

Vssq

Vddq

Vdd

NC

Vssq

Vddq

Vssq

Vddq

Vssq

Vddq

N

P

NAND

DNU

R

MSDRAM

137 FBGA: Top View (Ball Down)

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PIN DESCRIPTION

Pin Name

/CE

Pin Function(NAND Flash)

Pin Name

CLK

Pin Function(Mobile SDRAM)

Chip Enable

System Clock

/RE

Read Enable

CKE

Clock Enable

/WP

Write Protection

Write Enable

/CS

Chip Select

/WEn

ALE

/RAS

Row Address Strobe

Column Address Strobe

Write Enable

Address Latch Enable

Command Latch Enable

Ready/Busy Output

Data Input/Output

Power Supply

/CAS

CLE

/WEd

R/B

A0 ~ A11

BA0 ~ BA1

DQM0~DQM3

DQ0d ~ DQ31

Vdd

Address Input

IO0 ~ IO15

Vcc

Bank Address Input

Lower Input/Output Data Mask

Data Input/Output

Power Supply

Vss

Ground

Vddq

Data Out Power

Ground

Pin Name

NC

Pin Function

Vss

No Connection

Do Not Use

Vssq

DQ Ground

DNU

ORDERING INFORMATION

D

KB E 00

0 0 2 M - F 407

Samsung

MCP Memory(4chips)

Access Time

407 : NAND Flash 50ns

NAND Flash 50ns

Mobile SDRAM 15ns

Device Type

NAND + NAND + SDRAM+SDRAM

NOR Flash Density, Voltage,

Organization, Bank Size, Boot Block

00 = None

Package

F = FBGA

NAND Flash Density, Voltage, Organization

D = 256M+256M, 1.8V/1.8V, X16

Version

M = 1st Generation

UtRAM Density, Voltage, Organization

0 = None

DRAM Interface, Density,

SRAM Density, Voltage, Organization

0 = None

Voltage, Organization, Option

2 = SDR, 128M+128M, 1.8V/1.8V, X32

NOTE :

1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.

Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose,

such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

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FUNCTIONAL BLOCK DIAGRAM

CE

X-Buffers

512M+16M Bit

NAND flash ARRAY

RE

Latches

& Decoders

WP

(256Mb NAND * 2Chip)

(256 + 8)Word x 131072

Y-Buffers

Latches

& Decoders

WEn

ALE

page Register & S/A

Y-Gating

CLE

IO0 to IO15

R/B

Vcc

Command

Register

I/O Buffers & Latches

Vccq

Vss

Control Logic

& High Voltage

Generator

Output

Driver

Global Buffers

CLK

CKE

CS

Bank Select

Data Input Register

2M x 32

RAS

CAS

WEd

DQ0d to DQ31d

A0~A12

BA0~BA1

Column Decoder

DQM0~DQM3

UDQM

Latency & Burst Length

Vdd

Vddq

Programming Register

Vss

Vssq

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512Mb(32Mb x 16)

NAND Flash DDP C-Die

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Figure 1.NAND Flash ARRAY ORGANIZATION

1 Block =32 Pages

= (8K + 256) Word

1 Page = 264 Word

1 Block = 264 Word x 32 Pages

= (8K + 256) Word

1 Device = 264Words x 32Pages x 4096 Blocks

= 528 Mbits

128K Pages

(=4,096 Blocks)

Page Register

(=256 Words)

16 bit

256Word

8 Word

I/O 0 ~ I/O 15

Page Register

256 Word

I/O 0

A0

I/O 1

A1

I/O 2

A2

I/O 3

I/O 4

A4

I/O 5

A5

I/O 6

A6

I/O 7

A7

I/O8 to 15

Column Address

1st Cycle

2nd Cycle

3rd Cycle

4rd Cycle

A3

A12

A20

L*

Row Address

(Page Address)

A9

A10

A18

L*

A11

A19

L*

A13

A21

L*

A14

A22

L*

A15

A23

L*

A16

A24

L*

A17

A25

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

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PRODUCT INTRODUCTION

The NAND Flash is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 264 columns. Spare eight columns

are located from column address of 256~263. A 264-word data register is connected to memory cell arrays accommodating data

transfer between the IO buffers and memory during page read and page program operations. The memory array is made up of 16

cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two

NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization

is shown in Figure 1. The program and read operations are executed on a page basis, while the erase operation is executed on a

block basis. The memory array consists of 4096 separately erasable 8K-Word blocks. It indicates that the bit by bit erase operation

is prohibited on the NAND Flash.

The NAND Flash has addresses multiplexed into lower 8 IO’s. The NAND Flash allows sixteen bit wide data transport into and out of

page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to

future densities by maintaining consistency in system board design. Command, address and data are all written through IO¢s by

bringing WE to low while CEn is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the IO pins. Some commands require one bus cycle. For

example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like

Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution.

The 32M-word physical space requires 25 addresses, thereby requiring four cycles for word-level addressing: column address, low

row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the

required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are

selected by writing specific commands into the command register. Table 1 defines the specific commands of the NAND Flash.

Table 1. COMMAND SET

Function

1st. Cycle

00h

2nd. Cycle

Acceptable Command during Busy

Read ID

Reset

-

50h

-

90h

FFh

-

O

Page Program

Copy-Back Program

Block Erase

80h

10h

8Ah

D0h

-

00h

60h

Read Status

70h

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ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

VIN/OUT

VCC

Rating

Unit

-0.6 to + 2.45

-0.2 to + 2.45

-40 to +125

-65 to +150

5

Voltage on any pin relative to VSS

V

VCCQ

Temperature Under Bias

Storage Temperature

Short Circuit Current

NOTE :

TBIAS

°C

TSTG

Ios

mA

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, TA=-25 to 85°C)

Parameter

Supply Voltage

Symbol

VCC

Min

1.7

0

Typ.

1.8

0

Max

1.95

0

Unit

V

VCCQ

VSS

V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter

Symbol

Test Conditions

tRC=50ns, CE=VIL

IOUT=0mA

Min

Typ

Max

Unit

Sequential Read

ICC1

-

8

20

Operating

Current

Program

Erase

ICC2

ICC3

ISB1

ISB2

ILI

-

8

-

20

mA

Stand-by Current(TTL)

Stand-by Current(CMOS)

Input Leakage Current

Output Leakage Current

CE=VIH, WP=0V/VCC

CE=VCC-0.2, WP=0V/VCC

VIN=0 to Vcc(max)

1

10

-

50

±10

mA

ILO

VOUT=0 to Vcc(max)

-

VCCQ

I/O pins

VCCQ-0.4

VCC-0.4

-

+0.3

Input High Voltage

VIH

VCC

Except I/O pins

+0.3

V

Input Low Voltage, All inputs

Output High Voltage Level

Output Low Voltage Level

Output Low Current(R/B)

VIL

VOH

-

IOH=-100mA

IOL=100uA

-0.3

-

0.4

-

VCCQ-0.1

VOL

-

0.1

-

IOL(R/B)

VOL=0.1V

3

4

mA

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VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

NVB

4026

-

4096

Blocks

NOTE :

1. The NAND Flash may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is

presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or

program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

3. The 2nd and 3rd blocks are good upon shipping.

4. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.

AC TEST CONDITION

( Vcc=1.7V~1.95V , TA=-40 to 85°C unless otherwise noted)

Parameter

Value

0V to VccQ

Input Pulse Levels

Input Rise and Fall Times

5ns

Input and Output Timing Levels

Output Load (VccQ:1.8V +/-10%)

VccQ/2

1 TTL GATE and CL=30pF

CAPACITANCE(TA=25°C, VCC=1.8V, f=1.0MHz)

Item

Symbol

Test Condition

Min

Max

20

Unit

pF

Input/Output Capacitance

Input Capacitance

CI/O

VIL=0V

-

CIN

VIN=0V

20

pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE

H

L

ALE

L

CE

L

WE

RE

H

WP

Mode

X

Command Input

Read Mode

Write Mode

H

L

H

X

Address Input(4clock)

Command Input

H

L

H

L

H

Address Input(4clock)

L

H

Data Input

L

H

X

Data Output

L

X

H

X

During Read(Busy)

X

H

During Program(Busy)

During Erase(Busy)

Write Protect

X

H

L

X⁽¹⁾

X

(2)

X

Stand-by

0V/VCC

NOTE :

1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

Max

500

2

Unit

Program Time

tPROG

-

200

ms

Main Array

-

cycles

ms

Number of Partial Program Cycles

in the Same Page

Nop

Spare Array

3

Block Erase Time

tBERS

2

3

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AC Timing Characteristics for Command / Address / Data Input

Parameter

Symbol

tCLS

tCLH

tCS

Min

Max

Unit

ns

CLE Set-up Time

CLE Hold Time

CE Setup Time

CE Hold Time

0

-

10

0

.-

-

tCH

10

25 ⁽¹⁾

0

WE Pulse Width

ALE Setup Time

ALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

tWP

-

tALS

tALH

tDS

-

10

20

10

45

15

-

tDH

-

tWC

-

WE High Hold Time

tWH

-

NOTE :

1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

AC Characteristics for Operation

Parameter

Symbol

Min

-

Max

Uni

ms

ns

ms

Data Transfer from Cell to Register

tR

10

ALE to RE Delay

tAR

10

20

25

-

CLE to RE Delay

tCLR

tRR

Ready to RE Low

-

RE Pulse Width

tRP

-

WE High to Busy

tWB

tRC

100

-

Read Cycle Time

50

-

CE Access Time

tCEA

tREA

tRHZ

tCHZ

tOH

45

35

30

20

-

RE Access Time

-

RE High to Output Hi-Z

CE High to Output Hi-Z

RE or CE High to Output hold

RE High Hold Time

Output Hi-Z to RE Low

WE High to RE Low

Device Resetting Time(Read/Program/Erase)

-

15

0

tREH

tIR

-

tWHR

tRST

60

-

5/10/500⁽¹⁾

NOTE :

1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

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NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-

mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality

level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-

mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design

must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-

anteed to be a valid block, does not require Error Correction.

Identifying Invalid Block(s)

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid

block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page sof every invalid

block has non-FFFFh data at the column address of 256 and 261. Since the invalid block information is also erasable in most cases,

it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid

block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure

2). Any intentional erasure of the original invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFh" at the column address256 and 261

of the 1st and 2nd page in the block

*

No

Create (or update)

Check "FFh" ?

Invalid Block(s) Table

Yes

No

Last Block ?

Yes

End

Figure 2. Flow chart to create invalid block table.

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NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-

ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect

the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased

empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of

memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block

replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Erase Failure

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Write

Read

Program Failure

Single Bit Failure

Verify ECC -> ECC Correction

: Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

ECC

Program Flow Chart

If ECC is used, this verification

operation is not needed.

Start

Write 80h

Write 00h

Write Address

Wait for tR Time

Write Address

Write Data

Write 10h

*

No

Program Error

Verify Data

Read Status Register

Yes

Program Completed

No

I/O 6 = 1 ?

or R/B = 1 ?

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

*

Yes

*

No

Program Error

I/O 0 = 0 ?

Yes

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NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Write 60h

Write 00h

Write Block Address

Write Address

Read Data

Write D0h

Read Status Register

ECC Generation

No

I/O 6 = 1 ?

or R/B = 1 ?

Reclaim the Error

Verify ECC

Yes

*

No

Page Read Completed

Erase Error

I/O 0 = 0 ?

Yes

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

*

Block Replacement

Block A

1st

2

{

(n-1)th

nth

an error occurs.

(page)

Buffer memory of the controller.

Block B

1st

1

{

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)

* Step3

Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.

* Step4

Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

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Pointer Operation

Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command

sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the

starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer com-

mand is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is

written. A complete read operation prior to ’80h’ command is not necessary.

Table 2. Destination of the pointer

"A" area

"B" area

(00h plane)

(50h plane)

Command

Pointer position

Area

256 Word

8 Word

00h

50h

0 ~ 255 word

256 ~ 263 word

main array(A)

spare array(B)

"A"

"B"

Internal

Page Register

Pointer select

command

(00h, 50h)

Pointer

Figure 3. Block Diagram of Pointer Operation

(1) Command input sequence for programming ’A’ area

The address pointer is set to ’A’ area(0~255), and sustained

Address / Data input

80h 10h

00h

80h

10h

00h

’A’,’B’ area can be programmed.

’00h’ command can be omitted.

It depends on how many data are inputted.

(2) Command input sequence for programming ’B’ area

The address pointer is set to ’B’ area(256~263), and sustained

Address / Data input

80h 10h

50h

80h

10h

50h

Only ’B’ area can be programmed.

’50h’ command can be omitted.

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MCP MEMORY

Preliminary

KBE00D002M-F407

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal

264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for

voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-

ing would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

WE

ALE

I/Ox

80h

Start Add.(4Cycle)

Data Input

10h

tCS

tCH

tCEA

CE

tREA

RE

tWP

tOH

WE

I/Ox

out

Figure 5. Read Operation with CE don’t-care.

CLE

CE

CE don’t-care

RE

ALE

tR

R/B

WE

I/Ox

Data Output(sequential)

00h

Start Add.(4Cycle)

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MCP MEMORY

Preliminary

KBE00D002M-F407

Command Latch Cycle

CLE

CE

tCLH

tCH

tCLS

tCS

tWP

WE

tALS

tALH

ALE

I/Ox

tDH

tDS

Command

Address Latch Cycle

tCLS

CLE

tCS

tWC

CE

tCH

tWP

WE

tWH

tALH tALS

tWH

tALH tALS

tWH

tALH tALS

tALH

tDH

tALS

ALE

I/OX

tDH

tDS

A0~A7

A9~A16

A17~A24

A25

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Preliminary

KBE00D002M-F407

Input Data Latch Cycle

tCLH

CLE

CE

tCH

tWC

tALS

ALE

tWP

WE

tWH

tDH

tDS

I/Ox

DIN 0

DIN 1

DIN n

Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)

tRC

CE

tCHZ*

tOH

tREH

tREA

tRP

RE

tRHZ*

tOH

I/Ox

Dout

tRR

R/B

NOTES :

1.Transition is measured ±200mV from steady state voltage with load.

2.This parameter is sampled and not 100% tested.

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MCP MEMORY

Preliminary

KBE00D002M-F407

Status Read Cycle

tCLR

CLE

CE

tCLS

tCS

tCLH

tCH

tWP

WE

RE

tCEA

tCHZ

tOH

tWHR

tRHZ

tOH

tDH

tREA

tDS

tIR

Status Output

I/Ox

70h

READ1 OPERATION(READ ONE PAGE)

CLE

CE

tCHZ

tOH

tWC

WE

tWB

tAR

ALE

tRHZ

tOH

tR

tRC

RE

N Address

tRR

Dout 264

A17 ~ A24

00h

A0 ~ A7

A9 ~ A16

Dout N

Dout N+1

Dout N+2

A25

I/Ox

R/B

Column

Address

Page(Row)

Address

Busy

X16 device : m = 264 , Read CMD = 00h

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Preliminary

KBE00D002M-F407

READ1 OPERATION (INTERCEPTED BY CE)

CLE

CE

WE

ALE

RE

tWB

tCHZ

tOH

tAR

tR

tRC

tRR

A9 ~ A16 A17 ~ A24

Dout N+2

00h or 01h A0 ~ A7

Dout N

Dout N+1

A25

I/Ox

R/B

Page(Row)

Address

Column

Address

Busy

READ2 OPERATION (READ ONE PAGE)

CLE

CE

WE

ALE

RE

tR

tWB

tAR

tRR

Dout

n+m

n+M

50h

A0 ~ A7 A9 ~ A16 A17 ~ A24

A25

I/Ox

R/B

Selected

Row

M Address

A0~A3 : Valid Address

A4~A7 : Don¢t care

8

256

Start

address M

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MCP MEMORY

Preliminary

KBE00D002M-F407

PAGE PROGRAM OPERATION

CLE

CE

tWC

WE

ALE

RE

tPROG

tWB

Din

N

Din

255

A25

10h

80h

A0 ~ A7 A9 ~ A16 A17 ~ A24

70h

I/O0

I/Ox

R/B

Sequential Data Column

Input Command Address

Program

Command

1 up to 256 Word Data

Serial Input

Read Status

Command

Page(Row)

Address

I/O0=0 Successful Program

I/O0=1 Error in Program

COPY-BACK PROGRAM OPERATION

CLE

CE

tWC

WE

ALE

RE

tWB

tPROG

tWB

tR

8Ah

00h

A0~A7 A9~A16 A17~A24

A25

A0~A7 A9~A16 A17~A24 A25

10h

70h

I/O0

I/Ox

R/B

Column

Read Status

Command

Page(Row)

Address

Busy

Copy-Back Data

Input Command

I/O0=0 Successful Program

I/O0=1 Error in Program

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Preliminary

KBE00D002M-F407

BLOCK ERASE OPERATION (ERASE ONE BLOCK)

CLE

CE

tWC

WE

tBERS

tWB

ALE

RE

60h

A9 ~ A16 A17 ~ A24

DOh

70h

I/O 0

A25

I/Ox

R/B

Page(Row)

Address

Busy

I/O0=0 Successful Erase

Read Status I/O0=1 Error in Erase

Command

Auto Block Erase Setup Command

Erase Command

MANUFACTURE & DEVICE ID READ OPERATION

CLE

CE

WE

ALE

tAR

RE

tREA

I/Ox

90h

00h

XX46h

ECh

Read ID Command

Address. 1cycle

Maker Code

Device Code

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Preliminary

KBE00D002M-F407

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-

ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-

tion. Two types of operations are available : random read, serial page read.

The random read mode is enabled when the page address is changed. The 264 words of data within the selected page are trans-

ferred to the data registers in less than 10ms(tR). The system controller can detect the completion of this data transfer(tR) by analyz-

ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially

pulsing RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column

address[column 255 /263 depending on the state of GND input pin].

The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of

256~263 words may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0~A2 set the start-

ing address of the spare area while addresses A3~A7 must be "L". The Read1 command is needed to move the pointer back to the

main area. Figures 6, 7 show typical sequence and timings for each read operation.

Figure 6. Read1 Operation

CLE

CE

WE

ALE

tR

R/B

RE

I/Ox

Start Add.(4Cycle)

A0 ~ A7 & A9 ~ A25

00h

Data Output(Sequential)

(00h Command)

Main array

Data Field

Spare Field

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Preliminary

KBE00D002M-F407

Figure 7. Read2 Operation

CLE

CE

WE

ALE

R/B

tR

RE

Start Add.(4Cycle)

I/Ox

50h

Data Output(Sequential)

Spare Field

A0 ~ A2 & A9 ~ A25

Main array

A3 ~ A7 are "L"

Data Field

Spare Field

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Preliminary

KBE00D002M-F407

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive

words up to 264, in a single page program cycle. The number of consecutive partial page programming operation within the same

page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done

in any random order in a block. A page program cycle consists of a serial data loading period in which up to 264 words of data may-

be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the

appropriate cell. About the pointer operation, please refer to the attached technical notes.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and

then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm com-

mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-

gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,

thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be

entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by mon-

itoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid

while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The

internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read

Status command mode until another valid command is written to the command register.

Figure 8. Program Operation

tPROG

R/B

I/Ox

Pass

80h

Address & Data Input

I/O0

Fail

10h

70h

COPY-BACK PROGRAM

The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within

the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are

removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of

the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execu-

tion of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation

with "00h" command with the address of the source page moves the whole 264words data into the internal buffer. As soon as the

Flash returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page fol-

lowed. The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the

Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the

memory array is internally partitioned into two different planes, copy-back program is allowed only within the same memory plane.

Thus, A14 and A25, the plane address, of source and destination page address must be the same.

Figure 9. Copy-Back Program Operation

tR

tPROG

R/B

I/Ox

Add.(4Cycles)

Pass

00h

Add.(4Cycles)

I/O0

Fail

8Ah

70h

Source Address

Destination Address

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Preliminary

KBE00D002M-F407

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup

command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block

address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that

memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When

the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 10 details the sequence.

Figure 10. Block Erase Operation

tBERS

R/B

Pass

60h

I/O0

Fail

I/Ox

70h

Address Input(3Cycle)

Block Add. : A9 ~ A25

D0h

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs

the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows

the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE

does not need to be toggled for updated status. Refer to table 3 for specific Status Register definitions. The command register

remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read

cycle, a read command(00h or 50h) should be given before sequential page read cycle.

Table 3. Read Status Register Definition

I/O #

Status

Definition

"0" : Successful Program / Erase

I/O 0

Program / Erase

"1" : Error in Program / Erase

I/O 1

I/O 2

"0"

Reserved for Future

Use

I/O 3

I/O 4

I/O 5

I/O 6

Device Operation

Write Protect

Not use

"0" : Busy

"1" : Ready

"1" : Not Protected

I/O 7

"0" : Protected

Don’t care

I/O 8~15

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Preliminary

KBE00D002M-F407

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register

remains in Read ID mode until further commands are issued to it. Figure 11 shows the operation sequence.

Figure 11. Read ID Operation

CLE

tCEA

CE

WE

tAR

ALE

RE

tWHR

tREA

I/Ox

ECh

00h

XX46h

90h

Address. 1cycle

Maker code

Device code

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. Refer to table 4 for device status after reset operation. If the device is

already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST

after the Reset command is written. Refer to Figure 12 below.

Figure 12. RESET Operation

tRST

R/B

I/Ox

FFh

Table4. Device Status

After Power-up

After Reset

Operation Mode

Waiting for next command

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Preliminary

KBE00D002M-F407

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-

ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin

is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart. Its value can be deter-

mined by the following guidance.

Rp

ibusy

Vccqn

VOL : 0.1V, VOH : Vccq-0.1V

Ready Vccqn

R/Bn

open drain output

VOH

VOL

Busy

tf

tr

GND

Device

@ Vcc = 1.8V, Ta = 25°C , C_L= 30pF

Ibusy

300n

3m

1.7

200n

100n

2m

1m

120

0.85

60

90

tr

30

0.57

1.7

0.43

1.7

2K

tf

4K

1K

3K

Rp(ohm)

Rp value guidance

Vccq(Max.) - VOL(Max.)

1.9V

3mA + SIL

Rp(min, 1.8V part) =

=

IOL + SIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

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Preliminary

KBE00D002M-F407

Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 1.1V. WP pin provides hardware protection and is recommended to be kept at VIL

during power-up and power-down and recovery time of minimum 10ms is required before internal circuit gets ready for any command

sequences as shown in Figure 13. The two step command sequence for program/erase provides additional software protection.

Figure 13. AC Waveforms for Power Transition

~ 1.5V

VCC

High

WP

WE

10ms

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MCP MEMORY

Preliminary

KBE00D002M-F407

256Mb(8Mb x 32)

Mobile SDRAM DDP E‘-Die

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MCP MEMORY

Preliminary

KBE00D002M-F407

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

Unit

V

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

-1.0 ~ 2.6

V

-55 ~ +150

°C

W

Power dissipation

PD

1.0

50

Short circuit current

IOS

mA

NOTES:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Parameter

Symbol

VDD

VDDQ

VIH

Min

1.65

Typ

Max

Unit

V

Note

1.8

1.95

Supply voltage

1.65

1.8

1.95

V

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

NOTES :

0.8 x VDDQ

-0.3

-

0

-

VDDQ + 0.3

V

1

VIL

0.3

-

V

2

VOH

VOL

VDDQ -0.2

-

V

IOH = -0.1mA

IOL = 0.1mA

3

-

0.2

10

V

ILI

-10

-

uA

1. VIH (max) = 2.2V AC.The overshoot voltage duration is £ 3ns.

2. VIL (min) = -1.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.

4. Dout is disabled, 0V £ VOUT £ VDDQ.

CAPACITANCE (VDD = 2.5V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)

Symbol

CCLK

CIN

Min

3.0

1.5

3.0

Max

8.0

4.0

8.0

6.5

Unit

Note

Clock

pF

RAS, CAS, WE, CS, CKE

DQM

CIN

Address

CADD

COUT

DQ0 ~ DQ31

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Preliminary

KBE00D002M-F407

DC CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Version

Parameter

Symbol

Test Condition

Unit Note

-1L

-15

Burst length = 1

tRC ³ tRC(min)

IO = 0 mA

Operating Current

(One Bank Active)

ICC1

70

60

mA

1

ICC2P CKE £ VIL(max), tCC = 10ns

0.6

Precharge Standby Current in

power-down mode

ICC2PS CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

ICC2N

20

2

Input signals are changed one time during 20ns

Precharge Standby Current

in non power-down mode

mA

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

ICC2NS

Input signals are stable

ICC3P CKE £ VIL(max), tCC = 10ns

8

Active Standby Current

in power-down mode

ICC3PS CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

ICC3N

40

10

mA

Active Standby Current

in non power-down mode

(One Bank Active)

Input signals are changed one time during 20ns

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

ICC3NS

Input signals are stable

IO = 0 mA

Operating Current

(Burst Mode)

Page burst

4Banks Activated

ICC4

100

80

mA

1

tCCD = 2CLKs

Refresh Current

ICC5

ICC6

tARFC ³ tARFC(min)

170

Max 40

320

150

mA

2

3

Internal TCSR

4Banks

Max 85/70

600

°C

Self Refresh Current

CKE £ 0.2V

-G/F

uA

2Banks

1Bank

260

400

230

300

NOTES:

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Internal TCSR can be supported.

In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C

4. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).

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Preliminary

KBE00D002M-F407

AC OPERATING TEST CONDITIONS(VDD = 2.5V ± 0.2V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Parameter

AC input levels (Vih/Vil)

Value

0.9 x VDDQ / 0.2

0.5 x VDDQ

tr/tf = 1/1

Unit

V

Input timing measurement reference level

Input rise and fall time

V

ns

V

Output timing measurement reference level

Output load condition

0.5 x VDDQ

See Figure 2

VDDQ

13.9KW

Vtt=0.5 x VDDQ

VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA

VOL (DC) = 0.2V, IOL = 0.1mA

30pF

Output

50W

10.6KW

Output

Z0=50W

30pF

Figure 1. DC Output Load Circuit

Figure 2. AC Output Load Circuit

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Preliminary

KBE00D002M-F407

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-1L

19

-15

30

60

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

ns

1

28.5

60

Row precharge time

tRP(min)

ns

tRAS(min)

ns

Row active time

tRAS(max)

tRC(min)

100

us

Row cycle time

88.5

90

ns

1

2

3

2

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

tRDL(min)

2

CLK

-

tDAL(min)

tRDL + tRP

1

tCDL(min)

CLK

ns

tBDL(min)

1

105

120

1

Auto refresh cycle time

tARFC(min)

tSRFX(min)

tCCD(min)

Exit self refresh to active command

Col. address to col. address delay

Number of valid output data

ns

CLK

4

5

CAS latency=3

CAS latency=2

CAS latency=1

2

ea

1

0

NOTES:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

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AC CHARACTERISTICS(AC operating conditions unless otherwise noted)

-1L

-15

Parameter

Symbol

Unit

Note

Min

9.5

15

Max

Min

15

Max

CLK cycle time

CAS latency=3

CAS latency=2

CAS latency=1

CAS latency=3

CAS latency=2

CAS latency=1

CAS latency=3

CAS latency=2

CAS latency=1

tCC

tSAC

tOH

tCH

tCL

1000

ns

1

15

25

30

CLK to valid output delay

Output data hold time

CLK high pulse width

CLK low pulse width

Input setup time

7

8

9

ns

1,2

2

20

24

2.5

3.5

3.0

1.5

1

2.5

3.5

4.0

2.0

1

ns

3

2

tSS

Input hold time

tSH

CLK to output in Low-Z

tSLZ

CAS latency=3

CAS latency=2

CAS latency=1

7

8

9

CLK to output in Hi-Z

tSHZ

ns

20

24

NOTES :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

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KBE00D002M-F407

SIMPLIFIED TRUTH TABLE

A11,

A9 ~ A0

COMMAND

CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP

Note

Register

Refresh

Mode Register Set

Auto Refresh

H

X

H

L

X

OP CODE

1, 2

3

H

X

Entry

3

Self

L

H

L

H

X

L

H

X

H

X

H

3

Refresh

Exit

L

H

X

3

Bank Active & Row Addr.

V

Row Address

Read &

Column Address

Auto Precharge Disable

Auto Precharge Enable

L

Column

4

L

H

L

H

Address

(A0~A8)

H

4, 5

Write &

Column Address

Auto Precharge Disable

Auto Precharge Enable

L

Column

Address

(A0~A8)

4

H

X

L

H

L

H

L

X

V

H

4, 5

Burst Stop

Precharge

X

6

Bank Selection

All Banks

V

X

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

H

L

H

L

X

Clock Suspend or

Active Power Down

X

Exit

X

H

L

Entry

H

Precharge Power Down

Mode

H

L

Exit

L

H

X

V

X

DQM

X

7

H

L

X

H

X

H

No Operation Command

(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)

NOTES :

1. OP Code : Operand Code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are the same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

Partial self refresh can be issued only after setting partial self refresh mode of EMRS.

4. BA0 ~ BA1 : Bank select addresses.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency

is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).

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KBE00D002M-F407

A. MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with Normal MRS

*2

Address

A11 ~ A10/AP

A8

A7

A6

A5

A4

A3

A2

A1

A0

BA0 ~ BA1

A9

"0" Setting for

Normal MRS

*1

Function

W.B.L

Test Mode

CAS Latency

BT

Burst Length

RFU

Normal MRS Mode

Test Mode

CAS Latency

Burst Type

Type

Burst Length

A8 A7

Type

Mode Register Set

Reserved

A6 A5

A4

0

Latency

Reserved

1

A3

0

A2

A1

0

A0

0

BT=0

BT=1

0

1

0

1

0

1

0

1

0

1

0

1

Sequential

Interleave

0

1

2

4

8

1

2

4

8

1

0

1

Reserved

0

2

Mode Select

1

0

Reserved

1

3

BA1 BA0

Mode

1

Write Burst Length

Length

0

Reserved

0

Reserved Reserved

Setting

for Nor-

mal MRS

A9

0

1

0

1

0

Burst

0

1

0

Reserved Reserved

*3

1

Single Bit

1

Reserved

Full Page

Register Programmed with Extended MRS

Address

BA1

BA0

A11 ~ A10/AP

A9

A8

A7

A6

A5

A4

RFU

A3

A2

A1

A0

*1

Function

Mode Select

DS

PASR

RFU

EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)

*4

Mode Select

Driver Strength

A5 Driver Strength

Full

PASR

A0

BA1

BA0

Mode

A6

0

A2

A1

0

# of Banks

4 Banks

0

1

0

1

0

1

Normal MRS

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1/2

1/4

1/8

0

2 Banks

EMRS for Mobile SDRAM

Reserved

1

1 Bank

1

Reserved

Reserved Address

0

A11~A10/AP

0

A9

0

A8

0

A7

0

A4

0

A3

0

1

NOTES:

1. RFU(Reserved for future use) should stay "0" during MRS cycle.

2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

3. Full Page Length : x32 : 64Mb(256) , 128Mb (256), 256Mb (512), 512Mb (512)

4. Mobile SDRAM supports PASR of all banks, 1/2 of all banks and 1/4 of all banks.

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Preliminary

KBE00D002M-F407

Partial Array Self Refresh

1. In order to save power consumption, Mobile SDRAM has PASR option.

2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : 4 Banks(256Mb), 2 Banks(128Mb) and 1 Bank(64Mb).

BA1=0

BA0=0

BA1=0

BA0=1

BA1=0

BA0=0

BA1=0

BA0=1

BA1=0

BA0=0

BA1=0

BA0=1

BA1=1

BA0=0

BA1=1

BA0=1

BA1=1

BA0=0

BA1=1

BA0=1

BA1=1

BA0=0

BA1=1

BA0=1

- 1 Bank

- 4 Banks

- 2 Banks

Partial Self Refresh Area

Internal Temperature Compensated Self Refresh

1. In order to save power consumption, Mobile-DRAM includes the internal temperature sonsor and control units to control the self

refresh cycle automatically according to the two temperature range : Max 40 °C and Max 85 °C(for Extended), Max 70 °C(for

Commercial).

2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ginored.

Self Refresh Current (Icc6)

Temperature Range

Unit

4 Banks

600

2 Banks

400

1 Bank

300

Max 85/70 °C

Max 40 °C

uA

320

260

230

B. POWER UP SEQUENCE

1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.

- Apply VDD before or at the same time as VDDQ.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.

EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.

The default state without EMRS command issued is the half driver strength and all 4 banks refreshed.

The device is now ready for the operation selected by EMRS.

For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.

In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not

needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.

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Preliminary

KBE00D002M-F407

C. BURST SEQUENCE

1. BURST LENGTH = 4

Initial Address

Sequential

Interleave

A1

0

A0

0

1

2

3

1

2

3

0

2

3

0

1

3

0

1

2

0

1

2

3

1

0

3

2

3

0

1

3

2

1

0

1

0

1

2. BURST LENGTH = 8

Initial Address

Sequential

Interleave

A2

0

A1

0

A0

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

0

2

3

4

5

6

7

0

1

3

4

5

6

7

0

1

2

4

5

6

7

0

1

2

3

5

6

7

0

1

2

3

4

5

7

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

1

2

3

0

1

6

7

4

5

3

2

1

0

7

6

5

4

5

6

7

0

1

2

3

5

4

7

6

1

0

3

2

6

7

4

5

2

3

0

1

7

6

5

4

3

2

1

0

1

6

7

0

1

2

3

4

0

3

2

5

4

7

6

0

1

0

1

0

1

0

1

0

1

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Preliminary

KBE00D002M-F407

D. DEVICE OPERATIONS

ADDRESSES of 256Mb

ADDRESSES of 512Mb

BANK ADDRESSES (BA0 ~ BA1)

: In case x 16

This SDRAM is organized as four independent banks of

8,388,608 words x 16 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~

BA1 are latched at bank active, read, write, mode register set

and precharge operations.

This SDRAM is organized as four independent banks of

4,194,304 words x 16 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~

BA1 are latched at bank active, read, write, mode register set

and precharge operations.

: In case x 32

This SDRAM is organized as four independent banks of

4,194,304 words x 32 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~

BA1 are latched at bank active, read, write, mode register set

and precharge operations.

This SDRAM is organized as four independent banks of

2,097,152 words x 32 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~

BA1 are latched at bank active, read, write, mode register set

and precharge operations.

ADDRESS INPUTS (A0 ~ A12)

: In case x 16

The 22 address bits are required to decode the 4,194,304 word

locations are multiplexed into 13 address input pins (A0 ~ A12).

The 13 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 9 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

The 23 address bits are required to decode the 8,388,608 word

locations are multiplexed into 13 address input pins (A0 ~ A12).

The 13 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 10 bit column

addresses are latched along with CAS, WE and BA0 ~ BA1 dur-

ing read or write command.

: In case x 32

The 21 address bits are required to decode the 2,097,152 word

locations are multiplexed into 12 address input pins (A0 ~ A11).

The 12 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 9 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

The 22 address bits are required to decode the 4,194,304 word

locations are multiplexed into 13 address input pins (A0 ~ A12).

The 13 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 9 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

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Preliminary

KBE00D002M-F407

D. DEVICE OPERATIONS (continued)

CLOCK (CLK)

The clock input is used as the reference for all SDRAM opera-

DQM OPERATION

The DQM is used to mask input and output operations. It works

similar to OE during read operation and inhibits writing during

write operation. The read latency is two cycles from DQM and

zero cycle for write, which means DQM masking occurs two

cycles later in read cycle and occurs in the same cycle during

write cycle. DQM operation is synchronous with the clock. The

DQM signal is important during burst interruptions of write with

read or precharge in the SDRAM. Due to asynchronous nature of

the internal write, the DQM operation is critical to avoid unwanted

or incomplete writes when the complete burst write is not

required. Please refer to DQM timing diagram also.

tions. All operations are synchronized to the positive going edge

of the clock. The clock transitions must be monotonic between

VIL and VIH. During operation with CKE high all inputs are

assumed to be in a valid state (low or high) for the duration of

set-up and hold time around positive edge of the clock in order to

function well Q perform and ICC specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE

goes low synchronously with clock (set-up and hold time are the

same as other inputs), the internal clock is suspended from the

next clock cycle and the state of output and burst address is fro-

zen as long as the CKE remains low. All other inputs are ignored

from the next clock cycle after CKE goes low. When all banks are

in the idle state and CKE goes low synchronously with clock, the

SDRAM enters the power down mode from the next clock cycle.

The SDRAM remains in the power down mode ignoring the other

inputs as long as CKE remains low. The power down exit is syn-

chronous as the internal clock is suspended. When CKE goes

high at least "1CLK + tSS" before the high going edge of the

clock, then the SDRAM becomes active from the same clock

edge accepting all the input commands.

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various

operating modes of SDRAM. It programs the CAS latency, burst

type, burst length, test mode and various vendor specific options

to make SDRAM useful for variety of different applications. The

default value of the mode register is not defined, therefore the

mode register must be written after power up to operate the

SDRAM. The mode register is written by asserting low on CS,

RAS, CAS and WE (The SDRAM should be in active mode with

CKE already high prior to writing the mode register). The state of

address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS,

RAS, CAS and WE going low is the data written in the mode reg-

ister. Two clock cycles is required to complete the write in the

mode register. The mode register contents can be changed

using the same command and clock cycle requirements during

operation as long as all banks are in the idle state. The mode

register is divided into various fields depending on the fields of

functions. The burst length field uses A0 ~ A2, burst type uses

A3, CAS latency (read latency from column address) use A4 ~

A6, vendor specific options or test mode use A7 ~ A8, A10/AP ~

An and BA0 ~ BA1. The write burst length is programmed using

A9. A7 ~ A8, A10/AP ~ An and BA0 ~ BA1 must be set to low for

normal SDRAM operation. Refer to the table for specific codes

for various burst length, burst type and CAS latencies.

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no

operation (NOP). NOP does not initiate any new operation, but is

needed to complete operations which require more than single

clock cycle like bank activate, burst read, auto refresh, etc. The

device deselect is also a NOP and is entered by asserting CS

high. CS high disables the command decoder so that RAS, CAS,

WE and all the address inputs are ignored.

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KBE00D002M-F407

D. DEVICE OPERATIONS (continued)

The SDRAM has four internal banks in the same chip and shares

part of the internal circuitry to reduce chip area, therefore it

restricts the activation of four banks simultaneously. Also the

noise generated during sensing of each bank of SDRAM is high,

requiring some time for power supplies to recover before another

bank can be sensed reliably. tRRD(min) specifies the minimum

time required between activating different bank. The number of

clock cycles required between different bank activation must be

calculated similar to tRCD specification. The minimum time

required for the bank to be active to initiate sensing and restoring

the complete row of dynamic cells is determined by tRAS(min).

Every SDRAM bank activate command must satisfy tRAS(min)

specification before a precharge command to that active bank

can be asserted. The maximum time any bank can be in the

active state is determined by tRAS(max). The number of cycles for

both tRAS(min) and tRAS(max) can be calculated similar to tRCD

specification.

EXTENDED MODE REGISTER SET (EMRS)

The extended mode register stores the data for selecting driver

strength, partial self refresh or temperature compensated self

refresh. EMRS cycle is not mandatory and the EMRS command

needs to be issued only when DS or PASR is used. The default

state without EMRS command issued is half driver strength, and

all 4 banks refreshed. The extended mode register is written by

asserting low on CS, RAS, CAS, WE and high on BA1 ,low on

BA0(The SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register).

The state of address pins A0 ~ A11 in the same cycle as CS,

RAS, CAS and WE going low is written in the extended mode

register. Two clock cycles are required to complete the write

operation in the extended mode register. The mode register con-

tents can be changed using the same command and clock cycle

requirements during operation as long as all banks are in the idle

state. A0 - A2 are used for partial self refresh , A5 - A6 are used

for Driver strength, "Low" on BA1 and "High" on BA0 are used

for EMRS. All the other address pins except A0-A2, A5-A6 and

BA1, BA0 must be set to low for proper EMRS operation. Refer to

the table for specific codes.

BURST READ

The burst read command is used to access burst of data on con-

secutive clock cycles from an active row in an active bank. The

burst read command is issued by asserting low on CS and CAS

with WE being high on the positive edge of the clock. The bank

must be active for at least tRCD(min) before the burst read com-

mand is issued. The first output appears in CAS latency number

of clock cycles after the issue of burst read command. The burst

length, burst sequence and latency from the burst read command

is determined by the mode register which is already pro-

grammed. The burst read can be initiated on any column address

of the active row. The address wraps around if the initial address

does not start from a boundary such that number of outputs from

each I/O are equal to the burst length programmed in the mode

register. The output goes into high-impedance at the end of the

burst, unless a new burst read was initiated to keep the data out-

put gapless. The burst read can be terminated by issuing another

burst read or burst write in the same bank or the other active

bank or a precharge command to the same bank. The burst stop

command is valid at every page burst length.

BANK ACTIVATE.

The bank activate command is used to select a random row in an

idle bank. By asserting low on RAS and CS with desired row and

bank address, a row access is initiated. The read or write opera-

tion can occur after a time delay of tRCD(min) from the time of

bank activation. tRCD is an internal timing parameter of SDRAM,

therefore it is dependent on operating clock frequency. The mini-

mum number of clock cycles required between bank activate and

read or write command should be calculated by dividing

tRCD(min) with cycle time of the clock and then rounding off the

result to the next higher integer.

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MCP MEMORY

Preliminary

KBE00D002M-F407

D. DEVICE OPERATIONS (continued)

BURST WRITE

AUTO PRECHARGE

The burst write command is similar to burst read command and The precharge operation can also be performed by using auto

is used to write data into the SDRAM on consecutive clock precharge. The SDRAM internally generates the timing to satisfy

cycles in adjacent addresses depending on burst length and tRAS(min) and "tRP" for the programmed burst length and CAS

burst sequence. By asserting low on CS, CAS and WE with valid latency. The auto precharge command is issued at the same

column address, a write burst is initiated. The data inputs are time as burst read or burst write by asserting high on A10/AP. If

provided for the initial address in the same clock cycle as the burst read or burst write by asserting high on A10/AP, the bank is

burst write command. The input buffer is deselected at the end of left active until a new command is asserted. Once auto pre-

the burst length, even though the internal writing can be com- charge command is given, no new commands are possible to

pleted yet. The writing can be completed by issuing a burst read that particular bank until the bank achieves idle state.

and DQM for blocking data inputs or burst write in the same or

another active bank. The burst stop command is valid at every

burst length. The write burst can also be terminated by using

AUTO REFRESH

DQM for blocking data and procreating the bank tRDL after the The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to

last data input to be written into the active row. See DQM be refreshed every 64ms to maintain data. An auto refresh cycle

OPERATION also.

accomplishes refresh of a single row of storage cells. The inter-

nal counter increments automatically on every auto refresh cycle

to refresh all the rows. An auto refresh command is issued by

asserting low on CS, RAS and CAS with high on CKE and WE.

The auto refresh command can only be asserted with all banks

being in idle state and the device is not in power down mode

(CKE is high in the previous cycle). The time required to com-

plete the auto refresh operation is specified by tRC(min). The min-

imum number of clock cycles required can be calculated by

driving tRC with clock cycle time and them rounding up to the next

higher integer. The auto refresh command must be followed by

NOP's until the auto refresh operation is completed. All banks will

ALL BANKS PRECHARGE

All banks can be precharged at the same time by using Pre-

charge all command. Asserting low on CS, RAS, and WE with

high on A10/AP after all banks have satisfied tRAS(min) require-

ment, performs precharge on all banks. At the end of tRP after

performing precharge to all the banks, all banks are in idle state.

PRECHARGE

The precharge operation is performed on an active bank by be in the idle state at the end of auto refresh operation. The auto

asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1 refresh is the preferred refresh mode when the SDRAM is being

of the bank to be precharged. The precharge command can be used for normal data transactions. The 64Mb and 128Mb

asserted anytime after tRAS(min) is satisfied from the bank active SDRAM’s auto refresh cycle can be performed once in 15.6us or

command in the desired bank. tRP is defined as the minimum a burst of 4096 auto refresh cycles once in 64ms. The 256Mb

number of clock cycles required to complete row precharge is and 512Mb SDRAM’s auto refresh cycle can be performed once

calculated by dividing tRP with clock cycle time and rounding up in 7.8us or a burst of 8192 auto refresh cycles once in 64ms.

to the next higher integer. Care should be taken to make sure

that burst write is completed or DQM is used to inhibit writing

before precharge command is asserted. The maximum time any

bank can be active is specified by tRAS(max). Therefore, each

bank activate command. At the end of precharge, the bank

enters the idle state and is ready to be activated again. Entry to

Power down, Auto refresh, Self refresh and Mode register set

etc. is possible only when all banks are in idle state.

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MCP MEMORY

Preliminary

KBE00D002M-F407

D. DEVICE OPERATIONS(continued)

SELF REFRESH

The self refresh is another refresh mode available in the

SDRAM. The self refresh is the preferred refresh mode for data

retention and low power operation of SDRAM. In self refresh

mode, the SDRAM disables the internal clock and all the input

buffers except CKE. The refresh addressing and timing are inter-

nally generated to reduce power consumption.

The self refresh mode is entered from all banks idle state by

asserting low on CS, RAS, CAS and CKE with high on WE. Once

the self refresh mode is entered, only CKE state being low mat-

ters, all the other inputs including the clock are ignored in order

to remain in the self refresh mode.

The self refresh is exited by restarting the external clock and then

asserting high on CKE. This must be followed by NOP's for a

minimum time of tSRFX before the SDRAM reaches idle state to

begin normal operation. In case that the system uses burst auto

refresh during normal operation, it is recommended to use burst

8192 auto refresh cycles for 256Mb and 512Mb, and burst 4096

auto refresh cycles for 128Mb and 64Mb immediately before

entering self refresh mode and after exiting in self refresh mode.

On the other hand, if the system uses the distributed auto

refresh, the system only has to keep the refresh duty cycle.

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MCP MEMORY

Preliminary

KBE00D002M-F407

E. BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

1) Clock Suspended During Write

CLK

2) Clock Suspended During Read (BL=4)

CLK

CMD

CKE

WR

CMD

CKE

RD

Masked by CKE

Internal

CLK

Internal

CLK

D

D0

D1

D2

D3

DQ(CL2)

DQ(CL3)

DQ(CL2)

DQ(CL3)

Q0

Q1

Q2

Q1

Q3

Q2

Q0

Q3

Not Written

Suspended Dout

2. DQM Operation

1) Write Mask (BL=4)

CLK

2) Read Mask (BL=4)

CLK

CMD

DQM

CMD

DQM

WR

RD

Masked by CKE

D3

Masked by CKE

Hi-Z

DQ(CL2)

DQ(CL3)

DQ(CL2)

DQ(CL3)

Q0

Q2

Q1

Q3

Q2

D0

D1

Hi-Z

D3

Q3

DQM to Data-in Mask = 0

DQM to Data-out Mask = 2

3) DQM with Clock Suspended (Full Page Read) ^*2

CLK

CMD

RD

CKE

DQM

Hi-Z

Q0

Q2

Q1

Q4

Q3

Q6

Q5

Q7

Q6

Q8

Q7

DQ(CL2)

DQ(CL3)

Hi-Z

*NOTES :

1. CKE to CLK disable/enable = 1CLK.

2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"

3. DQM masks both data-in and data-out.

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MCP MEMORY

Preliminary

KBE00D002M-F407

3. CAS Interrupt (I)

1) Read interrupted by Read (BL=4) ^*1

CLK

RD RD

CMD

ADD

A

B

DQ(CL2)

DQ(CL3)

QA0 QB0 QB1 QB1 QB3

*2

tCCD

2) Write interrupted by Write (BL=2)

CLK

3) Write interrupted by Read (BL=2)

CLK

WR RD

WR WR

CMD

*2

tCCD

ADD

A

B

A

B

ADD

DQ

DQ(CL2)

DQ(CL3)

DA0

QB0 QB1

DA0 DB0 DB1

*3

tCDL

*3

tCDL

*NOTES:

1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.

By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.

2. tCCD : CAS to CAS delay. (=1CLK)

3. tCDL : Last data in to new column address delay. (=1CLK)

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MCP MEMORY

Preliminary

KBE00D002M-F407

4. CAS Interrupt (II) : Read Interrupted by Write & DQM

(a) CL=2, BL=4

CLK

i) CMD

RD WR

DQM

DQ

D0

D1

D2

D3

D2

ii) CMD

RD

WR

DQM

DQ

Hi-Z

D0

D1

D3

iii) CMD

RD

WR

DQM

DQ

Hi-Z

D0

D1

D2

D1

D3

D2

iv) CMD

RD

WR

DQM

DQ

Hi-Z

*1

Q0

D0

D3

(b) CL=3, BL=4

CLK

RD WR

i) CMD

DQM

DQ

D0

D1

D2

D3

D2

ii) CMD

RD

WR

DQM

DQ

D0

D1

D3

D2

iii) CMD

RD

WR

DQM

DQ

D0

D1

D3

D2

D1

iv) CMD

WR

DQM

DQ

Hi-Z

D0

D1

D3

D2

v) CMD

RD

WR

DQM

DQ

Hi-Z

*1

Q0

D0

D3

*NOTE:

1. To prevent bus contention, there should be at least one gap between data in and data out.

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Preliminary

KBE00D002M-F407

5. Write Interrupted by Precharge & DQM

1) tRDL = 2CLK

CLK

*3

CMD

DQM

WR

D0

PRE

*2

D1

D2

DQ

Masked by DQM

*NOTES:

1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.

2. To inhibit invalid write, DQM should be issued.

3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank pre-

charge of four banks operation.

6. Precharge

1) Normal Write

BL=4 & tRDL=2CLK

CLK

CMD

DQ

WR

D0

PRE

D1

D2

D3

*1

tRDL

2) Normal Read (BL=4)

CLK

*2

RD

PRE

Q2

CMD

1

Q0

Q1

Q0

Q3

Q2

DQ(CL2)

2

Q1

Q3

DQ(CL3)

7. Auto Precharge

1) Normal Write (BL=4)

CLK

2) Normal Read (BL=4)

CLK

CMD

DQ

WR

D0

ACT

CMD

RD

DQ(CL2)

DQ(CL3)

Q0

Q1

Q0

Q2

Q1

Q3

Q2

D1

D2

D3

tRDL =2CLK

tDAL =tRDL + tRP

Q3

*4

*3

Auto Precharge Starts

*3

Auto Precharge Starts@tRDL=2CLK

*NOTES:

1. SAMSUNG can support tRDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK.

2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of other activated bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same bank is illegal

4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP .

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MCP MEMORY

Preliminary

KBE00D002M-F407

8. Burst Stop & Interrupted by Precharge

1) Normal Write

BL=4 & tRDL=2CLK

CLK

WR

D0

PRE

CMD

DQM

D1

D2

tRDL

DQ

*1

2) Write Burst Stop (BL=8)

CLK

3) Read Interrupted by Precharge (BL=4)

CLK

WR

STOP

RD

PRE

Q0

CMD

DQ(CL2)

DQ(CL3)

1

Q1

Q0

DQM

DQ

2

D0

D1

D2

D3

Q1

*2

tBDL

4) Read Burst Stop (BL=4)

CLK

RD

STOP

Q0

CMD

1

Q1

Q0

DQ(CL2)

DQ(CL3)

2

Q1

9. MRS

1) Mode Register Set

CLK

*4

CMD

PRE

MRS

ACT

tRP

2CLK

*NOTES:

1. SAMSUNG can support tRDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK.

2. tBDL : 1 CLK ; Last data in to burst stop delay.

Read or write burst stop command is valid at every burst length.

3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively.

4. PRE : All banks precharge is necessary.

MRS can be issued only at all banks precharge state.

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MCP MEMORY

Preliminary

KBE00D002M-F407

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit

CLK

2) Power Down (=Precharge Power Down) Exit

CLK

CKE

tSS

*2

*1

Internal

CLK

RD

NOP ACT

CMD

11. Auto Refresh & Self Refresh

Auto Refresh

An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the

clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external

address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed,

all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto

refresh command must be greater than or equal to the tARFC(min).

CLK

Auto

Refresh

PRE

CMD

Command

CKE = High

tRP

tARFC(min) = 105ns

Self Refresh

A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once

the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self

refresh command, all of the external control signals including system clock(CLK) can be disabled except CKE. The clock is internally

disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before returning

CKE high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during normal

opreation, it is recommended to use burst 4096 auto refresh cycle immediately before entering self refresh mode and after exiting in

self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty

cycle.

CLK

Stable Clock

Self

Refresh

ACT

NOP

Command

tSRFX(min) = 120ns

CKE

tSS

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MCP MEMORY

Preliminary

KBE00D002M-F407

12. About Burst Type Control

At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=1, 2, 4, 8 and full page.

Sequential Counting

Basic

MODE

At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting.

Interleave Counting

Every cycle Read/Write Command with random column address can realize Random

Column Access.

That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

Random

MODE

Random column Access

tCCD = 1 CLK

13. About Burst Length Control

At MRS A2,1,0 = "000".

At auto precharge, tRAS should not be violated.

1

At MRS A2,1,0 = "001".

At auto precharge, tRAS should not be violated.

2

Basic

MODE

4

8

At MRS A2,1,0 = "010".

At MRS A2,1,0 = "011".

At MRS A2,1,0 = "111".

Full Page

Wrap around mode(infinite burst length) should be stopped by burst stop.

RAS interrupt or CAS interrupt.

At MRS A9 = "1".

Read burst =1, 2, 4, 8, full page write Burst =1.

At auto precharge of write, tRAS should not be violated.

Special

MODE

BRSW

Random

MODE

tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively

Using burst stop command, any burst length control is possible.

Burst Stop

Before the end of burst, Row precharge command of the same bank stops read/write

burst with Row precharge.

RAS Interrupt

(Interrupted by Precharge) tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.

During read/write burst with auto precharge, RAS interrupt can not be issued.

Interrupt

MODE

Before the end of burst, new read/write stops read/write burst and starts new

CAS Interrupt

read/write burst.

During read/write burst with auto precharge, CAS interrupt can not be issued.

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Preliminary

KBE00D002M-F407

FUNCTION TRUTH TABLE (TABLE 1)

Current

State

CS

RAS

CAS

WE

BA

Address

Action

Note

H

L

H

L

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

NOP

X

ILLEGAL

2

X

H

L

BA

X

CA, A10/AP ILLEGAL

IDLE

H

L

RA

A10/AP

X

Row (& Bank) Active ; Latch RA

L

NOP

4

5

L

H

L

Auto Refresh or Self Refresh

L

OP code

X

OP code Mode Register Access

X

H

L

X

H

L

X

H

L

X

NOP

X

NOP

X

ILLEGAL

2

Row

Active

H

L

BA

X

CA, A10/AP Begin Read ; latch CA ; determine AP

L

H

L

H

L

RA

ILLEGAL

L

A10/AP

Precharge

L

X

H

L

X

ILLEGAL

X

H

L

X

H

L

X

NOP (Continue Burst to End --> Row Active)

Term burst --> Row active

X

H

L

BA

X

CA, A10/AP Term burst, New Read, Determine AP

CA, A10/AP Term burst, New Write, Determine AP

Read

L

3

2

H

L

H

L

RA

ILLEGAL

L

A10/AP

Term burst, Precharge timing for Reads

ILLEGAL

L

X

H

L

X

H

L

X

H

L

X

NOP (Continue Burst to End --> Row Active)

Term burst --> Row active

X

H

L

BA

X

CA, A10/AP Term burst, New read, Determine AP

CA, A10/AP Term burst, New Write, Determine AP

3

2

3

Write

L

H

L

H

L

RA

ILLEGAL

L

A10/AP

Term burst, precharge timing for Writes

ILLEGAL

L

X

H

L

X

H

L

X

H

L

X

NOP (Continue Burst to End --> Precharge)

ILLEGAL

X

Read with

Auto

Precharge

X

H

L

BA

X

CA, A10/AP ILLEGAL

RA, RA10 ILLEGAL

H

L

2

L

X

ILLEGAL

X

H

L

X

H

L

X

NOP (Continue Burst to End --> Precharge)

ILLEGAL

X

Write with

Auto

Precharge

X

BA

X

CA, A10/AP ILLEGAL

RA, RA10 ILLEGAL

H

L

X

ILLEGAL

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MCP MEMORY

Preliminary

KBE00D002M-F407

FUNCTION TRUTH TABLE (TABLE 1)

Current

CS

H

L

RAS

X

H

L

CAS

X

H

L

WE

X

H

L

BA

X

Address

Action

NOP --> Idle after tRP

Note

X

NOP --> Idle after tRP

ILLEGAL

L

X

2

4

Precharging

L

X

H

L

BA

X

CA

ILLEGAL

L

H

L

RA

ILLEGAL

L

A10/AP

NOP --> Idle after tRP

ILLEGAL

L

X

H

L

X

H

L

X

H

L

X

H

L

X

NOP --> Row Active after tRCD

ILLEGAL

X

Row

Activating

L

X

2

L

X

H

L

BA

X

CA

ILLEGAL

L

H

L

RA

ILLEGAL

L

A10/AP

ILLEGAL

L

X

H

L

X

ILLEGAL

H

L

X

H

L

X

H

L

X

NOP --> Idle after tRC

ILLEGAL

X

Refreshing

L

X

L

H

L

X

ILLEGAL

L

X

ILLEGAL

H

L

X

H

L

X

H

L

X

NOP --> Idle after 2 clocks

ILLEGAL

Mode

Register

Accessing

X

L

X

L

X

ILLEGAL

L

X

ILLEGAL

Abbreviations : RA = Row Address

NOP = No Operation Command

BA = Bank Address

CA = Column Address

AP = Auto Precharge

*NOTES:

1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.

2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the

state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).

5. Illegal if any bank is not idle.

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Preliminary

KBE00D002M-F407

FUNCTION TRUTH TABLE (TABLE 2)

Current

State

CKE

(n-1)

CKE

n

CS

RAS

CAS

WE

Address

Action

Note

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

RA

X

Exit Self Refresh --> Idle after tsRFX(ABI)

Exit Self Refresh --> Idle after tsRFX (ABI)

ILLEGAL

6

L

Self

Refresh

L

X

H

L

ILLEGAL

L

X

H

L

ILLEGAL

L

X

H

L

X

H

L

NOP (Maintain Self Refresh)

INVALID

H

L

X

H

L

Exit Power Down --> ABI

ILLEGAL

All

Banks

Precharge

Power

L

7

L

X

H

L

ILLEGAL

Down

L

X

H

L

ILLEGAL

L

X

H

L

X

H

L

NOP (Maintain Low Power Mode)

Refer to Table 1

H

L

H

L

Enter Power Down

ILLEGAL

L

8

All

Banks

Idle

L

X

H

L

ILLEGAL

L

H

L

Row (& Bank) Active

Enter Self Refresh

L

8

L

OP Code Mode Register Access

L

X

NOP

H

L

H

L

Refer to Operations in Table 1

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

Maintain Clock Suspend

Any State

other than

Listed

9

H

L

above

L

Abbreviations : ABI = All Banks Idle, RA = Row Address

*NOTES:

6. CKE low to high transition is asynchronous.

7. CKE low to high transition is asynchronous if restarts internal clock.

A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.

8. Power down and self refresh can be entered only from the all banks idle state.

9. Must be a legal command.

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MCP MEMORY

Preliminary

KBE00D002M-F407

Power Up Sequence

Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1

Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

Page Read Cycle at Different Bank @Burst Length=4

Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK

Read & Write Cycle at Different Bank @Burst Length=4

Read & Write Cycle With Auto Precharge l @Burst Length=4

Read & Write Cycle With Auto Precharge ll @Burst Length=4

Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4

Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK

Burst Read Single bit Write Cycle @Burst Length =2

Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4

Self Refresh Entry & Exit Cycle & Exit Cycle

Mode Register Set Cycle and Auto Refresh Cycle

Extended Mode Register Set Cycle

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Preliminary

KBE00D002M-F407

Power Up Sequence for Mobile SDRAM

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

CLOCK

CKE

Hi

CS

RAS

CAS

ADDR

BA0

BA1

Key

RAa

A10/AP

DQ

RAa

Hi-Z

WE

High level is necessary

tRP

DQM

tARFC

Precharge

(All Bank)

Auto

Refresh

Auto

Refresh

Normal

MRS

Extended

MRS

Row Active

(A-Bank)

: Don’t care

*NOTES:

1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.

- Apply VDD before or at the same time as VDDQ.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.

EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.

The default state without EMRS command issued is half driver strength, all 4 banks refreshed.

The device is now ready for the operation selected by EMRS.

For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.

In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again

at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.

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Preliminary

KBE00D002M-F407

Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1

tCH

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

CS

tCC

tCL

HIGH

tSH

tRP

tRAS

tRC

*Note 1

tRCD

tSS

tSH

RAS

CAS

tSS

tSH

tSS

Ca

ADDR

BA0,BA1

A10/AP

Ra

Cb

Cc

Rb

tSS

*Note 2

BS

*Note 2,3

BS

*Note 2,3

BS

*Note 2,3 *Note 4

BS BS

*Note 2

BS

*Note 3

*Note 3 *Note 4

Ra

Rb

tSH

Db

tSAC

Qa

DQ

WE

Qc

tSS

tSS tSH

tSLZ

tOH

tSS tSH

DQM

Row Active

Read

Write

Read

Row Active

Precharge

: Don’t care

*NOTES:

1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA0,BA1.

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Preliminary

KBE00D002M-F407

Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

*Note 1

tRC

CS

RAS

*Note 2

CAS

ADDR

BA0

Ra

Ca

Rb

Cb

BA1

A10/AP

CL=2

Ra

Rb

tOH

Qa0 Qa1 Qa2 Qa3

Db0 Db1 Db2 Db3

tRDL

tSHZ

tRCD

tSAC

tOH

*Note 4

tSHZ

DQ

{

CL=3

Qa0 Qa1 Qa2 Qa3

tSAC

tRDL

*Note 4

WE

DQM

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don’t care

*NOTES:

1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data

is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.

3. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)

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Preliminary

KBE00D002M-F407

Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

*Note 2

CAS

ADDR

BA0

Ra

Ca

Cb

Cc

Cd

Rb

BA1

A10/AP

CL=2

Ra

Rb

tRDL

Qa0 Qa1 Qb0 Qb1 Qb2

Dc0 Dc1 Dd0 Dd1

tRCD

tDAL

*Note 4

DQ

{

CL=3

Qa0 Qa1 Qb0 Qb1

Dc0 Dc1 Dd0 Dd1

tCDL

WE

*Note 1

*Note 3

DQM

Row Active

(A-Bank)

Read

(A-Bank)

Read

(A-Bank)

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

Row Active

(A-Bank)

: Don’t care

*NOTES:

1. To write data before burst read ends, DQM should be asserted three cycle prior to write

command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

4. tDAL ,last data in to active delay, is 2CLK + tRP.

Revision 0.1

August 2003

- 59 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Page Read Cycle at Different Bank @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

*Note 1

CS

RAS

*Note 2

CAS

ADDR

BA0

RAa

RBb CAa

RCc CBb

RDd CCc

CDd

BA1

A10/AP

CL=2

RAa

RBb

RCc

RDd

QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2

QDd0 QDd1 QDd2

DQ

{

CL=3

QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2

WE

DQM

Row Active

(A-Bank)

Read

(A-Bank)

Read

(B-Bank)

Read

(C-Bank)

Read

(D-Bank)

Precharge

(D-Bank)

Row Active

(B-Bank)

Row Active

(C-Bank)

Row Active

(D-Bank)

Precharge

(C-Bank)

Precharge

(A-Bank)

Precharge

(B-Bank)

: Don’t care

*NOTES:

1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.

2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

Revision 0.1

August 2003

- 60 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

CS

HIGH

RAS

CAS

ADDR

BA0

*Note 2

RAa

RAb CAa

CBb RCc

RDd CCc

CDd

BA1

A10/AP

DQ

RAa

RBb

RCc

RDd

DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2

tCDL

tRDL

WE

*Note 1

DQM

Row Active

(A-Bank)

Write

(A-Bank)

Write

(B-Bank)

Row Active

(D-Bank)

Write

(D-Bank)

Precharge

(All Banks)

Row Active

(B-Bank)

Row Active

(C-Bank)

Write

(C-Bank)

: Don’t care

*NOTES:

1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.

Revision 0.1

August 2003

- 61 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Read & Write Cycle at Different Bank @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

ADDR

BA0

RAa

CAa

RDb

CDb RBc

CBc

BA1

A10/AP

CL=2

RAa

RDb

RBc

tCDL

*Note 1

QAa0 QAa1 QAa2 QAa3

DDb0 DDb1 DDb2 DDb3

QBc0 QBc1 QBc2

QBc0 QBc1

DQ

{

CL=3

QAa0 QAa1 QAa2 QAa3

WE

DQM

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Write

(D-Bank)

Read

(B-Bank)

Row Active

(D-Bank)

Row Active

(B-Bank)

: Don’t care

*NOTE:

1. tCDL should be met to complete write.

Revision 0.1

August 2003

- 62 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Read & Write Cycle with Auto Precharge I @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

ADDR

BA0

RAa

RBb CAa

CBb

RAc

CAc

BA1

A10/AP

DQ CL=2

RAa

RBb

RAc

QAa0 QAa1 QBb0 QBb1 QBb2 DBb3

DAc0 DAc1

CL=3

QAa0 QAa1 QBb0 QBb1 QBb2 DBb3

WE

DQM

Row Active

(A-Bank)

Read with Read without Auto

Auto Pre Precharge(B-Bank)

Precharge

(B-Bank)

Row Active

(A-Bank)

Write with

Auto Precharge

(A-Bank)

charge

Auto Precharge

Start Point

(A-Bank)

(A-Bank) *Note1

Row Active

(B-Bank)

: Don’t care

*NOTE:

1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.

- if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank

auto precharge will start at B-Bank read command input point .

- any command can not be issued at A-Bank during tRP after A-Bank auto precharge starts.

Revision 0.1

August 2003

- 63 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Read & Write Cycle with Auto Precharge II @Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

ADDR

BA0

Ra

Ca

Rb

Cb

BA1

A10/AP

DQ CL=2

Ra

Rb

Qa0 Qa1 Qa2 Qa3

Qb0 Qb1 Qb2 Qb3

CL=3

Qa0 Qa1 Qa2 Qa3

Qb0 Qb1 Qb2 Qb3

WE

DQM

*Note1

Auto Precharge

Start Point

Row Active

(A-Bank)

Read with

Auto Precharge

(A-Bank)

Read with

Auto Precharge

(B-Bank)

Auto Precharge

Start Point

(A-Bank)

(B-Bank)

Row Active

(B-Bank)

: Don’t care

*NOTE:

1. Any command to A-bank is not allowed in this period.

tRP is determined from at auto precharge start point

Revision 0.1

August 2003

- 64 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA0

Ra

Ca

Cb

Cc

BA1

A10/AP

DQ

Ra

Qa0 Qa1

Qa2

Qa3

Qb0 Qb1

tSHZ

Dc0

Dc2

tSHZ

WE

*Note 1

DQM

Row Active

Read

Clock

Suspension

Read

Read DQM

Write

DQM

Write

DQM

Write

Clock

Suspension

: Don’t care

*NOTE:

1. DQM is needed to prevent bus contention.

Revision 0.1

August 2003

- 65 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page Burst

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

CAS

ADDR

BA0

RAa

CAa

CAb

BA1

A10/AP

CL=2

RAa

1

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

QAa0 QAa1 QAa2 QAa3 QAa4

DQ

2

{

CL=3

QAa0 QAa1 QAa2 QAa3 QAa4

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

WE

DQM

Precharge

(A-Bank)

Row Active

(A-Bank)

Read

(A-Bank)

Burst Stop

Read

(A-Bank)

: Don’t care

*NOTES:

1. At full page mode, burst is finished by burst stop or precharge.

2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the label 1, 2 on them.

But at burst write, Burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of "Full page write burst stop cycle".

3. Burst stop is valid at every burst length.

Revision 0.1

August 2003

- 66 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst,

tRDL=2CLK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

CS

HIGH

RAS

CAS

ADDR

BA0

RAa

CAa

CAb

BA1

A10/AP

DQ

RAa

tBDL

tRDL

*Note 1

*Note 1,2

DAa0 DAa1 DAa2 DAa3 DAa4

DAb0 DAb1 DAb2 DAb3 DAb4 DAb5

WE

DQM

Row Active

(A-Bank)

Write

(A-Bank)

Burst Stop

Write

(A-Bank)

Precharge

(A-Bank)

: Don’t care

*NOTES:

1. At full page mode, burst is finished by burst stop or precharge.

2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding

memory cell. It is defined by AC parameter of tRDL.

DQM at write interrupted by precharge command is needed to prevent invalid write.

DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

Revision 0.1

August 2003

- 67 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Burst Read Single bit Write Cycle @Burst Length=2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

HIGH

CS

RAS

*Note 2

CAS

ADDR

BA0

RAa

CAa RBb CAb

RCc

CBc

CCd

BA1

A10/AP

CL=2

RAa

RBb

RCc

DAa0

QAb0 QAb1

DBc0

QCd0 QCd1

DQ

{

CL=3

DAa0

QAb0 QAb1

QCd0 QCd1

WE

DQM

Precharge

(C-Bank)

Row Active

(A-Bank)

Row Active

(B-Bank)

Row Active

(C-Bank)

Read

(C-Bank)

Write

Read with

Write with

Auto Precharge

(B-Bank)

(A-Bank) Auto Precharge

(A-Bank)

: Don’t care

*NOTES:

1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.

Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,

the next cycle starts the precharge.

Revision 0.1

August 2003

- 68 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

CS

tSS

*Note 1

tSS

*Note 2

*Note 3

RAS

CAS

ADDR

BA

Ra

Ca

Ra

A10/AP

DQ

Qa0 Qa1 Qa2

tSHZ

WE

DQM

Precharge

Power-down

Entry

Row Active

Read

Precharge

Power-down

Exit

Active

Power-down

Entry

Active

Power-down

Exit

: Don’t care

*NOTES:

1. All banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least 1CLK + tSS prior to Row active command.

3. Can not violate minimum refresh specification. (64ms)

Revision 0.1

August 2003

- 69 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Self Refresh Entry & Exit Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

*Note 2

*Note 4

tSRFX

*Note 1

*Note 6

*Note 3

tSS

CS

RAS

CAS

ADDR

BA0,BA1

A10/AP

DQ

Hi-Z

WE

DQM

Self Refresh Entry

Self Refresh Exit

Auto Refresh

: Don’t care

*NOTES:

TO ENTER SELF REFRESH MODE

1. CS, RAS & CAS with CKE should be low at the same clcok cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.

3. The device remains in self refresh mode as long as CKE stays "Low".

cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS starts from high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb, 512Mb) of burst auto refresh is required before self refresh entry and

after self refresh exit if the system uses burst refresh.

Revision 0.1

August 2003

- 70 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Mode Register Set Cycle

Auto Refresh Cycle

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

8

9

10

CLOCK

CKE

CS

HIGH

*Note 2

tARFC

RAS

CAS

ADDR

BA0

*Note 1

*Note 3

Key

Ra

BA1

DQ

Hi-Z

WE

DQM

MRS

New Command

Auto Refresh

New Command

: Don’t care

* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

*NOTES:

MODE REGISTER SET CYCLE

1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register.

2. Minimum 2 clock cycles should be met before new RAS activation.

3. Please refer to Mode Register Set table.

Revision 0.1

August 2003

- 71 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

Extended Mode Register Set Cycle

0

1

2

3

4

5

6

CLOCK

CKE

CS

HIGH

*Note 2

RAS

CAS

ADDR

BA0

*Note 1

*Note 3

Key

Ra

BA1

Hi-Z

DQ

WE

DQM

EMRS New Command

: Don’t care

*NOTES:

EXTENDED MODE REGISTER SET CYCLE

1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register.

2. Minimum 2 clock cycles should be met before new RAS activation.

3. Please refer to Mode Register Set table.

Revision 0.1

August 2003

- 72 -

Advance

MCP MEMORY

Preliminary

KBE00D002M-F407

PACKAGE DIMENSION

137-Ball Fine pitch Ball Grid Array Package (measured in millimeters)

Units:millimeters

#A1 INDEX MARK

10.50±0.10

A

0.10 MAX

10.50±0.10

0.80x9=7.20

(Datum A)

B

10 9

8 7 6 5 4 3 2 1

0.80

A

B

C

D

#A1

(Datum B)

E

F

G

H

J

K

L

M

N

P

R

3.60

0.32±0.05

1.30±0.10

137-Æ0.45±0.05

BOTTOM VIEW

TOP VIEW

Æ

0.20

M A B

Revision 0.1

August 2003

- 73 -


型号：	KBE00D002M-F407
厂家：	SAMSUNG
描述：	Memory Circuit, Flash+SDRAM, CMOS, PBGA137 动态存储器内存集成电路
文件：	总73页 (文件大小：1306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KBE00D002M-F407 [SAMSUNG]

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