K9S6408V0B_技术文档

K9S5608V0C/B K9S6408V0C/B

K9S2808V0C/B

TM

SmartMedia

Document Title

SmartMedia^TMCard

Revision History

Revision No History

Draft Date

Remark

0.0

0.1

Initial issue

July 17th 2000

Nov. 20th 2000

Advanced

Information

Preliminary

1. Explain how pointer operation works in detail.

2. Updated operation for tRST timing

- If reset command(FFh) is written at Ready state, the device goes

into Busy for maximum 5us.

0.2

1. Renamed the 17th pin from Vcc to LVD(Low Voltage Detect)

-The LVD is used to electrically detect the proper supply voltage.

By connecting this pin to Vss through a pull-down resister, it is pos-

sible to distinguish 3.3V product from 5V product. When 3.3V is

applied as Vcc to pins 12 and 22, a ’High’ level can be detected

on the system side if the device is a 3.3V product, and ’Low’ level

for 5V product.

Mar. 2th 2001

Final

0.3

1.Powerup sequence is added

Sep. 7th 2001

Recovery time of minimum 1ms is required before internal circuit gets

ready for any command sequences

~ 2.5V

V

CC

High

WP

WE

1ms

2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.

3. AC parameter tAR1 value : 100ns --> 20ns

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you

have any questions, please contact the SAMSUNG branch office near your office.

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K9S5608V0C/B K9S6408V0C/B

K9S2808V0C/B

TM

SmartMedia

Revision History

Revision No History

Draft Date

Remark

1. Unified access timing parameter definition for multiple operating modes

- Changed AC characteristics (Before)

0.4

Sep. 7th 2001

Final

Parameter

Symbol

Min

Max

-

Unit

ALE to RE Delay (ID read)

ALE to RE Delay (Read cycle)

RE Low to Status Output

CE Low to Status Output

RE access time(Read ID)

tAR1

tAR2

100

-

ns

tRSTO

tCSTO

tREADID

-

35

45

35

- AC characteristics (After)

. Deleted tRSTO, tCSTO and tREADID / Added tCLR, tCEA

Parameter

ALE to RE Delay (ID read)

ALE to RE Delay (Read cycle)

CLE to RE Delay

Symbol

tAR1

Min

50

10

-

Max

Unit

-

tAR2

ns

tCLR

CE Access Time

tCEA

45

CLE

tCR

CE

WE

tAR

ALE

RE

tREA

90h

I/O0~7

00h

ECh

Maker code

Address. 1cycle

CLE

CE

tCEA

WE

tAR

ALE

RE

tWHR

tREA

90h

I/O0~7

00h

ECh

Maker code

Address. 1cycle

Note : For more detailed features and specifications including FAQ, please refer to Samsung Flash web site.

http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you

have any questions, please contact the SAMSUNG branch office near your office.

2

K9S5608V0C/B K9S6408V0C/B

K9S2808V0C/B

TM

SmartMedia

Revision History

Revision No History

Draft Date

Remark

tCLS

CLE

tCLS

tCS

tCLH

tCH

CE

tWP

WE

tCSTO

tCHZ

tWHR

RE

tDH

tDS

tRSTO

tIR

tRHZ

I/O

0~

7

Status Output

70h

tCLS

CLE

CE

tCLS

tCS

tCLH

tCH

tWP

WE

tCEA

tCHZ

tWHR

RE

tDH

tREA

tDS

70h

tIR

tRHZ

I/O

0

~

7

Status Output

1. Eliminated the duplicated AC parameter.

- AC characteristics (Before)

0.5

Feb. 9th 2002

Final

. Replaced tAR1,tAR2 with tAR

Parameter

ALE to RE Delay (ID read)

ALE to RE Delay (Read cycle)

CLE to RE Delay

Symbol

tAR1

Min

Max

Unit

50

10

-

tAR2

ns

tCLR

CE Access Time

tCEA

45

- AC characteristics (After)

Parameter

Symbol

tAR

Min

10

-

Max

Unit

ALE to RE Delay

CLE to RE Delay

CE Access Time

-

tCLR

ns

tCEA

45

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you

have any questions, please contact the SAMSUNG branch office near your office.

3

K9S5608V0C/B K9S6408V0C/B

K9S2808V0C/B

TM

SmartMedia

SmartMedia^TMCard

FEATURES

GENERAL DESCRIPTION

•Single 2.7V~3.6V Supply

Using Nand flash memory, SmartMedia provides the most cost-

effective solution for the solid state mass storage market. A pro-

gram operation is implemented by the single page of 528 bytes

in typical 200ms and an erase operation is done by the single

block of 16K bytes (K9S6408V0X: 8K bytes) in typical 2ms.

Data in a page can be read out at 50ns cycle time per byte. The

I/O pins serve as ports for address and data inputs/outputs as

well as command inputs. The on-chip writing controller auto-

mates all program and erase functions including pulse repeti-

tion, where required, and internal verification and margining of

data. Even the write-intensive systems can take advantage of

the SmartMeida¢s extended reliability of 100K program/erase

cycles by providing ECC(Error Correcting Code) with real time

mapping-out algorithm. (*Endurance varies according to its

density. please refer to Features). SmartMedia is an optimum

solution for data storage applications such as solid state file

storage, digital voice recorder, digital still camera and other por-

table applications requiring non-volatility.

•Organization

- Memory Cell Array :

8MB(K9S6408V0X) : ( 8M + 256K)bit x 8bit

16MB(K9S2808V0X) : (16M + 512K)bit x 8bit

32MB(K9S5608V0X) : (32M + 1,024K)bit x 8bit

- Data Register : (512 + 16)bit x8bit

•Automatic Program and Erase

- Page Program : (512 + 16)Byte

- Block Erase

32MB, 16MB(K9S56/2808V0X) : (16K + 512)Byte

8MB (K9S6408V0X) : (8K + 256)Byte

•528-Byte Page Read Operation

- Random Access : 10ms(Max.)

* K9S6408V0B/A : 7ms(Max.)

* K9S6408V0C : 10ms(Max.)

- Serial Page Access : 50ns(Min.)

•Fast Write Cycle Time

- Program Time : 200ms(Typ.)

- Block Erase Time : 2ms(Typ.)

•Command/Address/Data Multiplexed I/O Port

•Hardware Data Protection

- Program/Erase Lockout During Power Transitions

•Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

* K9S6408V0X : 1Million Program/Erase Cycles

- Data Retention : 10 years

PIN DESCRIPTION

Device

Unique ID Support

K9S2808V0X

K9S5608V0X

K9S6408V0C

O

•Command Register Operation

TM

•22pad SmartMedia (SSFDC)

•Unique ID for Copyright Protection

K9S6408V0A/M

X

PIN DESCRIPTION

TM

SmartMedia CARD(SSFDC)

Pin Name

Pin Function

Data Input/Outputs

Command Latch Enable

I/O0 ~ I/O7

CLE

ALE

CE

12

22

22 VCC

21 CE

20 RE

19 R/B

18 GND

17 LVD

16 I/O7

15 I/O6

14 I/O5

13 I/O4

12 VCC

1

2

3

4

5

6

7

8

9

VSS

Address Latch Enable

Chip Enable

Read Enable

Write Enable

Write Protect

Low Voltage Detect

Ground

CLE

ALE

WE

WP

I/O0

I/O1

I/O2

I/O3

RE

WE

11

1

WP

LVD

GND

R/B

ID 32MB

10 VSS

11 VSS

Ready/Busy output

Power

VCC

VSS

Ground

22 PAD SmartMedia^TM

N.C

No Connection

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs and do not leave VCC or VSS disconnected.

The pin 17(LVD) is used to detect 5V or 3.3V product electrically. Please, refer to the SmartMedia Application note for detail.

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Figure 1. FUNCTIONAL BLOCK DIAGRAM

VCC

VSS

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

K9S6408V0X : 64M + 2M Bit

K9S2808V0X : 128M + 4M Bit

K9S5608V0X : 256M + 8M Bit

X-Buffers

A9 - A24

Latches

NAND Flash

ARRAY

& Decoders

Y-Buffers

A0 - A7

K9S6408V0X : (512 + 16)Byte x 16,384

K9S2808V0X : (512 + 16)Byte x 32,768

K9S5608V0X : (512 + 16)Byte x 65,536

Latches

& Decoders

Page Register & S/A

Y-Gating

A8

Command

Register

VCC

VSS

I/O Buffers & Latches

CE

RE

WE

Control Logic

& High Voltage

Generator

I/0 0

I/0 7

Output

Driver

Global Buffers

CLE ALE

WP

5

K9S5608V0C/B K9S6408V0C/B

K9S2808V0C/B

TM

SmartMedia

Figure 2. ARRAY ORGANIZATION

Pages

1st half Page Register

(8MB) : 1block=16pages

(16MB/32MB) : 1block=32pages

2nd half Page Register

(=256 Bytes)

8 bit

512B Byte

16 Byte

I/O 0 ~ I/O 7

Page Register

512 Byte

ARRAY ORGANIZATION

1 Page

1 Block

1 Device

K9S6408V0X

K9S2808V0X

K9S5608V0X

528 Byte

528Byte

528 Byte

528 Bytes x 16 Pages

528Bytes x 32 Pages

528 Byte x 32 Pages

528 Byte x 16Pages x 1024 Blocks

528Byte x 32Pages x 1024 Blocks

528Bytes x 32Pages x 2048 Blocks

NOTE : Column Address : Starting Address of the Register.

I/O 0

A0

I/O 1

A1

I/O 2

A2

I/O 3

A3

I/O 4

A4

I/O 5

A5

I/O 6

A6

I/O 7

A7

1st Cycle

2nd Cycle

3rd Cycle

Column Address

Row Address

(Page Address)

A9

A10

A18

A11

A19

A12

A20

A13

A21

A14

A22

A15

A23

A16

A24

A17

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

A22: K9S6408V0X should be designated up to A22, addresse A23 to A24 must be set to "Low".

A23: K9S2808V0X should be designated up to A23, address A24 must be set to "Low".

A24: K9S5608V0X should be designated up to A24.

* A8 is set to "Low" or "High" by the 00h or 01h Command.

* The device ignores any additional input of address cycles than reguired.

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TM

SmartMedia

PRODUCT INTRODUCTION

The SmartMeida has the memory organization as following Table1. Spare sixteen columns are located from column address of 512

to 527. A 528-byte data register is connected to memory cell arrays and is accommodating data-transfer between the I/O buffers and

memory cell arrays during page read and page program operations. The memory array is made up of 16 cells that are serially con-

nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two 16

cell memory array. The array organization is shown in Figure 2. The program and the read operations are executed on a page basis,

while the erase operation is executed on a block basis.

The SmartMedia has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows system upgrade to

future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except

for Block Erase and Page Program commands which require two cycles: one cycle for a setup and another for an execution. The

physical space of the SmartMedia varies according to its density and from 8MB to 32MB SmartMedia require three cycles for byte-

level addressing; column address, row address, in that order. Page Read and Page Program need the same three address cycles fol-

lowing the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations

are selected by writing specific commands into the command register. Table 2. defines the specific commands of the SmartMedia.

Table 1.MEMORY ORGANIZATION

Memory Organization

66Mbit (69,206,016 bit)

132Mbit (138,412,032 bit)

264Mbit (276,824,064 bit)

Number of rows(Pages)

16,384 rows

Number of columns

528 columns

K9S6408V0X

K9S2808V0X

K9S5608V0X

32,768 rows

528 columns

65,536 rows

528 columns

Table 2. COMMAND SETS

Function

1st. Cycle

00h/01h⁽¹⁾

50h

2nd. Cycle

Acceptable Command during Busy

-

-

Read ID

90h

-

Reset

FFh

O

Page Program

Block Erase

Read Status

80h

10h

D0h

-

60h

70h

NOTE: 1. The 00h command defines starting address of the 1st half of registers.The 01h command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, address pointer is automatically moved to the 1st half register(00h) on the

next cycle.

Caution : Any undefined command inputs are prohibited except for above command sets of Table2.

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PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched

into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of

WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.

However, when the device is in the busy state during program or erase, CE high is ignored and does not return the device to standby

mode.

Write Enable(WE)

The WE input controls writing to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z

when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when

the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is

in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip

is deselected or when outputs are disabled.

Low Voltage Detect(LVD)

The LVD is used to detect the proper supply voltage electrically. By connecting this pin to Vss through a pull-down resister, it is pos-

sible to distinguish 3.3V product from 5V product. When 3.3V is applied as Vcc to pins 12 and 22, a ’High’ level can be detected on

the system side if the device is a 3.3V product, and ’Low’ level for 5V product.

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K9S5608V0C/B K9S6408V0C/B

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SmartMedia

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

VIN

Rating

Unit

-0.6 to + 4.6

-10 to +65

-20 to +65

Voltage on any pin relative to VSS

V

VCC

Temperature Under Bias

Storage Temperature

NOTE :

TBIAS

TSTG

°C

1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, TA=0 to 55°C)

Parameter

Supply Voltage

Symbol

VCC

Min

2.7

0

Typ.

3.3

0

Max

3.6

0

Unit

V

VSS

V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter

Sequential Read

Program

Symbol

ICC1

ICC2

ICC3

ISB1

ISB2

ILI

Test Conditions

Min

Typ

10

-

Max

Unit

tRC=50ns, CE=VIL, IOUT=0mA

-

20

Operating

Current

-

mA

Erase

-

CE=VIH, WP=0V/VCC

CE=VCC-0.2, WP=0V/VCC

VIN=0 to 3.6V

VOUT=0 to 3.6V

-

20

Stand-by Current(TTL)

-

1

Stand-by Current(CMOS)

Input Leakage Current

10

-

50

-

±10

VCC+0.3

0.8

-

mA

Output Leakage Current

Input High Voltage, All inputs

Input Low Voltage, All inputs

Output High Voltage Level

Output Low Voltage Level

Output Low Current(R/B)

ILO

-

VIH

2.0

-0.3

2.4

-

VIL

-

V

VOH

VOL

IOH=-400mA

-

IOL=2.1mA

-

0.4

-

IOL(R/B) VOL=0.4V

8

10

mA

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K9S5608V0C/B K9S6408V0C/B

K9S2808V0C/B

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SmartMedia

VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

K9S6408V0X

K9S2808V0X

K9S5608V0X

1,014

1,004

2013

1,020

1,024

2048

Valid Block Number

NVB

Blocks

-

NOTE :

1. The K9SXX08V0X may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not

erase or program factory-marked bad blocks. Refer to the attached technical notes for an appropriate management of invalid blocks.

2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.

(Refer to the attached technical notes)

AC TEST CONDITION

(TA=0 to 55°C, VCC=2.7V~3.6V unless otherwise noted)

Parameter

Input Pulse Levels

Value

0.4V to 2.4V

Input Rise and Fall Times

Input and Output Timing Levels

Output Load (3.0V +/-10%)

Output Load (3.3V +/-10%)

5ns

1.5V

1 TTL GATE and CL=50pF

1 TTL GATE and CL=100pF

CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)

Item

Symbol

CI/O

Test Condition

VIL=0V

Min

Max

10

Unit

pF

Input/Output Capacitance

Input Capacitance

-

CIN

VIN=0V

10

pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE

H

L

ALE

L

CE

L

WE

RE

H

WP

Mode

X

Command Input

Read Mode

H

L

H

X

Address Input(3clock)

Command Input

H

L

H

Write Mode

Data Input

H

L

H

Address Input(3clock)

L

H

L

H

X

sequential Read & Data Output

During Read(Busy)

During Program(Busy)

During Erase(Busy)

Write Protect

X

L

X

H

X

X⁽¹⁾

H

L

X

(2)

X

Stand-by

0V/VCC

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

tPROG

-

200

500

2

ms

Main Array

cycles

ms

Number of Partial Program Cycles

in the Same Page

Nop

-

Spare Array

3

Block Erase Time

tBERS

2

3

10

K9S5608V0C/B K9S6408V0C/B

K9S2808V0C/B

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SmartMedia

AC Timing Characteristics for Command / Address / Data Input

Parameter

Symbol

tCLS

tCLH

tCS

Min

Max

Unit

ns

CLE setup Time

CLE Hold Time

CE setup Time

CE Hold Time

0

-

10

0

tCH

10

25⁽¹⁾

0

WE Pulse Width

ALE setup Time

ALE Hold Time

Data setup Time

Data Hold Time

Write Cycle Time

tWP

tALS

tALH

tDS

10

20

10

50

15

tDH

tWC

WE High Hold Time

tWH

NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

AC Characteristics for Operation

Parameter

Data Transfer from Cell to Register

CLE to RE Delay

Symbol

tR

Min

-

Max

Unit

ms

ns

ms

10

tCLR

tAR

10

20

30

-

ALE to RE Delay

Ready to RE Low

tRR

-

RE Pulse Width

tRP

-

WE High to Busy

tWB

100

-

Read Cycle Time

tRC

50

-

RE Access Time

tREA

tRHZ

tCHZ

tREH

tIR

35

30

20

-

RE High to Output Hi-Z

15

-

CE High to Output Hi-Z

RE High Hold Time

15

0

Output Hi-Z to RE Low

-

Last RE High to Busy (at sequential read)

CE High to Ready (in case of interception by CE at read)

CE High Hold Time(at the last serial read)⁽²⁾

WE High to RE Low

tRB

-

100

tCRY

tCEH

tWHR

tRST

-

50 +tr(R/B)⁽¹⁾

100

60

-

Device Resetting Time(Read/Program/Erase)

5/10/500⁽³⁾

NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.

3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

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SmartMedia

SmartMedia Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-

mation regarding the invalid block(s) is so called as the invalid block information. An invalid block(s) does not affect the performance

of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be

able to mask out the invalid block(s) via address mapping.

Identifying Invalid Block(s)

SSFDC Forum specifies the logical format and physical format to ensure compatibility of SmartMedia. Samsung pre-formats Smart-

Media in the Forum-compliant format prior to shipping. The physical format standard by SSFDC Forum specifies that invalid block

information is written at the 6th byte of spare area in invalid blocks with two or more "0" bits, while valid blocks are erased(FFh). Since

the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. There-

fore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid

block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original invalid block information is prohib-

ited.

Start

Set Block Address = 0

Increment Block Address

No

Create (or update)

Invalid Block(s) Table

Check "FFh" ?

Check "FFh" at the column address 517

*

of the first page in the block

Yes

No

Last Block ?

Yes

End

Figure 3. Flow chart to create invalid block table.

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SmartMedia

SmartMedia Technical Notes (Continued)

Error in write or read operation

Over its life time, the additional invalid blocks may be developed during its use. Refer to the qualification report for the actual data.The

following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after

erase or program, block replacement should be done. Because program status failure during a page program does not affect the data

of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block

and reprogramming the current target data and copying the rest data of the replaced block. To improve the efficiency of memory

space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replace-

ment. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Erase Failure

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Write

Read

Program Failure

Single Bit Failure

Verify ECC -> ECC Correction

: Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

ECC

Program Flow Chart

If ECC is used, this verification

operation is not needed.

Start

Write 80h

Write 00h

Write Address

Wait for tR Time

Write Address

Write Data

Write 10h

*

No

Program Error

Verify Data

Read Status Register

Yes

Program Completed

No

I/O 6 = 1 ?

or R/B = 1 ?

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

*

Yes

*

No

Program Error

I/O 0 = 0 ?

Yes

13

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SmartMedia Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Write 60h

Write 00h

Write Block Address

Write Address

Read Data

Write D0h

Read Status Register

ECC Generation

No

I/O 6 = 1 ?

or R/B = 1 ?

Reclaim the Error

Verify ECC

Yes

*

No

Page Read Completed

Erase Error

I/O 0 = 0 ?

Yes

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

*

Block Replacement

Block A

1st

2

{

(n-1)th

nth

an error occurs.

(page)

Buffer memory of the controller.

Block B

1st

1

{

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during the program operation.

* Step2

Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)

* Step3

Then, copy the data in the 1st ~ (n-1)th page of the Block ’A’ to the same location of the Block ’B’.

* Step4

Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or using other appropriate scheme.

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Pointer Operation of the SmartMedia

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’

command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets

the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole

page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective

only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the

address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted

before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from

’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.

Destination of the pointer

"A" area

(00h plane)

"B" area

(01h plane)

"C" area

(50h plane)

Command

Pointer position

Area

00h

01h

50h

0 ~ 255 byte

256 ~ 511 byte

512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

256 Byte

16 Byte

"A"

"B"

"C"

Internal

Page Register

Pointer select

commnad

(00h, 01h, 50h)

Pointer

Figure 4. Block Diagram of Pointer Operation

(1) Command input sequence for programming ’A’ area

The address pointer is set to ’A’ area(0~255), and sustained

Address / Data input

80h 10h

00h

80h

10h

00h

’A’,’B’,’C’ area can be programmed.

’00h’ command can be omitted.

It depends on how many data are inputted.

(2) Command input sequence for programming ’B’ area

The address pointer is set to ’B’ area(256~512), and will be reset to

’A’ area after every program operation is executed.

Address / Data input

80h 10h

01h

80h

10h

01h

’B’, ’C’ area can be programmed.

It depends on how many data are inputted.

’01h’ command must be rewritten before

every program operation

(3) Command input sequence for programming ’C’ area

The address pointer is set to ’C’ area(512~527), and sustained

Address / Data input

80h 10h

50h

80h

10h

50h

Only ’C’ area can be programmed.

’50h’ command can be omitted.

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System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or sequential read as shown below. The internal 528byte

page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or

audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would

provide significant savings in power consumption.

Figure 5. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

WE

ALE

80h

Start Add.(3Cycle)

Data Input

10h

I/O0~7

CE

(Min. 10ns)

tCS

(Max. 45ns)

tCEA

tCH

CE

RE

tREA

tWP

WE

I/O0~7

out

Figure 6. Read Operation with CE don’t-care.

CLE

CE don’t-care

Must be held

low during tR.

CE

RE

ALE

tR

R/B

WE

00h

Start Add.(3Cycle)

Data output (Sequential)

I/O0~7

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SmartMedia

Command Latch Cycle

CLE

tCLH

tCH

tCLS

tCS

CE

tWP

WE

tALS

tALH

ALE

tDH

tDS

Command

I/O0~7

Address Latch Cycle

tCLS

CLE

CE

tCS

tWC

tWP

WE

tWH

tALH tALS

tWH

tALH

tALS

tALH

tALS

ALE

tDH

tDS

A0~A7

A9~A16

I/O0~7

A17~A24

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

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Input Data Latch Cycle

tCLH

CLE

CE

tCH

tWC

tALS

ALE

tWP

WE

tWH

tDH

tDS

I/O0~7

DIN 1

DIN 511

DIN 0

Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

tRC

CE

tREH

tCHZ

tRHZ

tREA

tRP

tREA

RE

tRHZ

Dout

I/O0~7

R/B

Dout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

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Status Read Cycle

tCLR

CLE

tCLS

tCLH

tCS

CE

tCH

tWP

WE

tCEA

tCHZ

tWHR

RE

tDH

tREA

tDS

tIR

tRHZ

Status Output

I/O0~7

70h

READ1 OPERATION(READ ONE PAGE)

CLE

tCEH

CE

tCHZ

tWC

WE

tWB

tCRY

tAR

ALE

tRHZ

tR

tRC

RE

tRR

A17 ~ A24

Dout N+3

00h or 01h A0 ~ A7 A9 ~ A16

Dout N+1 Dout N+2

Dout 527

tRB

Dout N

I/O0~7

R/B

Column

Address

Page(Row)

Address

Busy

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

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SmartMedia

READ1 OPERATION(INTERCEPTED BY CE)

CLE

CE

WE

tWB

tCHZ

tAR

ALE

tR

tRC

RE

tRR

A9 ~ A16

A17 ~ A24

Dout N+3

00h or 01h A0 ~ A7

Dout N

Dout N+1 Dout N+2

I/O0~7

R/B

Page(Row)

Address

Column

Address

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

Busy

READ2 OPERATION(READ ONE PAGE)

CLE

CE

WE

ALE

RE

tR

tWB

tAR

tRR

Dout

50H

A0 ~ A7 A9 ~ A16 A17 ~ A24

Dout 527

511+M+1

I/O0~7

R/B

511+M

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

Selected

Row

M Address

A0~A3 : Valid Address

A4~A7 : Don¢t care

16

512

Start

address M

20

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SmartMedia

SEQUENTIAL ROW READ OPERATION (Within a block especially for 64Mb-Cdie and 128Mb Bdie)

CLE

CE

WE

ALE

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

RE

Dout

N

Dout

N+1

Dout

N+2

Dout

527

Dout

0

Dout

1

Dout

2

Dout

527

00h

A0 ~ A7 A9 ~ A16

A17 ~ A24

I/O0~7

R/B

Ready

Busy

M

M+1

Output

N

Output

PAGE PROGRAM OPERATION

CLE

CE

tWC

WE

tPROG

tWB

ALE

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

RE

Din

527

Din

N

Din

N+1

10h

Program

80h

A0 ~ A7 A9 ~ A16 A17 ~ A24

70h

I/O0

I/O0~7

R/B

Sequential Data Column

Input Command Address

1 up to 528 Byte Data

Serial Input

Read Status

Command

Page(Row)

Address

Command

I/O0=0 Successful Program

I/O0=1 Error in Program

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SmartMedia

BLOCK ERASE OPERATION (ERASE ONE BLOCK)

CLE

CE

tWC

WE

tBERS

tWB

ALE

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

RE

A9 ~ A16 A17 ~ A24

60h

DOh

70h

I/O 0

I/O0~7

R/B

Page(Row)

Address

Busy

I/O0=0 Successful Erase

Read Status I/O0=1 Error in Erase

Command

Auto Block Erase

Setup Command

Erase Command

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SmartMedia

MANUFACTURE & DEVICE ID READ OPERATION

tCLR

CLE

CE

WE

tAR

ALE

RE

tREA

1st

2nd

75h

3rd

A5

90h

00h

ECh

I/O 0 ~ 7

Read ID Command

Address. 1cycle

Maker Code

Device Code

UniqueID Code

K9S6408V0X : E6h

K9S2808V0X : 73h

K9S5608V0X : 75h

NOTE :

The 3rd byte of device IDs represents whether there is Unigue ID or not. If A5h is read out, that means that the Smart Media has the Unigue ID.

ID Definition Table

90 ID : Access command = 90H

READ ID (1)

Value

Description

1^stByte

2^ndByte

3^rdByte

ECh

*75h

A5h

Maker Code

Device Code

Unique1D code

NOTE :

*Device Code : K9S6408V0X : E6h , K9S2808V0X : 73h , K9S5608V0X: 75h

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SmartMedia

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-

ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-

tion. Three types of operations are available : random read, sequential read and sequential row read.

The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred

to the data registers in less than 10ms(tR). The system controller can detect the completion of this data transfer(tR) by monitoringing

the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by pulsing RE

sequentially. High to low transitions of the RE clock output the data starting from the selected column address up to the last column

address.

After the data of the last column address is clocked out, the next page is automatically selected for sequential row read.

Waiting 10ms again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way

the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to

527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while

addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row

read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is

needed to move the pointer back to the main area. Figures 7 through 10 show typical sequence and timings for each read operation.

Figure 7. Read1 Operation

CLE

CE

WE

ALE

tR

R/B

RE

Start Add.(3Cycle)

A0 ~ A7 & A9 ~ A24

00h

Data Output (Serial Access)

I/O0~7

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

(00h Command)

(01h Command)*

1st half array 2st half array

Data Field

Spare Field

Data Field

Spare Field

* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half

array (00h) at next cycle.

24

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SmartMedia

Figure 8. Read2 Operation

CLE

CE

WE

ALE

tR

R/B

RE

Start Add.(3Cycle)

A0 ~ A3 & A9 ~ A24

50h

Data Output(Serial Access)

Spare Field

I/O0~7

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

(A4 ~ A7 :

Don¢t Care)

1st half array

2nd half array

Data Field

Spare Field

Figure 9. Sequential Row Read1 Operation

tR

R/B

Start Add.(3Cycle)

A0 ~ A7 & A9 ~ A24

Data Output

1st

Data Output

I/O0 ~ 7

00h

01h

2nd

(528 Byte)

Nth

(528 Byte)

(00h Command)

(01h Command)

1st half array

2nd half array

1st half array

2nd half array

1st

2nd

Nth

2nd

Nth

Block

Data Field

Spare Field

Data Field

Spare Field

The Sequential Read 1 and Read 2 operations are allowed only within a block and after the last page of a block

is readout, the sequential read operation must be terminated by bringing CE high. When the page address

moves onto the next block, read command and address must be given.

25

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Figure 10. Sequential Row Read2 Operation

tR

R/B

I/O0~7

50h

Start Add.(3Cycle)

A0 ~ A3 & A9 ~ A24

Data Output

1st

Data Output

2nd

(16Byte)

Nth

(16Byte)

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

(A4 ~ A7 :

Don¢t Care)

1st

Block

Nth

Data Field

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis, however it does allow multiple partial page programing of a byte or consecutive

bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same

page without an intervening erase operation has the limit by its density. (See the Table of Program/Erase Characteristics) It is advis-

able not to program more often than recommend. It might cause failures due to disturbance when it exceeds its limits. The failure

mode could be that data "1" of the erased cell might be changed into data"0"of the programmed cell.

The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which

up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is

programmed into the appropriate cell. Serial data loading can be started from the 2nd half array by moving pointer. About the pointer

operation, please refer to the attached technical notes.The serial data loading period begins by inputting the Serial Data Input com-

mand(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do

not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previ-

ously entering the serial data will not initiate the programming process. The internal write-controller automatically executes the algo-

rithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process

starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller

can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the

Read Status command and Reset command are valid while programming is in progress. When the Page Program is completed, the

Write Status Bit(I/O 0) may be checked(Figure 11). The internal write verify detects only errors for "1"s that are not successfully pro-

grammed to "0"s. The command register remains in Read Status command mode until another valid command is written to the com-

mand register.

Figure 11. Program & Read Status Operation

tPROG

R/B

Pass

I/O0~7

80h

Address & Data Input

I/O0

Fail

10h

70h

A0 ~ A7 & A9 ~ A24

528 Byte Data

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

26

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SmartMedia

BLOCK ERASE

The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase

Setup command(60h). Only address A14 to (A22: K9S6408V0X, A23: K9S2808V0X, A24: K9S5608V0X) is valid while A9 to A13 is

ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step

sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise

conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When

the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

Figure 12. Block Erase Operation

tBERS

R/B

Pass

I/O0~7

60h

I/O0

Fail

Address Input(2Cycle)

Block Add. : A9 ~ A24

70h

D0h

A22: K9S6408V0X

A23: K9S2808V0X

A24: K9S5608V0X

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs

the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows

the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE

does not need to be toggled for updated status. Refer to Table3 for specific Status Register definitions. The command register

remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read

mode, a read command(00h or 50h) should be given before the sequential read cycle.

Read Status Register Definition

I/O #

Status

Definition

"0" : Successful Program / Erase

I/O 0

Program / Erase

"1" : Error in Program / Erase

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

"0"

Reserved for Future

Use

Device Operation

Write Protect

"0" : Busy

"1" : Ready

"1" : Not Protected

"0" : Protected

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READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Three read cycles sequentially output the manufacture code(ECH), the device code (K9S6408V0X : E6h , K9S2808V0X : 73h ,

K9S5608V0X: 75h), the UniqueID code(A5h) respectively. The command register remains in Read ID mode until further commands are

issued to it. Figure 13 shows the operation sequence.

Figure 13. Read ID Operation

tCLR

CLE

tCEA

CE

WE

tAR

ALE

RE

tWHR

tREA

I/O0~7

90h

00h

ECh

75h

A5h

Maker code

UniqueID code

Address. 1cycle

Device code

K9S6408V0X : E6h

K9S2808V0X : 73h

K9S5608V0X : 75h

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is

already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST

after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 14 below.

Figure 14. RESET Operation

tRST

R/B

I/O0~7

FFh

Table 4. Device Status

After Power-up

After Reset

Operation Mode

Waiting for next command

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READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read operations. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-

ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is

an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Figure 15). Its value can be

determined by the following guidance.

Rp

ibusy

VCC

Ready Vcc

R/B

2.0V

open drain output

0.8V

Busy

tf

tr

GND

Device

Figure 15. Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 3.3V, Ta = 25°C , C_L= 100pF

381

3.3

Ibusy

300n

3m

290

1.1

1.65

189

200n

100n

2m

1m

tr

tf

96

0.825

4.2

2K

4.2

3K

4.2

4K

1K

Rp(ohm)

Rp value guidance

VCC(Max.) - VOL(Max.)

3.2V

8mA + SIL

Rp(min) =

=

IOL + SIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

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Data Protection & Power up Sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL

during power-up and power-down as shown in Figure 16. The two step command sequence for program/erase provides additional

software protection.

Figure 16. AC Waveforms for Power Transition

~ 2.5V

VCC

High

WP

WE

1ms

30

TM

SmartMedia

SmartMedia Dimensions

Unit:mm

DIMENSIONS

22 PAD SOLID STATE FLOPPY DISK CARD (3.3V)

SOLID STATE PRODUCT OUTLINE

37.0±0.1

0.15±0.05

5.0±0.2

Index Label Area

10.0±0.2

Write Protect Area

Contact Area

(+0.1mm package body surface)

33.0±0.2

45.0±0.1

0.76±0.08

0.5mm Chamfer 4.2(Min)

1.5±0.1

(3.3V Card)

27.0

2.140 TYP

0.400 TYP

22

12

8.650

7.900

6.500

0.000

6.500

7.900

8.650

1

11

31


型号：	K9S6408V0B
厂家：	SAMSUNG
描述：	SmartMedia CARD SM卡
文件：	总31页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K9S6408V0B [SAMSUNG]

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