K9K1208U0A-YCB0 [SAMSUNG]
64M x 8 Bit NAND Flash Memory; 64M ×8位NAND闪存
| 型号： | K9K1208U0A-YCB0 |
| 厂家： | 
SAMSUNG |
| 描述： | 64M x 8 Bit NAND Flash Memory |
| 文件： | 总27页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
Document Title
64M x 8 Bit NAND Flash Memory
Revision History
Revision No History
Draft Date
Remark
0.0
1. Initial issue
Dec. 6th 2000
Preliminary
- Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection).
So, /SE pin is don’t-cared regardless of external logic input level and is
fixed as low internally.
1. Changed plane address in Copy-Back Program
Dec. 28th 2000
Jan. 17th 2001
0.1
0.2
- A14, the plane address, of source and destination page address must be
the same. => A14 and A25, the plane address, of source and destination
page address must be the same.
Final
1. In addition, explain WE function in pin description
- The WE must be held high when outputs are activated.
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
64M x 8 Bit NAND Flash Memory
FEATURES
GENERAL DESCRIPTION
· Voltage Supply : 2.7V~3.6V
The K9K1208U0A are a 64M(67,108,864)x8bit NAND Flash
Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation programs the 528-
byte page in typically 200ms and an erase operation can be per-
formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 60ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. Even the
write-intensive systems can take advantage of the
K9K1208U0A¢s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. The K9K1208U0A-YCB0/YIB0 is an
optimum solution for large nonvolatile storage applications such
as solid state file storage and other portable applications requir-
ing non-volatility.
· Organization
- Memory Cell Array : (64M + 2,048K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
· Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
· 528-Byte Page Read Operation
- Random Access : 10ms(Max.)
- Serial Page Access : 60ns(Min.)
· Fast Write Cycle Time
- Program time : 200ms(Typ.)
- Block Erase Time : 2ms(Typ.)
· Command/Address/Data Multiplexed I/O Port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
· Command Register Operation
· Package :
- K9K1208U0A-YCB0/YIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
PIN CONFIGURATION
PIN DESCRIPTION
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
Pin Name
I/O0 ~ I/O7
CLE
ALE
Pin Function
Data Input/Outputs
3
4
5
6
Command Latch Enable
Address Latch Enable
Chip Enable
7
8
CE
9
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
CE
RE
Read Enable
12mm x 20mm
WE
Write Enable
WP
Write Protect
R/B
Ready/Busy output
Power
VCC
VSS
Ground
N.C
No Connection
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
2
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
X-Buffers
A9 - A25
512M + 16M Bit
Latches
NAND Flash
ARRAY
& Decoders
Y-Buffers
Latches
A0 - A7
& Decoders
(512 + 16)Byte x 131072
Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
I/0 7
Output
Driver
CLE ALE
WP
Figure 2. ARRAY ORGANIZATION
1 Block = 32 Pages
= (16K + 512) Byte
1 Page = 528 Byte
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 4,096 Blocks
= 528 Mbits
128K Pages
(=4,096 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512B Byte
16 Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
Column Address
Row Address
(Page Address)
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A9
A10
A18
*L
A11
A19
*L
A12
A20
*L
A13
A21
*L
A14
A22
*L
A15
A23
*L
A16
A24
*L
A17
A25
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
3
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9K1208U0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1208U0A.
The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address
cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9K1208U0A.
Table 1. COMMAND SETS
Function
1st. Cycle
00h/01h(1)
50h
2nd. Cycle
Acceptable Command during Busy
Read 1
Read 2
Read ID
Reset
-
-
90h
-
-
FFh
O
O
Page Program
Block Erase
Read Status
80h
10h
D0h
-
60h
70h
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half
register(00h) on the next cycle.
4
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN
Rating
Unit
-0.6 to + 4.6
-0.6 to + 4.6
-10 to +125
-40 to +125
-65 to +150
Voltage on any pin relative to VSS
V
VCC
K9K1208U0A-YCB0
K9K1208U0A-YIB0
Temperature Under Bias
TBIAS
TSTG
°C
°C
Storage Temperature
NOTE :
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9K1208U0A-YCB0 :TA=0 to 70°C, K9K1208U0A-YIB0:TA=-40 to 85°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Unit
V
VSS
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Min
Max
Parameter
Sequential Read
Program
Symbol
ICC1
ICC2
ICC3
ISB1
ISB2
ILI
Test Conditions
Typ
10
15
15
-
Unit
tRC=60ns, CE=VIL, IOUT=0mA
-
20
Operating
Current
-
-
25
mA
Erase
-
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to 3.6V
VOUT=0 to 3.6V
-
-
25
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage
-
-
1
10
-
50
-
±10
±10
VCC+0.3
0.8
-
mA
ILO
-
-
VIH
2.0
-0.3
2.4
-
-
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
VIL
-
-
V
VOH
VOL
IOH=-400mA
-
IOL=2.1mA
-
0.4
-
IOL(R/B) VOL=0.4V
8
10
mA
6
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
4,026
-
4,096
Blocks
NOTE :
1. The K9K1208U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try
to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(K9K1208U0A-YCB0 :TA=0 to 70°C, K9K1208U0A-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)
Parameter
Input Pulse Levels
Value
0.4V to 2.4V
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (3.0V +/-10%)
Output Load (3.3V +/-10%)
5ns
1.5V
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
CI/O
Test Condition
VIL=0V
Min
Max
30
Unit
pF
Input/Output Capacitance
Input Capacitance
-
-
CIN
VIN=0V
30
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
Mode
X
Command Input
Read Mode
H
L
H
X
Address Input(4clock)
Command Input
H
L
L
L
H
H
Write Mode
Data Input
H
L
H
H
Address Input(4clock)
L
L
L
H
H
L
L
L
H
H
X
X
X
X
X
sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
L
L
L
H
X
X
X
X
X
X
X
X
X
X
H
H
X
X
H
L
X(1)
X
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
500
2
Unit
Program Time
tPROG
-
-
-
-
200
ms
Main Array
Spare Array
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
3
Block Erase Time
tBERS
2
3
7
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE setup Time
CLE Hold Time
CE setup Time
CE Hold Time
0
-
-
-
-
-
-
-
-
-
-
-
10
0
tCH
10
25(1)
0
WE Pulse Width
ALE setup Time
ALE Hold Time
Data setup Time
Data Hold Time
Write Cycle Time
tWP
tALS
tALH
tDS
10
20
15
60
25
tDH
tWC
WE High Hold Time
tWH
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay( ID read )
ALE to RE Delay(Read cycle)
CE to RE Delay( ID read)
Ready to RE Low
Symbol
tR
Min
-
Max
Unit
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tAR1
tAR2
tCR
100
50
100
20
30
-
-
-
-
tRR
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
Read Cycle Time
tRC
60
-
-
RE Access Time
tREA
tRHZ
tCHZ
tREH
tIR
35
RE High to Output Hi-Z
15
-
30
CE High to Output Hi-Z
20
RE High Hold Time
25
0
-
Output Hi-Z to RE Low
-
Last RE High to Busy(at sequential read)
CE High to Ready(in case of interception by CE at read)
CE High Hold Time(at the last serial read)(2)
RE Low to Status Output
tRB
-
100
50 +tr(R/B)(1)
tCRY
tCEH
tRSTO
tCSTO
tWHR
tREADID
tRST
-
100
-
-
35
CE Low to Status Output
-
45
WE High to RE Low
60
-
-
RE access time(Read ID)
Device Resetting Time(Read/Program/Erase)
35
5/10/500(3)
-
NOTE :
1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
8
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to
be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impos-
sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any inten-
tional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address 517
*
of the 1st and 2nd page in the block
No
Create (or update)
Invalid Block(s) Table
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
9
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that
the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block
failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 80h
Write 00h
Write Address
Wait for tR Time
Write Address
Write Data
Write 10h
*
No
Program Error
Verify Data
Read Status Register
Yes
Program Completed
No
I/O 6 = 1 ?
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
10
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Buffer
memory
error occurs
Page a
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
Block A
Block B
11
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
Pointer Operation of K9K1208U0A
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effec-
tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command,
the address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be input-
ted before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting
from ’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
"A" area
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
256 Byte
256 Byte
16 Byte
Table 1. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
00h
80h
10h
00h
80h
10h
’A’,’B’,’C’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
Address / Data input
80h 10h
01h
80h
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’C’ area can be programmed.
’50h’ command can be omitted.
12
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
80h
Start Add.(4Cycle)
Data Input
Data Input
10h
I/O0~7
CE
(Min. 10ns)
tCS
(Max. 45ns)
tCEA
tCH
CE
RE
tREA
tWP
WE
I/O0~7
out
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
Figure 4. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
CE
RE
ALE
tR
R/B
WE
Data Output(sequential)
I/O0~7
00h
Start Add.(4Cycle)
13
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
* Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/O0~7
* Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tWH
tALH tALS
tALH
tDH
tALS
ALE
tDH
tDH
tDH
tDS
tDS
tDS
tDS
A9~A16
A0~A7
I/O0~7
A17~A24
A25
14
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
* Input Data Latch Cycle
tCLH
CLE
CE
tCH
tWC
tALS
ALE
WE
tWP
tWP
tWP
tWH
tDH
tDH
tDH
tDS
tDS
tDS
DIN 511
I/O0~7
DIN 1
DIN 0
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tREH
tCHZ*
tREA
tREA
tREA
RE
tRHZ
tRHZ*
Dout
I/O0~7
R/B
Dout
Dout
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
15
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
* Status Read Cycle
tCLS
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tWHR
RE
tCSTO
tCHZ*
tDH
tDS
tRSTO
tIR
tRHZ*
Status Output
I/O0~7
70h
READ1 OPERATION(READ ONE PAGE)
CLE
tCEH
CE
tCHZ*
tWC
WE
ALE
RE
tWB
tCRY
tAR2
tRHZ*
tR
tRC
tRR
A9 ~ A16
A17 ~ A24
00h or 01h A0 ~ A7
Dout N+1 Dout N+2
Dout 527
tRB
Dout N
A25
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
16
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
READ1 OPERATION(INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tAR2
ALE
tR
tRC
RE
tRR
A9 ~ A16 A17 ~ A24
Dout N+2
00h or 01h A0 ~ A7
Dout N
Dout N+1
A25
I/O0~7
Page(Row)
Address
Column
Address
Busy
R/B
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE
ALE
RE
tR
tWB
tAR2
tRR
Dout
511+M
50h
A9 ~ A16 A17 ~ A24
Dout 527
A0 ~ A7
A25
I/O0~7
R/B
Selected
Row
M Address
A0~A3 : Valid Address
A4~A7 : Don¢t care
16
512
Start
address M
17
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
SEQUENTIAL ROW READ OPERATION (WITHIN A BLOCK)
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
527
Dout
0
Dout
1
Dout
527
00h
A0 ~ A7 A9 ~ A16 A17 ~ A24
A25
I/O0~7
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
Din
N
Din
527
A25
10h
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24
Column
70h
I/O0
I/O0~7
R/B
Sequential Data
Input Command
Program
Command
1 up to 528 Byte Data
Serial Input
Read Status
Command
Page(Row)
Address
Address
I/O0=0 Successful Program
I/O0=1 Error in Program
18
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
60h
A9 ~ A16 A17 ~ A24
DOh
70h
I/O 0
A25
I/O0~7
R/B
Page(Row)
Address
Busy
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase Setup Command
Erase Command
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
RE
tREADID
00h
ECh
76h
90h
I/O 0 ~ 7
Read ID Command
Maker Code
Device Code
Address. 1cycle
19
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10ms(tR). The system controller can detect the completion of this data transfer(tR) by analyz-
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 60ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10ms again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare
area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for
sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00h/01h) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each
read operation.
Figure 3. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
00h
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A25
Data Output(Sequential)
I/O0~7
(00h Command)
(01h Command)*
1st half array
2st half array
1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
20
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
Figure 4. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
Data Output(Sequential)
Spare Field
50h
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A25
I/O0~7
(A4 ~ A7 :
Don¢t Care)
1st half array
2nd half array
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation
tR
tR
tR
R/B
Data Output
1st
Data Output
Data Output
I/O0 ~ 7
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A25
00h
01h
2nd
(528 Byte)
Nth
(528 Byte)
(01h Command)
(00h Command)
1st half array
2nd half array
1st half array
2nd half array
1st
1st
2nd
Nth
2nd
Nth
Block
Data Field
Spare Field
Data Field
Spare Field
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
21
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
Figure 6. Sequential Row Read2 Operation
tR
tR
tR
R/B
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A25
Data Output
1st
I/O0~7
50h
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A4 ~ A7 :
Don¢t Care)
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 2 for main array and 3 for spare array. The addressing may be done in
any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation
tPROG
R/B
Pass
I/O0~7
80h
Address & Data Input
I/O0
Fail
10h
70h
A0 ~ A7 & A9 ~ A25
528 Byte Data
22
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execu-
tion of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation
with "00h" command with the address of the source page moves the whole 528byte data into the internal buffer. As soon as the Flash
returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed.
The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back
Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory
array is internally partitioned into four different planes, copy-back program is allowed only within the same memory plane. Thus, A14
and A25, the plane address, of source and destination page address must be the same.
Figure 8. Copy-Back Program Operation
tR
tPROG
R/B
Add.(4Cycles)
Pass
I/O0~7
Add.(4Cycles)
00h
I/O0
Fail
8Ah
70h
A0 ~ A7 & A9 ~ A25
Source Address
A0 ~ A7 & A9 ~ A25
Destination Address
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence.
Figure 9. Block Erase Operation
tBERS
R/B
Pass
I/O0~7
60h
I/O0
Fail
70h
Address Input(3Cycle)
Block Add. : A9 ~ A25
D0h
23
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Staus Register Definition
I/O #
Status
Definition
"0" : Successful Program / Erase
I/O 0
Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
"0"
"0"
"0"
"0"
"0"
Reserved for Future
Use
Device Operation
Write Protect
"0" : Busy
"1" : Ready
"1" : Not Protected
"0" : Protected
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECH), and the device code (76H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE
tCR
CE
WE
tAR1
ALE
RE
tREADID
I/O0~7
00h
76h
90h
ECh
Address. 1cycle
Maker code
Device code
24
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation
tRST
R/B
I/O0~7
FFh
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
Rp
VCC
VCC(Max.) - VOL(Max.)
3.2V
Rp =
=
8mA + SIL
IOL + SIL
R/B
open drain output
where IL is the sum of the input currents of all devices tied to the
R/B pin.
GND
Device
25
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional
software protection.
Figure 11. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
High
26
FLASH MEMORY
Package Dimensions
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8¡Æ
0.45~0.75
0.018~0.030
0.50
0.020
(
)
27
相关型号：
K9K1208U0C-DIB00
Flash, 64MX8, 30ns, PBGA63, 9 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TBGA-63
SAMSUNG
K9K1208U0C-GCB00
Flash, 64MX8, 30ns, PBGA63, 9 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FBGA-63
SAMSUNG
K9K1208U0C-GIB00
Flash, 64MX8, 30ns, PBGA63, 9 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FBGA-63
SAMSUNG
K9K1208U0C-HCB00
Flash, 64MX8, 30ns, PBGA63, 9 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TBGA-63
SAMSUNG
©2020 ICPDF网 联系我们和版权申明