K9F2808Q0B-DCB00_技术文档

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Document Title

16M x 8 Bit NAND Flash Memory

Revision History

Revision No. History

Draft Date

Remark

0.0

0.1

0.2

Initial issue.

May 28th 2001

Advance

K9F2808U0B(3.3V device)’s qualification is finished

Jun. 30th 2001

Jul. 30th 2001

K9F2808Q0B (1.8V device)

- Changed typical read operation current (Icc1) from 8mA to 5mA

- Changed typical program operation current (Icc2) from 8mA to 5mA

- Changed typical erase operation current (Icc3) from 8mA to 5mA

- Changed typical program time(tPROG) from 200us to 300us

- Changed ALE to RE Delay (ID read, tAR1) from 100ns to 20ns

- Changed CLE hold time(tCLH) from 10ns to 15ns

- Changed CE hold time(tCH) from 10ns to 15ns

K9F2808Q0B

: Preliminary

- Changed ALE hold time(tALH) from 10ns to 15ns

- Changed Data hold time(tDH) from 10ns to 15ns

- Changed CE Access time(tCEA) from 45ns to 60ns

- Changed Read cycle time(tRC) from 50ns to 70ns

- Changed Write Cycle time(tWC) from 50ns to 70ns

- Changed RE Access time(tREA) from 35ns to 40ns

- Changed RE High Hold time(tREH) from 15ns to 20ns

- Changed WE High Hold time(tWH) from 15ns to 20ns

0.3

1. Device Code is changed

- TBGA package information : ’B’ --> ’D’

Aug. 23th 2001

ex) K9F2808Q0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0

K9F2808U0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0

2. VIH ,VIL of K9F2808Q0B(1.8 device) is changed

(before revision)

I/O pins

VccQ-0.4

VCC-0.4

VccQ

VCC

Input High Voltage

VIH

VIL

Except I/O pins

-

Input Low Voltage,

All inputs

-

0

0.4

(after revision)

VccQ-0.4

VccQ+

0.3

I/O pins

Input High Voltage

VIH

VIL

VCC

+0.3

Except I/O pins

-

VCC-0.4

-0.3

-

Input Low Voltage,

All inputs

0.4

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

1

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Revision History

Revision No. History

Draft Date

Remark

0.4

1. IOL(R/B) of 1.8V device is changed.

Nov 5th 2001

Preliminary

-min. Value: 7mA -->3mA

-typ. Value: 8mA -->4mA

2. AC parameter is changed.

tRP(min.) : 30ns --> 25ns

0.5

Feb 15th 2002

1. Parameters are changed in 1.8V part(K9F2808Q0B) .

- tCH is changed from 15ns to 20ns

- tCLH is changed from 15ns to 20ns

- tALH is changed from 15ns to 20ns

- tDH is changed from 15ns to 20ns

0.6

0.7

May 3rd 2002

1. Parameters are changed in 1.8V part(K9F2808Q0B) .

- tRP is changed from 25ns to 35ns

- tWB is changed from 100ns to 150ns

- tREA is changed from 40ns to 45ns

1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device

2. The min. Vcc value 1.8V devices is changed.

Jul 14th 2003

K9F28XXQ0B : Vcc 1.65V~1.95V --> 1.70V~1.95V

3. New definition of the number of invalid blocks is added.

(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb

memory space.)

4. Note is added.

(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for

durations of 20 ns or less.)

0.8

1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.

2. PKG(TSOP1, WSOP1) Dimension Change

May 21th 2004

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

2

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

16M x 8 Bit Bit NAND Flash Memory

PRODUCT LIST

Part Number

K9F2808Q0B-D

K9F2808U0B-Y

K9F2808U0B-D

K9F2808U0B-V

Vcc Range

Organization

PKG Type

TBGA

1.7 ~ 1.95V

TSOP1

TBGA

X8

2.7 ~ 3.6V

WSOP1

FEATURES

· Voltage Supply

· Command/Address/Data Multiplexed I/O Port

· Hardware Data Protection

- Program/Erase Lockout During Power Transitions

· Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

· Command Register Operation

· Package

- K9F2808U0B-YCB0/YIB0 :

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F2808X0B-DCB0/DIB0

- K9F2808Q0B : 1.7~1.95V

- K9F2808U0B : 2.7 ~ 3.6 V

· Organization

- Memory Cell Array : (16M + 512K)bit x 8bit

- Data Register : (512 + 16)bit x8bit

· Automatic Program and Erase

- Page Program : (512 + 16)Byte

- Block Erase : (16K + 512)Byte

· 528-Byte Page Read Operation

- Random Access : 10ms(Max.)

- Serial Page Access

63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)

- K9F2808U0B-VCB0/VIB0

- K9F2808Q0B : 70ns

- K9F2808U0B : 50ns

· Fast Write Cycle Time

- Program Time

48 - Pin WSOP I (12X17X0.7mm)

* K9F2808U0B-V(WSOPI ) is the same device as

K9F2808U0B-Y(TSOP1) except package type.

- K9F2808Q0B : 300ms(Typ.)

- K9F2808U0B : 200ms(Typ.)

- Block Erase Time : 2ms(Typ.)

GENERAL DESCRIPTION

The K9F2808X0B is a 16M(16,777,216)x8bit NAND Flash Memory with a spare 512K(524,288)x8bit. The device is offered in 1.8V or

3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can

be performed programs in typical 200ms on a 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte

block. Data in a page can be read out at 70ns/50ns(K9F2808Q0B:70ns, K9F2808U0B:50ns) cycle time per byte. The I/O pins serve

as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase

functions including pulse repetition, where required, and internal verification and margining of data. Even write-intensive systems can

take advantage of the K9F2808X0B’s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code)

with real time mapping-out algorithm.

The K9F2808X0B is suitable for use in data memory of mobile communication system to reduce not only mount area but also power

consumption.

3

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

PIN CONFIGURATION (TSOP1)

K9F2808U0B-YCB0/YIB0

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

N.C

2

N.C

3

N.C

4

N.C

5

GND

6

R/B

7

RE

8

CE

9

N.C

10

N.C

11

Vcc

Vss

N.C

CLE

ALE

WE

WP

N.C

12

13

14

15

16

17

18

19

20

21

22

23

24

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

Unit :mm/Inch

20.00±0.20

0.787±0.008

#1

#48

#24

#25

1.00±0.05

0.039±0.002

0.05

0.002

MIN

1.20

0.047

MAX

18.40±0.10

0.724±0.004

0~8°

0.45~0.75

0.018~0.030

0.50

0.020

(

)

4

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

PIN CONFIGURATION (TBGA)

K9F2808X0B-DCB0/DIB0

DNU DNU

DNU

DNU DNU

/WP ALE NC /CE /WE R/B

NC

/RE CLE NC

NC

NC NC

NC I/O0 NC

NC

Vcc

NC I/O1 NC VCCQ I/O5 I/O7

Vss I/O2 I/O3 I/O4 I/O6 Vss

DNU DNU

(Top View)

PACKAGE DIMENSIONS

63-Ball TBGA (measured in millimeters)

Top View

Bottom View

9.00±0.10

A

0.80 x9= 7.20

0.80 x5= 4.00

0.80

4

9.00±0.10

B

6

5

3

2

1

(Datum A)

#A1

A

B

C

D

E

F

(Datum B)

G

H

63-Æ0.45±0.05

2.00

Æ

0.20 M A B

Side View

9.00±0.10

0.08MAX

0.45±0.05

5

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

PIN CONFIGURATION (WSOP1)

K9F2808U0B-VCB0/VIB0

N.C

DNU

N.C

I/O7

I/O6

I/O5

I/O4

N.C

DNU

N.C

Vcc

N.C

DNU

N.C

R/B

RE

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

CE

9

DNU

N.C

Vcc

Vss

N.C

DNU

CLE

ALE

WE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Vss

N.C

DNU

N.C

I/O3

I/O2

I/O1

I/O0

N.C

DNU

N.C

WP

N.C

DNU

N.C

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

Unit :mm

48 - WSOP1 - 1217F

0.70 MAX

0.58±0.04

15.40±0.10

#1

#48

#24

#25

(0.01Min)

0.45~0.75

17.00±0.20

6

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

PIN DESCRIPTION

Pin Name

Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

CLE

The I/O pins are used to input command, address and data, and to output data during read operations. The

I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

ALE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase operation. Regarding CE control during

read operation, refer to ’Page read’ section of Device operation.

CE

READ ENABLE

RE

WE

WP

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

R/B

OUTPUT BUFFER POWER

VccQ

VccQ is the power supply for Output Buffer.

VccQ is internally connected to Vcc, thus should be biased to Vcc.

POWER

Vcc

Vss

N.C

VCC is the power supply for device.

GROUND

NO CONNECTION

Lead is not internally connected.

GND INPUT FOR ENABLING SPARE AREA

GND

DNU

To do sequential read mode including spare area , connect this input pin to Vss or set to static low state

or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.

DO NOT USE

Leave it disconnected.

NOTE: Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

7

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Figure 1. FUNCTIONAL BLOCK DIAGRAM

VCC

VSS

X-Buffers

A9 - A23

Latches

128M + 4M Bit

NAND Flash

ARRAY

& Decoders

Y-Buffers

A0 - A7

Latches

& Decoders

(512 + 16)Byte x 32768

Page Register & S/A

Y-Gating

A8

Command

Register

Vcc/VccQ

VSS

I/O Buffers & Latches

Global Buffers

CE

RE

WE

Control Logic

& High Voltage

Generator

I/0 0

Output

Driver

I/0 7

CLE ALE WP

Figure 2. ARRAY ORGANIZATION

1 Block =32 Pages

= (16K + 512) Byte

1 Page = 528 Byte

1 Block = 528 Bytes x 32 Pages

= (16K + 512) Byte

1 Device = 528Byte x 32Pages x 1024 Blocks

= 132 Mbits

32K Pages

(=1,024 Blocks)

1st half Page Register

(=256 Bytes)

2nd half Page Register

(=256 Bytes)

8 bit

512B Byte

16 Byte

I/O 0 ~ I/O 7

Page Register

512 Byte

I/O 0

A0

I/O 1

A1

I/O 2

I/O 3

A3

I/O 4

A4

I/O 5

A5

I/O 6

A6

I/O 7

A7

1st Cycle

A2

A11

A19

Column Address

Row Address

(Page Address)

2nd Cycle

3rd Cycle

A9

A10

A18

A12

A20

A13

A21

A14

A22

A15

A23

A16

*L

A17

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

* A8 is set to "Low" or "High" by the 00h or 01h Command.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

8

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

PRODUCT INTRODUCTION

The K9F2808X0B is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare 16 columns are

located in 512 to 527 column address. A 528-byte data register is connected to memory cell arrays accommodating data transfer

between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that

are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND struc-

tured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in

Figure 2. Program and read operations are executed on a page basis, while erase operation is executed on a block basis. The mem-

ory array consists of 1024 blocks, and a block is separately erasable by 16K-byte unit. It indicates that the bit by bit erase operation

is prohibited on the K9F2808X0B.

The K9F2808X0B has addresses multiplexed with 8 I/O¢s. This scheme dramatically reduces pin counts and allows systems

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through

I/O¢s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle

except Page Program command and Block Erase command which require two cycles: one cycle for setup and another for execution.

The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low

row address and high row address, in that order. Page Read and Page Program need the same three address cycles following

required command input. In Block Erase operation, however, only two row address cycles are used. Device operations are selected

by writing specific commands into command register. Table 1 defines the specific commands of the K9F2808X0B.

Table 1. COMMAND SETS

Function

1st. Cycle

00h/01h⁽¹⁾

50h

2nd. Cycle

Acceptable Command during Busy

Read ID

Reset

-

90h

-

FFh

O

Page Program

Block Erase

Read Status

80h

10h

D0h

-

60h

70h

NOTE: 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.

After data access on 2nd half of register by the 01h command, start pointer is automatically moved to

1st half register(00h) on the next cycle.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

9

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

K9F2808Q0B(1.8V)

-0.6 to + 2.45

K9F2808U0B(3.3V)

VIN/OUT

VCC

-0.6 to + 4.6

V

Voltage on any pin relative to VSS

-0.2 to + 2.45

VccQ

-0.2 to + 2.45

K9F2808X0B-YCB0,DCB0

K9F2808X0B-YIB0,DIB0

-10 to + 125

-40 to + 125

-65 to + 150

Temperature

Under Bias

TBIAS

TSTG

°C

Storage Temperature

NOTE:

1. Minimum DC voltage is -0.6V on input/output pins and -0.2V on Vcc and VccQ pins. During transitions, this level may undershoot to -2.0V for periods

<20ns. Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F2808X0B-YCB0,DCB0:TA=0 to 70°C, K9F2808X0B-YIB0,DIB0:TA=-40 to 85°C)

K9F2808Q0B(1.8V)

K9F2808U0B(3.3V)

Parameter

Symbol

Unit

Min

1.7

0

Typ.

1.8

0

Max

1.95

0

Min

2.7

0

Typ.

3.3

0

Max

3.6

0

Supply Voltage

VCC

VCCQ

VSS

V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

K9F2808Q0B(1.8V)

K9F2808U0B(3.3V)

Parameter

Symbol

Test Conditions

Unit

Min

Typ

Max

Min Typ

Max

CE=VIL, IOUT=0mA

Operat-

ing

Sequential Read

ICC1 K9F2808Q0B: tRC=70ns

K9F2808U0B: tRC=50ns

-

5

15

-

10

20

Current

mA

Program

Erase

ICC2

ICC3

ISB1

ISB2

ILI

-

5

-

15

-

10

-

20

-

Stand-by Current(TTL)

Stand-by Current(CMOS)

Input Leakage Current

Output Leakage Current

CE=VIH, WP=0V/VCC

CE=VCC-0.2, WP=0V/VCC

VIN=0 to Vcc(max)

VOUT=0 to Vcc(max)

1

10

-

50

10

-

50

±10

mA

ILO

-

VccQ+0.

3

I/O pins

VccQ-0.4

2.0

-

VccQ+0.3

Input High Voltage

VIH*

VCC

+0.3

Except I/O pins

-

VCC-0.4

-0.3

-

2.0

-0.3

2.4

-

VCC+0.3

Input Low Voltage, All inputs

Output High Voltage Level

Output Low Voltage Level

VIL*

0.4

0.8

-

V

K9F2808Q0B :IOH=-100mA

K9F2808U0B :IOH=-400mA

VOH

VccQ-0.1

-

K9F2808Q0B :IOL=100uA

K9F2808U0B :IOL=2.1mA

VOL

IOL

-

0.1

-

0.4

-

K9F2808Q0B :VOL=0.1V

Output Low Current(R/B)

3

4

8

10

mA

(R/B) K9F2808U0B :VOL=0.4V

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

10

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

NVB

1004

-

1024

Blocks

NOTE:

1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-

sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-

gram factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.

AC TEST CONDITION

(K9F2808X0B-YCB0,DCB0 :TA=0 to 70°C, K9F2808X0B-YIB0,DIB0:TA=-40 to 85°C

K9F2808Q0B : Vcc=1.7V~1.95V , K9F2808U0B : Vcc=2.7V~3.6V unless otherwise noted)

Parameter

K9F2808Q0B

0V to VccQ

5ns

K9F2808U0B

0.4V to 2.4V

5ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

VccQ/2

1.5V

K9F2808Q0B:Output Load (VccQ:1.8V +/-10%)

K9F2808U0B:Output Load (VccQ:3.0V +/-10%)

1 TTL GATE and CL=30pF

-

1 TTL GATE and CL=50pF

1 TTL GATE and CL=100pF

K9F2808U0B:Output Load (VccQ:3.3V +/-10%)

CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)

Item

Symbol

Test Condition

Min

Max

10

Unit

pF

Input/Output Capacitance

Input Capacitance

CI/O

VIL=0V

-

CIN

VIN=0V

10

pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE

H

L

ALE

L

CE

L

WE

RE

H

WP

X

Mode

Command Input

Read Mode

Write Mode

H

L

H

X

Address Input(3clock)

Command Input

H

L

H

L

H

Address Input(3clock)

L

H

Data Input

L

H

X

Data Output

L

H

X

During Read(Busy) on K9F2808U0B_Y or K9F2808U0B_V

During Read(Busy) on the devices except K9F2808U0B_Y

and K9F2808U0B_V

X

H

X

H

During Program(Busy)

During Erase(Busy)

Write Protect

H

L

X⁽¹⁾

X

(2)

Stand-by

0V/VCC

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

11

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

K9F2808Q0B:300

K9F2808U0B:200

Program Time

tPROG

-

500

ms

Main Array

Spare Array

-

2

3

cycles

ms

Number of Partial Program Cycles

in the Same Page

Nop

Block Erase Time

tBERS

2

12

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

K9F2808Q0B

K9F2808U0B

Parameter

Symbol

Unit

Min

0

Max

Min

0

Max

CLE Set-up Time

CLE Hold Time

CE Setup Time

CE Hold Time

tCLS

tCLH

tCS

-

ns

20

0

10

0

tCH

20

25 ⁽¹⁾

0

10

25

0

WE Pulse Width

ALE Setup Time

ALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

WE High Hold Time

tWP

tALS

tALH

tDS

20

70

20

10

20

10

50

15

tDH

tWC

tWH

NOTE :

1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

AC Characteristics for Operation

K9F2808Q0B

K9F2808U0B

Parameter

Symbol

Unit

Min

-

Max

Min

Max

Data Transfer from Cell to Register

ALE to RE Delay( ID read )

ALE to RE Delay(Read cycle)

CLE to RE Delay

tR

10

-

10

ms

ns

ms

tAR1

tAR2

tCLR

tRR

20

50

20

35

-

20

50

20

25

-

Ready to RE Low

-

RE Pulse Width

tRP

-

WE High to Busy

tWB

150

100

Read Cycle Time

tRC

70

-

50

-

CE Access Time

tCEA

tREA

tRHZ

tCHZ

tREH

tIR

60

45

RE Access Time

-

45

-

35

RE High to Output Hi-Z

CE High to Output Hi-Z

RE High Hold Time

15

-

30

15

-

30

20

0

-

15

0

-

Output Hi-Z to RE Low

WE High to RE Low

-

tWHR

tRST

60

-

60

-

5/10/500⁽¹⁾

Device Resetting Time(Read/Program/Erase)

Last RE High to Busy

(at sequential read)

tRB

-

100

-

100

ns

K9F2808U0B-Y

only

CE High to Ready(in case of inter-

ception by CE at read)

tCRY

50 +tr(R/B)⁽³⁾

-

50 +tr(R/B)⁽³⁾

-

CE High Hold Time(at the last

serial read)⁽²⁾

tCEH

100

NOTE :

1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.

3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

13

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-

mation regarding invalid block(s) is so called as the invalid block information. Devices ,regardless of having invalid block(s), have the

same quality level because all valid blocks have same AC and DC characteristics. An invalid block(s) does not affect the perfor-

mance of valid block(s) because it’s bit line and common source line is isolated by a select transistor. The system design must be

able to mask out invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be

a valid block, does not require Error Correction.

Identifying Invalid Block(s)

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid

block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either 1st or 2nd page of every invalid block

has non-FFh data at the column address of 517. Since invalid block information is also erasable in most cases, it is impossible to

recover the information once it was erased. Therefore, system must be able to recognize the invalid block(s) based on the original

invalid block information and create invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the

original invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFh" at the column address 517

*

of the 1st and 2nd page in the block

No

Create (or update)

Invalid Block(s) Table

Check "FFh" ?

Yes

No

Last Block ?

Yes

End

Figure 3. Flow chart to create invalid block table.

14

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for actual

data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-

ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect

the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased

empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of mem-

ory space, we recommend using ECC without any block replacement in read or verification failure due to single bit error case. The

said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Erase Failure

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Write

Read

Program Failure

Single Bit Failure

Verify ECC -> ECC Correction

: Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

ECC

Program Flow Chart

If ECC is used, this verification

operation is not needed.

Start

Write 80h

Write 00h

Write Address

Wait for tR Time

Write Address

Write Data

Write 10h

*

No

Program Error

Verify Data

Read Status Register

Yes

Program Completed

No

I/O 6 = 1 ?

or R/B = 1 ?

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

*

Yes

*

No

Program Error

I/O 0 = 0 ?

Yes

15

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Write 60h

Write 00h

Write Block Address

Write Address

Read Data

Write D0h

Read Status Register

ECC Generation

No

I/O 6 = 1 ?

or R/B = 1 ?

Reclaim the Error

Verify ECC

Yes

*

No

Page Read Completed

Erase Error

I/O 0 = 0 ?

Yes

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

*

Block Replacement

Block A

1st

2

{

(n-1)th

nth

an error occurs.

(page)

Buffer memory of the controller.

Block B

1st

1

{

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)

* Step3

Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.

* Step4

Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

16

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Pointer Operation of K9F2808X0B

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’

command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets

the pointer to ’C’ area(512~527byte). With these commands, starting column address can be set to somewhere of a whole

page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is entered. But, ’01h’ command is effective only

for one time operation. After any operation of Read, Program, Erase, Reset, Power_Up following ’01h’ command, the address pointer

returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be entered before ’80h’ com-

mand is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from ’B’ area, ’01h’

command must be entered right before ’80h’ command is written.

Table 2. Destination of the pointer

"A" area

(00h plane)

"B" area

(01h plane)

"C" area

(50h plane)

Command

Pointer position

Area

00h

01h

50h

0 ~ 255 byte

256 ~ 511 byte

512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

256 Byte

16 Byte

"A"

"B"

"C"

Internal

Page Register

Pointer select

commnad

(00h, 01h, 50h)

Pointer

Figure 4. Block Diagram of Pointer Operation

(1) Command input sequence for programming ’A’ area

The address pointer is set to ’A’ area(0~255), and sustained

Address / Data input

80h 10h

00h

80h

10h

00h

’A’,’B’,’C’ area can be programmed.

’00h’ command can be omitted.

It depends on how many data are inputted.

(2) Command input sequence for programming ’B’ area

The address pointer is set to ’B’ area(256~512), and will be reset to

’A’ area after every program operation is executed.

Address / Data input

80h 10h

01h

80h

10h

01h

’B’, ’C’ area can be programmed.

It depends on how many data are inputted.

’01h’ command must be rewritten before

every program operation

(3) Command input sequence for programming ’C’ area

The address pointer is set to ’C’ area(512~527), and sustained

Address / Data input

80h 10h

50h

80h

10h

50h

Only ’C’ area can be programmed.

’50h’ command can be omitted.

17

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during data-loading or sequential data-reading as shown below. The internal

528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for

voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-

ing would provide significant saving in power consumption.

Figure 5. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

WE

ALE

80h

Start Add.(3Cycle)

Data Input

10h

I/O0~7

tCS

tCH

tCEA

CE

RE

CE

tREA

tWP

WE

I/O0~7

out

Figure 6. Read Operation with CE don’t-care.

On K9F2808U0B_Y or K9F2808U0B_V

CE must be held

low during tR

CLE

CE

CE don’t-care

RE

ALE

tR

R/B

WE

Data Output(sequential)

00h

Start Add.(3Cycle)

I/O0~7

18

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Command Latch Cycle

CLE

tCLH

tCH

tCLS

tCS

CE

tWP

WE

tALH

tALS

ALE

tDH

tDS

Command

I/O0~7

Address Latch Cycle

tCLS

CLE

CE

tCS

tWC

tWP

WE

tWH

tALH

tALS

tWH

tALH tALS

tALH

tALS

ALE

tDH

tDS

A0~A7

A9~A16

I/O0~7

A17~A23

19

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Input Data Latch Cycle

tCLH

CLE

tCH

CE

tWC

tALS

ALE

tWP

WE

tWH

tDH

tDS

I/O0~7

DIN 0

DIN 1

DIN 511

Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

tRC

CE

tCHZ

tOH

tREH

tREA

tRP

RE

tRHZ

tOH

Dout

I/O0~7

R/B

Dout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

20

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Status Read Cycle

tCLR

CLE

tCLS

tCS

tCLH

CE

tCH

tWP

WE

tCEA

tCHZ

tOH

tWHR

RE

tRHZ

tOH

tDH

tREA

tDS

tIR

Status Output

I/O0~7

70h

READ1 OPERATION (READ ONE PAGE)

CLE

1)

On K9F2808U0B_Y or K9F2808U0B_V

CE must be held

low during tR

tCEH

CE

tCHZ

tOH

tWC

WE

tWB

tCRY

tAR2

ALE

tRHZ

tOH

tR

tRC

RE

tRR

A9 ~ A16 A17 ~ A24

Dout N+2 Dout N+3

00h or 01h A0 ~ A7

Dout N

Dout N+1

Dout 527

tRB

I/O0~7

R/B

Column

Address

Page(Row)

Address

Busy

1)

NOTE : 1) is only valid on K9F2808U0B_Y or K9F2808U0B_V

21

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

READ2 OPERATION (READ ONE PAGE)

CLE

CE

On K9F2808U0B_Y or K9F2808U0B_V

CE must be held

low during tR

WE

ALE

RE

tR

tWB

tAR2

tRR

Dout

511+M+1

Dout

50h

A0 ~ A7 A9 ~ A16 A17 ~ A23

Dout 527

I/O0~7

R/B

511+M

Selected

Row

M Address

A0~A3 : Valid Address

A4~A7 : Don¢t care

16

512

Start

address M

PAGE PROGRAM OPERATION

CLE

CE

tWC

WE

ALE

RE

tWB

tPROG

Din

N

Din

N+1

Din

527

10h

80h

A0 ~ A7 A9 ~ A16 A17 ~ A23

70h

I/O0

I/O0~7

R/B

Sequential Data Column

Input Command Address

Program

Command

Read Status

Command

1 up to 528 Byte Data

Serial Input

Page(Row)

Address

I/O0=0 Successful Program

I/O0=1 Error in Program

22

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

BLOCK ERASE OPERATION (ERASE ONE BLOCK)

CLE

CE

tWC

WE

tBERS

tWB

ALE

RE

A9 ~ A16 A17 ~ A23

60h

DOh

70h

I/O 0

I/O0~7

R/B

Page(Row)

Address

Busy

I/O0=0 Successful Erase

Read Status I/O0=1 Error in Erase

Command

Auto Block Erase

Setup Command

Erase Command

MANUFACTURE & DEVICE ID READ OPERATION

tCLR

CLE

CE

WE

ALE

tAR1

RE

tREA

Device

Code*

90h

00h

ECh

Maker Code

I/O 0 ~ 7

Address. 1cycle

Read ID Command

Device Code

Device

Device Code*

K9F2808Q0B

K9F2808U0B

33h

73h

23

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing 00h

to the command register along with three address cycles. Once the command is latched, it does not need to be written for the follow-

ing page read operation. Two types of operation are available : random read, serial page read. The random read mode is enabled

when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than

10ms(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data

in a page is loaded into the registers, they may be read out by sequential RE pulse of 70ns/50n(K9F2808Q0B:70ns,

K9F2808U0B:50ns) period cycle. High to low transitions of the RE clock take out the data from the selected column address up to the

last column address.

Read1 and Read2 commands determine pointer which selects either main area or spare area. The spare area(512 to 527 bytes) may

be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of spare area while addresses

A4 to A7 are ignored. To move the pointer back to the main area, Read1 command(00h/01h) is needed. Figures 7 through 8 show

typical sequence and timing for each read operation.

Figure 7,8 details the sequence.

Sequential Row Read is available only on K9F2808U0B_Y or K9F2808U0B_V :

After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10ms

again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation

is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of

each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of

a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the

next block, read command and address must be given. Figures 7-1, 8-1 show typical sequence and timings for sequential row read

operation.

Figure 7. Read1 Operation

CLE

On K9F2808U0B_Y or K9F2808U0B_V

CE must be held

low during tR

CE

WE

ALE

tR

R/B

RE

Start Add.(3Cycle)

A0 ~ A7 & A9 ~ A23

Data Output(Sequential)

(01h Command)*

00h

I/O0~7

(00h Command)

1st half array 2st half array

Data Field

Spare Field

Data Field

Spare Field

* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.

24

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Figure 8. Read2 Operation

CLE

On K9F2808U0B_Y or K9F2808U0B_V

CE must be held

CE

low during tR

WE

ALE

tR

R/B

RE

50h

Data Output(Sequential)

Spare Field

Start Add.(3Cycle)

A0 ~ A3 & A9 ~ A23

I/O0~7

(A4 ~ A7 :

Don¢t Care)

1st half array

2nd half array

Data Field

Spare Field

Figure 7-1. Sequential Row Read1 Operation (only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block)

tR

R/B

Data Output

1st

Data Output

I/O0 ~ 7

00h

01h

Start Add.(3Cycle)

A0 ~ A7 & A9 ~ A24

2nd

(528 Byte)

Nth

(528 Byte)

(GND input=L, 00h Command)

(GND input=L, 01h Command)

(GND input=H, 00h Command)

1st half array

2nd half array

1st half array

2nd half array

1st half array

2nd half array

1st

2nd

Nth

Block

2nd

Nth

2nd

Nth

Data Field

Spare Field

Data Field

Spare Field

Data Field

Spare Field

25

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Figure 8-1. Sequential Row Read2 Operation (GND Input=Fixed Low)

(only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block)

tR

R/B

Start Add.(3Cycle)

Data Output

1st

Data Output

I/O0~7

50h

Data Output

2nd

(16Byte)

Nth

(16Byte)

A0 ~ A3 & A9 ~ A24

(A4 ~ A7 :

Don¢t Care)

1st

Block

Nth

Data Field

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis, but it allows multiple partial page program of one byte or consecutive bytes up

to 528, in a single page program cycle. The number of consecutive partial page program operation within the same page without

intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random

order in a block. Page program cycle consists of a serial data loading(up to 528 bytes of data) into the page register, and program of

loaded data into the appropriate cell. Serial data loading can start in 2nd half array by moving pointer. About the pointer operation,

please refer to the attached technical notes. Serial data loading is executed by entering the Serial Data Input command(80h) and

three cycle address input and then serial data loading. The bytes except those to be programmed need not to be loaded. The Page

Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering 80h will not initiate

program process. The internal write controller automatically executes the algorithms and timings necessary for program and verifica-

tion, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered,

with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output,

or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in

progress. When the Page Program is completed, the Write Status Bit(I/O 0) may be checked(Figure 9). The internal write verification

detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command

mode until another valid command is written to the command register.

Figure 9 details the sequence.

Figure 9. Program & Read Status Operation

tPROG

R/B

Pass

I/O0~7

80h

Address & Data Input

I/O0

Fail

10h

70h

A0 ~ A7 & A9 ~ A23

528 Byte Data

26

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

BLOCK ERASE

The Erase operation is done on a block(16K Bytes) basis. Block Erase is executed by entering Erase Setup command(60h) and 2

cycle block addresses and Erase Confirm command(D0h). Only address A14 to A23 is valid while A9 to A13 is ignored. This two-

step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external

noise condition. At the rising edge of WE after erase confirm command input, internal write controller handles erase and erase-veri-

fication. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked.

Figure 10 details the sequence.

Figure 10. Block Erase Operation

tBERS

R/B

Pass

I/O0~7

60h

I/O0

Fail

70h

Address Input(2Cycle)

Block Add. : A9 ~ A23

D0h

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h command to command register, a read cycle takes out the

content of the Status Register to the I/O pins on the falling edge of CE or RE. This two line control allows the system to poll the

progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be tog-

gled for updated status. Refer to table 3 for specific Status Register definitions. The command register remains in Status Read mode

until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or

50h) should be given before sequential page read cycle.

Table3. Read Status Register Definition

I/O #

Status

Definition

"0" : Successful Program / Erase

I/O 0

Program / Erase

"1" : Error in Program / Erase

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

"0"

Reserved for Future

Use

Device Operation

Write Protect

"0" : Busy

"1" : Ready

"1" : Not Protected

"0" : Protected

27

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (73h) respectively. The command register

remains in Read ID mode until further commands are issued to it.

Figure 11 shows the operation sequence.

Figure 11. Read ID Operation

tCLR

CLE

tCEA

CE

WE

tAR1

ALE

tWHR

RE

tREA

Device

Code*

I/O0~7

90h

00h

ECh

Maker code

Device code

Address. 1cycle

Device

Device Code*

K9F2808Q0B

33h

73h

K9F2808U0B

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. Refer to table 4 for device status after reset operation. If the device is

already in reset state, new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after

the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 12 below.

Figure 12. RESET Operation

tRST

R/B

I/O0~7

FFh

Table4. Device Status

After Power-up

After Reset

Operation Mode

Waiting for next command

28

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-

ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin

is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 13). Its value can be

determined by the following guidance.

Rp

ibusy

VCC

1.8V device - VOL : 0.1V, VOH : VccQ-0.1V

3.3V device - VOL : 0.4V, VOH : 2.4V

Ready Vcc

R/B

open drain output

VOH

C_L

VOL

Busy

tf

tr

GND

Device

Figure 13. Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 1.8V, Ta = 25°C , C_L= 30pF

@ Vcc = 3.3V, Ta = 25°C , C_L= 100pF

400

2.4

Ibusy

300n

3m

300n

3m

300

1.2

1.7

200n

100n

2m

1m

200n

100n

200

0.8

2m

1m

120

0.85

60

90

tr

30

100

3.6

0.6

3.6

0.57

1.7

0.43

3.6

2K

3.6

tf

1.7

2K

tf

1.7

4K

1K

3K

4K

1K

3K

Rp(ohm)

Rp value guidance

VCC(Max.) - VOL(Max.)

1.85V

Rp(min, 1.8V part) =

=

IOL + SIL

3mA + SIL

VCC(Max.) - VOL(Max.)

3.2V

Rp(min, 3.3V part) =

IOL + SIL

8mA + SIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

29

K9F2808Q0B

K9F2808U0B

FLASH MEMORY

Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 1.1V/2V(K9F2808Q0B:1.1V, K9F2808U0B:2V). WP pin provides hardware pro-

tection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10ms is required

before internal circuit gets ready for any command sequences as shown in Figure 14. The two step command sequence for program/

erase provides additional software protection.

Figure 14. AC Waveforms for Power Transition

K9F2808Q0B : ~ 1.5V

K9F2808U0B : ~ 2.5V

K9F2808Q0B : ~ 1.5V

K9F2808U0B : ~ 2.5V

VCC

High

WP

WE

10ms

30


型号：	K9F2808Q0B-DCB00
厂家：	SAMSUNG
描述：	Flash, 16MX8, 45ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, 0.80 MM PITCH, TBGA-63 内存集成电路
文件：	总30页 (文件大小：507K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K9F2808Q0B-DCB00 [SAMSUNG]

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