K8S6415ETB-FC7CT_技术文档

NOR FLASH MEMORY

K8S6415ET(B)B

64Mb B-die SLC NOR Specification

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* Samsung Electronics reserves the right to change products or specification without notice.

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Revision 1.2

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NOR FLASH MEMORY

K8S6415ET(B)B

Document Title

64M Bit (4M x16) Muxed Burst , Multi Bank NOR Flash Memory

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial Issue

October 20, 2004

1.0

Revision

March 22, 2005

- Specification finalized

- Add the requirement and note of Quadruple word program operation

1.1

1.2

Bottom boot block description is added

January 09, 2006

"Asynchronous mode may not support read following four sequential

invalid read condition within 200ns." is added

September 08, 2006

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Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

64M Bit (4M x16) Muxed Burst , Multi Bank NOR Flash Memory

FEATURES

• Single Voltage, 1.7V to 1.95V for Read and Write operations

• Organization

- 4,194,304 x 16 bit ( Word Mode Only)

• Multiplexed Data and Address for reduction of interconnections

- A/DQ0 ~ A/DQ15

• Read While Program/Erase Operation

• Multiple Bank Architecture

GENERAL DESCRIPTION

The K8S6415E featuring single 1.8V power supply is a 64Mbit

Muxed Burst Multi Bank Flash Memory organized as 4Mbx16.

The memory architecture of the device is designed to divide its

memory arrays into 135 blocks with independent hardware pro-

tection. This block architecture provides highly flexible erase

and program capability. The K8S6415E NOR Flash consists of

sixteen banks. This device is capable of reading data from one

bank while programming or erasing in the other bank.

- 16 Banks (4Mb Partition)

• OTP Block : Extra 256Byte block

• Read Access Time (@ CL=30pF)

- Asynchronous Random Access Time :

90ns (54MHz) / 80ns (66MHz)

- Synchronous Random Access Time :

88.5ns (54MHz) / 70ns (66MHz)

- Burst Access Time :

14.5ns (54MHz) / 11ns (66MHz)

• Burst Length :

- Continuous Linear Burst

- Linear Burst : 8-word & 16-word with No-wrap & Wrap

• Block Architecture

Regarding read access time, the K8S6415E provides an 14.5ns

burst access time and an 90ns initial access time at 54MHz. At

66MHz, the K8S6415E provides an 11ns burst access time and

70ns initial access time. The device performs a program opera-

tion in units of Single 16 bits (word) and an erase operation in

units of a block. Single or multiple blocks can be erased. The

block erase operation is completed within typically 0.7 sec. The

device requires 15mA as program/erase current in the

extended temperature ranges.

The K8S6415E NOR Flash Memory is created by using Sam-

sung's advanced CMOS process technology. This device is

available in 44 ball FBGA package.

- Eight 4Kword blocks and one hundreds twenty seven

32Kword blocks

- Bank 0 contains eight 4 Kword blocks and seven 32Kword

blocks

- Bank 1 ~ Bank 15 contain one hundred twenty 32Kword blocks

• Reduce program time using the VPP

PIN DESCRIPTION

• Support Single & Quad word accelerate program

Pin Name

Pin Function

Address Inputs

• Power Consumption (Typical value, CL=30pF)

- Burst Access Current : 30mA

A16 - A21

- Program/Erase Current : 15mA

- Read While Program/Erase Current : 40mA

- Standby Mode/Auto Sleep Mode : 15uA

• Block Protection/Unprotection

- Using the software command sequence

- Last two boot blocks are protected by WP=VIL

- All blocks are protected by VPP=VIL

• Handshaking Feature

A/DQ0 - A/DQ15 Multiplexed Address/Data input/output

CE

OE

Chip Enable

Output Enable

RESET

VPP

Hardware Reset Pin

Accelerates Programming

Write Enable

- Provides host system with minimum latency by monitoring

RDY

• Erase Suspend/Resume

WE

• Program Suspend/Resume

• Unlock Bypass Program/Erase

• Hardware Reset (RESET)

• Data Polling and Toggle Bits

- Provides a software method of detecting the status of program

or erase completion

• Endurance

100K Program/Erase Cycles Minimum

• Data Retention : 10 years

WP

Hardware Write Protection Input

Clock

CLK

RDY

AVD

Vcc

Ready Output

Address Valid Input

Power Supply

VSS

Ground

• Extended Temperature : -25°C ~ 85°C

• Support Common Flash Memory Interface

• Low Vcc Write Inhibit

• Package : 44 - ball FBGA Type, 7.5x8.5mm

0.5 mm ball pitch

1.0 mm (Max.) Thickness

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

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NOR FLASH MEMORY

K8S6415ET(B)B

44 Ball FBGA TOP VIEW (BALL DOWN)

1

2

3

4

5

6

7

8

9

10

A

B

RDY

A21

VSS

CLK

VCC

WE

VPP

A19

A17

NC

VCC

VSS

A16

A20

AVD

NC

RESET

WP

A18

A/DQ9

VCC

CE

VSS

OE

C

D

A/DQ7

A/DQ6 A/DQ13 A/DQ12 A/DQ3

A/DQ2

A/DQ8

A/DQ1

A/DQ15 A/DQ14

VSS

A/DQ5

A/DQ4 A/DQ11 A/DQ10

A/DQ0

FUNCTIONAL BLOCK DIAGRAM

Bank 0

X

Bank 0

Address

Dec

Cell Array

Vcc

Vss

Latch &

Control

Y Dec

Vpp

CLK

CE

Latch &

Control

Y Dec

Bank 1

Cell Array

OE

WE

WP

Bank 1

Address

X

I/O

Interface

&

Dec

Bank

RESET

RDY

Control

Bank 15

Cell Array

Bank 15

Address

X

AVD

Dec

Latch &

Control

Y Dec

A16~A21

Erase

A/DQ0~

A/DQ15

Control

High

Voltage

Gen.

Block

Inform

Program

Control

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NOR FLASH MEMORY

K8S6415ET(B)B

ORDERING INFORMATION

K 8 S 64 1 5 E T B - D E 7C

Samsung

NOR Flash Memory

Access Time

Refer to Table 1

Device Type

Multiplexed Burst

Operating Temperature Range

C = Commercial Temp. (0 °C to 70 °C)

E = Extended Temp. (-25 °C to 85 °C)

Package

F : FBGA

Density

64Mbits

D : FBGA(Lead Free)

Organization

x16 Organization

Version

3rd Generation

Block Architecture

T = Top Boot Block,

B = Bottom Boot Block

Operating Voltage Range

1.7 V to 1.95V

Table 1. PRODUCT LINE-UP

K8S6415E

7C

Synchronous/Burst

7B

Asynchronous

7B

7C

Speed Option

(54MHz) (66MHz)

Max. Initial Access Time (tIAA, ns)

Max. Burst Access Time (tBA, ns)

Max. OE Access Time (tOE, ns)

88.5

14.5

20

70

11

20

Max Access Time (tAA, ns)

90

20

80

20

VCC=1.7V-1.95V

Max CE Access Time (tCE, ns)

Max OE Access Time (tOE, ns)

Table 2. K8S6415E DEVICE BANK DIVISIONS

Bank 0

Bank 1 ~ Bank 15

Mbit

Block Sizes

Mbit

Block Sizes

Eight 4Kwords,

Seven 32Kwords

One hundred

twenty 32Kwords

4 Mbit

60 Mbit

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K8S6415ET(B)B

Table 3. Block Address Table

Bank

Block

BA134

BA133

BA132

BA131

BA130

BA129

BA128

BA127

BA126

BA125

BA124

BA123

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

Block Size

4 Kwords

(x16) Address Range

3FF000h-3FFFFFh

3FE000h-3FEFFFh

3FD000h-3FDFFFh

3FC000h-3FCFFFh

3FB000h-3FBFFFh

3FA000h-3FAFFFh

3F9000h-3F9FFFh

3F8000h-3F8FFFh

3F0000h-3F7FFFh

3E8000h-3EFFFFh

3E0000h-3E7FFFh

3D8000h-3DFFFFh

3D0000h-3D7FFFh

3C8000h-3CFFFFh

3C0000h-3C7FFFh

3B8000h-3BFFFFh

3B0000h-3B7FFFh

3A8000h-3AFFFFh

3A0000h-3A7FFFh

398000h-39FFFFh

390000h-397FFFh

388000h-38FFFFh

380000h-387FFFh

378000h-37FFFFh

370000h-377FFFh

368000h-36FFFFh

360000h-367FFFh

358000h-35FFFFh

350000h-357FFFh

348000h-34FFFFh

340000h-347FFFh

338000h-33FFFFh

330000h-337FFFh

328000h-32FFFFh

320000h-327FFFh

318000h-31FFFFh

310000h-317FFFh

308000h-30FFFFh

300000h-307FFFh

2F8000h-2FFFFFh

2F0000h-2F7FFFh

2E8000h-2EFFFFh

2E0000h-2E7FFFh

2D8000h-2DFFFFh

2D0000h-2D7FFFh

2C8000h-2CFFFFh

2C0000h-2C7FFFh

4 Kwords

Bank0

4 Kwords

32 Kwords

Bank1

Bank2

Bank3

Bank4

BA98

BA97

BA96

BA95

BA94

BA93

BA92

BA91

BA90

BA89

BA88

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K8S6415ET(B)B

Table 3. Block Address Table (Continued)

Bank

Block

BA87

BA86

BA85

BA84

BA83

BA82

BA81

BA80

BA79

BA78

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

BA46

BA45

BA44

BA43

BA42

Block Size

32 Kwords

(x16) Address Range

2B8000h-2BFFFFh

2B0000h-2B7FFFh

2A8000h-2AFFFFh

2A0000h-2A7FFFh

298000h-29FFFFh

290000h-297FFFh

288000h-28FFFFh

280000h-287FFFh

278000h-27FFFFh

270000h-277FFFh

268000h-26FFFFh

260000h-267FFFh

258000h-25FFFFh

250000h-257FFFh

248000h-24FFFFh

240000h-247FFFh

238000h-23FFFFh

230000h-237FFFh

228000h-22FFFFh

220000h-227FFFh

218000h-21FFFFh

210000h-217FFFh

208000h-20FFFFh

200000h-207FFFh

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

Bank5

Bank6

Bank7

Bank8

Bank9

Bank10

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K8S6415ET(B)B

Table 3. Block Address Table (Continued)

Bank

Block

BA41

BA40

BA39

BA38

BA37

BA36

BA35

BA34

BA33

BA32

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA21

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

32 Kwords

(x16) Address Range

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

Bank10

Bank11

Bank12

Bank13

Bank14

Bank15

32 Kwords

BA8

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

Table 3-1. OTP Block Addresses

Block Address

A21 ~ A8

Block Size

(x16) Address Range

OTP

3FFF80h-3FFFFFh

7FFFh

128words

After entering OTP block, any issued addresses should be in the range of OTP block address

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K8S6415ET(B)B

PRODUCT INTRODUCTION

The K8S6415E is an 64Mbit (67,108,364 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply

operating within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mecha-

nism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To pro-

vide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into

135 blocks (32-Kword x 127 , 4-Kword x 8, ). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks

can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the pro-

grammed data, 135 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the K8S6415E provides a

burst access of 14.5ns with initial access times of 90ns at 30pF. At 66MHz, the K8S6415E provides a burst access of 11ns with initial

access times of 70ns at 30pF. The command set of K8S6415E is compatible with standard Flash devices. The device uses Chip

Enable (CE), Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For

burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective com-

mand codes. The command codes to be combined with addresses and data are sequentially written to the command registers using

microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase cir-

cuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The

K8S6415E is implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/

Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and ver-

ifies data at specified address. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and

then executes the erase operation. The K8S6415E has means to indicate the status of completion of program/erase operations. The

status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device auto-

matically resets itself to the read mode. The device requires only 25 mA as burst and asynchronous mode read current and 15 mA

for program/erase operations.

Table 4. Device Bus Operations

Operation

CE

OE

WE

A16-21

A/DQ0-15 RESET

CLK

AVD

Asynchronous Read Operation

Add In/

H

L

H

Add In

L

DOUT

Write

L

H

X

L

H

X

H

L

Add In

Add In / DIN

High-Z

H

L

X

Standby

X

H

X

H

X

Hardware Reset

Load Initial Burst Address

X

Add In

X

High-Z

Add In

H

L

Burst

DOUT

Burst Read Operation

L

H

X

Terminate Burst Read Cycle via CE

H

X

L

X

H

X

High-Z

Add In

X

Terminate Burst Read Cycle via RESET

X

Terminate Current Burst Read Cycle and Start

New Burst Read Cycle

Add In

H

Note : L=VIL (Low), H=VIH (High), X=Don’t Care.

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K8S6415ET(B)B

COMMAND DEFINITIONS

The K8S6415E operates by selecting and executing its operational modes. Each operational mode has its own command set. In

order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg-

ister. Writing incorrect information which include address and data or writing an improper command will reset the device to the read

mode. The defined valid register command sequences are stated in Table 5.

Table 5. Command Sequences

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle

4th Cycle

5th Cycle 6th Cycle

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

RA

RD

Asynchronous Read

1

XXXH

F0H

Reset(Note 5)

1

4

3

2

5

6

1

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X00H

ECH

Autoselect

Manufacturer ID(Note 6)

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X01H

Note6

Autoselect

Device ID(Note 6)

555H

AAH

2AAH

55H

(BA)555H

90H

(BA)X02H

00H/01H

PA

Autoselect

Block Protection Verify(Note 7)

555H

AAH

2AAH

55H

555H

Program

A0H

PD

555H

AAH

2AAH

55H

555H

Unlock Bypass

20H

XXX

PA

Unlock Bypass Program(Note 8)

Unlock Bypass Block Erase(Note 8)

Unlock Bypass Chip Erase(Note 8)

Unlock Bypass Reset

A0H

PD

XXX

BA

80H

30H

XXXH

80H

XXXH

10H

XXXH

90H

XXXH

00H

XXX

PA1

PA2

PD2

555H

80H

PA3

PD3

PA4

PD4

Quadruple word Accelerated Program(Note9)

Chip Erase

A5H

PD1

2AAH

55H

555H

AAH

555H

AAH

555H

AAH

2AAH

55H

555H

10H

BA

555H

AAH

2AAH

55H

555H

80H

2AAH

55H

Block Erase

30H

(DA)XXXH

B0H

Erase Suspend (Note 10)

Erase Resume (Note 11)

Program Suspend (Note12)

Program Resume (Note11)

(DA)XXXH

30H

(DA)XXXH

B0H

(DA)XXXH

30H

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K8S6415ET(B)B

Table 5. Command Sequences (Continued)

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle

Add

Block Protection/Unprotection (Note 13)

Data

XXX

60H

XXX

60H

ABP

60H

3

Add

(DA)X55H

98H

CFI Query (Note 14)

Data

1

3

4

Add

Set Burst Mode Configuration Register (Note 15)

Data

555H

AAH

2AAH

55H

(CR)555H

C0H

Addr

555H

AAH

2AAH

55H

555H

70H

Enter OTP Block Region

Data

Addr

555H

AAH

2AAH

55H

555H

75H

XXX

00H

Exit OTP Block Region

Data

Notes:

1. RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A21 ~ A12)

DA : Bank Address (A21 ~ A18) , ABP : Address of the block to be protected or unprotected , CR : Configuration Register Setting

2. The 4th cycle data of autoselect mode and RD are output data. The others are input data.

3. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD and Device ID.

4. Unless otherwise noted, address bits A21 ~ A11 are don’t cares.

5. The reset command is required to return to read mode.

If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode.

If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode.

If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that

bank was in erase suspend mode.

6. The 3rd and 4th cycle bank address of autoselect mode must be same.

Device ID Data : "2250H" for Top Boot Block Device, "2251H" for Bottom Boot Block Device

7. Normal Block Protection Verify : 00H for an unprotected block and 01H for a protected block.

OTP Block Protect verify (with OTP Block Address after Entering OTP Block) : 00H for unlocked, and 01H for locked.

8. The unlock bypass command sequence is required prior to this command sequence.

9. Quadruple word accelerated program is invoked only at Vpp=V^ID,Vpp setup is required prior to this command sequence.

PA1, PA2, PA3, PA4 have the same A21~A2 address.

10. The system may read and program in non-erasing blocks when in the erase suspend mode.

The system may enter the autoselect mode when in the erase suspend mode.

The erase suspend command is valid only during a block erase operation, and requires the bank address.

11. The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.

12. This mode is used only to enable Data Read by suspending the Program operation.

13. Set block address(BA) as either A6 = V^IH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH and A0 = VIL for protected.

14. Command is valid when the device is in Read mode or Autoselect mode.

15. See "Set Burst Mode Congiguration Register" for details.

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K8S6415ET(B)B

DEVICE OPERATION

The device has I/Os that accept both address and data information. To write a command or command sequence (which includes pro-

gramming data to the device and erasing blocks of memory), the system must drive CLK, AVD and CE to VIL and OE to VIH when

providing an address to the device, and drive CLK, WE and CE to VIL and OE to VIH when writing commands or data.

The device provide the unlock bypass mode to save its program time for program operation. Unlike the standard program command

sequence which is comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass

mode. One block, multiple blocks, or the entire device can be erased. Table 3 indicates the address space that each block occupies.

The device’s address space is divided into sixteen banks: Bank 0 contains the boot/parameter blocks, and the other banks(from Bank

1 to 15) consist of uniform blocks. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “block address”

is the address bits required to uniquely select a block. ICC2 in the DC Characteristics table represents the active current specification

for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

Read Mode

The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in

asynchronous mode. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset com-

mand is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase opera-

tion, or if the bank is in the autoselect mode.

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. That

means device enters burst read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst

read is finished(or terminated), the device return to asynchronous read mode automatically.

Asynchronous Read Mode

For the asynchronous read mode a valid address should be asserted on A/DQ0-A/DQ15 and A16-A21, while driving AVD and CE to

VIL. WE should remain at VIH . Note that CLK must remain low for asynchronous read mode. The address is latched at the rising

edge of AVD, and then the system can drive OE to VIL. The data will appear on A/DQ0-A/DQ15. Since the memory array is divided

into sixteen banks, each bank remains enabled for read access until the command register contents are altered.

Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the

delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of

OE to valid data at the output. The asynchronous access time is measured from a valid address, falling edge of AVD or falling edge

of CE whichever occurs last. To prevent the memory content from spurious altering during power transition, the initial state machine

is set for reading array data upon device power-up, or after a hardware reset.

Synchronous (Burst) Read Mode

The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the sys-

tem should determine how many clock cycles are desired for the initial word(tIAA) of each burst access and what mode of burst oper-

ation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further

details. The status data also can be read during burst read mode by using AVD signal with a bank address. To initiate the synchro-

nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed

the program or erase operation.

Continuous Linear Burst Read

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. Note that

the device is enabled for asynchronous mode when it first powers up. The initial word is output tIAA after the rising edge of the first

CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the

internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is cross-

ing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of addtional

clock cycle can vary from zero to three cycles, and the exact number of additional clock cycle depends on the starting address of

burst read.(Refer to Figure 13) The RDY output indicates this condition to the system by pulsing low. The device will continue to out-

put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the

system asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 4.) The reset command does not ter-

minate the burst read operation. When it accessed the bank is programming or erasing , continuous burst read mode will output sta-

tus data. And status data will be sustained until the system asserts CE high or RESET low or AVD low in conjunction with a new

address.

Note that at least 10ns is needed to start next burst read operation from terminating previous burst read operation in the

case of asserting CE high.

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8-,16-Word Linear Burst Read

As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of

words are read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which

the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given

mode.(See Table. 6)

Table 6. Burst Address Groups(Wrap mode only)

Burst Mode

8 word

Group Size

8 words

Group Address Ranges

0-7h, 8-Fh, 10-17h, ....

0-Fh, 10-1Fh, 20-2Fh, ....

16 word

16 words

As an example:

In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst

sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to

the first address in the selected group. In a similar manner, 16-word wrap mode begin their burst sequence on the starting address

written to the device, and then wrap back to the first address in the selected address group.

In no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequence would be 2-3-4-5-6-7-8-9h. The

burst sequence begins with the starting address written to the device, and continue to the 8th address from starting address. In a sim-

ilar manner, 16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the 16th

address from starting address. Also, when the address cross the word boundary in no-wrap mode, same number of additional clock

cycles as continuous linear mode is needed.

Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is

driven active for burst read mode. Upon power up, the number of total initial access cycles defaults to seven.

Handshaking

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word

of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait

state configuration.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE goes low indicates

the initial word of valid burst data. Using the autoselect command sequence the handshaking feature may be verified in the device.

Set Burst Mode Configuration Register

The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read

mode. The burst mode configuration register must be set before the device enter burst mode.

The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h,

address bits A11-A0 should be 555h, and address bits A18-A12 set the code to be latched. The device will power up or after a hard-

ware reset with the default setting.

Table 7. Burst Mode Configuration Register Table

Address Bit

Function

Settings(Binary)

1 = RDY active one clock cycle before data

0 = RDY active with data(default)

A18

RDY Active

A17

A16

000 = Continuous(default)

001 = 8-word linear with wrap

010 = 16-word linear with wrap

011 = 8-word linear with no-wrap

100 = 16-word linear with no-wrap

101 ~ 111 = Reserve

Burst Read Mode

A15

A14

A13

000 = Data is valid on the 4th active CLK edge after AVD transition to V^IH

001 = Data is valid on the 5th active CLK edge after AVD transition to V^IH

010 = Data is valid on the 6th active CLK edge after AVD transition to V^IH

011 = Data is valid on the 7th active CLK edge after AVD transition to V^IH(default)

Programmable Wait State

100 = Reserve

101 = Reserve

110 = Reserve

111 = Reserve

A12

Programmable Wait State Configuration

This feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be avail-

able. This value is determined by the input frequency of the device. Address bits A14-A12 determine the setting. (See Burst Mode

Configuration Register Table)

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The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst

mode. Note that hardware reset will set the wait state to the default setting, that is 7 initial cycles.

Burst Read Mode Setting

The device supports five different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and

16 word linear burst modes with no-wrap.

RDY Configuration

By default, the RDY pin will be high whenever there is valid data on the output. The device can be set so that RDY goes active one

data cycle before active data. Address bit A18 determine this setting. Note that RDY always go high with valid data in case of word

boundary crossing.

Table 8. Burst Address Sequences

Burst Address Sequence(Decimal)

Start

Addr.

Continuous Burst

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

8-word Burst

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

16-word Burst

0-1-2-3 ... -D-E-F

1-2-3-4 ... -E-F-0

2-3-4-5 ... -F-0-1

0

1

2

Wrap

.

0

1

2

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

0-1-2-3 ... -D-E-F

1-2-3-4 ... -E-F-10

2-3-4-5 ... -F-0-11

No-wrap

.

Autoselect Mode

By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by

asynchronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory

array). Standard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer

and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection.

Table 5 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank

that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The autoselect command may not be written

while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block

address is needed for the verification of block protection. The system may read at any address within the same bank any number of

times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To

terminate the autoselect operation, write Reset command(F0H) into the command register.

Table 9. Autoselect Mode Description

Description

Manufacturer ID

Address

(DA) + 00H

(DA) + 01H

(BA) + 02H

Read Data

ECH

Device ID

2250H(Top Boot Block), 2251H(Bottom Boot Block)

01H (protected), 00H (unprotected)

Block Protection/Unprotection

Standby Mode

When the CE and RESET inputs are both held at VCC ± 0.2V or the system is not reading or writing, the device enters Stand-by mode

to minimize the power consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE

input. When the device is in either of these standby modes, the device requires standard access time (tCE ) for read access before it

is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is

completed. ICC5 in the DC Characteristics table represents the standby current specification.

Automatic Sleep Mode

The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode.

When addresses remain stable for tAA+60ns, the device automatically enables this mode. The automatic sleep mode is independent

of the CE, WE, and OE control signals. In a sleep mode, output data is latched and always available to the system. When addresses

are changed, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current.

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Output Disable Mode

When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.

Block Protection & Unprotection

To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in

the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first

two cycles are written: addresses are don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h)

is written, while specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or

unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or

exit the sequence by writing F0h (reset command).

The device offers three types of data protection at the block level:

• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.

• When WP is at VIL, the two outermost blocks are protected.

• When VPP is at VIL, all blocks are protected.

Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.

Hardware Reset

The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least

a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write com-

mands for the duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. To

ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence.

As previously noted, when RESET is held at VSS ± 0.2V, the device enters standby mode. The RESET pin may be tied to the system

reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asyn-

chronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is

asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is

ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed

within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Char-

acteristics tables for RESET parameters and to Figure 6 for the timing diagram.

Software Reset

The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The

addresses are in Don’t Care state. The reset command may be written between the sequence cycles in an erase command

sequence before erasing begins, or in an program command sequence before programming begins. If the device begins erasure or

programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank

that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset com-

mand valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset com-

mand returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend

mode, writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase

operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase

Suspend)

Program

The K8S6415E can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal

Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two

cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory

location and the data to be programmed at that location are written. The device automatically generates adequate program pulses

and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not

required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored.

Note that a hardware reset during a program operation will cause data corruption at the corresponding location.

Accelerated Program Operation

The device provides Single/Quadruple word accelerated program operations through the Vpp input. Using this mode, faster manu-

facturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock

Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for

program operations. By removing VID returns the device to normal operation mode.

Note that Read while Accelerated Program and Program suspend mode are not guaranteed

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Single word accelerated program operation

The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-

cycle (PA - PD) is for program address and data ).

Quadruple word accelerated program operation

As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for qua-

druple word program command, and four cycles are for program address and data).

• Only four words programming is possible

• Each program address must have the same A21~A2 address

• The device automatically generates adequate program pulses and ignores other command after program command

• Program/Erase cycling must be limited below 100cycles for optimum performance.

• Read while Write mode is not guaranteed

Requirements : Ambient temperature : TA=30°C±10°C

Unlock Bypass

The K8S6415E provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip

erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command

sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four bus cycles,

the unlock bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issu-

ing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a

third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass pro-

gram/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles;

writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the

only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is com-

prised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase com-

mand(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock

bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset

command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data

(00H). Then, the device returns to the read mode.

To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the

unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit

the unlock bypass mode, just remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always

connected with VIH, VIL or VID.).

Chip Erase

To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus

cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two

more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the

entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the

command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.

Block Erase

To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six

bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is

written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine

automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the rising edge of AVD

, while the Block Erase command is latched on the rising edge of WE. Multiple blocks can be erased sequentially by writing the sixth

bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can

be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is needed.(Similarly,

only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase

command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command

will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the

Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command

written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase command will initiate the

Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window"

may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase oper-

ation.

The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device auto-

matically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to

reduce the time required for erase. By removing VID returns the device to normal operation mode.

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Erase Suspend / Resume

The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is pos-

sible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid

during the Block Erase operation including the time window of 50 us. The Erase Suspend command is not valid while the Chip Erase

or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation,

the device requires a maximum of 20 us(recovery time) to suspend the erase operation. Therefore system must wait for 20us(recov-

ery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data immediately from

a bank which don’t include the block being erased without recovery time(max. 20us) after Erase Suspend command. And, after the

maximum 20us recovery time, the device is availble for programming data in a block that is not being erased. But, when the Erase

Suspend command is written during the block erase time window (50 us) , the device immediately terminates the block erase time

window and suspends the erase operation. The system may also write the autoselect command sequence when the device is in the

Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Sus-

pend or Erase Resume command is executed, the addresses are in Don't Care state.

Program Suspend / Resume

The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program

operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during

Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 2us is needed to enter the Pro-

gram Suspend Read mode. Therefore system must wait for 2us(recovery time) to read the data from the bank which include the

block being programmed. Othwewise, system can read the data immediately from a bank which don't include block being pro-

grammed without ecovery time(max. 2us) after Program Suspen command. Like an Erase Suspend mode, the device can be

returned to Program mode by using a Program Resume command.

Read While Write Operation

The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write opera-

tion. An erase operation may also be suspended to read from or program to another location within the same bank(except the block

being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 12 shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write current

specifications.

OTP Block Region

The OTP Block feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic

Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that

block in any manner they choose. The customer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked

state or a "1" for Locked state.

The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence"

at Table8). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the

addresses (7FFF80h~7FFFFFh) normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection

Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block"

Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the

device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available

when the OTP Block is enabled.

Customer Lockable

In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated

programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block

is started by writing the "Enter OTP Block" Command sequence, and then the "Block Protection" Command sqeunce (Table 8) with

an OTP Block address. Hardware reset terminates Locking operation, and then makes exiting from OTP Block. The Locking opera-

tion has to be above 100us.

The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking

and none of the bits in the OTP Block space can be modified in any way.

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle.

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Low VCC Write Inhibit

To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc

< VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the

device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s

responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO.

Logical Inhibit

Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a log-

ical zero while OE is a logical one.

Power-up Protection

To avoid initiation of a write cycle during VCC power-up, RESET low must be asserted during Power-up. After RESET goes high. the

device is reset to the read mode.

FLASH MEMORY STATUS FLAGS

The K8S6415E has means to indicate its status of operation in the bank where a program or erase operation is in processes.

Address must include bank address being executed internal routine operation. The status is indicated by raising the device status

flag via corresponding DQ pins. The status data can be read during burst read mode by using AVD signal with a bank address. That

means status read is supported in synchronous mode. If status read is performed, the data provided in the burst read is identical to

the data in the initial access. To initiate the synchronous read again, a new address and AVD pulse is needed after the host has

completed status reads or the device has completed the program or erase operation. The corresponding DQ pins are DQ7, DQ6,

DQ5, DQ3 and DQ2.

Table 10. Hardware Sequence Flags

Status

DQ7

0

DQ6

Toggle

DQ5

DQ3

DQ2

1

Programming

0

1

Block Erase or Chip Erase

Erase Suspend Read

Toggle

Erase Suspended

Block

Toggle

(Note 1)

1

Data

Toggle

1

0

Data

0

Data

0

Non-EraseSuspended

Block

Erase Suspend Read

Data

DQ7

Data

1

In Progress

Erase Suspend

Program

Non-EraseSuspended

Block

Program Suspended

Block

Toggle

(Note 1)

Program Suspend Read

0

Non- program

Suspended Block

Data

No

Toggle

Programming

DQ7

0

Toggle

1

0

1

0

Exceeded

Time Limits

Block Erase or Chip Erase

Erase Suspend Program

(Note 2)

No

Toggle

DQ7

Notes :

1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block.

2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.

DQ7 : Data Polling

When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as

an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data

written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program

Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is

being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program

suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is

read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements

the data for approximately 1µs and the device then returns to the Read Mode without changing data in the block. If an attempt is

made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read

Mode without erasing the data in the block.

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K8S6415ET(B)B

DQ6 : Toggle Bit

Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,

DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend

Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6.

If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an

attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode

without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs and

the device then returns to the Read Mode without erasing the data in the block.

DQ5 : Exceed Timing Limits

If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.

DQ3 : Block Erase Timer

The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time win-

dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write

commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase

time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been

accepted, the software may check the status of DQ3 following each block erase command.

DQ2 : Toggle Bit 2

The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When

the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is

in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the

Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-

programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if

the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode.

RDY: Ready

Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low

state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.

Start

Read(DQ0~DQ7)

Valid Address

Start

Read(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

DQ6 = Toggle ?

Yes

DQ7 = Data ?

No

Yes

No

DQ5 = 1 ?

Yes

DQ5 = 1 ?

Yes

Read twice(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

No

Yes

DQ6 = Toggle ?

DQ7 = Data ?

Yes

Fail

No

Fail

Pass

Figure 2. Toggle Bit Algorithms

Figure 1. Data Polling Algorithms

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Commom Flash Memory Interface

Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-

tion of the device, such as memory size and electrical features. Once this information has been obtained, the system software will

know which command sets to use to enable flash writes, block erases, and control the flash component.

When the system writes the CFI command(98H) to address 55H , the device enters the CFI mode. And then if the system writes the

address shown in Table 11, the system can read the CFI data. Query data are always presented on the lowest-order data out-

puts(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the

reset command.

Table 11. Common Flash Memory Interface Code

Addresses

Description

Data

(Word Mode)

10H

11H

12H

0051H

0052H

0059H

Query Unique ASCII string "QRY"

13H

14H

0002H

0000H

Primary OEM Command Set

15H

16H

0040H

0000H

Address for Primary Extended Table

17H

18H

0000H

Alternate OEM Command Set (00h = none exists)

19H

1AH

0000H

Address for Alternate OEM Extended Table (00h = none exists)

Vcc Min. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

1BH

1CH

0017H

0019H

Vcc Max. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

Vpp(Acceleration Program) Supply Minimum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

1DH

1EH

0085H

0095H

Vpp(Acceleration Program) Supply Maximum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

Typical timeout per single word write 2^Nus

1FH

20H

21H

22H

23H

24H

25H

26H

27H

0004H

0000H

000AH

0011H

0005H

0000H

0004H

0000H

0017H

Typical timeout for Min. size buffer write 2^Nus(00H = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms(00H = not supported)

Max. timeout for word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical(00H = not supported)

Device Size = 2^Nbyte

28H

29H

0000H

Flash Device Interface description

2AH

2BH

0000H

Max. number of byte in multi-byte write = 2^N

Number of Erase Block Regions within device

2CH

0002H

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Table 11. Common Flash Memory Interface Code (Continued)

Description

Addresses

Data

(Word Mode)

2DH

2EH

2FH

30H

0007H

0000H

0020H

0000H

Erase Block Region 1 Information

Bits 0~15: y+1=block number

Bits 16~31: block size= z x 256bytes

31H

32H

33H

34H

007EH

0000H

0001H

Erase Block Region 2 Information

Erase Block Region 3 Information

35H

36H

37H

38H

0000H

39H

3AH

3BH

3CH

0000H

Erase Block Region 4 Information

Query-unique ASCII string "PRI"

40H

41H

42H

0050H

0052H

0049H

Major version number, ASCII

Minor version number, ASCII

43H

44H

0032H

0030H

Address Sensitive Unlock(Bits 1-0)

0 = Required, 1= Not Required

Silcon Revision Number(Bits 7-2)

45H

0000H

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46H

47H

0002H

0001H

Block Protect

00 = Not Supported, 01 = Supported

Block Temporary Unprotect 00 = Not Supported, 01 = Supported

Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported

48H

49H

0000H

0001H

Simultaneous Operation

00 = Not Supported, 01 = Supported

4AH

4BH

4CH

0001H

0000H

Burst Mode Type 00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page

Max. Operating Clock Frequency (MHz )

4EH

4FH

0042H

0000H

RWW(Read While Write) Functionality Restriction (00H = non exists , 01H = exists)

Handshaking

00 = Not Supported at both mode, 01 = Supported at Sync. Mode

10 = Supported at Async. Mode, 11 = Supported at both Mode

50H

0001H

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ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

-0.5 to +2.5

-0.5 to +9.5

-0.5 to +2.5

-10 to +125

-25 to +125

-65 to +150

5

Unit

Vcc

Voltage on any pin relative to VSS

V

VPP

VIN

All Other Pins

Commercial

Extended

Temperature Under Bias

Tbias

°C

Storage Temperature

Tstg

°C

mA

°C

Short Circuit Output Current

IOS

TA (Commercial Temp.)

TA (Extended Temp.)

0 to +70

Operating Temperature

-25 to + 85

°C

Notes :

1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns.

Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.

2. Minimum DC input voltage is -0.5V on V^PP. During transitions, this level may fall to -2.0V for periods <20ns.

Maximum DC input voltage is +9.5V on V^PPwhich, during transitions, may overshoot to +12.0V for periods <20ns.

3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )

Parameter

Symbol

Min

1.7

0

Typ.

1.8

0

Max

1.95

0

Unit

V

Supply Voltage

VCC

Supply Voltage

VSS

V

DC CHARACTERISTICS

Parameter

Symbol

ILI

Test Conditions

Min

Typ

Max

+ 1.0

35

Unit

µA

Input Leakage Current

VPP Leakage Current

Output Leakage Current

Active Burst Read Current

VIN=VSS to VCC, VCC=VCCmax

VCC=VCCmax , VPP=9.5V

- 1.0

-

ILIP

-

µA

ILO

VOUT=VSS to VCC, VCC=VCCmax, OE=VIH

- 1.0

-

+ 1.0

36

µA

ICCB1

CE=VIL, OE=VIH (Continuous Burst, 66MHz)

-

24

27

3

mA

µA

10MHz

40

Active Asynchronous

Read Current

ICC1

CE=VIL, OE=VIH

1MHz

5

Active Write Current (Note 2)

Read While Write Current

Accelerated Program Current

Standby Current

ICC2

ICC3

ICC4

ICC5

ICC6

CE=VIL, OE=VIH, WE=VIL, VPP=VIH

CE=VIL, OE=VIH

15

40

15

30

70

CE=VIL, OE=VIH , VPP=9.5V

CE= RESET=VCC ± 0.2V

RESET = VSS ± 0.2V

30

50

Standby Current During Reset

50

µA

CE=VSS ± 0.2V, Other Pins=VIL or VIH

VIL = VSS ± 0.2V, VIH = VCC ± 0.2V

Automatic Sleep Mode(Note 3)

ICC7

-

15

50

µA

Input Low Voltage

VIL

VIH

-0.5

VCC-0.4

-

0.4

V

Input High Voltage

-

VCC+0.4

Output Low Voltage

VOL

VOH

VID

IOL = 100 µA , VCC=VCCmin

IOH = -100 µA , VCC=VCCmin

-

0.1

-

Output High Voltage

VCC-0.1

8.5

Voltage for Accelerated Program

Low VCC Lock-out Voltage

9.0

-

9.5

1.3

VLKO

1.0

Notes:

1. Maximum ICC specifications are tested with VCC = VCCmax.

2. ICC active while Internal Erase or Internal Program is in progress.

3. Device enters automatic sleep mode when addresses are stable for tAA + 60ns.

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K8S6415ET(B)B

CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)

Item

Symbol

Test Condition

Min

Max

10

Unit

pF

Input Capacitance

CIN

VIN=0V

-

Output Capacitance

Control Pin Capacitance

COUT

CIN2

VOUT=0V

VIN=0V

10

pF

10

pF

Note : Capacitance is periodically sampled and not 100% tested.

AC TEST CONDITION

Parameter

Value

0V to VCC

5ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

VCC/2

CL = 30pF

Device

Under

Test

VCC

Input & Output

VCC/2

Test Point

* CL = 30pF including scope

and Jig capacitance

0V

Input Pulse and Test Point

Output Load

AC CHARACTERISTICS

Synchronous/Burst Read

7B

(54 MHz)

7C

(66 MHz)

Parameter

Symbol

Unit

Min

Max

Min

Max

Initial Access Time

tIAA

tBA

-

88.5

-

70

11

-

ns

Burst Access Time Valid Clock to Output Delay

AVD Setup Time to CLK

AVD Hold Time from CLK

AVD High to OE Low

14.5

tAVDS

tAVDH

tAVDO

tACS

5

7

0

5

7

4

-

5

6

0

5

6

4

-

Address Setup Time to CLK

Address Hold Time from CLK

Data Hold Time from Next Clock Cycle

Output Enable to Data

-

tACH

-

tBDH

-

tOE

20

14.5

20

15

-

20

11

20

15

-

Output Enable to RDY valid

CE Disable to High Z

tOER

tCEZ

-

OE Disable to High Z

tOEZ

-

CE Setup Time to CLK

tCES

7

-

6

-

CLK to RDY Setup Time

RDY Setup Time to CLK

CLK High or Low Time

tRDYA

tRDYS

tCLKH/L

tCLKHCL

14.5

-

11

-

4

4.5

-

4

3.5

-

CLK Fall or Rise Time

3

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K8S6415ET(B)B

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.

tCES

tCEZ

CE

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

A16-A21

Aa

tBA

tACH

A/DQ0:

A/DQ15

Hi-Z

Aa

Da

Da+1 Da+2

tIAA

Da+3

Da+n

tOEZ

OE

tOER

tRDYS

Hi-Z

tRDYA

Hi-Z

RDY

Figure 3. Continuous Burst Mode Read (66 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

4 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=0

18.5ns typ.

tCES

tCEZ

CE

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

A16-A21

Aa

tBA

tACH

A/DQ0:

A/DQ15

Hi-Z

Aa

Da

tIAA

Da+3

Da+n

Da+1

Da+2

tOEZ

OE

tOER

tRDYS

tRDYA

Hi-Z

RDY

Figure 4. Continuous Burst Mode Read (54 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

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K8S6415ET(B)B

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ..

tCES

CE

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

A16-A21

Aa

tBA

tACH

A/DQ0:

A/DQ15

Aa

D6

D7

D0

D2

D7

tIAA

D1

D3

D0

OE

tOER

tRDYS

Hi-Z

tRDYA

RDY

Figure 5. 8 word Linear Burst Mode with Wrap Around (66 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.

tCES

CE

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

A16-A21

Aa

tBA

tACH

A/DQ0:

A/DQ15

Aa

D6

D7

D0

D2

D7

tIAA

D1

D3

D0

OE

tOER

tRDYS

Hi-Z

tRDYA

RDY

Figure 6. 8 word Linear Burst with RDY Set One Cycle Before Data (Wrap Around Mode, CR setting : A18=1)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

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K8S6415ET(B)B

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2ns typ

tCES

tCEZ

CE

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

A16-A21

Aa

tBA

D8

tACH

A/DQ0:

A/DQ15

Hi-Z

Aa

D6

D7

D10

D13

tIAA

D9

tOEZ

OE

tOER

tRDYS

tRDYA

Hi-Z

RDY

Figure 7. 8 word Linear Burst Mode (No Wrap Case)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

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K8S6415ET(B)B

AC CHARACTERISTICS

Asynchronous Read

Parameter

7B

7C

Symbol

Unit

Min

Max

Min

Max

Access Time from CE Low

tCE

tAA

-

90

-

80

-

ns

Asynchronous Access Time

AVD Low Time

tAVDP

tAAVDS

tAAVDH

tOE

12

5

7

-

12

5

7

-

Address Setup Time to rising Edge of AVD

Address Hold Time from Rising Edge of AVD

Output Enable to Output Valid

-

20

-

20

-

Read

0

Output Enable Hold

Time

t^OEH

tOEZ

Toggle and

Data Polling

10

-

10

-

ns

Output Disable to High Z(Note 1)

15

Note: 1. Not 100% tested.

SWITCHING WAVEFORMS

Asynchronous Mode Read (tCE)

CE

tOE

OE

tOEH

WE

tCE

tOEZ

A/DQ0:

A/DQ15

VA

Valid RD

A16-A21

tAAVDS

AVD

tAAVDH

tAVDP

Hi-Z

RDY

27

Revision 1.2

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K8S6415ET(B)B

Asynchronous Mode Read (tAA)

Case 1 : Valid Address Transition occurs before AVD is driven to Low

CE

tOE

OE

tOEH

WE

tOEZ

A/DQ0:

A/DQ15

VA

Valid RD

tAA

A16-A21

VA

tAAVDS

tAAVDH

AVD

RDY

tAVDP

Hi-Z

Case 2 : Valid Address Transition occurs after AVD is driven to Low

CE

tOE

OE

tOEH

WE

tOEZ

A/DQ0:

A/DQ15

VA

Valid RD

tAA

VA

A16-A21

tAAVDH

tAAVDS

AVD

RDY

tAVDP

Hi-Z

Figure 8. Asynchronous Mode Read

Note: VA=Valid Read Address, RD=Read Data.

Asynchronous mode may not support read following four sequential invalid read condition within 200ns.

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K8S6415ET(B)B

AC CHARACTERISTICS

Hardware Reset(RESET)

Parameter

All Speed Options

Symbol

Unit

Max

Min

RESET Pin Low(During Internal Routines)

to Read Mode (Note)

t^Ready

µs

-

20

RESET Pin Low(NOT During Internal Routines)

to Read Mode (Note)

ns

-

500

RESET Pulse Width

tRP

t^RH

200

20

-

ns

µs

Reset High Time Before Read (Note)

RESET Low to Standby Mode

tRPD

Note: Not 100% tested.

SWITCHING WAVEFORMS

CE, OE

RESET

tRH

tRP

tReady

Reset Timings NOT during Internal Routines

CE, OE

RESET

tReady

tRP

Reset Timings during Internal Routines

Figure 9. Reset Timings

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K8S6415ET(B)B

AC CHARACTERISTICS

Erase/Program Operation

7B, 7C

Parameter

Symbol

Unit

Min

Typ

Max

WE Cycle Time(Note 1)

tWC

tAS

100

5

-

ns

µs

Address Setup Time

-

Address Hold Time

tAH

7

-

AVD Low Time

tAVDP

tDS

12

50

0

-

Data Setup Time

Data Hold Time

tDH

-

Read Recovery Time Before Write

CE Setup Time

tGHWL

tCS

-

0

-

0

CE Hold Time

tCH

-

0

WE Disable to AVD Enable

WE Pulse Width

tWEA

30

-

tWP

60

40

-

WE Pulse Width High

tWPH

tSR/W

tPGM

-

Latency Between Read and Write Operations

Word Programming Operation

Accelerated Single word Programming Operation

Accelerated Quad word Programming Operation

Main Block Erase Operation (Note 2)

VPP Rise and Fall Time

0

-

11.5

6.5

0.7

-

t^ACCPGM

t^ACCPGM_QUAD

t^BERS

tVPP

µs

-

µs

-

sec

ns

µs

500

1

VPP Setup Time (During Accelerated Programming)

V^CCSetup Time

tVPS

-

tVCS

µs

50

-

Notes:

1. Not 100% tested.

2. Not include the preprogramming time.

FLASH Erase/Program Performance

Limits

Typ.

0.7

0.2

91

Parameter

Unit

Comments

Min.

Max.

32 Kword

4 Kword

-

14

Block Erase Time

-

4

Excludes 00h programming prior to

erasure

sec

Chip Erase Time

-

Accelerated Chip Erase Time

Word Programming Time

60

-

210

120

-

11.5

6.5

46

Accelerated Single word Programming Time

Accelerated Quad word Programming Time

Chip Programming Time

µs

Excludes system level overhead

Accelerated Singl word Chip Programming Time

Accelerated Quad word Chip Programming Time

26

-

sec

6

-

Minimum 100,000 cycles guaran-

teed in all Bank

Erase/Program Endurance (Note 3)

100,000

-

Cycles

Notes:

1. 25°C, VCC = 1.8V, 100,000 cycles, typical pattern.

2. System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each

word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure.

3. 100K Program/Erase Cycle in all Bank

Requirements : Ambient temperature : TA=30°C±10°C

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K8S6415ET(B)B

SWITCHING WAVEFORMS

Program Operations

Program Command Sequence (last two cycles)

Read Status Data

tAS

tWEA

AVD

tAVDP

tAH

A16:A21

PA

VA

A/DQ0:

A/DQ15

In

Complete

555h

A0h

PD

Progress

tDS

tDH

CE

OE

WE

tCH

tWP

tWPH

tPGM

tCS

tWC

VIL

CLK

VCC

tVCS

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A16–A21 are don’t care during command sequence unlock cycles.

4. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

Figure 10. Program Operation Timing

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SWITCHING WAVEFORMS

Erase Operation

Erase Command Sequence (last two cycles)

tWEA

Read Status Data

tAS

AVD

tAVDP

tAH

A16:A21

BA

VA

555h for

chip erase chip erase

10h for

A/DQ0:

2AAh

In

Complete

55h

BA

30h

tDS

Progress

A/DQ15

tDH

CE

OE

tCH

tWP

WE

tWPH

tBERS

tCS

tWC

VIL

CLK

VCC

tVCS

Notes:

1. BA is the block address for Block Erase.

2. Address bits A16–A21 are don’t cares during unlock cycles in the command sequence.

3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

Figure 11. Chlp/Block Erase Operations

32

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

SWITCHING WAVEFORMS

Unlock Bypass Program Operations(Accelerated Program)

CE

AVD

WE

PA

A16:A21

A/DQ0:

A/DQ15

Don’t Care

tVPS

A0h

PD

Don’t Care

OE

1us

VID

tVPP

VPP

VIL or VIH

Unlock Bypass Block Erase Operations

CE

AVD

WE

BA

A16:A21

555h for

chip erase

10h for

chip erase

A/DQ0:

Don’t Care

A/DQ15

80h

BA

30h

Don’t Care

OE

1us

tVPS

VID

tVPP

VPP

VIL or VIH

Notes:

1. VPP can be left high for subsequent programming pulses.

2. Use setup and hold times from conventional program operations.

3. Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp.

Figure 12. Unlock Bypass Operation Timings

33

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

SWITCHING WAVEFORMS

Quad word Accelerated Program

CE

AVD

WE

A16:A21

PA1

PA2

PA3

PA4

Don’t Care

VA

A/DQ0:

A/DQ15

Complete

Don’t Care

A5H

PD1

PD3

PA4 PD4

PD2

OE

1us

tVPS

tACCPGM_QUAD

VID

tVPP

VPP

V

IL or VIH

Notes:

1. VPP can be left high for subsequent programming pulses.

2. Use setup and hold times from conventional program operations.

3. Quad word Acelerate program commands can be used when the VID is applied to Vpp.

Figure 13. Quad word Accelerated Program Operation Timings

34

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

SWITCHING WAVEFORMS

Data Polling Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

A16-A21

VA

tACH

A/DQ0:

VA

Status Data

VA

A/DQ15

tIAA

OE

tRDYS

Hi-Z

RDY

Notes:

1. VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data.

Figure 14. FLASH Data Polling Timings (During Internal Routine)

Toggle Bit Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

A16-A21

VA

tACH

A/DQ0:

A/DQ15

VA

Status Data

Toggle Status Data

tIAA

tOE

OE

tRDYS

Hi-Z

RDY

Notes:

1. VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling.

Figure 15. Toggle Bit Timings(During Internal Routine)

35

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

SWITCHING WAVEFORMS

Read While Write Operations

Last Cycle in

Program or

Block Erase

Begin another

Program or Erase

Command Sequences

Read status in same bank

and/or array data from other bank

Command Sequence

tWC

tRC

tWC

CE

OE

tOE

tOEH

tGHWL

WE

tWPH

tWP

tDS

tAA

tOEH

tDH

RA

A/DQ0:

A/DQ15

PA/BA

PD/30h

RD

RA

RD

555h

AAh

tSR/W

A16-A21

AVD

PA/BA

tAS

RA

tAH

Figure 16. Read While Write Operation

Note:

Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” and checking the status of the program or

erase operation in the “busy” bank.

36

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

Crossing of First Word Boundary in Burst Read Mode

The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no addtional

clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. Also, the number of addtional clock cycle

for the first word boundary can varies from zero to three cycles, and the exact number of additional clock cycle depends on the start-

ing address of burst read.

The rule to determine the additional clock cycle is as follows. All addresses can be divided into 4 groups. The applied rule is "The res-

idue obtained when the address is divided by 4" or "two LSB bits of address". Using this rule, all address can be divided by 4 different

groups as shown in below table. For simplicity of terminology, "4N" stands for the address of which the residue is "0"(or the two LSB

bits are "00") and "4N+1" for the address of which the residue is "1"(or the two LSB bits are "01"), etc.

The additional clock cycles for first word boundary crossing are zero, one, two or three when the burst read start from "4N" address,

"4N+1" address, "4N+2" address or "4N+3" address respectively.

Starting Address vs. Additional Clock Cycles for first word boundary

Srarting Address Group

for Burst Read

Additional Clock Cycles for

First Word Boundary Crossing

The Residue of (Address/4)

LSB Bits of Address

4N

0

1

2

3

00

01

10

11

0 cycle

1 cycle

2 cycles

3 cycles

4N+1

4N+2

4N+3

Case 1 : Start from "4N" address group

5 cycle for initial access shown.(66MHz case)

Programmable wait state function is set to 01h (Wait States 3)

Address/

Data Bus

Valid Address

3C

3D

3E

40

41

42

43

3F

CLK

AVD

3C

3D

41

42

43

44

3E

3F

40

No Additional Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00003FH , 00007FH , 0000BFH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 17. FLASH Crossing of first word boundary in burst read mode.

37

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

Case2 : Start from "4N+1" address group

5 cycle for initial access shown.(66MHz case)

Programmable wait state function is set to 01h (Wait States 3)

Address/

Data Bus

Valid Address

3D

3E

3F

40

41

42

43

CLK

AVD

3D

3E

41

42

43

44

40

Additional 1 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Case 3 : Start from "4N+2" address group

5 cycle for initial access shown.(66MHz case)

Programmable wait state function is set to 01h (Wait States 3)

Address/

Data Bus

Valid Address

3E

3F

40

41

42

43

CLK

AVD

3E

3F

41

42

43

44

40

Additional 2 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00003FH , 00007FH , 0000BFH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 18. FLASH Crossing of first word boundary in burst read mode.

38

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

Case4 : Start from "4N+3" address group

5 cycle for initial access shown.(66MHz case)

Programmable wait state function is set to 01h (Wait States 3)

Address/

Data Bus

Valid Address

3F

40

41

42

43

CLK

AVD

3F

40

41

42

43

44

Additional 3 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00003FH , 00007FH , 0000BFH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 19. Crossing of first word boundary in burst read mode.

39

Revision 1.2

September, 2006

NOR FLASH MEMORY

K8S6415ET(B)B

PACKAGE DIMENSIONS

44-Ball Fine Ball Grid Array Package

#A1 Index Mark

7.50±0.10

A

0.08 MAX

0.50x9=4.50

7.50±0.10

(Datum A)

(Datum B)

10 9 8 7 6 5 4 3 2 1

B

#A1

A

B

C

D

0.50

0.20±0.05

0.90±0.10

1.00

3.25

44-

∅ 0.30±0.05

∅

0.2

M A B

BOTTOM VIEW

TOP VIEW

40

Revision 1.2

September, 2006


型号：	K8S6415ETB-FC7CT
厂家：	SAMSUNG
描述：	Flash, 4MX16, 70ns, PBGA44, 内存集成电路闪存
文件：	总40页 (文件大小：944K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K8S6415ETB-FC7CT [SAMSUNG]

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