K8S1115ETC-DC1ET_技术文档

Rev. 1.1, Sep. 2010

K8S1215ETC

K8S1215EBC

K8S1215EZC

512Mb C-die NOR FLASH

9x11, 64FBGA, 32M x16, Muxed Burst, Multi Bank SLC

1.7V ~ 1.95V

datasheet

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- 1 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Revision History

Revision No.

History

Draft Date

Mar. 31, 2010

May. 03, 2010

Sep. 06, 2010

Remark

Target

Final

Editor

0.0

1.0

1.1

- First version for target specification.

- Specification is finalized.

-

- Added "CLK "HIGH" should be prohibited in asynchronous read

mode start (From CE LOW)" in Asynchronous read operation.

Final

- 2 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

512M Bit (32M x16) Muxed Burst / Multi Bank SLC NOR Flash Memory

1.0 FEATURES

2.0 GENERAL DESCRIPTION

• Single Voltage, 1.7V to 1.95V for Read and Write operations

• Organization

The K8S(10/11/12/13)15E featuring single 1.8V power supply is a 512Mbit

Muxed Burst Multi Bank Flash Memory organized as 32Mx16. The memory

architecture of the device is designed to divide its memory arrays into

512blocks(Uniform block part)/515 blocks (Boot block part) with indepen-

dent hardware protection. This block architecture provides highly flexible

erase and program capability. The K8S(10/11/12/13)15E NOR Flash con-

sists of sixteen banks. This device is capable of reading data from one bank

while programming or erasing in the other bank. Regarding read access

time, the K8S10/1215E provides an 11ns burst access time and an 95ns

initial access time at 66MHz. At 83MHz, the K8S10/1215E provides an 9ns

burst access time and an 95ns initial access time. At 108MHz, the K8S11/

1315E provides an 7ns burst access time and an 95ns initial access time.

At 133MHz, the K8S11/1315E provides an 6ns burst access time and an

95ns initial access time. The device performs a program operation in units

of 16 bits (Word) and erases in units of a block. Single or multiple blocks

can be erased. The block erase operation is completed within typically

0.6sec. The device requires 25mA as program/erase current in the

extended temperature ranges.

- 33,554,432 x 16 bit (Word Mode Only)

• Multiplexed Data and Address for reduction of interconnections

- A/DQ0 ~ A/DQ15

• Read While Program/Erase Operation

• Multiple Bank Architecture

- 16 Banks (32Mb Partition)

• OTP Block : Extra 512-Word block

• Read Access Time (@ CL=30pF)

- Asynchronous Random Access Time : 100ns

- Synchronous Random Access Time : 95ns

- Burst Access Time :

11ns (66MHz) / 9ns (83MHz) / 7ns (108MHz) /6ns (133MHz)

• Burst Length :

- Continuous Linear Burst

- Linear Burst : 8-word & 16-word with Wrap

• Block Architecture

- Uniform block part (K8S(10/11/12/13)15EZC) :

Five hundred twelve 64Kword blocks

- Boot block part (K8S(10/11/12/13)15ET(B)C) :

Four 16Kword blocks and five hundred eleven 64Kword blocks (Bank 0

contains four 16 Kword blocks and thirty-one 64Kword blocks, Bank 1 ~

Bank 15 contain four hundred eighty 64Kword blocks)

The K8S(10/11/12/13)15E NOR Flash Memory is created by using Sam-

sung's advanced CMOS process technology.

3.0 PIN DESCRIPTION

• Reduce program time using the VPP

• Support 512-word Buffer Program

Pin Name

Pin Function

• Power Consumption (Typical value, CL=30pF)

- Synchronous Read Current : 35mA at 133MHz

- Program/Erase Current : 25mA

- Read While Program/Erase Current : 45mA

- Standby Mode/Auto Sleep Mode : 30uA

• Block Protection/Unprotection

A16 - A24

Address Inputs

A/DQ0 - A/DQ15

Multiplexed Address/Data input/output

Chip Enable

CE

OE

Output Enable

- Using the software command sequence

- Last two boot blocks are protected by WP=VIL

(Boot block part : K8S(10/11/12/13)15ET(B)C)

- Last one block (BA511) is protected by WP=VIL

(Uniform block part : K8S(10/11/12/13)15EZC)

- All blocks are protected by VPP=VIL

• Handshaking Feature

- Provides host system with minimum latency by monitoring RDY

• Erase Suspend/Resume

• Program Suspend/Resume

• Unlock Bypass Program/Erase

RESET

VPP

Hardware Reset

Accelerates Programming

Write Enable

WE

WP

Hardware Write Protection Input

Clock

CLK

RDY

AVD

DPD

Vcc

Ready Output

Address Valid Input

Deep Power Down

Power Supply

• Blank Check Feature

• Hardware Reset (RESET)

• Deep Power Down Mode

• Data Polling and Toggle Bits

VSS

Ground

- Provides a software method of detecting the status of program

or erase completion

• Endurance

- 100K Program/Erase cycles

• Extended Temperature : -25°C ~ 85°C

• Support Common Flash Memory Interface

• Low Vcc Write Inhibit

• Output Driver Control by Configuration Register

• Package : 64Ball FBGA type (9mm x 11mm), 0.5mm ball pitch

1.0mm(Max.)Thickness

- 5 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

4.0 64Ball FBGA TOP VIEW (BALL DOWN)

1

2

3

4

5

6

7

8

9

10

A

B

C

DNU

VSS

A24

VCC

Vss

Vcc

DNU

RDY

Vcc

A21

A16

VSS

A20

CLK

AVD

VCC

A23

WE

VPP

WP

A19

A18

A17

CE

A22

Vss

RESET

D

E

F

Vss

A/DQ7

A/DQ6 A/DQ13 A/DQ12 A/DQ3

A/DQ2

A/DQ9

Vcc

A/DQ8

A/DQ1

DNU

OE

A/DQ15 A/DQ14

Vss

A/DQ5

Vcc

A/DQ4 A/DQ11 A/DQ10

A/DQ0

DNU

Vss

DPD

Vcc

DNU

- 6 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

5.0 FUNCTIONAL BLOCK DIAGRAM

Bank 0

Cell Array

Bank 0

Address

X

Dec

Vcc

Vss

Latch &

Control

Y Dec

Vpp

CLK

CE

Latch &

Control

Y Dec

Bank 1

Cell Array

OE

Bank 1

Address

X

I/O

Interface

&

Dec

WE

WP

Bank

RESET

RDY

Control

Bank 15

Cell Array

Bank 15

Address

X

AVD

Dec

DPD

Latch &

Control

Y Dec

A16~A24

Erase

A/DQ0~

A/DQ15

Control

High

Voltage

Gen.

Block

Inform

Program

Control

- 7 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

6.0 ORDERING INFORMATION

K8 S 12 15 E T C - S E 1F

Samsung

NOR Flash Memory

Access Time

1F : Refer to Table 1

Device Type

S : Multiplexed Burst

Operating Temperature Range

C : Commercial Temp. (0 °C to 70 °C)

E : Extended Temp. (-25 °C to 85 °C)

Density(*Note)

10 : 512Mbits for 66/83MHz(Sync MRS)

11 : 512Mbits for 108/133MHz(Sync MRS)

12 : 512Mbits for 66/83MHz(No option)

13 : 512Mbits for 108/133MHz(No option)

Package

S : FBGA (Lead Free,OSP)

F : FBGA

D : FBGA(Lead Free)

Version

B : 4th Generation

Organization

15 : x16 Organization

Block Architecture

T : Top Boot Block, B : Bottom Boot Block

Z : Uniform Block

Operating Voltage Range

E : 1.7 V to 1.95V

NOTE

Density : (1) 10 : 512Mb for 66/83Mhz with the Sync MRS option (Extended Configuration Register)

(2) 11 : 512Mb for 108/133Mhz with the Sync MRS option (Extended Configuration Register)

(3) 12 : 512Mb for 66/83Mhz with no option

(4) 13 : 512Mb for 108/133Mhz with no option

[Table 1] PRODUCT LINE-UP

K8S(10/11/12/13)15E

1C

1D

1E

1F

Mode

Speed Option

(66MHz)

(83MHz)

(108MHz)

(133MHz)

Max. Initial Access Time (tIAA, ns)

Max. Burst Access Time (tBA, ns)

Max. Access Time (tAA, ns)

95

11

95

9

95

7

95

6

Synchronous/Burst

Asynchronous

VCC=1.7V-

1.95V

100

15

100

15

100

15

100

15

Max. CE Access Time (tCE, ns)

Max. OE Access Time (tOE, ns)

[Table 2] PRODUCT Classification

Speed/Boot Option

Top

Bottom

Uniform

512Mb for 66/83MHz (Sync MRS option)

512Mb for 108/133MHz (Sync MRS option)

512Mb for 66/83MHz

K8S1015ETC

K8S1115ETC

K8S1215ETC

K8S1315ETC

K8S1015EBC

K8S1115EBC

K8S1215EBC

K8S1315EBC

K8S1015EZC

K8S1115EZC

K8S1215EZC

K8S1315EZC

512Mb for 108/133MHz

- 8 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

[Table 3] K8S(10/11/12/13)15E DEVICE BANK DIVISIONS

Bank 0 ~ Bank 15

Type

Block Sizes

512Mbit (Boot block part)

Four 16Kword blocks and five hundred eleven 64Kword blocks

512Mbit (Uniform block part)

Five hundred twelve 64Kword blocks

[Table 4] K8S(10/11/12/13)15EZC DEVICE BANK DIVISIONS (Uniform block)

Bank

Bank size

Quantity of Blocks

Block Size

0

32Mb

32

64 Kwords

1

2

32Mb

32

64 Kwords

3

4

5

6

7

8

9

10

11

12

13

14

15

[Table 5] K8S(10/11/12/13)15ETC DEVICE BANK DIVISIONS (Top Boot block)

Bank

Bank size

Quantity of Blocks

Block Size

16 Kwords

64 Kwords

4

0

32Mb

31

32

1

2

32Mb

3

4

5

6

7

8

9

10

11

12

13

14

15

- 9 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

[Table 6] K8S(10/11/12/13)15EBC DEVICE BANK DIVISIONS (Bottom Boot block)

Bank

Bank size

Quantity of Blocks

Block Size

15

32Mb

32

64 Kwords

14

13

12

11

10

9

32Mb

32

31

4

64 Kwords

16 Kwords

8

7

6

5

4

3

2

1

0

32Mb

- 10 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

7.0 PRODUCT INTRODUCTION

The K8S(10/11/12/13)15E is an 512Mbit (536,870,912 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operat-

ing within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program

EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the

device adapts a block memory architecture that divides its memory array into 512 blocks (64-Kword x 512 blocks, Uniform block part) / 515 blocks (16-

Kword x 4 + 64-Kword x 511, Boot block part). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased

when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 512 / 515 memory

blocks can be hardware protected. Regarding read access time, at 66MHz, the K8S10/1215E provides a burst access of 11ns with initial access times of

95ns at 30pF. At 83MHz, the K8S10/1215E provides a burst access of 9ns with initial access times of 95ns at 30pF. At 108MHz, the K8S11/1315E pro-

vides a burst access of 7ns with initial access times of 95ns at 30pF. At 133MHz, the K8S11/1315E provides a burst access of 6ns with initial access times

of 95ns at 30pF. The command set of K8S(10/11/12/13)15E is compatible with standard Flash devices. The device uses Chip Enable (CE), Write Enable

(WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For burst operations, the device additionally

requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes. The command codes to be combined with

addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an inter-

nal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the pro-

gram and erase operations. The K8S(10/11/12/13)15E is implemented with Internal Program/Erase Routines to execute the program/erase operations.

The Internal Program/Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and

verifies data at specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then executes

the erase operation. The K8S(10/11/12/13)15E has means to indicate the status of completion of program/erase operations. The status can be indicated

via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The

device requires only 35mA as burst and asynchronous mode read current and 25mA for Buffer program/erase operations.

[Table 7] Device Bus Operations

Operation

CE

OE

WE

A16-24

A/DQ0-15

RESET

CLK

AVD

Asynchronous Read Operation

L

H

Add In

Add In/DOUT

H

L

Write

L

H

X

L

H

X

H

L

X

H

X

H

Add In

Add In / DIN

High-Z

H

L

X

Standby

X

Hardware Reset

Load Initial Burst Address

X

Add In

X

High-Z

Add In

H

L

Burst

DOUT

Burst Read Operation

L

H

X

Terminate Burst Read Cycle

H

X

L

X

H

X

High-Z

Add In

X

Terminate Burst Read Cycle via RESET

X

Terminate Current Burst Read Cycle and Start

New Burst Read Cycle

Add In

H

NOTE : L=VIL (Low), H=VIH (High), X=Don’t Care.

- 11 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

8.0 COMMAND DEFINITIONS

The K8S(10/11/12/13)15E operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select

a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information

which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences

are stated in Table 8.

[Table 8] Command Sequences

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle

4th Cycle

5th Cycle 6th Cycle

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

D a t a

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

R A

RD

Asynchronous Read

1

XXXH

F0H

Reset^5),20)

1

4

3

2

6

1

3

1

4

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X00H

ECH

Autoselect

Manufacturer ID⁶⁾

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X01H

NOTE6

(BA)X02H

00H/01H

(DA)X03H

0 H / 1 H

Autoselect

Device ID⁶⁾

555H

AAH

2AAH

55H

(BA)555H

90H

Autoselect

Block Protection Verify⁷⁾

555H

A A H

2AAH

5 5 H

(DA)555H

9 0 H

Autoselect

Handshaking ^{6), 8)}

555H

AAH

2AAH

55H

555H

PA

Program

A0H

PD

555H

AAH

2AAH

55H

555H

Unlock Bypass

20H

XXX

PA

Unlock Bypass Program ⁹⁾

Unlock Bypass Block Erase⁹⁾

Unlock Bypass Chip Erase⁹⁾

Unlock Bypass Reset

Chip Erase

A0H

PD

XXX

BA

80H

30H

XXXH

80H

XXXH

10H

XXXH

90H

XXXH

00H

555H

AAH

2AAH

55H

555H

80H

555H

AAH

555H

AAH

2AAH

55H

555H

10H

BA

555H

AAH

2AAH

55H

555H

80H

2AAH

55H

Block Erase

30H

(DA)XXXH

B0H

Erase Suspend ¹⁰⁾

Erase Resume¹¹⁾

(DA)XXXH

30H

(DA)XXXH

B0H

Program Suspend ¹²⁾

Program Resume ¹¹⁾

Block Protection/Unprotection ¹³⁾

CFI Query ¹⁴⁾

(DA)XXXH

30H

XXX

60H

ABP

60H

(DA)X55H

98H

555H

AAH

2AAH

55H

BA

Blank check

BCH

D0H

- 12 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle

5th Cycle 6th Cycle

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

555H

AAH

BA

2AAH

55H

BA

PA

WBL

PD

Write to Buffer ¹⁵⁾

3

25H

WC

PD

Program buffer to Flash ¹⁵⁾

1

3

4

29H

555H

AAH

555H

AAH

555H

AAH

555H

AAH

555H

AAH

2AAH

55H

XXX

F0H

Write to Buffer Abort Reset ^16),20)

Set Burst Mode Configuration Register ^17),18)

Set Extended Configuration Register ^17),19)

Enter OTP Block Region

2AAH

55H

NOTE 18

C0H

2AAH

55H

NOTE 19

C5H

2AAH

55H

XXX

70H

2AAH

55H

555H

75H

XXX

00H

Exit OTP Block Region

NOTE :

1) RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data, BA : Block Address (A24 ~ A14), DA : Bank Address (A24 ~ A21)

ABP : Address of the block to be protected or unprotected, DI :Die revision ID, CR : Configuration Register Setting,

WBL : Write Buffer Location, WC : Word Count

2) The 4th cycle data of autoselect mode and RD are output data. The others are input data.

3) Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WC and Device ID.

4) Unless otherwise noted, address bits A24–A11 are don’t cares.

5) The reset command is required to return to read mode.

If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode.

If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode.

If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that

bank was in erase suspend mode.

6) The 3rd and 4th cycle bank address of autoselect mode must be same.

Device ID Data : Top(3010H), Bottom(3011H), Uniform(3012H)

7) Normal Block Protection Verify : 00H for an unprotected block and 01H for a protected block.

OTP Block Protect verify (with OTP Block Address after Entering OTP Block) : 00H for unlocked, and 01H for locked.

8) 0H for handshaking, 1H for non-handshaking

9) The unlock bypass command sequence is required prior to this command sequence.

10) The system may read and program in non-erasing blocks when in the erase suspend mode.

The system may enter the autoselect mode when in the erase suspend mode.

The erase suspend command is valid only during a block erase operation, and requires the bank address.

11) The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.

12) This mode is used only to enable Data Read by suspending the Program operation.

13) Set ABP (Address of the block to be protected or unprotected) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH

and A0 = VIL for protected.

14) Command is valid when the device is in Read mode or Autoselect mode.

15) For Buffer Program, Firstly Enter "Write to Buffer" Command sequence and then Enter Block Address and Word Count which is the number of word

data will be programmed. Word Count is smaller than the number of data wanted to program by one, Example if 15 words are wanted to program

then WC (Word Count) is 14. After Entering Command, Enter PA/PD’s (Program Addresses/ Program Data). Finally Enter "Program buffer to Flash"

Command sequence, This starts a buffer program operation. This Device supports 512-word Buffer Program.

There is some caution points.

- The number of PA/PD’s which are entered must be same to WC+1

- PA’s which are entered must be same A24~A9 address bits because Buffer Address is A24~A9 address and decided by PA entered firstly.

- If PA which are entered isn’t same Buffer Address, then PA/PD which is entered may be ignored and this buffer programming operation is aborted.

To return to normal operation, hardware reset or "Write to Buffer Abort Reset" command is issued.

- Overwrite for program buffer is also prohibited.

16) Command sequence resets device for next command after aborted write-to-buffer operation.

17) See "Set Burst Mode Configuration Register" for details.

18) On the third cycle, the data should be "C0h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched.

19) On the third cycle, the data should be "C5h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched.

20) After software reset and write to buffer abort reset command, min. 5us recovery time is needed for normal read mode.

- 13 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

9.0 DEVICE OPERATION

The device has inputs/outputs that accept both address and data information. To write a command or command sequence (which includes programming

data to the device and erasing blocks of memory), the system must drive CLK, AVD and CE to VIL and OE to VIH when providing an address to the device,

and drive CLK, WE and CE to VIL and OE to VIH when writing commands or data.

The device provides the unlock bypass mode to save its program time for program operation. Unlike the standard program command sequence which is

comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the

entire device can be erased. Table 17 indicates the address space that each block occupies. The device’s address space is divided into sixteen banks. A

“bank address” is the address bits required to uniquely select a bank. Similarly, a “block address” is the address bits required to uniquely select a block.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specifi-

cation tables and timing diagrams for write operations.

9.1 Read Mode

The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in asynchronous mode.

After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset command is required to return a bank to the read

(or erase-suspend-read) mode if DQ5 goes high during an active program/erase operation, or if the bank is in the autoselect mode.

(1) K8S1015ET(B)(Z)C : 66/83Mhz with the Sync MRS option (Extended Configuration Register)

(2) K8S1115ET(B)(Z)C : 108/133Mhz with the Sync MRS option (Extended Configuration Register)

The synchronous (burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register

Setting to A13=0, A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK.

(3) K8S1215ET(B)(Z)C : 66/83Mhz with no option

(4) K8S1315ET(B)(Z)C : 108/133Mhz with no option

The synchronous (burst) mode will automatically start on the rising edge of the CLK input while AVD is held low. If several CLKs exist in AVD

low, the last rising edge is valid CLK.

9.1.1. Asynchronous Read Mode

For the asynchronous read mode a valid address should be asserted on A/DQ0-A/DQ15 and A16-A24, while driving CLK and AVD and CE to VIL. WE and

OE should remain at VIH. Note that CLK must remain low for asynchronous read mode. The address is latched at the rising edge of AVD, and then the

system can drive OE to VIL. The data will appear on A/DQ0-A/DQ15. Since the memory array is divided into sixteen banks, each bank remains enabled

for read access until the command register contents are altered.

Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time (tCE) is the delay from the falling

edge of CE to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE to valid data at the output. The asyn-

chronous access time is measured from a valid address, falling edge of AVD or falling edge of CE whichever occurs last. To prevent the memory content

from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset.

9.1.2. Synchronous (Burst) Read Mode

The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the system should

determine how many clock cycles are desired for the initial word (tIAA) of each burst access and what mode of burst operation is desired using

"Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be

read by synchronous read mode with a bank address which is programming or erasing. This status data by synchronous read mode can be

output and sustained until the system asserts CE high or RESET low or AVD low in conjunction with a new address. To initiate the synchro-

nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the pro

gram or erase operation.

9.1.2.1 . Continuous Linear Burst Read

(1) K8S1015ET(B)(Z)C : 66/83Mhz with the Sync MRS option (Extended Configuration Register)

(2) K8S1115ET(B)(Z)C : 108/133Mhz with the Sync MRS option (Extended Configuration Register)

The synchronous (burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register

Setting to A13=0, A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK.

(3) K8S1215ET(B)(Z)C : 66/83Mhz with no option

(4) K8S1315ET(B)(Z)C : 108/133Mhz with no option

The synchronous (burst) mode will automatically start on the rising edge of the CLK input while AVD is held low. If several CLKs exist in AVD

low, the last rising edge is valid CLK.

The initial word is output tIAA after the rising edge of the last CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock

cycle, which automatically increments the internal address counter. Note that the device has internal address boundary that occurs every 16 words. When

the device is crossing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of additional

clock cycle can vary from zero to thirteen cycles, and the exact number of additional clock cycle depends on not olny the starting address of burst read but

also programmable wait state setting. The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential

burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the system asserts CE high or RESET

low or AVD low in conjunction with a new address.(See Table 7.) The reset command does not terminate the burst read operation. When it accesses the

bank is programming or erasing, continuous burst read mode will output status data. And status data will be sustained until the system asserts CE high or

RESET low or AVD low in conjunction with a new address. Note that at least 10ns is needed to start next burst read operation from terminating pre-

vious burst read operation in the case of asserting CE high.

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datasheet NOR FLASH MEMORY

8-, 16-Word Linear Burst Read

As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap mode, in which a fixed number of words are read from consecutive

addresses. In these modes, the addresses for burst read are determined by the group within which the starting address falls. The groups are sized

according to the number of words read in a single burst sequence for a given mode.(See Table. 9)

[Table 9] Burst Address Groups (Wrap mode only)

Burst Mode

8 word

Group Size

8 words

Group Address Ranges

0-7h, 8-Fh, 10-17h, ....

0-Fh, 10-1Fh, 20-2Fh, ....

16 word

16 words

As an example: In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst

sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the

selected group. In a similar manner, 16-word wrap mode begins its burst sequence on the starting address written to the device, and then wrap back to

the first address in the selected address group.

9.2 Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven from low to high for

burst read mode. Upon power up, the number of total initial access cycles defaults to fourteen.

9.3 Handshaking

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready

to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configuration.(See "Set Burst Mode

Configuration Register" for details.) The rising edge of RDY after OE goes low indicates the initial word of valid burst data. (RDY can be low active by

Extended configuration register A11 settng : RDY low indicates data valid) Using the autoselect command sequence, the handshaking feature will be ver-

ified in the device.

9.4 Set Burst Mode Configuration Register

The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The burst mode

configuration register must be set before the device enters burst mode. The burst mode configuration register is loaded with a three-cycle command

sequences. On the third cycle, the data should be C0h, address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be

latched. The device returns to default setting after power up or hardware reset.

9.4.1. Programmable Wait State Configuration

This feature informs the device the number of clock cycles that must elapse after AVD is driven from low to high before data will be available. This value

is determined by the input frequency of the device. Address bits A14-A11 determine the setting. (See Configuration Register table 10.) The Programma-

ble wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst mode. Note that hardware reset will revert

the wait state to the default setting, that is 14 initial cycles.

9.4.2. Burst Read Mode Setting

The device supports three different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap.

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datasheet NOR FLASH MEMORY

9.4.3. RDY Configuration

By default, the RDY pin will be high whenever there is valid data on the output. (RDY can be low active by Extended configuration register A11 setting :

RDY low indicates data valid) The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting.

The RDY pin behaves same way in word boundary crossing case.

[Table 10] Burst Mode Configuration Register Table

Address Bit

A21

Function

Settings (Binary)

000 = setting 0

001 = setting 1

A20

010 = setting 2 (Reserve)

011 = setting 3 (Reserve)

100 = setting 4 (default)

101 = setting 5 (Reserve)

110 = setting 6 (Reserve)

111 = setting 7

Output Driver Control

A19

0 = RDY active with data (default)

1 = RDY active one clock cycle before data

A18

RDY Active

A17

A16

A15

A14

A13

A12

000 = Continuous (default)

001 = 8-word linear with wrap

010 = 16-word linear with wrap

011 ~ 111 = Reserve

Burst Read Mode

0000 = Data is valid on the 4th active CLK edge after AVD transition to VIH

0001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (40Mhz*)

0010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (50/54Mhz*)

0011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (60/66Mhz*)

0100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (70Mhz*)

0101 = Data is valid on the 9th active CLK edge after AVD transition to VIH (80/83Mhz*)

0110 = Data is valid on the 10th active CLK edge after AVD transition to VIH (90/100Mhz*)

0111 = Data is valid on the 11th active CLK edge after AVD transition to VIH (108/110Mhz*)

1000 = Data is valid on the 12th active CLK edge after AVD transition to VIH (120Mhz*)

1001 = Data is valid on the 13th active CLK edge after AVD transition to VIH (133Mhz*,default)

1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH

1011 = Data is valid on the 15th active CLK edge after AVD transition to VIH

1100 ~1111 = Reserve

Programmable Wait State

A11

NOTE :

Initial wait state should be set according to it’s clock frequency. Table 10 recommend the program wait state for each clock frequencies.

Not 100% tested

[Table 11] Extended Configuration Register Table

Address Bit

Function

Settings (Binary)

A13

00 = Asynchronous Read Mode (default)

01 = Synchronous Burst Read Mode

10 ~ 11 = Reserve

Read Mode

A12

A11

0 = RDY signal is active high (default)

1 = RDY signal is active low

RDY Polarity

NOTE :

Default mode is asynchronous read mode. (A13=0, A12=0) In this mode device is still in asynchronous read even if it is in CLK rising while AVD low condition.

To use synchronous read mode, user should set Extended Configuration Register (A13=0, A12=1). In this mode both of asynchronous and synchronous read mode is available.

The synchronous (burst) mode should be started on the last rising edge of the CLK input while AVD is held low after Extended Mode Register Setting to A13=0, A12=1.

[Table 12] Burst Address Sequences

Burst Address Sequence

8-word Burst

Start

Addr.

Continuous Burst

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

16-word Burst

0-1-2-3 ... -D-E-F

1-2-3-4 ... -E-F-0

2-3-4-5 ... -F-0-1

0

1

2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

Wrap

2-3-4-5-6-7-0-1

.

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datasheet NOR FLASH MEMORY

9.5 Output Driver Setting

The device supports four kinds of output driver setting for matching the system characteristics. The users can tune the output driver impedance of the

data and RDY outputs by address bits A21-A19. (See Configuration Register Table) Table 13 shows which output driver would be tuned and the strength

according to A21-A19. Upon power-up or reset, the register will revert to the default setting.

[Table 13] Output Driver setting Table

Address Bits

Value

000

001

010

011

100

101

110

111

Function

Driver Multiplier : 1/3

Driver Multiplier : 1/2

Reserve

A21-A19

Driver Multiplier : 1 (default)

Reserve

Driver Multiplier : 1.5

9.6 Autoselect Mode

By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read

mode. The system can then read autoselect codes from the internal register (which is separate from the memory array). Standard asynchronous read

cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition,

this mode allows the host system to verify the block protection or unprotection. Table 14 shows the address and data requirements. The autoselect com-

mand sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The

autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated

by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block

address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiat-

ing another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write

Reset command(F0H) into the command register.

[Table 14] Autoselect Mode Description

Description

Manufacturer ID

Address

(DA) + 00H

(DA) + 01H

(BA) + 02H

(DA) + 03H

Read Data

ECH

Device ID

Top boot(3010H), Bottom boot(3011H), Uniform block(3012H)

01H (protected), 00H (unprotected)

Block Protection/Unprotection

Handshaking

0H : handshaking, 1H : non-handshaking

9.7 Standby Mode

When the CE inputs is held at VCC ± 0.2V, and the system is not reading or writing, the device enters Stand-by mode to minimize the power consumption.

In this mode, the device outputs are placed in the high impedance state, independent of the OE input. When the device is in either of these standby

modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or pro-

gramming, the device draws active current until the operation is completed. ICC5 in the DC Characteristics table represents the standby current specifica-

tion.

9.8 Automatic Sleep Mode

The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses

remain stable for tAA+60ns, the device automatically enables this mode. The Automatic sleep mode is depends on the CE, WE and OE signal, so CE, WE

and OE signals are held at any state. In a sleep mode, output data is latched and always available to the system. When OE is active, the device provides

new data without wait time. Automatic sleep mode current is equal to standby mode current.

9.9 Output Disable Mode

When the OE input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.

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datasheet NOR FLASH MEMORY

9.10 Block Protection & Unprotection

To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are pro-

tected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are

don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0

whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can

continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command).

The device offers three types of data protection at the block level:

• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.

• When WP is at VIL, the two outermost blocks are protected.(Boot block part : K8S(10/11/12/13)15ET(B)C)

• When WP is at VIL, the last one block (BA511) is protected.(Uniform block part :K8S(10/11/12/13)15EZC)

• When VPP is at VIL, all blocks are protected.

Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.

9.11 Hardware Reset

The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low (VIL) for at least a period of tRP, the

device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET pulse.

The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated

once the device is ready to accept another command sequence. The RESET pin may be tied to the system reset pin. If a system reset occurs during the

Internal Program or Erase Routine, the device will be automatically reset to the asynchronous read mode; this will enable the systems microprocessor to

read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the device requires a time of tREADY (dur-

ing Internal Routines) before the device is ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset

operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC

Characteristics tables for RESET parameters and to Figure 12 for the timing diagram. When RESET is at logic high, the device is in standard operation.

9.12 Software Reset

The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in

Don’t Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an pro-

gram command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is

completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode. The reset command valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the

reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset

command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing

the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset com-

mand returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend)

9.13 Program

The K8S(10/11/12/13)15E can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program

Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third

cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location

are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. Dur-

ing the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written

to the device will be ignored.

9.14 Accelerated Program

The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible.

When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses

the higher voltage on the input to reduce the time required for program operations. In accelerated program mode, the system would use a two-cycle pro-

gram command sequence for only a word program. By removing VID returns the device to normal operation mode.

Note that Read While Accelerated Program (Erase) and Program suspend (Erase suspend) mode are not guaranteed.

• Program/Erase cycling must be limited below 100cycles for optimum performance.

• Ambient temperature requirements : T_A= 30°C±10°C

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datasheet NOR FLASH MEMORY

9.15 Write Buffer Programming

Write Buffer Programming allows the system write to a maximum of 512-word in one programming operation. This results in faster effective programming

time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is

followed by a third write cycle containing the Write Buffer Load command written at the block address in which programming will occur. The fourth cycle

writes the block address and the number of word locations, minus one, to be programmed. For example, if the system will program 19 unique address

locations, then 12h should be written to the device. This tells the device how many write buffer addresses will be loaded with data. The number of loca-

tions to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be pro-

grammed. The write-buffer-page is selected by address bits A24(max.) ~ A9 entered at fifth cycle. All subsequent address/ data pairs must fall

within the selected write-buffer-page, so that all subsequent addresses must have the same address bit A24(max.) ~ A9 as those entered at

fifth cycle. Write buffer locations may be loaded in any order.

Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" command at the block

address. Any other command address/data combination aborts the Write Buffer Programming operation. The device then begins programming. Data poll-

ing should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine

the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/

resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command.

Note also that an address location cannot be loaded more than once into the write-buffer-page.

The Write Buffer Programming Sequence can be aborted in the following ways:

• Loading a value that is greater than the buffer size(512-word) during then number of word locations to Program step.

(In case, WC > 1FFH @Table 8)

• The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@Table 8)

• Writing a Program address to have a different write-buffer-page with selected write-buffer-page

( Address bits A24(max) ~ A9 are different)

• Writing non-exact "Program Buffer to Flash" command

The abort condition is indicated by DQ1 = 1, DQ7 = DATA (for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-to-Buffer-Abort

Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of Write-to-Buffer-Abort Reset command

sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode.

And from the third cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Programming features in Unlock Bypass

mode. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the DQ7 and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1."

9.16 Accelerated Write Buffer Programming

The device provides accelerated Write Buffer Program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory

is possible. When VID is asserted on the Vpp input, the device temporarily unprotects any protected blocks, and uses the higher voltage on the input to

reduce the time required for program operations. In accelerated Write Buffer Program mode, the system must enter "Write to Buffer" and "Program Buffer

to Flash" command sequence to be same as them of normal Write Buffer Programming. Note that the third cycle of "Write to Buffer Abort Reset" com-

mand sequence is required in an accelerated mode.

Note that Read While Accelerated Write Buffer Program and Program suspend mode are not guaranteed.

• Program/Erase cycling must be limited below 100cycles for optimum performance.

• Ambient temperature requirements : T_A= 30°C±10°C

9.17 Chip Erase

To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the

command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip

erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The

automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns

to the read mode.

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Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

9.18 Block Erase

To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the

command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two

more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior

to erasing it. The block address is latched on the rising edge of AVD, while the Block Erase command is latched on the rising edge of WE. Multiple blocks

can be erased sequentially by writing the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block

Erase command (30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle (block address and 30H) is

needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase com-

mand writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us

"time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of

"time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After

the 50us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and

command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend com-

mand during Block Erase operation.

The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device automatically enters the

Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. By

removing VID returns the device to normal operation mode.

9.19 Blank check

The Blank Check operation is used one block at a time to check whether a block is completely erased or not. It is not available during Program Suspend

or Erase Suspend. For using Blank Check, first issue the command which has 4-cycle and check the status. The Bank addressed in Blank Check Com-

mand is automatically changed to Status check mode, until Reset command (XXXH / F0H) is issued.

During a blank check operation, DQ status flags indicates a busy status (DQ6, DQ2 = toggle / DQ5=0). Upon completion, the DQ status flags indicates

that Blank check operation is passed (DQ6 = toggle, DQ5=1 and DQ1=1). That means the block is completely erased.

In Blank check operation failure case, the DQ status flags indicates DQ6 = toggle, DQ5=1 and DQ1=0. The block is not completely erased.

No other commands will be recognized except status read operation during Blank Check operation. Blank Check cannot be suspended. After the comple-

tion of the Blank Check operation, any valid command can be issued after Reset command (XXXH / F0H).

NOTE that, unexpected power off or hardware reset during internal write routine may make blank check operation unavailable. And Blank check cannot

be used in OTP block area.

9.20 Unlock Bypass

The K8S(10/11/12/13)15E provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase, chip erase, write

to buffer and write to buffer abort reset operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass

command sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four bus cycles, the unlock

bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command

sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H).

Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program com-

mand sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data.

This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command

sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase com-

mand(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command

sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles.

The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode.

To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass mode.

Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just remove the

asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always connected with VIH, VIL or VID.).

9.21 Erase Suspend / Resume

The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is possible to protect or

unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid during the Block Erase operation

including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running.

When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 30us(recovery time) to suspend the

erase operation. Therefore system must wait for 30us(recovery time) to read the data from the bank which include the block being erased. Otherwise,

system can read the data immediately from a bank which don’t include the block being erased without recovery time (max. 30us) after Erase Suspend

command. And, after the maximum 30us recovery time, the device is available for programming data in a block that is not being erased. But, when the

Erase Suspend command is written during the block erase time window (50us), the device terminates the block erase time window and suspends the

erase operation in about 2us. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the

Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the

addresses are in the bank address which is operating in Erase Suspend or Erase Resume. While erase can be suspended and resumed multiple

times, a minimum 30us is required from resume to the next suspend.

- 20 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

9.22 Program Suspend / Resume

The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program operation. The device

accepts a Program Suspend command in Program mode (including Program operations performed during Erase Suspend) but other commands are

ignored. After input of the Program Suspend command, 10us is needed to enter the Program Suspend Read mode. Therefore system must wait for

10us(recovery time) to read the data from the bank which include the block being programmed. Otherwise, system can read the data immediately from a

bank which don't include block being programmed without recovery time(max.10us) after Program Suspend command. Like an Erase Suspend mode, the

device can be returned to Program mode by using a Program Resume command. While program can be suspended and resumed multiple times, a

minimum 30us is required from resume to the next suspend.

In the program suspend mode, protect/unprotect command is prohibited.

9.23 Read While Write Operation

The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write operation. An erase operation

may also be suspended to read from or program to another location within the same bank (except the block being erased). The Read While Write opera-

tion is prohibited during the chip erase operation. Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero

latency. Refer to the DC Characteristics table for read-while-write current specifications.

9.24 OTP Block Region

The OTP Block feature provides a 512-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN).

The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to utilize the that block in any manner they choose. The cus-

tomer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked state or a "1" for Locked state.

The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 8). After the

system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (1FFFE00h~1FFFFFFh : Top Boot

block device/Uniform block device, 0000000h-00001FFh : Bottom Boot block device) normally and may check the Protection Verify Bit (DQ0) by using the

"Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit

OTP Block" Command sequence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device

reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is

enabled.

Customer Lockable

In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and

Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP

Block" Command sequence, and then the "Block Protection" Command sequence (Table 8) with an OTP Block address. The Locking operation has to be

above 100us. "Exit OTP Block" command sequence and Hardware reset makes locking operation finished and then exiting from OTP Block after 30us.

The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the

bits in the OTP Block space can be modified in any way.

Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operations. After

entering OTP block, program/erase operation on main blocks is prohibited. Enter OTP block command is not allowed while other operation is

executing.

9.25 Low VCC Write Inhibit

To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc < VLKO (Lock-Out

Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode.Sub-

sequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to

prevent unintentional writes when Vcc is above VLKO.

9.26 Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle.

9.27 Logical Inhibit

Write cycles are inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a

logical one.

- 21 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

10.0 FLASH MEMORY STATUS FLAGS

The K8S(10/11/12/13)15E has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must

include bank address being executed internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins. The

status data can be read during burst read mode by using AVD signal with a bank address. That means status read is supported in synchronous mode. If

status read is performed, the data provided in the burst read is identical to the data in the initial access. To initiate the synchronous read again, a new

address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation. The corre-

sponding DQ pins are DQ7, DQ6, DQ5, DQ3, DQ2 and DQ1.

[Table 15] Hardware Sequence Flags

Status

DQ7

0

DQ6

DQ5

DQ3

DQ2

1

DQ1

Programming

Toggle

0

1

0

Block Erase or Chip Erase or Blank check

Toggle

Erase Suspended

Toggle¹⁾

Data

1

Erase Suspend Read

Block

1

Data

Toggle

1

0

Data

0

Data

0

Data

0

Non-Erase Suspended

Erase Suspend Read

Block

Data

DQ7

Data

In Progress

Erase Suspend

Program

Non-Erase Suspended

Block

Program Suspended

Block

Toggle¹⁾

Data

Program Suspend Read

0

Non- program

Suspended Block

Program Suspend Read

Programming

Data

DQ7

0

Toggle

1

0

1

0

1

0

No Toggle

(NOTE 2)

No Toggle

0

1

0

1

Block Erase or Chip Erase or Blank check Fail

Blank check Pass

Exceeded

Time Limits

0

Erase Suspend Program

BUSY state

DQ7

Write-to-

Buffer³⁾

Exceeded Timing Limits

ABORT State

NOTE :

1) DQ2 will toggle when the device performs successive read operations from the erase/program suspended block.

2) If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.

3) Note that DQ7 during Write-to-Buffer-Programming indicates the data-bar for DQ7 data for the last loaded write-buffer address location.

DQ7 : Data Polling

When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the

Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts

to read the block being erased or bank contains the block, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can be

detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the sys-

tem tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erase-sus-

pended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected

block, DQ7 outputs complements the data for approximately 2us and the device then returns to the Read Mode without changing data in the block. If an

attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without

erasing the data in the block.

DQ6 : Toggle Bit

Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling

DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that

belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or pro-

grammed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 2us

and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for

approximately 100μs and the device then returns to the Read Mode without erasing the data in the block. #OE or #CE should be toggled in each toggle bit

status read.

- 22 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

DQ5 : Exceed Timing Limits

If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. Also the result of blank check

can be checked by DQ5=1.

DQ3 : Block Erase Timer

The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50μs of the block erase time window expires. In this

case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is

completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can

be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase com-

mand.

DQ2 : Toggle Bit 2

The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes

the Internal Erase Routine, DQ2 toggles if the bank including an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Lim-

its, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only

if an address in the erasing or programming block is read. If a non-erasing or non-programmed block address is read during the Erase/Program Suspend

mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend

mode. #OE or #CE should be toggled in each toggle bit status read.

DQ1 : Buffer Program Abort Indicator

DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-

Abort-Reset command sequence to return the device to reading array data. Also DQ1 will go High if the blank check is passed. DQ1 will go low in the

blank check failure.

RDY: Ready

Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low state, data is not valid

at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.

Start

Read(DQ0~DQ7)

Valid Address

Start

Read(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

DQ6 = Toggle ?

Yes

DQ7 = Data ?

No

Yes

No

DQ5 = 1 ?

Yes

DQ5 = 1 ?

Yes

Read twice(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

No

Yes

DQ6 = Toggle ?

DQ7 = Data ?

Yes

Fail

No

Fail

Pass

Figure 1. Data Polling Algorithms

Figure 2. Toggle Bit Algorithms

- 23 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

11.0 Deep Power Down

In order to reduce the power consumption of the device, it shall a deep power down mode implemented on a separate pin. The deep power down mode is

active when the deep power down signal is activated, high state. In deep power down the device shall turn off all circuitry in order to reach a power con-

sumption of 2uA(typ). The device shall exit the deep power down mode within 75us after that the deep power down signal has been de-activated, set to

low. In deep power down the state of the device chip select shall have no impact on the device power consumption. All programming capabilities of the

device are inhibited.

At the power up, the device shall accept any order of activation of the reset and deep power down signal. The device shall respond within the specified

time for the signal that was deactivated/activated latest. The deep power down mode is activated when DPD pin high state only. If DPD is asserted during

a program or erase operation, the device requires a time of tDP(During Internal Routines) before the device is ready to enter DPD mode.

Note that user never float the DPD that is, DPD is always connected with VIH, VIL.

Deep Power Down (DPD)

All Speed Options

Parameter

Symbol

Unit

Min

Typ

Max

DPD Pin High (NOT During Internal Routines)

to DPD Mode*

tDP

100

-

ns

DPD Pin High (During Internal Routines)

to DPD Mode*

μs

tDP

20

75

-

DPD Low Time Before Read*

twkup

μs

NOTE : Not 100% tested.

SWITCHING WAVEFORMS

CE, OE

twkup

DPD

tDP

DPD Timings NOT during Internal Routines

CE, OE

DPD

twkup

tDP

DPD Timings during Internal Routines

Figure 3. DPD Timings

- 24 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

12.0 Common Flash Memory Interface

Common Flash Memory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such

as memory size and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable

flash writes, block erases, and control the flash component.

When the system writes the CFI command(98H) to address 55H, the device enters the CFI mode. And then if the system writes the address shown in

Table 16, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the

upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command.

[Table 16] Common Flash Memory Interface Code

Description

Addresses

(Word Mode)

Data

10H

11H

12H

0051H

0052H

0059H

Query Unique ASCII string "QRY"

13H

14H

0002H

0000H

Primary OEM Command Set

15H

16H

0040H

0000H

Address for Primary Extended Table

17H

18H

0000H

Alternate OEM Command Set (00h = none exists)

19H

1AH

0000H

Address for Alternate OEM Extended Table (00h = none exists)

Vcc Min. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

1BH

1CH

1DH

1EH

0017H

0019H

0085H

0095H

Vcc Max. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

Vpp (Acceleration Program) Supply Minimum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

Vpp (Acceleration Program) Supply Maximum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

Typical timeout per single word write 2^Nus

1FH

20H

21H

22H

23H

24H

25H

26H

27H

0007H

000AH

0013H

0003H

001AH

Typical timeout for Max buffer write 2^Nus(00H = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms(00H = not supported)

Max. timeout for word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical(00H = not supported)

Device Size = 2^Nbyte

28H

29H

0000H

Flash Device Interface description

2AH

2BH

000AH

0000H

Max. number of byte in multi-byte write = 2^N

Number of Erase Block Regions within device¹⁾

2CH

0002H

2DH

2EH

2FH

30H

0003H

0000H

0080H

0000H

Erase Block Region 1 Information (Boot block part : (K8S(10/11/12/13)ET(B)C) )

Bits 0~15: y+1=block number

Bits 16~31: block size= z x 256bytes

- 25 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Addresses

Data

Description

(Word Mode)

2DH

2EH

2FH

30H

00FFH

0001H

0000H

0002H

Erase Block Region 1 Information (Uniform block part : (K8S(10/11/12/13)EZC))

Bits 0~15: y+1=block number

Bits 16~31: block size= z x 256bytes

31H

32H

33H

34H

00FEH

0001H

0000H

0002H

Erase Block Region 2 Information (Boot block part : (K8S(10/11/12/13)ET(B)C))

Erase Block Region 2 Information (Uniform block part : (K8S(10/11/12/13)EZC))

31H

32H

33H

34H

0000H

35H

36H

37H

38H

0000H

Erase Block Region 3 Information

39H

3AH

3BH

3CH

0000H

Erase Block Region 4 Information

Query-unique ASCII string "PRI"

40H

41H

42H

0050H

0052H

0049H

Major version number, ASCII

Minor version number, ASCII

43H

44H

0031H

Address Sensitive Unlock(Bits 1-0)

0 = Required, 1= Not Required

Silcon Revision Number(Bits 7-2)

45H

0000H

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46H

47H

0002H

0001H

Block Protect

00 = Not Supported, 01 = Supported

Block Temporary Unprotect 00 = Not Supported, 01 = Supported

Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported

48H

49H

0000H

0001H

Simultaneous Operation

00 = Not Supported, 01 = Supported

4AH

4BH

4CH

0001H

0000H

Burst Mode Type 00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 03 = 16 Word Page

Top/Bottom Boot/Uniform Block Flag

02H = Bottom Boot Device, 03H = Top Boot Device, 04H = Uniform Device

4DH

0003H

Max. Operating Clock Frequency (MHz) ²⁾

4EH

4FH

0085H

0000H

RWW(Read While Write) Functionality Restriction (00H = non exists, 01H = exists)

Handshaking

00 = Not Supported at both mode, 01 = Supported at Sync. Mode

10 = Supported at Async. Mode, 11 = Supported at both Mode

50H

0001H

NOTE :

1) Uniform block part (K8S(10/11/12/13)EZC) : Data is 01H

Boot block part (K8S(10/11/12/13)ET(B)C) : Data is 02H

2) Max. Operating Clock Frequency : Data is 85H in 108/133Mhz part (K8S(11/13)15E(T/B/Z)C), Data is 53H in 66/83Mhz part (K8S(10/12)15E(T/B/Z)C)

- 26 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

13.0 ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

-0.5 to +2.5

-0.5 to +9.5

-0.5 to +2.5

-65 to +100

5

Unit

Vcc

VPP

Vcc

VIN

Voltage on any pin relative to VSS

V

All Other Pins

Storage Temperature

Tstg

°C

mA

°C

Short Circuit Output Current

IOS

TA (Commercial Temp.)

TA (Extended Temp.)

0 to +70

Operating Temperature

-25 to + 85

°C

NOTE :

1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns.

Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.

2) Minimum DC input voltage is -0.5V on V^PP. During transitions, this level may fall to -2.0V for periods <20ns.

Maximum DC input voltage is +9.5V on V^PPwhich, during transitions, may overshoot to +12.0V for periods <20ns.

3) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

- 27 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

14.0 RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

1.7

0

Typ.

1.8

0

Max

1.95

0

Unit

V

Supply Voltage

VCC

Supply Voltage

VSS

V

NOTE : Voltage reference to GND

1) Data retention is not guaranteed on Operating condition Extended temperature(-25’C~85’C) over.

15.0 DC CHARACTERISTICS

Parameter

Symbol

Test Conditions

Min

- 1.0

-

Typ

Max

+ 1.0

35

Unit

μA

I_LI

V_IN=V_SSto V_CC, V_CC=V_CCmax

Input Leakage Current

-

V_CC=V_CCmax , V_PP=V_CCmax

μA

I_LIP

VPP Leakage Current

V

_CC=V_CCmax , V_PP=9.5V

-

μA

I_LO

V_OUT=V_SSto V_CC, V_CC=V_CCmax, OE=V_IH

CE=V_IL, OE=V_IH(@133MHz)

Output Leakage Current

Active Burst Read Current

- 1.0

-

+ 1.0

55

μA

I_CCB1

35

mA

Active Asynchronous

Read Current

I_CC1

CE=V_IL, OE=V_IH

10MHz

-

35

55

mA

Active Write Current ²⁾

I_CC2

I_CC3

I_CC4

I_CC5

I_CC6

CE=V_IL, OE=V_IH, WE=V_IL, V_PP=V_IH

CE=V_IL, OE=V_IH

-

25

45

20

30

40

70

mA

μA

Read While Write Current

Accelerated Program Current

Standby Current

CE=V_IL, OE=V_IH, V_PP=9.5V

30

CE= RESET=VCC ± 0.2V

RESET = V_SS± 0.2V

120

Standby Current During Reset

μA

CE=V_SS± 0.2V, Other Pins=V_ILor V_IH

V_IL= V_SS± 0.2V, V_IH= V_CC± 0.2V

Automatic Sleep Mode ³⁾

I_CC7

-

30

120

μA

I_CC8

V_IL

Deep Power Down Mode

Input Low Voltage

-

2

30

0.4

μA

V

-0.5

-

V_IH

V_CC-0.4

V_CC+0.4

Input High Voltage

-

V

V_OL

V_OH

V_ID

I_OL= 100 μA , V_CC=V_CCmin

I_OH= -100 μA , V_CC=V_CCmin

Output Low Voltage

-

0.1

-

V

V_CC-0.1

Output High Voltage

V

Voltage for Accelerated Program

Low VCC Lock-out Voltage

8.5

9.0

-

9.5

1.4

5

V

V_LKO

-

V

V_PP= 9.5V

0.8

-

mA

μA

I_vpp

Vpp current in program/erase

V

_PP= 1.95V

50

NOTE :

1) Maximum ICC specifications are tested with V

= V max.

CC

2) I

active while Internal Erase or Internal Program is in progress.

CC

3) Device enters automatic sleep mode when addresses are stable for t + 60ns.

AA

- 28 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

16.0 VCC POWER-UP

All Speed Options

Parameter

Symbol

Unit

Min

200

Max

t_VCS

t_RH

Vcc Setup Time

-

μs

Time between RESET (high) and CE (low)

NOTE : Not 100% tested.

ns

SWITCHING WAVEFORMS

tVCS

tVCCmin

Vcc/Vccq

VIH

RESET

CE

tRH

DPD

Low

Figure 4. Vcc Power-up Diagram

NOTE : DPD should be low during power-up sequence.

17.0 CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)

Item

Symbol

Test Condition

Min

Max

10

Unit

pF

C_IN

V_IN=0V

Input Capacitance

-

C_OUT

C_IN2

V_OUT=0V

V_IN=0V

Output Capacitance

10

pF

Control Pin Capacitance

10

pF

- 29 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

18.0 AC TEST CONDITION

Parameter

Value

Input Pulse Levels

0V to VCC

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

3ns(max)@66Mhz, 2.5ns(max)@83Mhz, 1.5ns(max)@108Mhz, 1ns(max)@133Mhz

VCC/2

CL = 30pF

3ns(max)

Address to Address Skew

Device

Under

Test

VCC

Input & Output

VCC/2

Test Point

* CL = 30pF including scope

0V

and Jig capacitance

Input Pulse and Test Point (including CLK characterization)

Output Load

19.0 AC CHARACTERISTICS

19.1 Synchronous/Burst Read

1C

1D

1E

1F

(66 MHz)

(83 MHz)

(108 MHz)

(133 MHz)

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

95

Min

Max

95

t_IAA

t_BA

Initial Access Time

-

95

11

-

95

9

-

ns

Burst Access Time Valid Clock to Output Delay

AVD Setup Time to CLK

AVD Hold Time from CLK

AVD High to OE Low

-

7

-

6

-

t_AVDS

t_AVDH

t_AVDO

t_ACS

t_ACH

t_BDH

t_OER

t_CEZ

5

4

3.5

2.5

2

-

2

-

2

-

2

-

0

-

0

-

0

-

0

-

Address Setup Time to CLK

Address Hold Time from CLK

Data Hold Time from Next Clock Cycle

Output Enable to RDY valid

CE Disable to High Z

5

-

4

-

3.5

-

2.5

-

6

-

5

-

2

-

2

-

3

-

3

-

2

-

2

-

11

9

-

9

-

7

9

-

6

9

-

t_OEZ

t_CES

t_RDY

t_RDYA

t_RDYS

t_CLK

OE Disable to High Z

-

3.5

-

CE Setup Time to CLK

6

4.5

4

CE Enable to RDY active

CLK to RDY Setup Time

RDY Setup Time to CLK

CLK period

-

11

-

9

-

7

-

6

-

3

-

3

2

15.1

-

12.05

-

9.26

-

7.52

-

0.4x

t_CLK

0.6x

t_CLK

0.4x

t_CLK

0.6x

t_CLK

0.4x

t_CLK

0.6x

t_CLK

0.4x

t_CLK

0.6x

t_CLK

t_CLKH/L

CLK High or Low Time

CLK Fall or Rise Time

ns

t_CLKHCL

-

3

-

2.5

-

1.5

-

1

- 30 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

13 cycles for initial access shown.

CR setting : A14=1, A13=0, A12=0, A11=1

7.5ns typ(133MHz).

tCES

tCEZ

CE

1

2

3

4

5

11

12

13

CLK

tAVDS

tAVDO

tAVDH

AVD

tBDH

tACS

Aa

A16-A24

tBA

tACH

Aa

Hi-Z

A/DQ0:

A/DQ15

Da+n

tOEZ

tIAA

Da Da+1

tRDYS

Da+3

Da+4 Da+5

Da+6

Da+2

OE

tOER

tRDY

tRDYA

RDY

Hi-Z

Figure 5. Continuous Burst Mode Read (133 MHz)

NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

11 cycles for initial access shown.

CR setting : A14=0, A13=1, A12=1, A11=1

9.25ns typ(108MHz).

tCES

tCEZ

CE

11

1

2

3

4

9

10

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

Aa

A16-A24

tBA

tACH

Aa

A/DQ0:

A/DQ15

Hi-Z

Da

Da+2

Da+1

Da+3

Da+5 Da+6

Da+4

Da+n

tIAA

tOEZ

OE

tOER

tRDY

tRDYS

tRDYA

RDY

Hi-Z

Figure 6. Continuous Burst Mode Read (108 MHz)

NOTE: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

- 31 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

13 cycles for initial access shown.

CR setting : A14=1, A13=0, A12=0, A11=1

7.5ns typ(133MHz).

tCES

CE

1

2

3

4

11

12

13

CLK

tAVDS

tAVDO

tAVDH

AVD

tBDH

tACS

Aa

A16-A24

tBA

tACH

Aa

A/DQ0:

A/DQ15

tIAA

D1

D3

D5

D6

D0

D2

D4

D7

D0

OE

tOER

tRDY

tRDYS

tRDYA

RDY

Hi-Z

Figure 7. 8 word Linear Burst Mode with Wrap Around (133 MHz)

NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

13 cycles for initial access shown.

CR setting : A14=1, A13=0, A12=0, A11=1

7.5ns typ(133MHz).

tCES

CE

1

2

3

4

10

11

12

13

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

Aa

A16-A24

tBA

tACH

A/DQ0:

A/DQ15

Aa

tIAA

D1

D3

D5

D6

D0

D2

D4

D7

D0

OE

tOER

tRDY

tRDYS

tRDYA

RDY

Hi-Z

Figure 8. 8 word Linear Burst with RDY Set One Cycle Before Data (Wrap Around Mode, CR setting : A18=1)

NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

- 32 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

13 cycles for initial access shown.

CR setting : A14=1, A13=0, A12=0, A11=1

7.5ns typ(133MHz).

tCES

tCEZ

CE

1

2

3

4

5

11

12

13

CLK

tAVDS

tAVDO

AVD

tAVDH

tBDH

tACS

Aa

A16-A24

tBA

tACH

Hi-Z

A/DQ0:

A/DQ15

Aa

D6

tIAA

D7

D8

D10

D0

tOEZ

D9

D15

OE

tOER

tRDY

tRDYS

tRDYA

RDY

Hi-Z

Figure 9. 16 word Linear Burst Mode with Wrap Around (133Mhz)

NOTE: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

- 33 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

19.2 Asynchronous Read

All speed

Parameter

Symbol

Unit

Min

Max

t_CE

t_AA

Access Time from CE Low

-

100

ns

Asynchronous Access Time

100

t_AVDP

t_AAVDS

t_AAVDH

t_OE

AVD Low time

12

5

-

Address Setup Time to rising Edge of AVD

Address Hold Time from Rising Edge of AVD

Output Enable to Output Valid

2

-

0

15

-

ns

Read

Output Enable

Hold Time

t_OEH

t_OEZ

Toggle and Data Polling

10

-

Output Disable to High Z*

9

NOTE: Not 100% tested.

SWITCHING WAVEFORMS

Asynchronous Mode Read (tCE)

VIL

CLK

CE

OE

WE

tOE

tOEH

tCE

tOEZ

A/DQ0:

A/DQ15

VA

Valid RD

A16-A24

AVD

tAAVDS

tAAVDH

tAVDP

Hi-Z

RDY

Figure 10. Asynchronous Mode Read (tCE)

NOTE :

1) VA=Valid Read Address, RD=Read Data.

Asynchronous mode may not support read following four sequential invalid read condition within 200ns.

2) CLK "HIGH" should be prohibited in asynchronous read mode start (From CE LOW).

- 34 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Asynchronous Mode Read (tAA)

Case 1 : Valid Address Transition occurs before AVD is driven to Low

VIL

CLK

CE

tOE

OE

tOEH

WE

tOEZ

A/DQ0:

A/DQ15

VA

Valid RD

tAA

A16-A24

VA

tAAVDS

tAAVDH

AVD

RDY

tAVDP

Hi-Z

Case 2 : Valid Address Transition occurs after AVD is driven to Low

VIL

CLK

CE

tOE

OE

tOEH

WE

tOEZ

A/DQ0:

A/DQ15

VA

Valid RD

tAA

A16-A24

VA

tAAVDH

tAAVDS

AVD

RDY

tAVDP

Hi-Z

Figure 11. Asynchronous Mode Read (tAA)

NOTE :

1) VA=Valid Read Address, RD=Read Data.

2) Asynchronous mode may not support read following four sequential invalid read condition within 200ns.

3) CLK "HIGH" should be prohibited in asynchronous read mode start (From CE LOW).

- 35 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

19.3 Hardware Reset(RESET)

All Speed Options

Parameter

Symbol

Unit

Min

Max

RESET Pin Low(During Internal Routines)

to Read Mode*

t_Ready

-

20

μs

RESET Pin Low(NOT During Internal Routines)

to Read Mode*

-

500

ns

t_RP

t_RH

RESET Pulse Width

200

-

ns

Reset High Time Before Read*

NOTE : Not 100% tested.

SWITCHING WAVEFORMS

CE, OE

tRH

RESET

tRP

tReady

Reset Timings NOT during Internal Routines

CE, OE

RESET

tReady

tRP

Reset Timings during Internal Routines

Figure 12. Reset Timings

- 36 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

19.4 Erase/Program Operation

All speed options

Parameter

Symbol

Unit

Min

75

5

Typ

Max

WE Cycle Time¹⁾

t_WC

t_AS

-

ns

μs

sec

ms

ns

μs

Address Setup Time

Address Hold Time

AVD Low Time

-

t_AH

2

-

t_AVDP

t_DS

12

30

0

-

Data Setup Time

-

t_DH

Data Hold Time

-

t_GHWL

t_CS

Read Recovery Time Before Write

CE Setup Time

0

-

0

-

t_CH

CE Hold Time

0

-

t_WEA

WE High to AVD low

WE Pulse Width

30

45

0

-

t_WP

-

t_WPH

WE Pulse Width High

Latency Between Read and Write Operations

t_SR/W

t_PGM

-

Word Programming Operation ²⁾

Single word Buffer Program ²⁾

-

80

250

716.8

80

0.7

358.4

0.6

7

t_{PGM_BP}

t_ACCPGM

t_{ACCPGM_BP}

t_BERS

t_BLANK

t_VPP

-

512-word Buffer Program ⁴⁾

-

Accelerated Programming Operation ³⁾

Accelerated Single word Buffer Program ³⁾

-

Accelerated 512-word Buffer Program ⁴⁾

Block Erase Operation (64KW block)

Blank check Operation (64KW block)

VPP Rise and Fall Time

-

500

1

-

t_VPS

VPP Setup Time (During Accelerated Programming)

-

NOTE :

1) Not 100% tested.

2) Internal programming algorithm is optimized for Buffer Program, so Normal word programming or Single word Buffer Program use Buffer Program algorithm.

3) Internal programming algorithm for supporting Accelerated mode uses a method to double the number of words programmed simultaneously.

4) Typical 512-word Buffer Program time pays due regard to that Each program data pattern ("11", "10". "01", "00") has a same portion in 512-word Buffer.

- 37 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

19.5 Erase/Program Performance

Limits

Typ.

Parameter

Min.

Unit

Comments

Max.

3.0

64 Kword

16 Kword

-

0.6

0.3

Block Erase Time

1.5

Chip Erase Time ³⁾

307.8

0.4

1539

3.0

Includes 00h programming

prior to erasure

sec

64 Kword

16 Kword

Accelerated Block Erase Time

0.2

1.5

Accelerated Chip Erase Time ³⁾

Word Programming Time

205.2

80

1026

550

7

512-word Buffer Programming Time

Accelerated Word Programming Time

1.4

μs / word

80

550

3.5

Excludes system level over-

head

Accelerated 512-word Buffer Programming Time

Chip Buffer Programming Time

0.7

46.9

23.4

7

234.5

117

-

sec

ms

Accelerated Buffer Chip Programming Time

Blank check time

NOTE :

1)25°C, VCC = 1.8V, 100,000 cycles, typical pattern.

2) System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each word.

3) Chip Erase time & Accel. Chip Erase time for boot block part : K8S(10/11/12/13)15ET(B)C

- 38 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

Program Operations

Program Command Sequence (last two cycles)

Read Status Data

tAS

tWEA

AVD

tAVDP

tAH

A16:A24

PA

VA

A/DQ0:

555h

In

Complete

A0h

PD

VA

Progress

A/DQ15

tDS

tDH

CE

OE

tCH

tWP

WE

tWPH

tPGM

tCS

tWC

VIL

CLK

tVCS

VCC

NOTE :

1) PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2) “In progress” and “complete” refer to status of program operation.

3) A16–A24 are don’t care during command sequence unlock cycles.

4) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

Figure 13. Program Operation Timing

- 39 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

Buffer Program Operations

Buffer Program Command Sequence

Word Count

"Buffer to Flash"

Program Address/Data pairs (WC+1)

tAS

AVD

tAH

tAVDP

A16:A24

BA

PA_1

PA_0

PA_N

BA

A/DQ0:

A/DQ15

2AAh

55h

25h

BA

WC

PD_1

29h

BA

555h

A0h

tDS

PD_0

PD_N

CE

OE

WE

tWP

tPGM_BP

tWPH

tWC

tCS

VIL

CLK

VCC

tVCS

NOTE :

1) BA = Block Address, WC = Word Count, PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2) Sequential PA_1, PA_2, ... , PA_N must have same address bits A24(max.) ~ A9 as PA_0 entered firstly

3) The number of Program/Data pairs entered must be same as WC+1 because WC = N.

4) “In progress” and “complete” refer to status of program operation.

5) A16–A24 are don’t care during command sequence unlock cycles.

6) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

Figure 14. Buffer Program Operation Timing

- 40 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

Erase Operation

Erase Command Sequence (last two cycles)

Read Status Data

tAS

tWEA

AVD

tAVDP

tAH

A16:A24

BA

VA

555h for

chip erase chip erase

10h for

A/DQ0:

2AAh

In

Complete

55h

BA

30h

tDS

VA

Progress

A/DQ15

tDH

CE

OE

tCH

tWP

WE

tWPH

tBERS

tCS

tWC

VIL

CLK

tVCS

VCC

NOTE :

1) BA is the block address for Block Erase.

2) Address bits A16–A24 are don’t cares during unlock cycles in the command sequence.

3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

Figure 15. Chlp/Block Erase Operations

- 41 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

Unlock Bypass Program Operations(Accelerated Program)

CE

AVD

WE

PA

A16:A24

A/DQ0:

Don’t Care

tVPS

A0h

PD

Don’t Care

A/DQ15

OE

VID

tVPP

VPP

VIL or VIH

Unlock Bypass Block Erase Operations

CE

AVD

WE

BA

A16:A24

A/DQ0:

555h for

chip erase

10h for

chip erase

Don’t Care

80h

BA

30h

Don’t Care

A/DQ15

OE

tVPS

VID

tVPP

VPP

VIL or VIH

NOTE :

1) VPP can be left high for subsequent programming pulses.

2) Use setup and hold times from conventional program operations.

3) Conventional Program/Erase commands as well as Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp.

Figure 16. Unlock Bypass Operation Timings

- 42 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

Data Polling Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

VA

A16-A24

VA

tACH

VA

A/DQ0:

A/DQ15

Status Data

VA

tIAA

OE

tRDYS

Hi-Z

RDY

NOTE :

1) VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data.

Figure 17. Data Polling Timings (During Internal Routine)

Toggle Bit Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

VA

A16-A24

VA

tACH

VA

A/DQ0:

A/DQ15

Status Data

VA

tIAA

OE

tRDYS

Hi-Z

RDY

NOTE :

1) VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling.

Figure 18. Toggle Bit Timings(During Internal Routine)

- 43 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

SWITCHING WAVEFORMS

Read While Write Operations

Last Cycle in

Program or

Block Erase

Begin another

Program or Erase

Command Sequences

Read status in same bank

and/or array data from other bank

Command Sequence

tWC

tRC

tWC

CE

OE

tOE

tOEH

tGHWL

WE

tWPH

tWP

tDS

tAA

tOEH

tDH

RA

A/DQ0:

A/DQ15

PA/BA PD/30h

RD

RA

RD

555h

AAh

tSR/W

A16-A24

AVD

PA/BA

tAS

RA

tAH

Figure 19. Read While Write Operation

NOTE :

Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” and checking the status of the program or erase operation in the “busy”

bank.

- 44 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

20.0 Crossing of First Word Boundary in Burst Read Mode

The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no additional clock cycle is needed

from 2nd word boundary crossing to the end of continuous burst read. Also, the number of additional clock cycle for the first word boundary can vary from

zero to thirteen cycles, and the exact number of additional clock cycle depends on the starting address of burst read and programmable wait state set-

tings.

For example, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A14~A11) is "0011" (which means data is valid on

the 7th active CLK edge after AVD transition to Vih), six additional clock cycle is needed.

Similarly, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A14~A11) is "0010" (which means data is valid on the 6th

active CLK edge after AVD transition to Vih), five additional clock cycle is needed.

Below table shows the starting address vs. additional clock cycles for first word boundary.

Starting Address vs. Additional Clock Cycles for first word boundary

1)

Srarting

Address Group

for

Additional Clock Cycles for First Word Boundary

The Residue of

(Address/16)

LSB Bits

of Address

A14~A11 "0000"

Valid data : 4th CLK

A14~A11 "0001"

A14~A11 "0010"

A14~A11 "1010"

Valid data : 14th CLK

...

Valid data : 5th CLK

Valid data : 6th CLK

Burst Read

16N

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0 cycle

1 cycle

2 cycle

3 cycle

0 cycle

1 cycle

2 cycle

3 cycle

4 cycle

0 cycle

1 cycle

2 cycle

3 cycle

4 cycle

5 cycle

...

0 cycle

1 cycle

2 cycle

3 cycle

4 cycle

5 cycle

6 cycle

7 cycle

8 cycle

9 cycle

10 cycle

11 cycle

12 cycle

13 cycle

16N+1

16N+2

16N+3

16N+4

16N+5

16N+6

16N+7

16N+8

16N+9

16N+10

16N+11

16N+12

16N+13

16N+14

16N+15

2

3

4

5

6

7

8

9

10

11

12

13

14

15

NOTE :

1) Address bit A14~A11 means the programmable wait state on burst mode configuration register. Refer to Table 10.

- 45 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Case 1 : Start from "16N" address group

14th rising edge CLK

CR setting : A14=1, A13=0, A12=1, A11=0

A16-A24

Aa

A/DQ0:

A/DQ15

0B

0C

0D

0E

0F

10

11

12

CLK

AVD

00

0B

0C

10

11

12

13

0D

0E

0F

No Additional Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

NOTE :

1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc.

2) Address 000000H is also a boundary crossing.

3) No additional clock cycles are needed except for 1st boundary crossing.

Figure 20. Crossing of first word boundary in burst read mode.

Case 2 : Start from "16N+3" address group

14th rising edge CLK

CR setting : A14=1, A13=0, A12=1, A11=0

Aa

A16-A24

0F

Aa

A/DQ0:

A/DQ15

0D

0E

10

11

12

13

CLK

0D

0E

12

13

14

0F

10

00

11

AVD

Additional 1 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

NOTE :

1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc.

2) Address 000000H is also a boundary crossing.

3) No additional clock cycles are needed except for 1st boundary crossing.

Figure 21. Crossing of first word boundary in burst read mode.

- 46 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Case3 : Start from "16N+4" address group

14th rising edge CLK

CR setting : A14=1, A13=0, A12=1, A11=0

A16-A24

Aa

0F

A/DQ0:

A/DQ15

0E

10

11

12

13

CLK

00

0F

11

12

13

14

0E

10

AVD

Additional 2 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Case 4 : Start from "16N+15" address group

14th rising edge CLK

CR setting : A14=1, A13=0, A12=1, A11=0

A16-A24

Aa

A/DQ0:

A/DQ15

3F

10

11

CLK

10

3F

00

11

12

AVD

Additional 13 Cycle for First Word Boundary

CE

OE

tOER

RDY

NOTE :

1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc.

2) Address 000000H is also a boundary crossing.

3) No additional clock cycles are needed except for 1st boundary crossing.

Figure 22. Crossing of first word boundary in burst read mode.

- 47 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

[Table 17] Top Boot Block Address Table

Bank

Block

BA514

BA513

BA512

BA511

BA510

BA509

BA508

BA507

BA506

BA505

BA504

BA503

BA502

BA501

BA500

BA499

BA498

BA497

BA496

BA495

BA494

BA493

BA492

BA491

BA490

BA489

BA488

BA487

BA486

BA485

BA484

BA483

BA482

BA481

BA480

BA479

BA478

BA477

BA476

BA475

BA474

BA473

BA472

BA471

BA470

Block Size

16 kwords

64 kwords

(x16) Address Range

1FFC000h-1FFFFFFh

1FF8000h-1FFBFFFh

1FF4000h-1FF7FFFh

1FF0000h-1FF3FFFh

1FE0000h-1FEFFFFh

1FD0000h-1FDFFFFh

1FC0000h-1FCFFFFh

1FB0000h-1FBFFFFh

1FA0000h-1FAFFFFh

1F90000h-1F9FFFFh

1F80000h-1F8FFFFh

1F70000h-1F7FFFFh

1F60000h-1F6FFFFh

1F50000h-1F5FFFFh

1F40000h-1F4FFFFh

1F30000h-1F3FFFFh

1F20000h-1F2FFFFh

1F10000h-1F1FFFFh

1F00000h-1F0FFFFh

1EF0000h-1EFFFFFh

1EE0000h-1EEFFFFh

1ED0000h-1EDFFFFh

1EC0000h-1ECFFFFh

1EB0000h-1EBFFFFh

1EA0000h-1EAFFFFh

1E90000h-1E9FFFFh

1E80000h-1E8FFFFh

1E70000h-1E7FFFFh

1E60000h-1E6FFFFh

1E50000h-1E5FFFFh

1E40000h-1E4FFFFh

1E30000h-1E3FFFFh

1E20000h-1E2FFFFh

1E10000h-1E1FFFFh

1E00000h-1E0FFFFh

1DF0000h-1DFFFFFh

1DE0000h-1DEFFFFh

1DD0000h-1DDFFFFh

1DC0000h-1DCFFFFh

1DB0000h-1DBFFFFh

1DA0000h-1DAFFFFh

1D90000h-1D9FFFFh

1D80000h-1D8FFFFh

1D70000h-1D7FFFFh

1D60000h-1D6FFFFh

Bank 0

Bank 1

- 48 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA469

BA468

BA467

BA466

BA465

BA464

BA463

BA462

BA461

BA460

BA459

BA458

BA457

BA456

BA455

BA454

BA453

BA452

BA451

BA450

BA449

BA448

BA447

BA446

BA445

BA444

BA443

BA442

BA441

BA440

BA439

BA438

BA437

BA436

BA435

BA434

BA433

BA432

BA431

BA430

BA429

BA428

BA427

BA426

BA425

Block Size

64 kwords

(x16) Address Range

1D50000h-1D5FFFFh

1D40000h-1D4FFFFh

1D30000h-1D3FFFFh

1D20000h-1D2FFFFh

1D10000h-1D1FFFFh

1D00000h-1D0FFFFh

1CF0000h-1CFFFFFh

1CE0000h-1CEFFFFh

1CD0000h-1CDFFFFh

1CC0000h-1CCFFFFh

1CB0000h-1CBFFFFh

1CA0000h-1CAFFFFh

1C90000h-1C9FFFFh

1C80000h-1C8FFFFh

1C70000h-1C7FFFFh

1C60000h-1C6FFFFh

1C50000h-1C5FFFFh

1C40000h-1C4FFFFh

1C30000h-1C3FFFFh

1C20000h-1C2FFFFh

1C10000h-1C1FFFFh

1C00000h-1C0FFFFh

1BF0000h-1BFFFFFh

1BE0000h-1BEFFFFh

1BD0000h-1BDFFFFh

1BC0000h-1BCFFFFh

1BB0000h-1BBFFFFh

1BA0000h-1BAFFFFh

1B90000h-1B9FFFFh

1B80000h-1B8FFFFh

1B70000h-1B7FFFFh

1B60000h-1B6FFFFh

1B50000h-1B5FFFFh

1B40000h-1B4FFFFh

1B30000h-1B3FFFFh

1B20000h-1B2FFFFh

1B10000h-1B1FFFFh

1B00000h-1B0FFFFh

1AF0000h-1AFFFFFh

1AE0000h-1AEFFFFh

1AD0000h-1ADFFFFh

1AC0000h-1ACFFFFh

1AB0000h-1ABFFFFh

1AA0000h-1AAFFFFh

1A90000h-1A9FFFFh

Bank 1

Bank 2

- 49 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA424

BA423

BA422

BA421

BA420

BA419

BA418

BA417

BA416

BA415

BA414

BA413

BA412

BA411

BA410

BA409

BA408

BA407

BA406

BA405

BA404

BA403

BA402

BA401

BA400

BA399

BA398

BA397

BA396

BA395

BA394

BA393

BA392

BA391

BA390

BA389

BA388

BA387

BA386

BA385

BA384

BA383

BA382

BA381

BA380

Block Size

64 kwords

(x16) Address Range

1A80000h-1A8FFFFh

1A70000h-1A7FFFFh

1A60000h-1A6FFFFh

1A50000h-1A5FFFFh

1A40000h-1A4FFFFh

1A30000h-1A3FFFFh

1A20000h-1A2FFFFh

1A10000h-1A1FFFFh

1A00000h-1A0FFFFh

19F0000h-19FFFFFh

19E0000h-19EFFFFh

19D0000h-19DFFFFh

19C0000h-19CFFFFh

19B0000h-19BFFFFh

19A0000h-19AFFFFh

1990000h-199FFFFh

1980000h-198FFFFh

1970000h-197FFFFh

1960000h-196FFFFh

1950000h-195FFFFh

1940000h-194FFFFh

1930000h-193FFFFh

1920000h-192FFFFh

1910000h-191FFFFh

1900000h-190FFFFh

18F0000h-18FFFFFh

18E0000h-18EFFFFh

18D0000h-18DFFFFh

18C0000h-18CFFFFh

18B0000h-18BFFFFh

18A0000h-18AFFFFh

1890000h-189FFFFh

1880000h-188FFFFh

1870000h-187FFFFh

1860000h-186FFFFh

1850000h-185FFFFh

1840000h-184FFFFh

1830000h-183FFFFh

1820000h-182FFFFh

1810000h-181FFFFh

1800000h-180FFFFh

17F0000h-17FFFFFh

17E0000h-17EFFFFh

17D0000h-17DFFFFh

17C0000h-17CFFFFh

Bank 2

Bank 3

Bank 4

- 50 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA379

BA378

BA377

BA376

BA375

BA374

BA373

BA372

BA371

BA370

BA369

BA368

BA367

BA366

BA365

BA364

BA363

BA362

BA361

BA360

BA359

BA358

BA357

BA356

BA355

BA354

BA353

BA352

BA351

BA350

BA349

BA348

BA347

BA346

BA345

BA344

BA343

BA342

BA341

BA340

BA339

BA338

BA337

BA336

Block Size

64 kwords

(x16) Address Range

17B0000h-17BFFFFh

17A0000h-17AFFFFh

1790000h-179FFFFh

1780000h-178FFFFh

1770000h-177FFFFh

1760000h-176FFFFh

1750000h-175FFFFh

1740000h-174FFFFh

1730000h-173FFFFh

1720000h-172FFFFh

1710000h-171FFFFh

1700000h-170FFFFh

16F0000h-16FFFFFh

16E0000h-16EFFFFh

16D0000h-16DFFFFh

16C0000h-16CFFFFh

16B0000h-16BFFFFh

16A0000h-16AFFFFh

1690000h-169FFFFh

1680000h-168FFFFh

1670000h-167FFFFh

1660000h-166FFFFh

1650000h-165FFFFh

1640000h-164FFFFh

1630000h-163FFFFh

1620000h-162FFFFh

1610000h-161FFFFh

1600000h-160FFFFh

15F0000h-15FFFFFh

15E0000h-15EFFFFh

15D0000h-15DFFFFh

15C0000h-15CFFFFh

15B0000h-15BFFFFh

15A0000h-15AFFFFh

1590000h-159FFFFh

1580000h-158FFFFh

1570000h-157FFFFh

1560000h-156FFFFh

1550000h-155FFFFh

1540000h-154FFFFh

1530000h-153FFFFh

1520000h-152FFFFh

1510000h-151FFFFh

1500000h-150FFFFh

Bank 4

Bank5

- 51 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA335

BA334

BA333

BA332

BA331

BA330

BA329

BA328

BA327

BA326

BA325

BA324

BA323

BA322

BA321

BA320

BA319

BA318

BA317

BA316

BA315

BA314

BA313

BA312

BA311

BA310

BA309

BA308

BA307

BA306

BA305

BA304

BA303

BA302

BA301

BA300

BA299

BA298

BA297

BA296

BA295

BA294

BA293

BA292

BA291

Block Size

64 kwords

(x16) Address Range

14F0000h-14FFFFFh

14E0000h-14EFFFFh

14D0000h-14DFFFFh

14C0000h-14CFFFFh

14B0000h-14BFFFFh

14A0000h-14AFFFFh

1490000h-149FFFFh

1480000h-148FFFFh

1470000h-147FFFFh

1460000h-146FFFFh

1450000h-145FFFFh

1440000h-144FFFFh

1430000h-143FFFFh

1420000h-142FFFFh

1410000h-141FFFFh

1400000h-140FFFFh

13F0000h-13FFFFFh

13E0000h-13EFFFFh

13D0000h-13DFFFFh

13C0000h-13CFFFFh

13B0000h-13BFFFFh

13A0000h-13AFFFFh

1390000h-139FFFFh

1380000h-138FFFFh

1370000h-137FFFFh

1360000h-136FFFFh

1350000h-135FFFFh

1340000h-134FFFFh

1330000h-133FFFFh

1320000h-132FFFFh

1310000h-131FFFFh

1300000h-130FFFFh

12F0000h-12FFFFFh

12E0000h-12EFFFFh

12D0000h-12DFFFFh

12C0000h-12CFFFFh

12B0000h-12BFFFFh

12A0000h-12AFFFFh

1290000h-129FFFFh

1280000h-128FFFFh

1270000h-127FFFFh

1260000h-126FFFFh

1250000h-125FFFFh

1240000h-124FFFFh

1230000h-123FFFFh

Bank 5

Bank 6

- 52 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA290

BA289

BA288

BA287

BA286

BA285

BA284

BA283

BA282

BA281

BA280

BA279

BA278

BA277

BA276

BA275

BA274

BA273

BA272

BA271

BA270

BA269

BA268

BA267

BA266

BA265

BA264

BA263

BA262

BA261

BA260

BA259

Block Size

64 kwords

(x16) Address Range

1220000h-122FFFFh

1210000h-121FFFFh

1200000h-120FFFFh

11F0000h-11FFFFFh

11E0000h-11EFFFFh

11D0000h-11DFFFFh

11C0000h-11CFFFFh

11B0000h-11BFFFFh

11A0000h-11AFFFFh

1190000h-119FFFFh

1180000h-118FFFFh

1170000h-117FFFFh

1160000h-116FFFFh

1150000h-115FFFFh

1140000h-114FFFFh

1130000h-113FFFFh

1120000h-112FFFFh

1110000h-111FFFFh

1100000h-110FFFFh

10F0000h-10FFFFFh

10E0000h-10EFFFFh

10D0000h-10DFFFFh

10C0000h-10CFFFFh

10B0000h-10BFFFFh

10A0000h-10AFFFFh

1090000h-109FFFFh

1080000h-108FFFFh

1070000h-107FFFFh

1060000h-106FFFFh

1050000h-105FFFFh

1040000h-104FFFFh

1030000h-103FFFFh

Bank 6

Bank 7

- 53 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA258

BA257

BA256

BA255

BA254

BA253

BA252

BA251

BA250

BA249

BA248

BA247

BA246

BA245

BA244

BA243

BA242

BA241

BA240

BA239

BA238

BA237

BA236

BA235

BA234

BA233

BA232

BA231

BA230

BA229

BA228

BA227

BA226

BA225

BA224

BA223

BA222

BA221

BA220

BA219

BA218

BA217

BA216

BA215

BA214

Block Size

64 kwords

(x16) Address Range

1020000h-102FFFFh

1010000h-101FFFFh

1000000h-100FFFFh

0FF0000h-0FFFFFFh

0FE0000h-0FEFFFFh

0FD0000h-0FDFFFFh

0FC0000h-0FCFFFFh

0FB0000h-0FBFFFFh

0FA0000h-0FAFFFFh

0F90000h-0F9FFFFh

0F80000h-0F8FFFFh

0F70000h-0F7FFFFh

0F60000h-0F6FFFFh

0F50000h-0F5FFFFh

0F40000h-0F4FFFFh

0F30000h-0F3FFFFh

0F20000h-0F2FFFFh

0F10000h-0F1FFFFh

0F00000h-0F0FFFFh

0EF0000h-0EFFFFFh

0EE0000h-0EEFFFFh

0ED0000h-0EDFFFFh

0EC0000h-0ECFFFFh

0EB0000h-0EBFFFFh

0EA0000h-0EAFFFFh

0E90000h-0E9FFFFh

0E80000h-0E8FFFFh

0E70000h-0E7FFFFh

0E60000h-0E6FFFFh

0E50000h-0E5FFFFh

0E40000h-0E4FFFFh

0E30000h-0E3FFFFh

0E20000h-0E2FFFFh

0E10000h-0E1FFFFh

0E00000h-0E0FFFFh

0DF0000h-0DFFFFFh

0DE0000h-0DEFFFFh

0DD0000h-0DDFFFFh

0DC0000h-0DCFFFFh

0DB0000h-0DBFFFFh

0DA0000h-0DAFFFFh

0D90000h-0D9FFFFh

0D80000h-0D8FFFFh

0D70000h-0D7FFFFh

0D60000h-0D6FFFFh

Bank 7

Bank 8

Bank 9

- 54 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA213

BA212

BA211

BA210

BA209

BA208

BA207

BA206

BA205

BA204

BA203

BA202

BA201

BA200

BA199

BA198

BA197

BA196

BA195

BA194

BA193

BA192

BA191

BA190

BA189

BA188

BA187

BA186

BA185

BA184

BA183

BA182

BA181

BA180

BA179

BA178

BA177

BA176

BA175

BA174

BA173

BA172

BA171

BA170

BA169

Block Size

64 kwords

(x16) Address Range

0D50000h-0D5FFFFh

0D40000h-0D4FFFFh

0D30000h-0D3FFFFh

0D20000h-0D2FFFFh

0D10000h-0D1FFFFh

0D00000h-0D0FFFFh

0CF0000h-0CFFFFFh

0CE0000h-0CEFFFFh

0CD0000h-0CDFFFFh

0CC0000h-0CCFFFFh

0CB0000h-0CBFFFFh

0CA0000h-0CAFFFFh

0C90000h-0C9FFFFh

0C80000h-0C8FFFFh

0C70000h-0C7FFFFh

0C60000h-0C6FFFFh

0C50000h-0C5FFFFh

0C40000h-0C4FFFFh

0C30000h-0C3FFFFh

0C20000h-0C2FFFFh

0C10000h-0C1FFFFh

0C00000h-0C0FFFFh

0BF0000h-0BFFFFFh

0BE0000h-0BEFFFFh

0BD0000h-0BDFFFFh

0BC0000h-0BCFFFFh

0BB0000h-0BBFFFFh

0BA0000h-0BAFFFFh

0B90000h-0B9FFFFh

0B80000h-0B8FFFFh

0B70000h-0B7FFFFh

0B60000h-0B6FFFFh

0B50000h-0B5FFFFh

0B40000h-0B4FFFFh

0B30000h-0B3FFFFh

0B20000h-0B2FFFFh

0B10000h-0B1FFFFh

0B00000h-0B0FFFFh

0AF0000h-0AFFFFFh

0AE0000h-0AEFFFFh

0AD0000h-0ADFFFFh

0AC0000h-0ACFFFFh

0AB0000h-0ABFFFFh

0AA0000h-0AAFFFFh

0A90000h-0A9FFFFh

Bank 9

Bank 10

- 55 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA168

BA167

BA166

BA165

BA164

BA163

BA162

BA161

BA160

BA159

BA158

BA157

BA156

BA155

BA154

BA153

BA152

BA151

BA150

BA149

BA148

BA147

BA146

BA145

BA144

BA143

BA142

BA141

BA140

BA139

BA138

BA137

BA136

BA135

BA134

BA133

BA132

BA131

BA130

BA129

BA128

BA127

BA126

BA125

BA124

Block Size

64 kwords

(x16) Address Range

0A80000h-0A8FFFFh

0A70000h-0A7FFFFh

0A60000h-0A6FFFFh

0A50000h-0A5FFFFh

0A40000h-0A4FFFFh

0A30000h-0A3FFFFh

0A20000h-0A2FFFFh

0A10000h-0A1FFFFh

0A00000h-0A0FFFFh

09F0000h-09FFFFFh

09E0000h-09EFFFFh

09D0000h-09DFFFFh

09C0000h-09CFFFFh

09B0000h-09BFFFFh

09A0000h-09AFFFFh

0990000h-099FFFFh

0980000h-098FFFFh

0970000h-097FFFFh

0960000h-096FFFFh

0950000h-095FFFFh

0940000h-094FFFFh

0930000h-093FFFFh

0920000h-092FFFFh

0910000h-091FFFFh

0900000h-090FFFFh

08F0000h-08FFFFFh

08E0000h-08EFFFFh

08D0000h-08DFFFFh

08C0000h-08CFFFFh

08B0000h-08BFFFFh

08A0000h-08AFFFFh

0890000h-089FFFFh

0880000h-088FFFFh

0870000h-087FFFFh

0860000h-086FFFFh

0850000h-085FFFFh

0840000h-084FFFFh

0830000h-083FFFFh

0820000h-082FFFFh

0810000h-081FFFFh

0800000h-080FFFFh

07F0000h-07FFFFFh

07E0000h-07EFFFFh

07D0000h-07DFFFFh

07C0000h-07CFFFFh

Bank 10

Bank 11

Bank 12

- 56 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA123

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

Block Size

64 kwords

(x16) Address Range

07B0000h-07BFFFFh

07A0000h-07AFFFFh

0790000h-079FFFFh

0780000h-078FFFFh

0770000h-077FFFFh

0760000h-076FFFFh

0750000h-075FFFFh

0740000h-074FFFFh

0730000h-073FFFFh

0720000h-072FFFFh

0710000h-071FFFFh

0700000h-070FFFFh

06F0000h-06FFFFFh

06E0000h-06EFFFFh

06D0000h-06DFFFFh

06C0000h-06CFFFFh

06B0000h-06BFFFFh

06A0000h-06AFFFFh

0690000h-069FFFFh

0680000h-068FFFFh

0670000h-067FFFFh

0660000h-066FFFFh

0650000h-065FFFFh

0640000h-064FFFFh

0630000h-063FFFFh

0620000h-062FFFFh

0610000h-061FFFFh

0600000h-060FFFFh

05F0000h-05FFFFFh

05E0000h-05EFFFFh

05D0000h-05DFFFFh

05C0000h-05CFFFFh

05B0000h-05BFFFFh

05A0000h-05AFFFFh

0590000h-059FFFFh

0580000h-058FFFFh

0570000h-057FFFFh

0560000h-056FFFFh

0550000h-055FFFFh

0540000h-054FFFFh

0530000h-053FFFFh

0520000h-052FFFFh

0510000h-051FFFFh

0500000h-050FFFFh

Bank 12

BA98

BA97

BA96

BA95

BA94

BA93

BA92

BA91

BA90

BA89

BA88

Bank13

BA87

BA86

BA85

BA84

BA83

BA82

BA81

BA80

- 57 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA79

BA78

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

BA46

BA45

BA44

BA43

BA42

BA41

BA40

BA39

BA38

BA37

BA36

BA35

Block Size

64 kwords

(x16) Address Range

04F0000h-04FFFFFh

04E0000h-04EFFFFh

04D0000h-04DFFFFh

04C0000h-04CFFFFh

04B0000h-04BFFFFh

04A0000h-04AFFFFh

0490000h-049FFFFh

0480000h-048FFFFh

0470000h-047FFFFh

0460000h-046FFFFh

0450000h-045FFFFh

0440000h-044FFFFh

0430000h-043FFFFh

0420000h-042FFFFh

0410000h-041FFFFh

0400000h-040FFFFh

03F0000h-03FFFFFh

03E0000h-03EFFFFh

03D0000h-03DFFFFh

03C0000h-03CFFFFh

03B0000h-03BFFFFh

03A0000h-03AFFFFh

0390000h-039FFFFh

0380000h-038FFFFh

0370000h-037FFFFh

0360000h-036FFFFh

0350000h-035FFFFh

0340000h-034FFFFh

0330000h-033FFFFh

0320000h-032FFFFh

0310000h-031FFFFh

0300000h-030FFFFh

02F0000h-02FFFFFh

02E0000h-02EFFFFh

02D0000h-02DFFFFh

02C0000h-02CFFFFh

02B0000h-02BFFFFh

02A0000h-02AFFFFh

0290000h-029FFFFh

0280000h-028FFFFh

0270000h-027FFFFh

0260000h-026FFFFh

0250000h-025FFFFh

0240000h-024FFFFh

0230000h-023FFFFh

Bank 13

Bank 14

- 58 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA34

BA33

BA32

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

64 kwords

(x16) Address Range

0220000h-022FFFFh

0210000h-021FFFFh

0200000h-020FFFFh

01F0000h-01FFFFFh

01E0000h-01EFFFFh

01D0000h-01DFFFFh

01C0000h-01CFFFFh

01B0000h-01BFFFFh

01A0000h-01AFFFFh

0190000h-019FFFFh

0180000h-018FFFFh

0170000h-017FFFFh

0160000h-016FFFFh

0150000h-015FFFFh

0140000h-014FFFFh

0130000h-013FFFFh

0120000h-012FFFFh

0110000h-011FFFFh

0100000h-010FFFFh

00F0000h-00FFFFFh

00E0000h-00EFFFFh

00D0000h-00DFFFFh

00C0000h-00CFFFFh

00B0000h-00BFFFFh

00A0000h-00AFFFFh

0090000h-009FFFFh

0080000h-008FFFFh

0070000h-007FFFFh

0060000h-006FFFFh

0050000h-005FFFFh

0040000h-004FFFFh

0030000h-003FFFFh

0020000h-002FFFFh

0010000h-001FFFFh

0000000h-000FFFFh

Bank 14

Bank 15

BA8

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

[Table 18] Top Boot OTP Block Addresses

Block Address

Block Size

(x16) Address Range*

A24 ~ A8

OTP

1FFFFh

512 words

1FFFE00h-1FFFFFFh

After entering OTP Block, any issued addresses should be in the range of OTP block address.

- 59 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

[Table 19] Bottom Boot Block Address Table

Bank

Block

BA514

BA513

BA512

BA511

BA510

BA509

BA508

BA507

BA506

BA505

BA504

BA503

BA502

BA501

BA500

BA499

BA498

BA497

BA496

BA495

BA494

BA493

BA492

BA491

BA490

BA489

BA488

BA487

BA486

BA485

BA484

BA483

BA482

BA481

BA480

BA479

BA478

BA477

BA476

BA475

BA474

BA473

BA472

BA471

BA470

Block Size

64 Kwords

64 kwords

(x16) Address Range

1FF0000h-1FFFFFFh

1FE0000h-1FEFFFFh

1FD0000h-1FDFFFFh

1FC0000h-1FCFFFFh

1FB0000h-1FBFFFFh

1FA0000h-1FAFFFFh

1F90000h-1F9FFFFh

1F80000h-1F8FFFFh

1F70000h-1F7FFFFh

1F60000h-1F6FFFFh

1F50000h-1F5FFFFh

1F40000h-1F4FFFFh

1F30000h-1F3FFFFh

1F20000h-1F2FFFFh

1F10000h-1F1FFFFh

1F00000h-1F0FFFFh

1EF0000h-1EFFFFFh

1EE0000h-1EEFFFFh

1ED0000h-1EDFFFFh

1EC0000h-1ECFFFFh

1EB0000h-1EBFFFFh

1EA0000h-1EAFFFFh

1E90000h-1E9FFFFh

1E80000h-1E8FFFFh

1E70000h-1E7FFFFh

1E60000h-1E6FFFFh

1E50000h-1E5FFFFh

1E40000h-1E4FFFFh

1E30000h-1E3FFFFh

1E20000h-1E2FFFFh

1E10000h-1E1FFFFh

1E00000h-1E0FFFFh

1DF0000h-1DFFFFFh

1DE0000h-1DEFFFFh

1DD0000h-1DDFFFFh

1DC0000h-1DCFFFFh

1DB0000h-1DBFFFFh

1DA0000h-1DAFFFFh

1D90000h-1D9FFFFh

1D80000h-1D8FFFFh

1D70000h-1D7FFFFh

1D60000h-1D6FFFFh

1D50000h-1D5FFFFh

1D40000h-1D4FFFFh

1D30000h-1D3FFFFh

Bank 15

Bank 14

- 60 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA469

BA468

BA467

BA466

BA465

BA464

BA463

BA462

BA461

BA460

BA459

BA458

BA457

BA456

BA455

BA454

BA453

BA452

BA451

BA450

BA449

BA448

BA447

BA446

BA445

BA444

BA443

BA442

BA441

BA440

BA439

BA438

BA437

BA436

BA435

BA434

BA433

BA432

BA431

BA430

BA429

BA428

BA427

BA426

BA425

Block Size

64 kwords

(x16) Address Range

1D20000h-1D2FFFFh

1D10000h-1D1FFFFh

1D00000h-1D0FFFFh

1CF0000h-1CFFFFFh

1CE0000h-1CEFFFFh

1CD0000h-1CDFFFFh

1CC0000h-1CCFFFFh

1CB0000h-1CBFFFFh

1CA0000h-1CAFFFFh

1C90000h-1C9FFFFh

1C80000h-1C8FFFFh

1C70000h-1C7FFFFh

1C60000h-1C6FFFFh

1C50000h-1C5FFFFh

1C40000h-1C4FFFFh

1C30000h-1C3FFFFh

1C20000h-1C2FFFFh

1C10000h-1C1FFFFh

1C00000h-1C0FFFFh

1BF0000h-1BFFFFFh

1BE0000h-1BEFFFFh

1BD0000h-1BDFFFFh

1BC0000h-1BCFFFFh

1BB0000h-1BBFFFFh

1BA0000h-1BAFFFFh

1B90000h-1B9FFFFh

1B80000h-1B8FFFFh

1B70000h-1B7FFFFh

1B60000h-1B6FFFFh

1B50000h-1B5FFFFh

1B40000h-1B4FFFFh

1B30000h-1B3FFFFh

1B20000h-1B2FFFFh

1B10000h-1B1FFFFh

1B00000h-1B0FFFFh

1AF0000h-1AFFFFFh

1AE0000h-1AEFFFFh

1AD0000h-1ADFFFFh

1AC0000h-1ACFFFFh

1AB0000h-1ABFFFFh

1AA0000h-1AAFFFFh

1A90000h-1A9FFFFh

1A80000h-1A8FFFFh

1A70000h-1A7FFFFh

1A60000h-1A6FFFFh

Bank 14

Bank 13

- 61 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA424

BA423

BA422

BA421

BA420

BA419

BA418

BA417

BA416

BA415

BA414

BA413

BA412

BA411

BA410

BA409

BA408

BA407

BA406

BA405

BA404

BA403

BA402

BA401

BA400

BA399

BA398

BA397

BA396

BA395

BA394

BA393

BA392

BA391

BA390

BA389

BA388

BA387

BA386

BA385

BA384

BA383

BA382

BA381

BA380

Block Size

64 kwords

(x16) Address Range

1A50000h-1A5FFFFh

1A40000h-1A4FFFFh

1A30000h-1A3FFFFh

1A20000h-1A2FFFFh

1A10000h-1A1FFFFh

1A00000h-1A0FFFFh

19F0000h-19FFFFFh

19E0000h-19EFFFFh

19D0000h-19DFFFFh

19C0000h-19CFFFFh

19B0000h-19BFFFFh

19A0000h-19AFFFFh

1990000h-199FFFFh

1980000h-198FFFFh

1970000h-197FFFFh

1960000h-196FFFFh

1950000h-195FFFFh

1940000h-194FFFFh

1930000h-193FFFFh

1920000h-192FFFFh

1910000h-191FFFFh

1900000h-190FFFFh

18F0000h-18FFFFFh

18E0000h-18EFFFFh

18D0000h-18DFFFFh

18C0000h-18CFFFFh

18B0000h-18BFFFFh

18A0000h-18AFFFFh

1890000h-189FFFFh

1880000h-188FFFFh

1870000h-187FFFFh

1860000h-186FFFFh

1850000h-185FFFFh

1840000h-184FFFFh

1830000h-183FFFFh

1820000h-182FFFFh

1810000h-181FFFFh

1800000h-180FFFFh

17F0000h-17FFFFFh

17E0000h-17EFFFFh

17D0000h-17DFFFFh

17C0000h-17CFFFFh

17B0000h-17BFFFFh

17A0000h-17AFFFFh

1790000h-179FFFFh

Bank 13

Bank 12

Bank 11

- 62 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA379

BA378

BA377

BA376

BA375

BA374

BA373

BA372

BA371

BA370

BA369

BA368

BA367

BA366

BA365

BA364

BA363

BA362

BA361

BA360

BA359

BA358

BA357

BA356

BA355

BA354

BA353

BA352

BA351

BA350

BA349

BA348

BA347

BA346

BA345

BA344

BA343

BA342

BA341

BA340

BA339

BA338

BA337

BA336

Block Size

64 kwords

(x16) Address Range

1780000h-178FFFFh

1770000h-177FFFFh

1760000h-176FFFFh

1750000h-175FFFFh

1740000h-174FFFFh

1730000h-173FFFFh

1720000h-172FFFFh

1710000h-171FFFFh

1700000h-170FFFFh

16F0000h-16FFFFFh

16E0000h-16EFFFFh

16D0000h-16DFFFFh

16C0000h-16CFFFFh

16B0000h-16BFFFFh

16A0000h-16AFFFFh

1690000h-169FFFFh

1680000h-168FFFFh

1670000h-167FFFFh

1660000h-166FFFFh

1650000h-165FFFFh

1640000h-164FFFFh

1630000h-163FFFFh

1620000h-162FFFFh

1610000h-161FFFFh

1600000h-160FFFFh

15F0000h-15FFFFFh

15E0000h-15EFFFFh

15D0000h-15DFFFFh

15C0000h-15CFFFFh

15B0000h-15BFFFFh

15A0000h-15AFFFFh

1590000h-159FFFFh

1580000h-158FFFFh

1570000h-157FFFFh

1560000h-156FFFFh

1550000h-155FFFFh

1540000h-154FFFFh

1530000h-153FFFFh

1520000h-152FFFFh

1510000h-151FFFFh

1500000h-150FFFFh

14F0000h-14FFFFFh

14E0000h-14EFFFFh

14D0000h-14DFFFFh

Bank 11

Bank 10

- 63 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA335

BA334

BA333

BA332

BA331

BA330

BA329

BA328

BA327

BA326

BA325

BA324

BA323

BA322

BA321

BA320

BA319

BA318

BA317

BA316

BA315

BA314

BA313

BA312

BA311

BA310

BA309

BA308

BA307

BA306

BA305

BA304

BA303

BA302

BA301

BA300

BA299

BA298

BA297

BA296

BA295

BA294

BA293

BA292

BA291

Block Size

64 kwords

(x16) Address Range

14C0000h-14CFFFFh

14B0000h-14BFFFFh

14A0000h-14AFFFFh

1490000h-149FFFFh

1480000h-148FFFFh

1470000h-147FFFFh

1460000h-146FFFFh

1450000h-145FFFFh

1440000h-144FFFFh

1430000h-143FFFFh

1420000h-142FFFFh

1410000h-141FFFFh

1400000h-140FFFFh

13F0000h-13FFFFFh

13E0000h-13EFFFFh

13D0000h-13DFFFFh

13C0000h-13CFFFFh

13B0000h-13BFFFFh

13A0000h-13AFFFFh

1390000h-139FFFFh

1380000h-138FFFFh

1370000h-137FFFFh

1360000h-136FFFFh

1350000h-135FFFFh

1340000h-134FFFFh

1330000h-133FFFFh

1320000h-132FFFFh

1310000h-131FFFFh

1300000h-130FFFFh

12F0000h-12FFFFFh

12E0000h-12EFFFFh

12D0000h-12DFFFFh

12C0000h-12CFFFFh

12B0000h-12BFFFFh

12A0000h-12AFFFFh

1290000h-129FFFFh

1280000h-128FFFFh

1270000h-127FFFFh

1260000h-126FFFFh

1250000h-125FFFFh

1240000h-124FFFFh

1230000h-123FFFFh

1220000h-122FFFFh

1210000h-121FFFFh

1200000h-120FFFFh

Bank 10

Bank 9

- 64 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA290

BA289

BA288

BA287

BA286

BA285

BA284

BA283

BA282

BA281

BA280

BA279

BA278

BA277

BA276

BA275

BA274

BA273

BA272

BA271

BA270

BA269

BA268

BA267

BA266

BA265

BA264

BA263

BA262

BA261

BA260

BA259

BA258

BA257

BA256

BA255

BA254

BA253

BA252

BA251

BA250

BA249

BA248

BA247

BA246

Block Size

64 kwords

(x16) Address Range

11F0000h-11FFFFFh

11E0000h-11EFFFFh

11D0000h-11DFFFFh

11C0000h-11CFFFFh

11B0000h-11BFFFFh

11A0000h-11AFFFFh

1190000h-119FFFFh

1180000h-118FFFFh

1170000h-117FFFFh

1160000h-116FFFFh

1150000h-115FFFFh

1140000h-114FFFFh

1130000h-113FFFFh

1120000h-112FFFFh

1110000h-111FFFFh

1100000h-110FFFFh

10F0000h-10FFFFFh

10E0000h-10EFFFFh

10D0000h-10DFFFFh

10C0000h-10CFFFFh

10B0000h-10BFFFFh

10A0000h-10AFFFFh

1090000h-109FFFFh

1080000h-108FFFFh

1070000h-107FFFFh

1060000h-106FFFFh

1050000h-105FFFFh

1040000h-104FFFFh

1030000h-103FFFFh

1020000h-102FFFFh

1010000h-101FFFFh

1000000h-100FFFFh

0FF0000h-0FFFFFFh

0FE0000h-0FEFFFFh

0FD0000h-0FDFFFFh

0FC0000h-0FCFFFFh

0FB0000h-0FBFFFFh

0FA0000h-0FAFFFFh

0F90000h-0F9FFFFh

0F80000h-0F8FFFFh

0F70000h-0F7FFFFh

0F60000h-0F6FFFFh

0F50000h-0F5FFFFh

0F40000h-0F4FFFFh

0F30000h-0F3FFFFh

Bank 8

Bank 7

- 65 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA245

BA244

BA243

BA242

BA241

BA240

BA239

BA238

BA237

BA236

BA235

BA234

BA233

BA232

BA231

BA230

BA229

BA228

BA227

BA226

BA225

BA224

BA223

BA222

BA221

BA220

BA219

BA218

BA217

BA216

BA215

BA214

BA213

BA212

BA211

BA210

BA209

BA208

BA207

BA206

BA205

BA204

BA203

BA202

BA201

Block Size

64 kwords

(x16) Address Range

0F20000h-0F2FFFFh

0F10000h-0F1FFFFh

0F00000h-0F0FFFFh

0EF0000h-0EFFFFFh

0EE0000h-0EEFFFFh

0ED0000h-0EDFFFFh

0EC0000h-0ECFFFFh

0EB0000h-0EBFFFFh

0EA0000h-0EAFFFFh

0E90000h-0E9FFFFh

0E80000h-0E8FFFFh

0E70000h-0E7FFFFh

0E60000h-0E6FFFFh

0E50000h-0E5FFFFh

0E40000h-0E4FFFFh

0E30000h-0E3FFFFh

0E20000h-0E2FFFFh

0E10000h-0E1FFFFh

0E00000h-0E0FFFFh

0DF0000h-0DFFFFFh

0DE0000h-0DEFFFFh

0DD0000h-0DDFFFFh

0DC0000h-0DCFFFFh

0DB0000h-0DBFFFFh

0DA0000h-0DAFFFFh

0D90000h-0D9FFFFh

0D80000h-0D8FFFFh

0D70000h-0D7FFFFh

0D60000h-0D6FFFFh

0D50000h-0D5FFFFh

0D40000h-0D4FFFFh

0D30000h-0D3FFFFh

0D20000h-0D2FFFFh

0D10000h-0D1FFFFh

0D00000h-0D0FFFFh

0CF0000h-0CFFFFFh

0CE0000h-0CEFFFFh

0CD0000h-0CDFFFFh

0CC0000h-0CCFFFFh

0CB0000h-0CBFFFFh

0CA0000h-0CAFFFFh

0C90000h-0C9FFFFh

0C80000h-0C8FFFFh

0C70000h-0C7FFFFh

0C60000h-0C6FFFFh

Bank 7

Bank 6

- 66 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA200

BA199

BA198

BA197

BA196

BA195

BA194

BA193

BA192

BA191

BA190

BA189

BA188

BA187

BA186

BA185

BA184

BA183

BA182

BA181

BA180

BA179

BA178

BA177

BA176

BA175

BA174

BA173

BA172

BA171

BA170

BA169

BA168

BA167

BA166

BA165

BA164

BA163

BA162

BA161

BA160

BA159

BA158

BA157

BA156

Block Size

64 kwords

(x16) Address Range

0C50000h-0C5FFFFh

0C40000h-0C4FFFFh

0C30000h-0C3FFFFh

0C20000h-0C2FFFFh

0C10000h-0C1FFFFh

0C00000h-0C0FFFFh

0BF0000h-0BFFFFFh

0BE0000h-0BEFFFFh

0BD0000h-0BDFFFFh

0BC0000h-0BCFFFFh

0BB0000h-0BBFFFFh

0BA0000h-0BAFFFFh

0B90000h-0B9FFFFh

0B80000h-0B8FFFFh

0B70000h-0B7FFFFh

0B60000h-0B6FFFFh

0B50000h-0B5FFFFh

0B40000h-0B4FFFFh

0B30000h-0B3FFFFh

0B20000h-0B2FFFFh

0B10000h-0B1FFFFh

0B00000h-0B0FFFFh

0AF0000h-0AFFFFFh

0AE0000h-0AEFFFFh

0AD0000h-0ADFFFFh

0AC0000h-0ACFFFFh

0AB0000h-0ABFFFFh

0AA0000h-0AAFFFFh

0A90000h-0A9FFFFh

0A80000h-0A8FFFFh

0A70000h-0A7FFFFh

0A60000h-0A6FFFFh

0A50000h-0A5FFFFh

0A40000h-0A4FFFFh

0A30000h-0A3FFFFh

0A20000h-0A2FFFFh

0A10000h-0A1FFFFh

0A00000h-0A0FFFFh

09F0000h-09FFFFFh

09E0000h-09EFFFFh

09D0000h-09DFFFFh

09C0000h-09CFFFFh

09B0000h-09BFFFFh

09A0000h-09AFFFFh

0990000h-099FFFFh

Bank 6

Bank 5

Bank 4

- 67 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA155

BA154

BA153

BA152

BA151

BA150

BA149

BA148

BA147

BA146

BA145

BA144

BA143

BA142

BA141

BA140

BA139

BA138

BA137

BA136

BA135

BA134

BA133

BA132

BA131

BA130

BA129

BA128

BA127

BA126

BA125

BA124

BA123

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

Block Size

64 kwords

(x16) Address Range

0980000h-098FFFFh

0970000h-097FFFFh

0960000h-096FFFFh

0950000h-095FFFFh

0940000h-094FFFFh

0930000h-093FFFFh

0920000h-092FFFFh

0910000h-091FFFFh

0900000h-090FFFFh

08F0000h-08FFFFFh

08E0000h-08EFFFFh

08D0000h-08DFFFFh

08C0000h-08CFFFFh

08B0000h-08BFFFFh

08A0000h08AFFFFh

0890000h-089FFFFh

0880000h-088FFFFh

0870000h-087FFFFh

0860000h-086FFFFh

0850000h-085FFFFh

0840000h-084FFFFh

0830000h-083FFFFh

0820000h-082FFFFh

0810000h-081FFFFh

0800000h-080FFFFh

07F0000h-07FFFFFh

07E0000h-07EFFFFh

07D0000h-07DFFFFh

07C0000h-07CFFFFh

07B0000h-07BFFFFh

07A0000h-07AFFFFh

0790000h-079FFFFh

0780000h-078FFFFh

0770000h-077FFFFh

0760000h-076FFFFh

0750000h-075FFFFh

0740000h-074FFFFh

0730000h-073FFFFh

0720000h-072FFFFh

0710000h-071FFFFh

0700000h-070FFFFh

06F0000h-06FFFFFh

06E0000h-06EFFFFh

06D0000h-06DFFFFh

06C0000h-06CFFFFh

Bank 4

Bank 3

- 68 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

BA98

BA97

BA96

BA95

BA94

BA93

BA92

BA91

BA90

BA89

BA88

BA87

BA86

BA85

BA84

BA83

BA82

BA81

BA80

BA79

BA78

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

Block Size

64 kwords

(x16) Address Range

06B0000h-06BFFFFh

06A0000h-06AFFFFh

0690000h-069FFFFh

0680000h-068FFFFh

0670000h-067FFFFh

0660000h-066FFFFh

0650000h-065FFFFh

0640000h-064FFFFh

0630000h-063FFFFh

0620000h-062FFFFh

0610000h-061FFFFh

0600000h-060FFFFh

05F0000h-05FFFFFh

05E0000h-05EFFFFh

05D0000h-05DFFFFh

05C0000h-05CFFFFh

05B0000h-05BFFFFh

05A0000h-05AFFFFh

0590000h-059FFFFh

0580000h-058FFFFh

0570000h-057FFFFh

0560000h-056FFFFh

0550000h-055FFFFh

0540000h-054FFFFh

0530000h-053FFFFh

0520000h-052FFFFh

0510000h-051FFFFh

0500000h-050FFFFh

04F0000h-04FFFFFh

04E0000h-04EFFFFh

04D0000h-04DFFFFh

04C0000h-04CFFFFh

04B0000h-04BFFFFh

04A0000h-04AFFFFh

0490000h-049FFFFh

0480000h-048FFFFh

0470000h-047FFFFh

0460000h-046FFFFh

0450000h-045FFFFh

0440000h-044FFFFh

0430000h-043FFFFh

0420000h-042FFFFh

0410000h-041FFFFh

0400000h-040FFFFh

03F0000h-03FFFFFh

Bank 3

Bank 2

Bank 1

- 69 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

BA46

BA45

BA44

BA43

BA42

BA41

BA40

BA39

BA38

BA37

BA36

BA35

BA34

BA33

BA32

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

Block Size

64 kwords

(x16) Address Range

03E0000h-03EFFFFh

03D0000h-03DFFFFh

03C0000h-03CFFFFh

03B0000h-03BFFFFh

03A0000h-03AFFFFh

0390000h-039FFFFh

0380000h-038FFFFh

0370000h-037FFFFh

0360000h-036FFFFh

0350000h-035FFFFh

0340000h-034FFFFh

0330000h-033FFFFh

0320000h-032FFFFh

0310000h-031FFFFh

0300000h-030FFFFh

02F0000h-02FFFFFh

02E0000h-02EFFFFh

02D0000h-02DFFFFh

02C0000h-02CFFFFh

02B0000h-02BFFFFh

02A0000h-02AFFFFh

0290000h-029FFFFh

0280000h-028FFFFh

0270000h-027FFFFh

0260000h-026FFFFh

0250000h-025FFFFh

0240000h-024FFFFh

0230000h-023FFFFh

0220000h-022FFFFh

0210000h-021FFFFh

0200000h-020FFFFh

01F0000h-01FFFFFh

01E0000h-01EFFFFh

01D0000h-01DFFFFh

01C0000h-01CFFFFh

01B0000h-01BFFFFh

01A0000h-01AFFFFh

0190000h-019FFFFh

0180000h-018FFFFh

0170000h-017FFFFh

0160000h-016FFFFh

0150000h-015FFFFh

0140000h-014FFFFh

0130000h-013FFFFh

0120000h-012FFFFh

Bank 1

Bank 0

- 70 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

64 kwords

16 kwords

(x16) Address Range

0110000h-011FFFFh

0100000h-010FFFFh

00F0000h-00FFFFFh

00E0000h-00EFFFFh

00D0000h-00DFFFFh

00C0000h-00CFFFFh

00B0000h-00BFFFFh

00A0000h-00AFFFFh

0090000h-009FFFFh

0080000h-008FFFFh

0070000h-007FFFFh

0060000h-006FFFFh

0050000h-005FFFFh

0040000h-004FFFFh

0030000h-003FFFFh

0020000h-002FFFFh

0010000h-001FFFFh

000C000h-000FFFFh

0008000h-000BFFFh

0004000h-0007FFFh

0000000h-0003FFFh

Bank 0

BA8

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

[Table 20] Bottom Boot OTP Block Addresses

Block Address

Block Size

(x16) Address Range*

A24 ~ A8

OTP

00000h

512 words

0000000h-00001FFh

After entering OTP Block, any issued addresses should be in the range of OTP block address.

- 71 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

[Table 21] Uniform Block Address Table

Bank

Block

BA511

BA510

BA509

BA508

BA507

BA506

BA505

BA504

BA503

BA502

BA501

BA500

BA499

BA498

BA497

BA496

BA495

BA494

BA493

BA492

BA491

BA490

BA489

BA488

BA487

BA486

BA485

BA484

BA483

BA482

BA481

BA480

BA479

BA478

BA477

BA476

BA475

BA474

BA473

BA472

BA471

BA470

Block Size

64 kwords

(x16) Address Range

1FF0000h-1FFFFFFh

1FE0000h-1FEFFFFh

1FD0000h-1FDFFFFh

1FC0000h-1FCFFFFh

1FB0000h-1FBFFFFh

1FA0000h-1FAFFFFh

1F90000h-1F9FFFFh

1F80000h-1F8FFFFh

1F70000h-1F7FFFFh

1F60000h-1F6FFFFh

1F50000h-1F5FFFFh

1F40000h-1F4FFFFh

1F30000h-1F3FFFFh

1F20000h-1F2FFFFh

1F10000h-1F1FFFFh

1F00000h-1F0FFFFh

1EF0000h-1EFFFFFh

1EE0000h-1EEFFFFh

1ED0000h-1EDFFFFh

1EC0000h-1ECFFFFh

1EB0000h-1EBFFFFh

1EA0000h-1EAFFFFh

1E90000h-1E9FFFFh

1E80000h-1E8FFFFh

1E70000h-1E7FFFFh

1E60000h-1E6FFFFh

1E50000h-1E5FFFFh

1E40000h-1E4FFFFh

1E30000h-1E3FFFFh

1E20000h-1E2FFFFh

1E10000h-1E1FFFFh

1E00000h-1E0FFFFh

1DF0000h-1DFFFFFh

1DE0000h-1DEFFFFh

1DD0000h-1DDFFFFh

1DC0000h-1DCFFFFh

1DB0000h-1DBFFFFh

1DA0000h-1DAFFFFh

1D90000h-1D9FFFFh

1D80000h-1D8FFFFh

1D70000h-1D7FFFFh

1D60000h-1D6FFFFh

Bank 0

Bank 1

- 72 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA469

BA468

BA467

BA466

BA465

BA464

BA463

BA462

BA461

BA460

BA459

BA458

BA457

BA456

BA455

BA454

BA453

BA452

BA451

BA450

BA449

BA448

BA447

BA446

BA445

BA444

BA443

BA442

BA441

BA440

BA439

BA438

BA437

BA436

BA435

BA434

BA433

BA432

BA431

BA430

BA429

BA428

BA427

BA426

BA425

Block Size

64 kwords

(x16) Address Range

1D50000h-1D5FFFFh

1D40000h-1D4FFFFh

1D30000h-1D3FFFFh

1D20000h-1D2FFFFh

1D10000h-1D1FFFFh

1D00000h-1D0FFFFh

1CF0000h-1CFFFFFh

1CE0000h-1CEFFFFh

1CD0000h-1CDFFFFh

1CC0000h-1CCFFFFh

1CB0000h-1CBFFFFh

1CA0000h-1CAFFFFh

1C90000h-1C9FFFFh

1C80000h-1C8FFFFh

1C70000h-1C7FFFFh

1C60000h-1C6FFFFh

1C50000h-1C5FFFFh

1C40000h-1C4FFFFh

1C30000h-1C3FFFFh

1C20000h-1C2FFFFh

1C10000h-1C1FFFFh

1C00000h-1C0FFFFh

1BF0000h-1BFFFFFh

1BE0000h-1BEFFFFh

1BD0000h-1BDFFFFh

1BC0000h-1BCFFFFh

1BB0000h-1BBFFFFh

1BA0000h-1BAFFFFh

1B90000h-1B9FFFFh

1B80000h-1B8FFFFh

1B70000h-1B7FFFFh

1B60000h-1B6FFFFh

1B50000h-1B5FFFFh

1B40000h-1B4FFFFh

1B30000h-1B3FFFFh

1B20000h-1B2FFFFh

1B10000h-1B1FFFFh

1B00000h-1B0FFFFh

1AF0000h-1AFFFFFh

1AE0000h-1AEFFFFh

1AD0000h-1ADFFFFh

1AC0000h-1ACFFFFh

1AB0000h-1ABFFFFh

1AA0000h-1AAFFFFh

1A90000h-1A9FFFFh

Bank 1

Bank 2

- 73 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA424

BA423

BA422

BA421

BA420

BA419

BA418

BA417

BA416

BA415

BA414

BA413

BA412

BA411

BA410

BA409

BA408

BA407

BA406

BA405

BA404

BA403

BA402

BA401

BA400

BA399

BA398

BA397

BA396

BA395

BA394

BA393

BA392

BA391

BA390

BA389

BA388

BA387

BA386

BA385

BA384

BA383

BA382

BA381

BA380

Block Size

64 kwords

(x16) Address Range

1A80000h-1A8FFFFh

1A70000h-1A7FFFFh

1A60000h-1A6FFFFh

1A50000h-1A5FFFFh

1A40000h-1A4FFFFh

1A30000h-1A3FFFFh

1A20000h-1A2FFFFh

1A10000h-1A1FFFFh

1A00000h-1A0FFFFh

19F0000h-19FFFFFh

19E0000h-19EFFFFh

19D0000h-19DFFFFh

19C0000h-19CFFFFh

19B0000h-19BFFFFh

19A0000h-19AFFFFh

1990000h-199FFFFh

1980000h-198FFFFh

1970000h-197FFFFh

1960000h-196FFFFh

1950000h-195FFFFh

1940000h-194FFFFh

1930000h-193FFFFh

1920000h-192FFFFh

1910000h-191FFFFh

1900000h-190FFFFh

18F0000h-18FFFFFh

18E0000h-18EFFFFh

18D0000h-18DFFFFh

18C0000h-18CFFFFh

18B0000h-18BFFFFh

18A0000h-18AFFFFh

1890000h-189FFFFh

1880000h-188FFFFh

1870000h-187FFFFh

1860000h-186FFFFh

1850000h-185FFFFh

1840000h-184FFFFh

1830000h-183FFFFh

1820000h-182FFFFh

1810000h-181FFFFh

1800000h-180FFFFh

17F0000h-17FFFFFh

17E0000h-17EFFFFh

17D0000h-17DFFFFh

17C0000h-17CFFFFh

Bank 2

Bank 3

Bank 4

- 74 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA379

BA378

BA377

BA376

BA375

BA374

BA373

BA372

BA371

BA370

BA369

BA368

BA367

BA366

BA365

BA364

BA363

BA362

BA361

BA360

BA359

BA358

BA357

BA356

BA355

BA354

BA353

BA352

BA351

BA350

BA349

BA348

BA347

BA346

BA345

BA344

BA343

BA342

BA341

BA340

BA339

BA338

BA337

BA336

Block Size

64 kwords

(x16) Address Range

17B0000h-17BFFFFh

17A0000h-17AFFFFh

1790000h-179FFFFh

1780000h-178FFFFh

1770000h-177FFFFh

1760000h-176FFFFh

1750000h-175FFFFh

1740000h-174FFFFh

1730000h-173FFFFh

1720000h-172FFFFh

1710000h-171FFFFh

1700000h-170FFFFh

16F0000h-16FFFFFh

16E0000h-16EFFFFh

16D0000h-16DFFFFh

16C0000h-16CFFFFh

16B0000h-16BFFFFh

16A0000h-16AFFFFh

1690000h-169FFFFh

1680000h-168FFFFh

1670000h-167FFFFh

1660000h-166FFFFh

1650000h-165FFFFh

1640000h-164FFFFh

1630000h-163FFFFh

1620000h-162FFFFh

1610000h-161FFFFh

1600000h-160FFFFh

15F0000h-15FFFFFh

15E0000h-15EFFFFh

15D0000h-15DFFFFh

15C0000h-15CFFFFh

15B0000h-15BFFFFh

15A0000h-15AFFFFh

1590000h-159FFFFh

1580000h-158FFFFh

1570000h-157FFFFh

1560000h-156FFFFh

1550000h-155FFFFh

1540000h-154FFFFh

1530000h-153FFFFh

1520000h-152FFFFh

1510000h-151FFFFh

1500000h-150FFFFh

Bank 4

Bank5

- 75 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA335

BA334

BA333

BA332

BA331

BA330

BA329

BA328

BA327

BA326

BA325

BA324

BA323

BA322

BA321

BA320

BA319

BA318

BA317

BA316

BA315

BA314

BA313

BA312

BA311

BA310

BA309

BA308

BA307

BA306

BA305

BA304

BA303

BA302

BA301

BA300

BA299

BA298

BA297

BA296

BA295

BA294

BA293

BA292

BA291

Block Size

64 kwords

(x16) Address Range

14F0000h-14FFFFFh

14E0000h-14EFFFFh

14D0000h-14DFFFFh

14C0000h-14CFFFFh

14B0000h-14BFFFFh

14A0000h-14AFFFFh

1490000h-149FFFFh

1480000h-148FFFFh

1470000h-147FFFFh

1460000h-146FFFFh

1450000h-145FFFFh

1440000h-144FFFFh

1430000h-143FFFFh

1420000h-142FFFFh

1410000h-141FFFFh

1400000h-140FFFFh

13F0000h-13FFFFFh

13E0000h-13EFFFFh

13D0000h-13DFFFFh

13C0000h-13CFFFFh

13B0000h-13BFFFFh

13A0000h-13AFFFFh

1390000h-139FFFFh

1380000h-138FFFFh

1370000h-137FFFFh

1360000h-136FFFFh

1350000h-135FFFFh

1340000h-134FFFFh

1330000h-133FFFFh

1320000h-132FFFFh

1310000h-131FFFFh

1300000h-130FFFFh

12F0000h-12FFFFFh

12E0000h-12EFFFFh

12D0000h-12DFFFFh

12C0000h-12CFFFFh

12B0000h-12BFFFFh

12A0000h-12AFFFFh

1290000h-129FFFFh

1280000h-128FFFFh

1270000h-127FFFFh

1260000h-126FFFFh

1250000h-125FFFFh

1240000h-124FFFFh

1230000h-123FFFFh

Bank 5

Bank 6

- 76 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA290

BA289

BA288

BA287

BA286

BA285

BA284

BA283

BA282

BA281

BA280

BA279

BA278

BA277

BA276

BA275

BA274

BA273

BA272

BA271

BA270

BA269

BA268

BA267

BA266

BA265

BA264

BA263

BA262

BA261

BA260

BA259

Block Size

64 kwords

(x16) Address Range

1220000h-122FFFFh

1210000h-121FFFFh

1200000h-120FFFFh

11F0000h-11FFFFFh

11E0000h-11EFFFFh

11D0000h-11DFFFFh

11C0000h-11CFFFFh

11B0000h-11BFFFFh

11A0000h-11AFFFFh

1190000h-119FFFFh

1180000h-118FFFFh

1170000h-117FFFFh

1160000h-116FFFFh

1150000h-115FFFFh

1140000h-114FFFFh

1130000h-113FFFFh

1120000h-112FFFFh

1110000h-111FFFFh

1100000h-110FFFFh

10F0000h-10FFFFFh

10E0000h-10EFFFFh

10D0000h-10DFFFFh

10C0000h-10CFFFFh

10B0000h-10BFFFFh

10A0000h-10AFFFFh

1090000h-109FFFFh

1080000h-108FFFFh

1070000h-107FFFFh

1060000h-106FFFFh

1050000h-105FFFFh

1040000h-104FFFFh

1030000h-103FFFFh

Bank 6

Bank 7

- 77 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA258

BA257

BA256

BA255

BA254

BA253

BA252

BA251

BA250

BA249

BA248

BA247

BA246

BA245

BA244

BA243

BA242

BA241

BA240

BA239

BA238

BA237

BA236

BA235

BA234

BA233

BA232

BA231

BA230

BA229

BA228

BA227

BA226

BA225

BA224

BA223

BA222

BA221

BA220

BA219

BA218

BA217

BA216

BA215

BA214

Block Size

64 kwords

(x16) Address Range

1020000h-102FFFFh

1010000h-101FFFFh

1000000h-100FFFFh

0FF0000h-0FFFFFFh

0FE0000h-0FEFFFFh

0FD0000h-0FDFFFFh

0FC0000h-0FCFFFFh

0FB0000h-0FBFFFFh

0FA0000h-0FAFFFFh

0F90000h-0F9FFFFh

0F80000h-0F8FFFFh

0F70000h-0F7FFFFh

0F60000h-0F6FFFFh

0F50000h-0F5FFFFh

0F40000h-0F4FFFFh

0F30000h-0F3FFFFh

0F20000h-0F2FFFFh

0F10000h-0F1FFFFh

0F00000h-0F0FFFFh

0EF0000h-0EFFFFFh

0EE0000h-0EEFFFFh

0ED0000h-0EDFFFFh

0EC0000h-0ECFFFFh

0EB0000h-0EBFFFFh

0EA0000h-0EAFFFFh

0E90000h-0E9FFFFh

0E80000h-0E8FFFFh

0E70000h-0E7FFFFh

0E60000h-0E6FFFFh

0E50000h-0E5FFFFh

0E40000h-0E4FFFFh

0E30000h-0E3FFFFh

0E20000h-0E2FFFFh

0E10000h-0E1FFFFh

0E00000h-0E0FFFFh

0DF0000h-0DFFFFFh

0DE0000h-0DEFFFFh

0DD0000h-0DDFFFFh

0DC0000h-0DCFFFFh

0DB0000h-0DBFFFFh

0DA0000h-0DAFFFFh

0D90000h-0D9FFFFh

0D80000h-0D8FFFFh

0D70000h-0D7FFFFh

0D60000h-0D6FFFFh

Bank 7

Bank 8

Bank 9

- 78 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA213

BA212

BA211

BA210

BA209

BA208

BA207

BA206

BA205

BA204

BA203

BA202

BA201

BA200

BA199

BA198

BA197

BA196

BA195

BA194

BA193

BA192

BA191

BA190

BA189

BA188

BA187

BA186

BA185

BA184

BA183

BA182

BA181

BA180

BA179

BA178

BA177

BA176

BA175

BA174

BA173

BA172

BA171

BA170

BA169

Block Size

64 kwords

(x16) Address Range

0D50000h-0D5FFFFh

0D40000h-0D4FFFFh

0D30000h-0D3FFFFh

0D20000h-0D2FFFFh

0D10000h-0D1FFFFh

0D00000h-0D0FFFFh

0CF0000h-0CFFFFFh

0CE0000h-0CEFFFFh

0CD0000h-0CDFFFFh

0CC0000h-0CCFFFFh

0CB0000h-0CBFFFFh

0CA0000h-0CAFFFFh

0C90000h-0C9FFFFh

0C80000h-0C8FFFFh

0C70000h-0C7FFFFh

0C60000h-0C6FFFFh

0C50000h-0C5FFFFh

0C40000h-0C4FFFFh

0C30000h-0C3FFFFh

0C20000h-0C2FFFFh

0C10000h-0C1FFFFh

0C00000h-0C0FFFFh

0BF0000h-0BFFFFFh

0BE0000h-0BEFFFFh

0BD0000h-0BDFFFFh

0BC0000h-0BCFFFFh

0BB0000h-0BBFFFFh

0BA0000h-0BAFFFFh

0B90000h-0B9FFFFh

0B80000h-0B8FFFFh

0B70000h-0B7FFFFh

0B60000h-0B6FFFFh

0B50000h-0B5FFFFh

0B40000h-0B4FFFFh

0B30000h-0B3FFFFh

0B20000h-0B2FFFFh

0B10000h-0B1FFFFh

0B00000h-0B0FFFFh

0AF0000h-0AFFFFFh

0AE0000h-0AEFFFFh

0AD0000h-0ADFFFFh

0AC0000h-0ACFFFFh

0AB0000h-0ABFFFFh

0AA0000h-0AAFFFFh

0A90000h-0A9FFFFh

Bank 9

Bank 10

- 79 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA168

BA167

BA166

BA165

BA164

BA163

BA162

BA161

BA160

BA159

BA158

BA157

BA156

BA155

BA154

BA153

BA152

BA151

BA150

BA149

BA148

BA147

BA146

BA145

BA144

BA143

BA142

BA141

BA140

BA139

BA138

BA137

BA136

BA135

BA134

BA133

BA132

BA131

BA130

BA129

BA128

BA127

BA126

BA125

BA124

Block Size

64 kwords

(x16) Address Range

0A80000h-0A8FFFFh

0A70000h-0A7FFFFh

0A60000h-0A6FFFFh

0A50000h-0A5FFFFh

0A40000h-0A4FFFFh

0A30000h-0A3FFFFh

0A20000h-0A2FFFFh

0A10000h-0A1FFFFh

0A00000h-0A0FFFFh

09F0000h-09FFFFFh

09E0000h-09EFFFFh

09D0000h-09DFFFFh

09C0000h-09CFFFFh

09B0000h-09BFFFFh

09A0000h-09AFFFFh

0990000h-099FFFFh

0980000h-098FFFFh

0970000h-097FFFFh

0960000h-096FFFFh

0950000h-095FFFFh

0940000h-094FFFFh

0930000h-093FFFFh

0920000h-092FFFFh

0910000h-091FFFFh

0900000h-090FFFFh

08F0000h-08FFFFFh

08E0000h-08EFFFFh

08D0000h-08DFFFFh

08C0000h-08CFFFFh

08B0000h-08BFFFFh

08A0000h-08AFFFFh

0890000h-089FFFFh

0880000h-088FFFFh

0870000h-087FFFFh

0860000h-086FFFFh

0850000h-085FFFFh

0840000h-084FFFFh

0830000h-083FFFFh

0820000h-082FFFFh

0810000h-081FFFFh

0800000h-080FFFFh

07F0000h-07FFFFFh

07E0000h-07EFFFFh

07D0000h-07DFFFFh

07C0000h-07CFFFFh

Bank 10

Bank 11

Bank 12

- 80 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA123

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

Block Size

64 kwords

(x16) Address Range

07B0000h-07BFFFFh

07A0000h-07AFFFFh

0790000h-079FFFFh

0780000h-078FFFFh

0770000h-077FFFFh

0760000h-076FFFFh

0750000h-075FFFFh

0740000h-074FFFFh

0730000h-073FFFFh

0720000h-072FFFFh

0710000h-071FFFFh

0700000h-070FFFFh

06F0000h-06FFFFFh

06E0000h-06EFFFFh

06D0000h-06DFFFFh

06C0000h-06CFFFFh

06B0000h-06BFFFFh

06A0000h-06AFFFFh

0690000h-069FFFFh

0680000h-068FFFFh

0670000h-067FFFFh

0660000h-066FFFFh

0650000h-065FFFFh

0640000h-064FFFFh

0630000h-063FFFFh

0620000h-062FFFFh

0610000h-061FFFFh

0600000h-060FFFFh

05F0000h-05FFFFFh

05E0000h-05EFFFFh

05D0000h-05DFFFFh

05C0000h-05CFFFFh

05B0000h-05BFFFFh

05A0000h-05AFFFFh

0590000h-059FFFFh

0580000h-058FFFFh

0570000h-057FFFFh

0560000h-056FFFFh

0550000h-055FFFFh

0540000h-054FFFFh

0530000h-053FFFFh

0520000h-052FFFFh

0510000h-051FFFFh

0500000h-050FFFFh

Bank 12

BA98

BA97

BA96

BA95

BA94

BA93

BA92

BA91

BA90

BA89

BA88

Bank13

BA87

BA86

BA85

BA84

BA83

BA82

BA81

BA80

- 81 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA79

BA78

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

BA46

BA45

BA44

BA43

BA42

BA41

BA40

BA39

BA38

BA37

BA36

BA35

Block Size

64 kwords

(x16) Address Range

04F0000h-04FFFFFh

04E0000h-04EFFFFh

04D0000h-04DFFFFh

04C0000h-04CFFFFh

04B0000h-04BFFFFh

04A0000h-04AFFFFh

0490000h-049FFFFh

0480000h-048FFFFh

0470000h-047FFFFh

0460000h-046FFFFh

0450000h-045FFFFh

0440000h-044FFFFh

0430000h-043FFFFh

0420000h-042FFFFh

0410000h-041FFFFh

0400000h-040FFFFh

03F0000h-03FFFFFh

03E0000h-03EFFFFh

03D0000h-03DFFFFh

03C0000h-03CFFFFh

03B0000h-03BFFFFh

03A0000h-03AFFFFh

0390000h-039FFFFh

0380000h-038FFFFh

0370000h-037FFFFh

0360000h-036FFFFh

0350000h-035FFFFh

0340000h-034FFFFh

0330000h-033FFFFh

0320000h-032FFFFh

0310000h-031FFFFh

0300000h-030FFFFh

02F0000h-02FFFFFh

02E0000h-02EFFFFh

02D0000h-02DFFFFh

02C0000h-02CFFFFh

02B0000h-02BFFFFh

02A0000h-02AFFFFh

0290000h-029FFFFh

0280000h-028FFFFh

0270000h-027FFFFh

0260000h-026FFFFh

0250000h-025FFFFh

0240000h-024FFFFh

0230000h-023FFFFh

Bank 13

Bank 14

- 82 -

Rev. 1.1

K8S1215E(T/B/Z)C

datasheet NOR FLASH MEMORY

Bank

Block

BA34

BA33

BA32

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

64 kwords

(x16) Address Range

0220000h-022FFFFh

0210000h-021FFFFh

0200000h-020FFFFh

01F0000h-01FFFFFh

01E0000h-01EFFFFh

01D0000h-01DFFFFh

01C0000h-01CFFFFh

01B0000h-01BFFFFh

01A0000h-01AFFFFh

0190000h-019FFFFh

0180000h-018FFFFh

0170000h-017FFFFh

0160000h-016FFFFh

0150000h-015FFFFh

0140000h-014FFFFh

0130000h-013FFFFh

0120000h-012FFFFh

0110000h-011FFFFh

0100000h-010FFFFh

00F0000h-00FFFFFh

00E0000h-00EFFFFh

00D0000h-00DFFFFh

00C0000h-00CFFFFh

00B0000h-00BFFFFh

00A0000h-00AFFFFh

0090000h-009FFFFh

0080000h-008FFFFh

0070000h-007FFFFh

0060000h-006FFFFh

0050000h-005FFFFh

0040000h-004FFFFh

0030000h-003FFFFh

0020000h-002FFFFh

0010000h-001FFFFh

0000000h-000FFFFh

Bank 14

Bank 15

BA8

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

[Table 22] Uniform OTP Block Addresses

Block Address

Block Size

(x16) Address Range*

A24 ~ A8

OTP

1FFFFh

512 words

1FFFE00h-1FFFFFFh

After entering OTP Block, any issued addresses should be in the range of OTP block address.

- 83 -


型号：	K8S1115ETC-DC1ET
厂家：	SAMSUNG
描述：	EEPROM Card, 32MX16, 95ns, Parallel, CMOS, PBGA64 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总83页 (文件大小：1511K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K8S1115ETC-DC1ET [SAMSUNG]

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