K7R320984C-FC30_技术文档

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

36Mb QDRII SRAM Specification

165 FBGA with Pb & Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.

ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-

lar applications where Product failure could result in loss of life or personal or physical harm, or any military

or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.1 August 2006

- 1 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

Document Title

1Mx36-bit, 2Mx18 and 4Mx9-bit QDR^TMII b4 SRAM

Revision History

Draft Date

Remark

Advance

Preliminary

Rev. No.

History

Jan. 17, 2006

Apr. 26. 2006

0.0

1. Initial document.

0.1

1. Put the data in the table of DC Characteristics, Pin Capacitance

and Thermal Resistance.

Preliminary

May. 4. 2006

0.2

1. Add 300MHz Bin

2. Change AC Characteristics.

Preliminary

Final

Jun. 05, 2006

Jun. 15, 2006

Jul. 10, 2006

0.3

0.4

1.0

1. Change Samsung JEDEC Code in ID REGISTER DEFINITION

1. Add x9 Organization.

1. Final

2. Change Vss/SA to NC/SA in Pin Configuration

Final

Aug. 23, 2006

1.1

1. Correct typo

Rev. 1.1 August 2006

- 2 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

TM

1Mx36-bit, 2Mx18 and 4Mx9-bit QDR II b4 SRAM

FEATURES

• 1.8V+0.1V/-0.1V Power Supply.

Part

Cycle Access

Time Time

• DLL circuitry for wide output data valid window and future fre-

quency scaling.

Org.

Unit

Number

• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,

1.8V+0.1V/-0.1V for 1.8V I/O.

• Separate independent read and write data ports

with concurrent read and write operation

• HSTL I/O

• Full data coherency, providing most current data.

• Synchronous pipeline read with self timed late write.

• Registered address, control and data input/output.

• DDR (Double Data Rate) Interface on read and write ports.

• Fixed 4-bit burst for both read and write operation.

• Clock-stop supports to reduce current.

• Two input clocks (K and K) for accurate DDR timing at clock

rising edges only.

K7R323684C-F(E)C(I)33 3.0

K7R323684C-F(E)C(I)30 3.3

K7R323684C-F(E)C(I)25 4.0

K7R321884C-F(E)C(I)33 3.0

K7R321884C-F(E)C(I)30 3.3

K7R321884C-F(E)C(I)25 4.0

K7R320984C-F(E)C(I)33 3.0

K7R320984C-F(E)C(I)30 3.3

K7R320984C-F(E)C(I)25 4.0

0.45

ns

X36

X18

X9

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches.

• Two echo clocks (CQ and CQ) to enhance output data

traceability.

* -F(E)C(I)

F(E) [Package type] : E-Pb Free, F-Pb

C(I) [Operating Temperature] : C-Commercial, I-Industrial

• Single address bus.

• Byte write (x9, x18, x36) function.

• Separate read/write control pin (R and W)

• Simple depth expansion with no data contention.

• Programmable output impedance.

• JTAG 1149.1 compatible test access port.

• 165FBGA(11x15 ball array) with body size of 15mmx17mm.

& Lead Free

• Operating in commercial and industrial temperature range.

FUNCTIONAL BLOCK DIAGRAM

36 (or 18)

DATA

REG

D (Data in)

72(or 36)

WRITE DRIVER

18

18 (or 19,20)

(or 19,20)

ADD

REG

ADDRESS

R

W

BWX

72

144

1Mx36

(2Mx18

4Mx9)

(or 36)

36 (or 18)

(or 72)

CTRL

Q (Data Out)

LOGIC

MEMORY

ARRAY

72

4 (or 2)

CQ, CQ

(or 36)

(Echo Clock out)

K

CLK

GEN

C

SELECT OUTPUT CONTROL

Notes: 1. Numbers in ( ) are for x18,x9 device

QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.

Rev. 1.1 August 2006

- 3 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7R323684C(1Mx36)

1

2

NC/SA*

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

3

NC/SA*

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

SA

4

5

6

7

8

9

10

NC/SA*

Q17

Q7

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

CQ

W

BW2

BW3

SA

K

BW1

BW0

SA

R

SA

Q27

D27

D28

Q29

Q30

D30

Doff

D31

Q32

Q33

D33

D34

Q35

TDO

SA

K

SA

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q9

VSS

VDDQ

VSS

SA

NC

VSS

SA

C

VSS

VDDQ

VSS

SA

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

D15

D6

Q14

D13

VREF

Q4

G

H

J

K

L

D3

Q11

Q1

M

N

P

R

D9

SA

D0

SA

C

SA

TMS

Notes : 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 3A for 72Mb, 10A for 144Mb and 2A for 288Mb.

2. BW⁰controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35.

PIN NAME

SYMBOL

K, K

PIN NUMBERS

DESCRIPTION

Input Clock

NOTE

6B, 6A

C, C

CQ, CQ

Doff

6P, 6R

11A, 1A

1H

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Address Inputs

1

SA

9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L

9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N

1C,1D,2E,1G,1J,2K,1M,1N,2P

D0-35

Data Inputs

11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L

9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N

3P,1B,2C,1E,1F,2J,1K,1L,2M,1P

Q0-35

Data Outputs

W

R

4A

8A

Write Control Pin, active when low

Read Control Pin, active when low

Block Write Control Pin, active when low

Input Reference Voltage

Output Driver Impedance Control Input

Power Supply (1.8 V)

BW0, BW1,BW2, BW3

7B,7A,5A,5B

2H,10H

VREF

ZQ

VDD

VDDQ

VSS

11H

2

3

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M, 8M,4N,8N

Output Power Supply (1.5V or 1.8V)

Ground

TMS

TDI

TCK

TDO

NC

10R

11R

2R

1R

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Clock

JTAG Test Data Output

No Connect

2A,3A,10A,6C

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to V^DDoutput impedance is set to minimum value and it cannot be connected to ground or left unconnected

3. Not connected to chip pad internally.

.

Rev. 1.1 August 2006

- 4 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7R321884C(2Mx18)

1

2

NC/SA*

Q9

3

4

5

6

7

8

9

SA

10

NC/SA*

NC

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

CQ

NC

Doff

NC

TDO

SA

W

BW1

NC

K

NC

R

D9

SA

K

BW0

SA

NC

VDDQ

NC

SA

NC

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

SA

VSS

VDDQ

VSS

SA

NC

VSS

SA

C

VSS

VDDQ

VSS

SA

Q7

D11

NC

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

NC

D6

Q12

D13

VREF

NC

G

H

J

NC

VREF

Q4

K

L

NC

D3

Q15

NC

M

N

P

R

Q1

D17

NC

SA

D0

TCK

SA

C

SA

TMS

Notes: 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.

2. BW⁰controls write to D0:D8 and BW1 controls write to D9:D17.

PIN NAME

SYMBOL

K, K

PIN NUMBERS

DESCRIPTION

Input Clock

NOTE

6B, 6A

C, C

CQ, CQ

Doff

6P, 6R

11A, 1A

1H

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Address Inputs

1

SA

3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D

3F,2G,3J,3L,3M,2N

D0-17

Data Inputs

11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E

2F,3G,3K,2L,3N,3P

Q0-17

Data Outputs

W

R

4A

8A

7B, 5A

2H,10H

11H

Write Control Pin, active when low

Read Control Pin, active when low

Block Write Control Pin, active when low

Input Reference Voltage

Output Driver Impedance Control Input

Power Supply (1.8 V)

BW0, BW1

VREF

ZQ

2

VDD

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

VDDQ

VSS

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply (1.5V or 1.8V)

Ground

4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

TMS

TDI

TCK

TDO

10R

11R

2R

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Clock

1R

JTAG Test Data Output

2A,10A,7A,1B,5B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,1F

9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M

2M,9M,1N,9N,10N,1P,2P,9P

NC

No Connect

3

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to V^DDoutput impedance is set to minimum value and it cannot be connected to ground or left unconnected

3. Not connected to chip pad internally.

.

Rev. 1.1 August 2006

- 5 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7R360984C(4Mx9)

1

2

NC/SA*

NC

3

SA

NC

Q4

NC

Q5

VDDQ

NC

D6

4

5

6

7

8

9

SA

10

SA

11

CQ

Q3

D3

NC

Q2

NC

ZQ

D1

NC

Q0

D0

NC

Q8

TDI

A

B

C

D

E

F

CQ

NC

Doff

NC

TDO

W

NC

SA

K

NC

BW

SA

R

SA

K

SA

NC

VDDQ

NC

SA

NC

D2

NC

VSS

VDDQ

VSS

SA

NC

VSS

SA

C

VSS

VDDQ

VSS

SA

D4

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

NC

VREF

Q1

G

H

J

D5

VREF

NC

K

L

NC

D8

Q6

M

N

P

R

NC

Q7

SA

D7

NC

SA

TCK

SA

C

SA

TMS

Notes: 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 2A for 72Mb.

2. BW controls write to D0:D8 .

PIN NAME

SYMBOL

K, K

PIN NUMBERS

DESCRIPTION

Input Clock

NOTE

6B, 6A

C, C

CQ, CQ

Doff

SA

D0-8

6P, 6R

11A, 1A

1H

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Address Inputs

1

3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

11M,11J,10E,11C,2D,2G,3L,2N,10P

11L,10J,11E,11B,3E,3G,2L,3P,11P

Data Inputs

Data Outputs

Q0-8

W

R

BW

VREF

ZQ

VDD

VDDQ

VSS

TMS

TDI

TCK

TDO

4A

8A

7B

2H,10H

Write Control Pin, active when low

Read Control Pin, active when low

Nybble Write Control Pin, active when low

Input Reference Voltage

Output Driver Impedance Control Input

Power Supply (1.8 V)

11H

2

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

Output Power Supply (1.5V or 1.8V)

Ground

10R

11R

2R

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Clock

JTAG Test Data Output

1R

2A,7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,6C,9C,10C,1D,3D,9D,

10D,11D,1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,

3J,9J,1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N

,9N,10N,11N,1P,2P,9P

NC

No Connect

3

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to V^DDoutput impedance is set to minimum value and it cannot be connected to ground or left unconnected

3. Not connected to chip pad internally.

.

Rev. 1.1 August 2006

- 6 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

GENERAL DESCRIPTION

The K7R323684C, K7R321884C and K7R320984C are 37,748,736-bits QDR (Quad Data Rate) Synchronous Pipelined Burst

SRAMs. They are organized as 1,048,576 words by 36bits for K7R323684C and 2,097,152 words by 18 bits for K7R321884C and

4,194,304 words by 9 bits for K7R320984C.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the

same cycle. Memory bandwidth is maximized as data can be transferred into SRAM on every rising edge of K and K, and transferred

out of SRAM on every rising edge of C and C. And totally independent read and write ports eliminate the need for high speed bus turn

around.

Address for read and write are latched on alternate rising edges of the input clock K. Data inputs, and all control signals are synchro-

nized to the input clock (K or K). Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high,

the data outputs are synchronized to the input clocks (K and K). Read data are referenced to echo clock (CQ or CQ) outputs.

Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 4-bit

sequential for both read and write operations, requiring tow full clock bus cycles. Any request that attempts to interrupt a burst opera-

tion in progress is ignored. Synchronous pipeline read and late write enable high speed operations. Simple depth expansion is

accomplished by using R and W for port selection. Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins. IEEE

1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

The K7R323684C, K7R321884C and K7R320984C are implemented with SAMSUNG's high performance 6T CMOS technology and

is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K. Address is presented and stored in the read

address register synchronized with K clock. For 4-bit burst DDR operation, it will access four 36-bit, 18-bit or 9-bit data words with

each read command.

The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge. Next burst data is trig-

gered by the rising edge of following C clock rising edge. The process continues until all four data are transferred. Continuous read

operations are initiated with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both C and

C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the R is disabled after a read operation, the K7R323684C, K7R321884C and K7R320984C will first complete burst read oper-

ation before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high imped-

ance state.

Write Operations

Write cycles are initiated by activating W at the rising edge of the positive input clock K. Address is presented and stored in the write

address register synchronized with K clock. For 4-bit burst DDR operation, it will write four 36-bit, 18-bit or 9-bit data words with each

write command.

The first “late” data is transferred and registered in to the device synchronous with next K clock rising edge. Next burst data is trans-

ferred and registered synchronous with following K clock rising edge. The process continues until all four data are transferred and

registered. Continuous write operations are initiated with K rising edge. And “late write” data is presented to the device on every ris-

ing edge of both K and K clocks.

The device disregards input data presented on the same cycle W disabled. When the W is disabled after a read operation, the

K7R323684C, K7R321884C and K7R320984C will first complete burst read operation before entering into deselect mode at the next

K clock rising edge.

The K7R323684C, K7R321884C and K7R320984C support byte write operations. With activating BW0 or BW1 (BW2 or BW3) in write

cycle, only one byte of input data is presented. In K7R321884C, BW0 controls write operation to D0:D8, BW1 controls write operation

to D9:D17. And in K7R323684C BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35. And in

K7R320984C BW controls write operation to D0:D8.

Rev. 1.1 August 2006

- 7 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

Single Clock Mode

The K7R323684C, K7R321884C and K7R320984C can be operated with the single clock pair K and K, instead of C or C for output

clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high dur-

ing operation. After power up, this device can’t change to or from single clock mode. System flight time and clock skew could not be

compensated in this mode.

Depth Expansion

Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read

and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed.

Programmable Impedance Output Buffer Operation

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).

The value of RQ (within 15%) is five times the output impedance desired. For example, 250Ω resistor will give an output impedance

of 50Ω.

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates

are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the

SRAM needs 1024 non-read cycles.

Echo clock operation

To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are syn-

chronized with internal data output. Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.

Clock Consideration

K7R323684C, K7R321884C and K7R320984C utilizes internal DLL (Delay-Locked Loops) for maximum output data valid window. It

can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.

Circuitry automatically resets the DLL when absence of input clock is detected.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied

simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ

does not exceed VDD by more than 0.5V during power-down.

Rev. 1.1 August 2006

- 8 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

Detail Specification of Power-Up Sequence in QDRII SRAM

QDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

• Power-Up Sequence

1. Apply power and keep Doff at low state (All other inputs may be undefined)

- Apply VDD before VDDQ

- Apply VDDQ before VREF or the same time with VREF

2. Just after the stable power and clock (K, K, C, C), take Doff to be high.

3. The additional 1024cycles of clock input is required to lock the DLL after enabling DLL

* Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds

(Min. 30ns) to reset the DLL after it become a stable clock status.

• DLL Constraints

1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as TKC var.

2. The lower end of the frequency at which the DLL can operate is 8.4ns.

3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency

and this may cause the failure in the initial stage.

Power up & Initialization Sequence (Doff pin controlled)

K,K

1024 cycle

Unstable

Any

Power-Up

DLL Locking Range

Inputs Clock

Status

CLKstage

Command

must be stable

V

DD

V

DDQ

V

REF

Doff

Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)

K,K

Min 30ns

1024 cycle

Unstable

Any

Stop Clock

Power-Up

DLL Locking Range

Inputs Clock

Status

CLKstage

Command

must be stable

V

DD

V

DDQ

V

REF

* Notes: When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 1024 cycles of clock input is needed to lock the DLL.

Rev. 1.1 August 2006

- 9 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

D

Q

K

R

W

OPERATION

D(A1)

D(A2)

D(A3)

D(A4)

Q(A1)

Q(A2)

Q(A3)

Q(A4)

Previous Previous Previous Previous Previous Previous Previous Previous

Stopped

X

H

X

H

X

Clock Stop

state

High-Z

DOUT

state

High-Z

DOUT

state

High-Z

DOUT

state

↑

X

High-Z No Operation

DOUT

Read

L⁴

X

at C(t+1) at C(t+2) at C(t+2) at C(t+3)

Din

H⁵

L⁴

↑

X

Write

at K(t+1) at K(t+1) at K(t+2) at K(t+2)

Notes: 1. X means "Don′t Care”.

2. The rising edge of clock is symbolized by ( ↑ ).

3. Before enter into clock stop status, all pending read and write operations will be completed.

4. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive K clock rising edges

is not permitted. The device will ignore the second request.

5. If this signal was LOW to initiated the previous cycle, this signal becomes a don′t care for this operation however it is strongly recommended

that this signal is brought HIGH as shown in the truth table.

WRITE TRUTH TABLE(x18)

K

↑

BW0

L

BW1

L

OPERATION

WRITE ALL BYTEs ( K↑ )

WRITE BYTE 0 ( K↑ )

↑

L

↑

L

H

L

H

WRITE BYTE 0 ( K↑ )

↑

H

L

WRITE BYTE 1 ( K↑ )

H

L

WRITE BYTE 1 ( K↑ )

↑

H

WRITE NOTHING ( K↑ )

H

Notes: 1. X means “Don′t Care”.

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).

3. Assumes a WRITE cycle was initiated.

4. This table illustrates operation for x18 devices. x9 device operation is similar except that BW controls D0:D8.

WRITE TRUTH TABLE(x36)

K

↑

BW0

L

BW1

L

BW2

L

BW3

L

OPERATION

WRITE ALL BYTEs ( K↑ )

WRITE BYTE 0 ( K↑ )

↑

L

↑

L

H

L

H

L

H

L

WRITE BYTE 0 ( K↑ )

H

WRITE BYTE 1 ( K↑ )

L

WRITE BYTE 1 ( K↑ )

H

WRITE BYTE 2 and BYTE 3 ( K↑ )

WRITE NOTHING ( K↑ )

L

H

Notes: 1. X means “Don′t Care”.

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (↑ ).

3. Assumes a WRITE cycle was initiated.

Rev. 1.1 August 2006

- 10 -

K7R323684C

K7R321884C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

K7R320984C

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on VDDQ Supply Relative to VSS

Voltage on Input Pin Relative to VSS

Storage Temperature

SYMBOL

VDD

RATING

-0.5 to 2.9

UNIT

V

VDDQ

VIN

-0.5 to VDD

V

-0.5 to VDD+0.3

-65 to 150

V

TSTG

TOPR

TBIAS

°C

Operating Temperature

Commercial / Industrial

0 to 70 / -40 to 85

-10 to 85

Storage Temperature Range Under Bias

*Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. V^DDQmust not exceed VDD during normal operation.

OPERATING CONDITIONS

PARAMETER

SYMBOL

VDD

Min

1.7

MAX

1.9

UNIT

V

Supply Voltage

Reference Voltage

VDDQ

1.4

1.9

VREF

0.68

0.95

DC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

TEST CONDITIONS

VDD=Max; VIN=VSS to VDDQ

MIN

MAX

+2

UNIT NOTES

Input Leakage Current

Output Leakage Current

IIL

-2

-

µA

IOL

Output Disabled,

+2

-33

-30

-25

-33

-30

-25

-33

-30

-25

-33

-30

-25

850

800

750

800

750

700

750

700

650

350

330

300

VDD=Max, IOUT=0mA

Cycle Time ≥ tKHKH Min

Operating Current (x36)

Operating Current (x18)

Operating Current (x9)

Standby Current (NOP)

ICC

ISB1

-

mA

1,5

1,6

-

VDD=Max, IOUT=0mA

Cycle Time ≥ tKHKH Min

-

VDD=Max, IOUT=0mA

Cycle Time ≥ tKHKH Min

-

Device deselected, IOUT=0mA, f=Max,

All Inputs≤0.2V or ≥ VDD-0.2V

-

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Input Low Voltage

Input High Voltage

VOH1

VOL1

VOH2

VOL2

VIL

VDDQ/2-0.12 VDDQ/2+0.12

V

2,7

3,7

4

IOH=-1.0mA

IOL=1.0mA

VDDQ-0.2

VSS

VDDQ

0.2

4

-0.3

VREF-0.1

VDDQ+0.3

8,9

8,10

VIH

VREF+0.1

Notes: 1. Minimum cycle. IOUT=0mA.

2. |I^OH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.

3. |I^OL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.

4. Minimum Impedance Mode when ZQ pin is connected to V^DD.

5. Operating current is calculated with 50% read cycles and 50% write cycles.

6. Standby Current is only after all pending read and write burst operations are completed.

7. Programmable Impedance Mode.

8. These are DC test criteria. DC design criteria is V^REF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.

9. V^IL(Min) DC=-0.3V, VIL (Min) AC=-1.5V(pulse width ≤ 3ns).

10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns)

Rev. 1.1 August 2006

- 11 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

AC ELECTRICAL CHARACTERISTICS

PARAMETER

Input High Voltage

Input Low Voltage

SYMBOL

MIN

MAX

-

UNIT

V

NOTES

1,2

VIH (AC)

VIL (AC)

VREF + 0.2

-

VREF - 0.2

V

1,2

Notes: 1. This condition is for AC function test only, not for AC parameter test.

2. To maintain a valid level, the transiting edge of the input must:

a) Sustain a constant slew rate from the current AC level through the target AC level, V^IL(AC)or VIH(AC)

b) Reach at least the target AC level

c) After the AC target level is reached, continue to maintain at least the target DC level, V^IL(DC)or VIH(DC)

AC TIMING CHARACTERISTICS

-33

-30

-25

PARAMETER

SYMBOL

UNIT

NOTE

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock Cycle Time (K, K, C, C)

Clock Phase Jitter (K, K, C, C)

Clock High Time (K, K, C, C)

Clock Low Time (K, K, C, C)

Clock to Clock (K↑ → K↑, C↑ → C↑)

Clock to data clock (K↑ → C↑, K↑→ C↑)

DLL Lock Time (K, C)

tKHKH

tKC var

tKHKL

3.00

8.40

0.20

3.30

8.40

0.20

4.00

8.40

0.20

ns

5

1.2

1.32

1.49

0.00

1024

30

1.60

1.80

0.00

1024

30

ns

tKLKH

ns

tKHKH

tKHCH

tKC lock

tKC reset

1.35

0.00

1024

30

ns

1.30

1.45

1.80

ns

cycle

ns

6

K Static to DLL reset

Output Times

C, C High to Output Valid

C, C High to Output Hold

C, C High to Echo Clock Valid

C, C High to Echo Clock Hold

CQ, CQ High to Output Valid

CQ, CQ High to Output Hold

C, High to Output High-Z

C, High to Output Low-Z

Setup Times

tCHQV

tCHQX

0.45

0.25

0.45

0.27

0.45

0.30

0.45

ns

3

-0.45

-0.25

-0.45

-0.27

-0.45

-0.30

-0.45

tCHCQV

tCHCQX

tCQHQV

tCQHQX

tCHQZ

7

3

tCHQX1

Address valid to K rising edge

Control inputs valid to K rising edge

Data-in valid to K, K rising edge

Hold Times

tAVKH

tIVKH

0.40

0.28

0.40

0.30

0.50

0.35

ns

2

tDVKH

K rising edge to address hold

K rising edge to control inputs hold

K, K rising edge to data-in hold

tKHAX

tKHIX

0.40

0.28

0.40

0.30

0.50

0.35

ns

tKHDX

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.

2. Control singles are R, W,BW0,BW1 and (BW2, BW3, also for x36 and BW for x9)

3. If C,C are tied high, K,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX¹is bigger than tCHQZ.

The specs as shown do not imply bus contention because tCHQX¹is a MIN parameter that is worst case at totally different test conditions

(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.

7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1 ns variation from echo clock to data.

The data sheet parameters reflect tester guard bands and test setup variations.

Rev. 1.1 August 2006

- 12 -

K7R323684C

K7R321884C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

K7R320984C

THERMAL RESISTANCE

PRMETER

Junction to Ambient

Junction to Case

SYMBOL

θJA

TYP

20.8

2.3

Unit

°C/W

NOTES

θJC

Junction to Pins

θJB

4.3

Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site

thermal impedance. T^J=TA + PD x θJA

PIN CAPACITANCE

PRMETER

Address Control Input Capacitance

Input and Output Capacitance

Clock Capacitance

SYMBOL

CIN

TESTCONDITION

TYP

3.5

4

MAX

Unit

pF

NOTES

VIN=0V

VOUT=0V

-

4

5

4

COUT

pF

CCLK

3

pF

Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.

2. Periodically sampled and not 100% tested.

AC TEST CONDITIONS

AC TEST OUTPUT LOAD

Parameter

Symbol

VDD

Value

1.7~1.9

1.4~1.9

1.25/0.25

0.75

Unit

V

0.75V

Core Power Supply Voltage

Output Power Supply Voltage

Input High/Low Level

VREF

VDDQ/2

VDDQ

VIH/VIL

VREF

V

50Ω

V

SRAM

Zo=50Ω

Input Reference Level

V

250Ω

Input Rise/Fall Time

TR/TF

0.3/0.3

VDDQ/2

ns

V

ZQ

Output Timing Reference Level

Note: Parameters are tested with RQ=250Ω

Overershoot Timing

Undershoot Timing

20% tKHKH(MIN)

VIH

VDDQ+0.5V

VDDQ+0.25V

VDDQ

VSS

VSS-0.25V

VSS-0.5V

20% tKHKH(MIN)

VIL

Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms

Rev. 1.1 August 2006

- 13 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

APPLICATION INRORMATION

R=250Ω

ZQ

SRAM#1

SRAM#4

CQ

Q

CQ

Q

Vt

D

SA

R

SA

R W BW0 BW1 C C K K

RW BW0 BW1 C C K K

Data In

Vt

Data Out

Address

R

W

BW

MEMORY

CONTROLLER

Return CLK

Vt

Source CLK

Return CLK

Source CLK

Vt

R=50Ω Vt=VREF

SRAM1 Input CQ

SRAM4 Input CQ

Rev. 1.1 August 2006

- 14 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

TIMING WAVE FORMS OF READ AND NOP

READ

NOP

tKHKH

tKLKH

K

tKHKH

tKHKL

K

tAVKH tKHAX

SA

R

A1

A2

tIVKH tKHIX

tCHQX1

Q

Q1-1

Q1-2

tCHQX

Q1-3

Q1-4

Q2-1

Q2-2

Q2-3

Q2-4

(Data Out)

tKHKH

tKHCH

tCHQV

tKLKH

C

tKHKL

tKHKH

tCHQZ

C

tCHCQV

tCHCQX

tCHQV

tCQHQV

CQ

tCQHQX

tCHCQV

tCHCQX

Don′t Care

Undefined

Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.

2. Outputs are disabled one cycle after a NOP.

TIMING WAVE FORMS OF WRITE AND NOP

WRITE

NOP

tKHKH

tKLKH

K

tKHKH

tKHKL

K

tAVKH tKHAX

SA

A1

A2

tIVKH tKHIX

tKHIX

W

D (Data In)

D1-1

D1-2

D1-3

D1-4

D2-1

D2-2

D2-3

D2-4

tDVKH

tKHDX

Don′t Care

Undefined

Note: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+0.

2. BWx (NWx) assumed active.

Rev. 1.1 August 2006

- 15 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

TIMING WAVE FORMS OF READ, WRITE AND NOP

READ

WRITE

READ

WRITE

NOP

K

SA

W

A1

A2

A3

A4

R

D (Data In)

D2-1

Q1-1

D2-2

Q1-2

D2-3

Q1-3

D2-4

Q1-4

D4-1

D4-2

Q3-2

D4-3

D (Data Out)

Q3-1

Q3-3

C

Don′t Care

Undefined

Note: 1. If address A3=A2, data Q3-1=D2-1, data Q3-2=D2-2 , data Q3-3=D2-3, data Q3-4=D2-4

Write data is forwarded immediately as read results.

2.BWx ( NWx) assumed active.

Rev. 1.1 August 2006

- 16 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

IDCODE

SAMPLE-Z

Boundary Scan Register

Identification Register

Boundary Scan Register

1

3

2

6

5

6

4

0

RESERVED Do Not Use

A,D

K,K

C,C

1

SAMPLE

Boundary Scan Register

1

RESERVED Do Not Use

SRAM

CORE

1

Q

CQ

BYPASS

Bypass Register

CQ

NOTE:

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

TDI

BYPASS Reg.

Identification Reg.

Instruction Reg.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

TDO

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V^SSwhen BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

Control Signals

TAP Controller

TMS

TCK

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

1

Run Test Idle

Select DR

0

Capture DR

0

Shift DR

1

Exit1 DR

0

Select IR

0

1

Capture IR

0

Shift IR

1

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 IR

1

Exit2 DR

1

0

Update DR

0

Update IR

1

Rev. 1.1 August 2006

- 17 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

32 bits

Boundary Scan

109 bits

1Mx36

2Mx18

4Mx9

3 bits

1 bit

109 bits

32 bits

ID REGISTER DEFINITION

Revision Number

Part Configuration

(28:12)

00def0wx0t0q0b0s0

Samsung JEDEC Code

(11: 1)

Part

Start Bit(0)

(31:29)

000

1Mx36

2Mx18

00011001110

1

4Mx9

000

Note : Part Configuration

/def=010 for 36Mb, /wx=11 for x36, 10 for x18 and 00 for x9

/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O

BOUNDARY SCAN EXIT ORDER

ORDER

PIN ID

ORDER

PIN ID

10D

9E

ORDER

73

PIN ID

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

2G

1H

1J

2J

3K

3J

2K

1K

2L

3L

1M

1L

3N

3M

1N

2M

3P

2N

2P

1P

3R

4R

4P

5P

5N

5R

Internal

1

2

6R

6P

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

3

4

6N

7P

10C

11D

9C

9D

11B

11C

9B

10B

11A

10A

9A

5

6

7N

7R

7

8

8R

8P

9

9R

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

11P

10P

10N

9P

10M

11N

9M

9N

11L

11M

9L

10L

11K

10K

9J

8B

7C

6C

8A

7A

7B

6B

6A

5B

5A

4A

5C

4B

3A

2A

1A

2B

3B

1C

1B

9K

98

99

10J

11J

11H

10G

9G

11F

11G

9F

100

101

102

103

104

105

106

107

108

109

10F

11E

10E

3D

3C

1D

Note: 1. NC pins are read as "X" (i.e. don′t care.)

Rev. 1.1 August 2006

- 18 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

JTAG DC OPERATING CONDITIONS

Parameter

Symbol

Min

1.7

Typ

Max

1.9

Unit

V

Note

Power Supply Voltage

VDD

VIH

1.8

Input High Level

1.3

-

VDD+0.3

0.5

V

Input Low Level

VIL

-0.3

1.4

V

Output High Voltage(IOH=-2mA)

Output Low Voltage(IOL=2mA)

VOH

VOL

VDD

V

VSS

0.4

V

Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.

JTAG AC TEST CONDITIONS

Parameter

Symbol

VIH/VIL

TR/TF

Min

1.8/0.0

1.0/1.0

0.9

Unit

V

Note

Input High/Low Level

Input Rise/Fall Time

ns

V

Input and Output Timing Reference Level

Note: 1. See SRAM AC test output load on page 11.

1

JTAG AC Characteristics

Parameter

Symbol

Min

50

20

5

Max

Unit

Note

TCK Cycle Time

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

-

5

-

5

-

5

-

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

-

5

-

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCLCH

tCHCL

tMVCH

tCHMX

TMS

TDI

tDVCH

tSVCH

tCHDX

tCHSX

PI

(SRAM)

tCLQV

TDO

Rev. 1.1 August 2006

- 19 -

K7R323684C

K7R321884C

K7R320984C

1Mx36, 2Mx18 & 4Mx9 QDR^TMII b4 SRAM

165 FBGA PACKAGE DIMENSIONS (Lead & Lead-Free)

15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

B

Top View

A

C

Side View

D

A

G

E

B

F

Bottom View

H ∅

E

Symbol

Value

15 ± 0.1

Units

Note

Symbol

Value

1.0

Units

mm

Note

A

B

C

D

mm

E

F

17 ± 0.1

1.3 ± 0.1

0.35 ± 0.05

14.0

G

H

10.0

0.5 ± 0.05

Rev. 1.1 August 2006

- 20 -


型号：	K7R320984C-FC30
厂家：	SAMSUNG
描述：	Standard SRAM, 4MX9, 0.45ns, CMOS, PBGA165 静态存储器
文件：	总20页 (文件大小：457K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7R320984C-FC30 [SAMSUNG]

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