K7N641845M-QC25_技术文档

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

Document Title

2Mx36 & 4Mx18-Bit Pipelined NtRAM^TM

Revision History

Draft Date

Remark

Rev. No.

History

Advance

Sep. 30. 2002

Oct. 8. 2002

0.0

1. Initial document.

Preliminary

0.1

1. Delete the speed bins (FT : 7.5ns, 8.5ns / PP : 200MHz)

1. Change to the New JTAG scan order.

1. Add the comment about Vdd/Vddq wide by note on page 13.

1. Delete the 119 BGA package type.

Feb. 25, 2003

Mar. 10, 2003

Aug. 18, 2004

Oct. 20, 2004

0.2

0.3

0.4

0.5

1. Delete the 1.8V and 3.3V Vdd voltage level

( Change the part number to K7N6436(18)45M from K7N6436(18)31M )

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Oct. 2004

Rev 0.5

- 1 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

64Mb NtRAM (Pipelined) Ordering Information

Speed

Org.

Part Number

Mode

VDD

FT ; Access Time(ns)

PKG

Temp

Pipelined ; Cycle Time(MHz)

4Mx18 K7N641845M-Q(F)C25/16

2Mx36 K7N643645M-Q(F)C25/16

Pipelined

2.5V

250/167MHz

C

Q:100TQFP

F:165FBGA

(Commercial

Temp.Range)

Oct. 2004

Rev 0.5

- 2 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

2Mx36 & 4Mx18-Bit Pipelined NtRAM^TM

FEATURES

GENERAL DESCRIPTION

• 2.5V ±5% Power Supply.

The K7N643645M and K7N641845M are 75,497,472-bits Syn-

• Byte Writable Function.

chronous Static SRAMs.

The NtRAM^TM, or No Turnaround Random Access Memory uti-

lizes all the bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input clock.

Burst order control must be tied "High or Low".

• Enable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data

contention .

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

• TTL-Level Three-State Outputs.

• 100-TQFP-1420A.

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-chip

write pulse generation

• 165FBGA(11x15 ball aray) with body size of 15mmx17mm.

and provides increased timing flexibility for incoming signals.

For read cycles, pipelined SRAM output data is temporarily

stored by an edge triggered output register and then released

to the output buffers at the next rising edge of clock.

The K7N643645M and K7N641845M are implemented with

SAMSUNG′s high performance CMOS technology and is avail-

able in 100pin TQFP and 165FBGA packages. Multiple power

and ground pins minimize ground bounce.

FAST ACCESS TIMES

PARAMETER

Cycle Time

Symbol

tCYC

tCD

-25

4.0

2.6

-16

6.0

3.5

Unit

ns

Clock Access Time

ns

Output Enable Access Time

tOE

ns

LOGIC BLOCK DIAGRAM

LBO

BURST

ADDRESS

COUNTER

A′0~A′1

A [0:20]or

A [0:21]

A0

~A

1

2Mx36, 4Mx18

MEMORY

ARRAY

ADDRESS

REGISTER

A2~A20 or A2~A21

WRITE

ADDRESS

REGISTER

WRITE

ADDRESS

REGISTER

DATA-IN

CLK

K

REGISTER

CKE

DATA-IN

REGISTER

CS

1

2

ADV

WE

CONTROL

LOGIC

OUTPUT

K

BW

x

REGISTER

(x=a,b,c,d or a,b)

BUFFER

OE

ZZ

36 or 18

DQa

0 ~ DQd7 or DQa0 ~ DQb8

DQPa ~ DQPd

NtRAM^TMand No Turnaround Random Access Memory are trademarks of Samsung.

Oct. 2004

Rev 0.5

- 3 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

DQPc

1

DQPb

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc0

2

DQc1

3

VDDQ

4

VSSQ

5

DQc2

6

DQc3

7

DQc4

8

DQc5

9

VSSQ

10

VDDQ

11

DQc6

12

100 Pin TQFP

(20mm x 14mm)

DQc7

13

VDD

14

VDD

15

VDD

ZZ

VDD

16

VSS

17

DQd0

18

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

DQd1

19

K7N643645M(2Mx36)

VDDQ

20

VSSQ

21

DQd2

22

DQd3

23

DQd4

24

DQd5

25

VSSQ

26

VDDQ

27

DQd6

28

DQd7

29

DQPd

30

PIN NAME

SYMBOL

PIN NAME

Address Inputs

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A20

32,33,34,35,36,37,42, VDD

43,44,45,46,47,48,49, VSS

50,81,82,83,84,99,

100

85

Power Supply(2.5V) 14,15,16,41,65,66,91

Ground

17,40,67,90

38,39

No Connect

N.C.

ADV

WE

Address Advance/Load

Read/Write Control Input 88

Clock

Clock Enable

Chip Select

Data Inputs/Outputs 52,53,56,57,58,59,62,63

Data Inputs/Outputs 68,69,72,73,74,75,78,79

Data Inputs/Outputs 2,3,6,7,8,9,12,13

Data Inputs/Outputs 18,19,22,23,24,25,28,29

Data Inputs/Outputs 51,80,1,30

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

CLK

CKE

CS1

CS2

89

87

98

97

92

BWx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

Output Power Supply 4,11,20,27,54,61,70,77

(2.5V)

VDDQ

VSSQ

OE

ZZ

Output Enable

Power Sleep Mode

Burst Mode Control

86

64

31

Output Ground

5,10,21,26,55,60,71,76

LBO

Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

Oct. 2004

Rev 0.5

- 4 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

VDDQ

VSSQ

N.C.

1

2

3

4

5

6

7

8

N.C.

VDDQ

VSSQ

N.C.

DQa0

DQa1

DQa2

VSSQ

VDDQ

DQa3

DQa4

VSS

N.C.

DQb8

DQb7

VSSQ

VDDQ

DQb6

DQb5

VDD

VSS

DQb4

DQb3

VDDQ

VSSQ

DQb2

DQb1

DQb0

N.C.

VSSQ

VDDQ

N.C.

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

(20mm x 14mm)

VDD

ZZ

DQa5

DQa6

VDDQ

VSSQ

DQa7

DQa8

N.C.

VSSQ

VDDQ

N.C.

K7N641845M(4Mx18)

PIN NAME

SYMBOL

PIN NAME

Address Inputs

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A21

32,33,34,35,36,37,42, VDD

43,44,45,46,47,48,49, VSS

50,80,81,82,83,84,99,

Power Supply(2.5V) 14,15,16,41,65,66,91

Ground

17,40,67,90

100

85

No Connect

1,2,3,6,7,25,28,29,30,

38,39,51,52,53,56,57,

75,78,79,95,96

N.C.

ADV

WE

Address Advance/Load

Read/Write Control Input 88

CLK

CKE

CS1

CS2

Clock

89

87

98

97

Clock Enable

Chip Select

Data Inputs/Outputs 58,59,62,63,68,69,72,73,74

Data Inputs/Outputs 8,9,12,13,18,19,22,23,24

DQa0~a8

DQb0~b8

92

BWx(x=a,b) Byte Write Inputs

93,94

86

64

Output Power Supply 4,11,20,27,54,61,70,77

(2.5V)

VDDQ

VSSQ

OE

ZZ

Output Enable

Power Sleep Mode

Burst Mode Control

Output Ground

5,10,21,26,55,60,71,76

LBO

31

NOTE : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

Oct. 2004

Rev 0.5

- 5 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7N643645M(2Mx36)

1

2

3

4

5

6

7

8

9

10

A

11

NC

CS2

NC**

NC

A

CS1

BWc

BWd

VSS

VDD

VSS

A

BWb

BWa

VSS

NC

CKE

WE

ADV

OE

A

B

C

D

E

F

A

CS2

CLK

VSS

NC

A

NC**

DQPb

DQb

ZZ

DQPc

DQc

NC

DQc

VDD

DQd

NC

A

VDDQ

NC

VSS

NC

VSS

VDD

VSS

A

VDDQ

NC

DQb

NC

DQa

NC

A

G

H

J

DQd

DQPd

NC

VDDQ

A

VDDQ

A

DQa

DQPa

NC

K

L

M

N

P

R

TDI

A1*

TDO

TCK

LBO

A

TMS

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

** Checked NoConnect(NC) pins are resered for higher density address, i.e. 11B for 128Mb and 1A for 256Mb.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

CLK

CKE

CS1

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

N.C.

No Connect

DQa

DQb

DQc

DQd

Data Inputs/Outputs

CS2

Chip Select

DQPa~Pd

BWx

(x=a,b,c,d)

Byte Write Inputs

VDDQ

Output Power Supply

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

Oct. 2004

Rev 0.5

- 6 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7N641845M(4Mx18)

1

NC**

NC

2

A

3

4

5

6

7

8

9

10

A

11

A

CS2

CS1

BWb

NC

CKE

WE

ADV

OE

A

B

C

D

E

F

A

CS2

BWa

VSS

NC

CLK

VSS

NC

A

NC**

DQPa

DQa

ZZ

NC

DQb

VDD

NC

A

VDDQ

NC

VSS

VDD

VSS

A

VSS

NC

VSS

VDD

VSS

A

VDDQ

NC

DQa

NC

A

NC

G

H

J

NC

DQb

DQPb

NC

VDDQ

A

VDDQ

A

NC

K

L

NC

M

N

P

R

NC

TDI

A1*

TDO

TCK

NC

LBO

A

TMS

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

** Checked NoConnect(NC) pins are resered for higher density address, i.e. 11B for 128Mb and 1A for 256Mb.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

CLK

CKE

CS1

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

No Connect

N.C.

Data Inputs/Outputs

DQa

DQb

DQPa, Pb

CS2

Chip Select

CS2

Chip Select

BWx

(x=a,b)

Byte Write Inputs

Output Power Supply

VDDQ

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

Oct. 2004

Rev 0.5

- 7 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

FUNCTION DESCRIPTION

The K7N643645M and K7N641845M are NtRAM^TMdesigned to sustain 100% bus bandwidth by eliminating turnaround cycle when

there is transition from Read to Write, or vice versa.

All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the

burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next

operation.

Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous

inputs are ignored and the internal device registers will hold their previous values.

NtRAM^TMlatches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)

are active .

Output Enable(OE) can be used to disable the output at any given time.

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the

address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven

high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data

is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must

be driven low for the device to drive out the requested data.

Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-

lined NtRAM^TMuses a late-late write cycle to utilize 100% of the bandwidth.

At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle

later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is

provided by the external address. The burst address counter wraps around to its initial state upon completion.

The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.

And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At

this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up

time.

BURST SEQUENCE TABLE

(Interleaved Burst, LBO=High)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst, LBO=Low)

Case 4

Case 1

Case 2

Case 3

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

Oct. 2004

Rev 0.5

- 8 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

STATE DIAGRAM FOR NtRAM^TM

WRITE

READ

BEGIN

READ

BEGIN

WRITE

READ

R

S

E

D

T

I

A

D

R

W

D

S

B

W

R

U

T

DESELECT

R

S

D

S

I

T

R

A

T

E

U

E

B

R

S

D

S

BURST

READ

BURST

WRITE

BURST

COMMAND

ACTION

DS

DESELECT

READ

WRITE

BEGIN READ

BEGIN WRITE

BEGIN READ

BURST

BEGIN WRITE

CONTINUE DESELECT

Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does

not change the state of the device.

2. States change on the rising edge of the clock(CLK)

Oct. 2004

Rev 0.5

- 9 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1 CS2 CS2 ADV WE BWx OE

CKE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

H

X

L

X

L

X

H

X

L

X

H

X

H

X

L

X

L

X

L

H

↑

N/A

Not Selected

X

H

X

H

X

H

X

H

X

L

N/A

Not Selected

H

L

N/A

Not Selected Continue

Begin Burst Read Cycle

Continue Burst Read Cycle

NOP/Dummy Read

Dummy Read

External Address

Next Address

External Address

Next Address

External Address

Next Address

N/A

X

L

X

L

H

L

H

X

L

X

L

H

L

Begin Burst Write Cycle

Continue Burst Write Cycle

NOP/Write Abort

Write Abort

X

L

X

L

H

L

X

L

H

X

H

X

Next Address

Current Address

Ignore Clock

Notes : 1. X means "Don′t Care".

2. The rising edge of clock is symbolized by (↑).

3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE(x36)

WE

H

L

BWa

X

BWb

X

BWc

X

BWd

X

OPERATION

READ

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

L

H

L

H

L

H

L

H

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

WRITE TRUTH TABLE(x18)

WE

BWa

X

BWb

OPERATION

H

X

H

L

READ

L

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

Oct. 2004

Rev 0.5

- 10 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

ASYNCHRONOUS TRUTH TABLE

Notes

OPERATION

ZZ

H

L

OE

X

I/O STATUS

High-Z

1. X means "Don′t Care".

2. Sleep Mode means power Sleep Mode of which stand-by current does

not depend on cycle time.

3. Deselected means power Sleep Mode of which stand-by current

depends on cycle time.

Sleep Mode

L

DQ

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

Deselected

L

X

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on Any Other Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 3.6

-0.3 to VDD+0.3

1.6

UNIT

V

VIN

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Operating Temperature

Storage Temperature Range Under Bias

-10 to 85

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS(0°C ≤ TA ≤ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

MIN

2.375

0

Typ.

2.5

0

MAX

2.625

0

UNIT

VDD

V

VDDQ

VSS

*Note : VDD and VDDQ must be supplied with identical vlotage levels.

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

SYMBOL

TEST CONDITION

VIN=0V

TYP

MAX

UNIT

pF

Input Capacitance

CIN

-

TBD

Output Capacitance

COUT

VOUT=0V

pF

*Note : Sampled not 100% tested.

Oct. 2004

Rev 0.5

- 11 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

DC ELECTRICAL CHARACTERISTICS(VDD=2.5V ±5%, TA=0°C to +70°C)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

+2

UNIT NOTES

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

VDD=Max ; VIN=VSS to VDD

-2

-

µA

IOL

Output Disabled,

+2

-25

-16

-25

TBD

VDD=Max IOUT=0mA

Operating Current

Standby Current

ICC

mA

1,2

Cycle Time ≥ tCYC Min

-

Device deselected, IOUT=0mA,

ZZ≤VIL, f=Max,

-

ISB

mA

-16

-

TBD

All Inputs≤0.2V or ≥ VDD-0.2V

Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,

ISB1

ISB2

mA

All Inputs=fixed (VDD-0.2V or 0.2V)

Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,

f=Max, All Inputs≤VIL or ≥VIH

Output Low Voltage

Output High Voltage

Input Low Voltage

Input High Voltage

VOL

VOH

VIL

IOL=1.0mA

IOH=-1.0mA

-

0.4

V

2.0

-0.3*

1.7

-

0.7

VIH

VDD+0.3**

3

Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.

2. Data states are all zero.

3. In Case of I/O Pins, the Max. V^IH=VDDQ+0.3V

VIH

VSS

VSS-0.4V

VSS-0.8V

20% tCYC(MIN)

TEST CONDITIONS

(TA=0 to 70°C, VDD=2.5V ±5%, unless otherwise specified)

PARAMETER

Input Pulse Level

VALUE

0 to 2.5V

1.0V/ns

Input Rise and Fall Time(Measured at 20% to 80%)

Input and Output Timing Reference Levels

Output Load

VDDQ/2

See Fig. 1

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

+2.5V

Dout

RL=50Ω

1667Ω

VL=VDDQ/2

Dout

1538Ω

30pF*

Zo=50Ω

5pF*

* Including Scope and Jig Capacitance

Fig. 1

Oct. 2004

Rev 0.5

- 12 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

AC TIMING CHARACTERISTICS

(VDD=2.5V ±5%, TA=0 to 70°C)

-25

-16

PARAMETER

SYMBOL

UNIT

MIN

4.0

-

MAX

MIN

6.0

-

MAX

Cycle Time

tCYC

tCD

-

ns

Clock Access Time

2.6

3.5

Output Enable to Data Valid

Clock High to Output Low-Z

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

tOE

-

2.6

-

3.5

ns

tLZC

tOH

1.5

0

-

1.5

0

-

ns

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

2.6

-

3.0

ns

-

2.6

-

3.0

-

ns

1.7

1.2

0.3

2

2.2

1.5

0.5

2

ns

Clock Low Pulse Width

tCL

-

ns

Address Setup to Clock High

CKE Setup to Clock High

tAS

-

ns

tCES

tDS

-

ns

Data Setup to Clock High

-

ns

Write Setup to Clock High (WE, BWX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

CKE Hold from Clock High

tWS

-

ns

tADVS

tCSS

tAH

-

ns

-

ns

-

ns

tCEH

tDH

-

ns

Data Hold from Clock High

-

ns

Write Hold from Clock High (WE, BWX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

-

ns

tADVH

tCSH

tPDS

tPUS

-

ns

-

ns

-

cycle

ZZ Low to Power Up

2

-

2

-

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges

when ADV is sampled low and CS is sampled low.

All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

4. To avoid bus contention, At a given voltage and temperature t^LZCis more than tHZC.

The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions

(0°C,2.625V) than t^HZC, which is a Max. parameter(worst case at 70°C,2.375V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

Oct. 2004

Rev 0.5

- 13 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

SLEEP MODE

SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SLEEP MODE is dictated by the length of time the ZZ is in a High state.

After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z

The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP

MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-

ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given

while the SRAM is transitioning out of SLEEP MODE.

SLEEP MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

Current during SLEEP MODE

CONDITIONS

SYMBOL

ISB2

MIN

MAX

UNITS

mA

ZZ ≥ VIH

TBD

ZZ active to input ignored

tPDS

2

cycle

tPUS

ZZ inactive to input sampled

ZZ active to SLEEP current

ZZ inactive to exit SLEEP current

tZZI

2

tRZZI

0

SLEEP MODE WAVEFORM

K

tPDS

ZZ setup cycle

tPUS

ZZ recovery cycle

ZZ

tZZI

Isupply

ISB2

tRZZI

All inputs

(except ZZ)

Deselect or Read Only

Normal

operation

cycle

Outputs

(Q)

High-Z

DON′T CARE

Oct. 2004

Rev 0.5

- 14 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

IDCODE

SAMPLE-Z

BYPASS

SAMPLE

Boundary Scan Register

Identification Register

Boundary Scan Register

Bypass Register

1

3

2

4

5

6

4

0

1

Boundary Scan Register

1

RESERVED Do Not Use

SRAM

CORE

1

BYPASS

Bypass Register

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

TDI

BYPASS Reg.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

TDO

Identification Reg.

Instruction Reg.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V^SSwhen BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

Control Signals

TAP Controller

TMS

TCK

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

1

Run Test Idle

Select DR

0

Select IR

0

1

Capture DR

0

Capture IR

0

Shift DR

1

Shift IR

1

Exit1 DR

0

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 DR

1

Exit2 IR

1

0

Update DR

0

Update IR

1

Oct. 2004

Rev 0.5

- 15 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

SCAN INFORMATION (165 FBGA )

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

1 bits

ID Register

32 bits

Boundary Scan

89 bits

2Mx36

4Mx18

3 bits

1 bits

32 bits

89 bits

ID REGISTER DEFINITION

Revision Number Part Configuration Vendor Definition Samsung JEDEC Code

Part

Start Bit(0)

(31:28)

(27:18)

(17:12)

XXXXXX

(11: 1)

2Mx36

4Mx18

0000

01001 00100

01010 00011

00001001110

1

0000

BOUNDARY SCAN EXIT ORDER

BIT

PIN ID

BIT

PIN ID

BIT

PIN ID

BIT

PIN ID

1

6N

7N

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

8A

8B

7A

7B

6B

6A

5B

5A

4A

4B

3B

3A

2A

2B

2C

1B

1A

1C

1D

1E

1F

1G

2D

2E

2F

2G

1H

3H

1J

79

80

81

82

83

84

85

86

87

88

89

1R

2R

3P

3R

2P

4R

4P

5N

6P

6R

2

3

10N

11P

8P

4

5

6

8R

7

9R

8

9P

9

10P

10R

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

9H

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

Internal

10H

11G

11F

11E

11D

10G

10F

10E

10D

11C

11A

11B

10A

10B

9A

1K

1L

1M

2J

2K

2L

2M

1N

2N

1P

9B

10C

Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don′t care).

Oct. 2004

Rev 0.5

- 16 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

JTAG DC OPERATING CONDITIONS

Parameter

Power Supply Voltage

Input High Level

Symbol

VDD

VIH

Min

2.375

1.7

Typ

Max

2.625

VDD+0.3

0.7

Unit

V

Note

2.5

-

V

Input Low Level

VIL

-0.3

2.0

V

Output High Voltage

Output Low Voltage

VOH

VOL

-

V

-

0.4

V

NOTE : The input level of SRAM pin is to follow the SRAM DC specification.

JTAG AC TEST CONDITIONS

Parameter

Input High/Low Level

Symbol

VIH/VIL

TR/TF

Min

Unit

Note

2.5/0

V

ns

V

Input Rise/Fall Time

1.0/1.0

VDDQ/2

Input and Output Timing Reference Level

JTAG AC Characteristics

Parameter

TCK Cycle Time

Symbol

Min

50

20

5

Max

Unit

Note

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

-

5

-

5

-

5

-

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

-

5

-

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCLCH

tCHCL

tMVCH

tCHMX

tCHDX

TMS

TDI

tDVCH

tSVCH

tCHSX

PI

(SRAM)

tCLQV

TDO

Oct. 2004

Rev 0.5

- 17 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

PACKAGE DIMENSIONS

100-TQFP-1420A

Units ; millimeters/Inches

22.00

20.00

±

0.30

0.20

0~8°

+ 0.10

- 0.05

±

0.127

16.00

14.00

±0.30

0.10 MAX

±0.20

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30

±0.10

0.10 MAX

1.40

±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

Oct. 2004

Rev 0.5

- 23 -

K7N643645M

K7N641845M

Preliminary

2Mx36 & 4Mx18 Pipelined NtRAM^TM

165 FBGA PACKAGE DIMENSIONS

15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

A

B

Top View

C

Side View

D

A

F

E

B

Bottom View

G

H

E

Symbol

Value

17 ± 0.1

Units

mm

Note

Symbol

Value

1.0

Units

mm

Note

A

B

C

D

E

F

15 ± 0.1

1.3 ± 0.1

0.35 ± 0.05

14.0

10.0

G

H

0.50 ± 0.05

Oct. 2004

Rev 0.5

- 24 -


型号：	K7N641845M-QC25
厂家：	SAMSUNG
描述：	2Mx36 & 4Mx18 Pipelined NtRAM 2Mx36及4Mx18流水线NtRAM
文件：	总24页 (文件大小：453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7N641845M-QC25 [SAMSUNG]

相关型号：

K7N641845M-QI160

K7N641845M-QI16T

K7N641845M-QI250

K7N641845M-QI25T

K7N643645M

K7N643645M-EC25T

K7N643645M-EI16T

K7N643645M-FC16

K7N643645M-FC160

K7N643645M-FC16T

K7N643645M-FC25

K7N643645M-FC250