K7N321845M-FC130_技术文档

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

TM

36Mb NtRAM Specification

100TQFP / 165FBGA with Pb only

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.

ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-

lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military

or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 3.0 February 2006

- 1 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

Document Title

1Mx36 & 2Mx18-Bit Pipelined NtRAM^TM

Revision History

Draft Date

May. 10. 2001

Aug. 29. 2001

Dec. 31. 2001

Rev. No.

History

Remark

0.0

0.1

0.2

1. Initial document.

Preliminary

1. Add 165FBGA package

1. Update JTAG scan order

2. Speed bin merge.

From K7N3236(18)09M to K7N3236(18)01M

3. AC parameter change.

tOH(min)/tLZC(min) from 0.8 to 1.5 at -25

tOH(min)/tLZC(min) from 1.0 to 1.5 at -22

tOH(min)/tLZC(min) from 1.0 to 1.5 at -20

Feb. 14. 2002

Apr. 20. 2002

0.3

0.4

1. Change pin out for 165FBGA

Preliminary

- x18/x36 ; 11B => from A to NC

, 2R ==> from NC to A

1. Insert pin at JTAG scan order of 165FBGA in connection with

pin out change

- x18/x36 ; insert Pin ID of 2R to BIT number of 69

May. 10. 2002

Sep. 26. 2002

Oct. 17. 2003

0.5

1.0

1.1

1. Add Icc, Isb, Isb1 and Isb2 values.

1. Final datasheet release.

Preliminary

Final

1. Change the Stand-by current (Isb)

Before After

Final

Isb - 25 : 120

- 22 : 110

170

160

150

140

110

100

- 20 : 100

- 16 :

90

80

- 15 :

- 13 :

Isb1

Isb2

:

Nov. 18. 2003

Feb. 16. 2006

2.0

3.0

1. Delete the 119BGA package

Final

2. Delete the 225MHz and 150MHz speed bin

1. Add the overshoot timing

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev. 3.0 February 2006

- 2 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

36Mb NtRAM(Flow Through / Pipelined) Ordering Information

Speed

Org.

Part Number

Mode

VDD

FT ; Access Time(ns)

PKG

Temp

Pipelined ; Cycle Time(MHz)

K7M321825M-QC75

FlowThrough 3.3

7.5ns

2Mx18

K7N321801M-Q(F)C25/20/16/13

K7N321845M-Q(F)C25/20/16/13

K7M323625M-QC75

Pipelined

3.3

2.5

250/200/167/133MHz

7.5ns

C

Q:100TQFP (Commercial

F:165FBGA Temperature

Range)

FlowThrough 3.3

1Mx36

K7N323601M-Q(F)C25/20/16/13

K7N323645M-Q(F)C25/20/16/13

Pipelined

3.3

2.5

250/200/167/133MHz

Rev. 3.0 February 2006

- 3 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

1Mx36 & 2Mx18-Bit Pipelined NtRAM^TM

FEATURES

GENERAL DESCRIPTION

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O.

• Byte Writable Function.

The K7N323601M and K7N321801M are 37,748,736-bits

Synchronous Static SRAMs.

The NtRAM^TM, or No Turnaround Random Access Memory uti-

lizes all the bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input clock.

Burst order control must be tied "High or Low".

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-chip

write pulse generation

and provides increased timing flexibility for incoming signals.

For read cycles, pipelined SRAM output data is temporarily

stored by an edge triggered output register and then released

to the output buffers at the next rising edge of clock.

The K7N323601M and K7N321801M are implemented with

SAMSUNG′s high performance CMOS technology and is avail-

able in 100pin TQFP and 165FBGA packages. Multiple power

and ground pins minimize ground bounce.

• Enable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data-

contention .

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

• 100-TQFP-1420A .

• 165FBGA(11x15 ball aray) with body size of 15mmx17mm.

FAST ACCESS TIMES

PARAMETER

Cycle Time

Clock Access Time

Symbol -25

-20

5.0

3.2

-16 -13 Unit

tCYC

tCD

4.0

2.6

6.0 7.5

3.5 4.2

ns

Output Enable Access Time tOE

LOGIC BLOCK DIAGRAM

LBO

A0~A1

BURST

ADDRESS

COUNTER

A

′

0

~A′1

A [0:19]or

1Mx36, 2Mx18

MEMORY

ARRAY

A [0:20]

ADDRESS

REGISTER

A

2

~A19 or A2~A20

WRITE

ADDRESS

REGISTER

DATA-IN

ADDRESS

CLK

CKE

K

REGISTER

K

REGISTER

DATA-IN

REGISTER

CS

1

2

ADV

WE

CONTROL

LOGIC

OUTPUT

REGISTER

K

BW

x

(x=a,b,c,d or a,b)

BUFFER

OE

ZZ

36 or 18

DQa ~ DQd7 or DQa0 ~ DQb8

DQP⁰a ~ DQPd

TM

NtRAM and No Turnaround Random Access Memory are trademarks of Samsung.

Rev. 3.0 February 2006

- 4 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

DQPc

1

DQPb

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc0

2

DQc1

3

VDDQ

4

VSSQ

5

DQc2

6

DQc3

7

DQc4

8

DQc5

9

VSSQ

10

VDDQ

11

DQc6

12

100 Pin TQFP

(20mm x 14mm)

DQc7

13

VDD

14

VDD

15

VDD

16

VDD

VSS

17

ZZ

DQd0

18

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

DQd1

19

K7N323601M(1Mx36)

VDDQ

20

VSSQ

21

DQd2

22

DQd3

23

DQd4

24

DQd5

25

VSSQ

26

VDDQ

27

DQd6

28

DQd7

29

DQPd

30

PIN NAME

SYMBOL

PIN NAME

Address Inputs

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A19

32,33,34,35,36,37,43, VDD

44,45,46,47,48,49,50, VSS

81,82,83,84,99,100

Power Supply(+3.3V) 14,15,16,41,65,66,91

Ground

17,40,67,90

ADV

WE

CLK

CKE

CS1

CS2

Address Advance/Load

85

No Connect

38,39,42

N.C.

Read/Write Control Input 88

Clock

89

Data Inputs/Outputs 52,53,56,57,58,59,62,63

Data Inputs/Outputs 68,69,72,73,74,75,78,79

Data Inputs/Outputs 2,3,6,7,8,9,12,13

Data Inputs/Outputs 18,19,22,23,24,25,28,29

Data Inputs/Outputs 51,80,1,30

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

Clock Enable

Chip Select

87

98

97

92

BWx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

86

64

31

Output Power Supply 4,11,20,27,54,61,70,77

(3.3V or 2.5V)

Output Ground

VDDQ

VSSQ

5,10,21,26,55,60,71,76

Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

Rev. 3.0 February 2006

- 5 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

1

N.C.

VDDQ

VSSQ

N.C.

DQa0

DQa1

DQa2

VSSQ

VDDQ

DQa3

DQa4

VSS

2

N.C.

3

VDDQ

VSSQ

N.C.

4

5

6

N.C.

7

DQb8

DQb7

VSSQ

VDDQ

DQb6

DQb5

VDD

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

(20mm x 14mm)

VDD

ZZ

VSS

DQb4

DQb3

VDDQ

VSSQ

DQb2

DQb1

DQb0

N.C.

DQa5

DQa6

VDDQ

VSSQ

DQa7

DQa8

N.C.

VSSQ

VDDQ

N.C.

K7N321801M(2Mx18)

VSSQ

VDDQ

N.C.

PIN NAME

SYMBOL

PIN NAME

Address Inputs

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A20

32,33,34,35,36,37,43

VDD

Power Supply(+3.3V) 14,15,16,41,65,66,91

Ground

44,45,46,47,48,49,50, VSS

17,40,67,90

80,81,82,83,84,99,100

ADV

WE

CLK

CKE

CS1

CS2

Address Advance/Load

85

No Connect

1,2,3,6,7,25,28,29,30,

38,39,42,51,52,53,

56,57,75,78,79,95,96

N.C.

Read/Write Control Input 88

Clock

89

Clock Enable

Chip Select

87

98

Data Inputs/Outputs 58,59,62,63,68,69,72,73,74

Data Inputs/Outputs 8,9,12,13,18,19,22,23,24

DQa0~a8

DQb0~b8

97

92

BWx(x=a,b) Byte Write Inputs

93,94

86

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

Output Power Supply 4,11,20,27,54,61,70,77

(3.3V or 2.5V)

Output Ground

VDDQ

VSSQ

64

31

5,10,21,26,55,60,71,76

NOTE : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

Rev. 3.0 February 2006

- 6 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7N323601M(1Mx36)

1

2

3

4

5

6

7

8

9

10

A

11

NC

CS2

NC

A

CS1

BWc

BWd

VSS

VDD

VSS

A

BWb

BWa

VSS

NC

CKE

WE

ADV

OE

A

B

C

D

E

F

NC

A

CS2

CLK

VSS

NC

A

NC

DQPc

DQc

NC

VDDQ

NC

VSS

NC

VSS

VDD

VSS

A

VDDQ

NC

DQb

NC

DQa

NC

A

DQPb

DQb

ZZ

DQc

VDD

DQd

NC

G

H

J

DQd

DQPd

NC

VDDQ

A

VDDQ

A

DQa

DQPa

NC

K

L

M

N

P

R

NC

TDI

A1*

TDO

TCK

LBO

A

TMS

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

N.C.

No Connect

CLK

DQa

DQb

DQc

DQd

Data Inputs/Outputs

CKE

CS1

Clock Enable

Chip Select

CS2

Chip Select

CS2

Chip Select

DQPa~Pd

BWx

(x=a,b,c,d)

Byte Write Inputs

VDDQ

Output Power Supply

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

Rev. 3.0 February 2006

- 7 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7N321801M(2Mx18)

1

NC

2

A

3

4

5

6

7

8

9

10

A

11

A

CS2

CS1

BWb

NC

CKE

WE

ADV

OE

A

B

C

D

E

F

NC

A

CS2

BWa

VSS

NC

CLK

VSS

NC

A

NC

DQb

VDD

NC

A

VDDQ

NC

VSS

VDD

VSS

A

VSS

NC

VSS

VDD

VSS

A

VDDQ

NC

DQa

NC

A

DQPa

DQa

ZZ

NC

G

H

J

NC

DQb

DQPb

NC

VDDQ

A

VDDQ

A

NC

K

L

NC

M

N

P

R

NC

TDI

A1*

TDO

TCK

NC

LBO

A

TMS

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

No Connect

N.C.

CLK

CKE

CS1

CS2

Clock Enable

Data Inputs/Outputs

DQa

DQb

DQPa, Pb

Chip Select

BWx

(x=a,b)

Byte Write Inputs

Output Power Supply

VDDQ

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

Rev. 3.0 February 2006

- 8 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

FUNCTION DESCRIPTION

The K7N323601M and K7N321801M are NtRAM^TMdesigned to sustain 100% bus bandwidth by eliminating turnaround cycle when

there is transition from Read to Write, or vice versa.

All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the

burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next

operation.

Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous

inputs are ignored and the internal device registers will hold their previous values.

NtRAM^TMlatches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)

are active .

Output Enable(OE) can be used to disable the output at any given time.

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the

address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven

high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data

is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must

be driven low for the device to drive out the requested data.

Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-

lined NtRAM^TMuses a late-late write cycle to utilize 100% of the bandwidth.

At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle

later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is

provided by the external address. The burst address counter wraps around to its initial state upon completion.

The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.

And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At

this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up

time.

BURST SEQUENCE TABLE

(Interleaved Burst, LBO=High)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst, LBO=Low)

Case 4

Case 1

Case 2

Case 3

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

Rev. 3.0 February 2006

- 9 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

STATE DIAGRAM FOR NtRAM^TM

WRITE

READ

BEGIN

READ

BEGIN

WRITE

READ

DESELECT

BURST

READ

BURST

WRITE

BURST

COMMAND

ACTION

DS

DESELECT

READ

WRITE

BEGIN READ

BEGIN WRITE

BEGIN READ

BURST

BEGIN WRITE

CONTINUE DESELECT

Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does

not change the state of the device.

2. States change on the rising edge of the clock(CLK)

Rev. 3.0 February 2006

- 10 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1 CS2 CS2 ADV WE BWx OE

CKE CLK

ADDRESS ACCESSED

N/A

Operation

Not Selected

H

X

L

X

L

X

H

X

L

X

H

X

H

X

L

X

L

X

L

H

↑

N/A

Not Selected

X

H

X

H

X

H

X

H

X

L

N/A

Not Selected

H

L

N/A

Not Selected Continue

Begin Burst Read Cycle

Continue Burst Read Cycle

NOP/Dummy Read

Dummy Read

External Address

Next Address

External Address

Next Address

External Address

Next Address

N/A

X

L

X

L

H

L

H

X

L

X

L

H

L

Begin Burst Write Cycle

Continue Burst Write Cycle

NOP/Write Abort

Write Abort

X

L

X

L

H

L

X

L

H

X

H

X

Next Address

Current Address

Ignore Clock

Notes : 1. X means "Don′t Care".

2. The rising edge of clock is symbolized by (↑).

3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE(x36)

WE

H

L

BWa

BWb

X

BWc

X

BWd

X

OPERATION

READ

X

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

L

H

L

H

L

H

L

H

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

WRITE TRUTH TABLE(x18)

WE

BWa

X

BWb

OPERATION

H

X

H

L

READ

L

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

Rev. 3.0 February 2006

- 11 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

ASYNCHRONOUS TRUTH TABLE

Notes

OPERATION

ZZ

H

L

OE

I/O STATUS

High-Z

1. X means "Don′t Care".

Sleep Mode

X

2. Sleep Mode means power Sleep Mode of which stand-by current does

not depend on cycle time.

L

DQ

3. Deselected means power Sleep Mode of which stand-by current

depends on cycle time.

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

Deselected

L

X

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on Any Other Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 4.6

-0.3 to VDD+0.3

1.6

UNIT

V

VIN

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Operating Temperature

Storage Temperature Range Under Bias

-10 to 85

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

MIN

3.135

0

Typ.

3.3

0

MAX

3.465

0

UNIT

VDD

V

VDDQ

VSS

OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

MIN

3.135

2.375

0

Typ.

3.3

2.5

0

MAX

3.465

2.9

UNIT

VDD

V

VDDQ

VSS

0

CAPACITANCE*(TA=25°C, f=1MHz)

Parameter

Symbol

Test Condition

VIN=0V

TYP

Max

5

Unit

pF

Input Capacitance

CIN

-

Output Capacitance

COUT

VOUT=0V

7

pF

*Notes : Sampled not 100% tested.

Rev. 3.0 February 2006

- 12 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT NOTES

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

VDD=Max ; VIN=VSS to VDD

-2

-

+2

µA

IOL

Output Disabled, Vout=VSS to VDDQ

+2

-25

-20

-16

-13

-25

-20

-16

-13

460

410

360

310

170

150

140

-

Device Selected, IOUT=0mA,

ZZ≤VIL , Cycle Time ≥ tCYC Min

Operating Current

ICC

ISB

mA

1,2

-

Device deselected, IOUT=0mA,

ZZ≤VIL, f=Max, All Inputs≤0.2V or ≥

VDD-0.2V

-

Device deselected, IOUT=0mA,

ZZ≤0.2V,

f=0, All Inputs=fixed (VDD-0.2V or

Standby Current

ISB1

ISB2

-

110

100

mA

Device deselected, IOUT=0mA,

ZZ≥VDD-0.2V, f=Max, All Inputs≤VIL

or ≥VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

Input High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL=8.0mA

IOH=-4.0mA

IOL=1.0mA

IOH=-1.0mA

-

0.4

V

2.4

-

0.4

-

2.0

-0.3*

2.0

-0.3*

1.7

0.8

VIH

VIL

VDD+0.3**

0.7

3

VIH

VDD+0.3**

Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.

2. Data states are all zero.

3. In Case of I/O Pins, the Max. V^IH=VDDQ+0.3V

Overshoot Timing

Undershoot Timing

20% tCYC(MIN)

VIH

VDDQ+1.0V

VDDQ+0.5V

VDDQ

VSS

VSS-0.5V

VSS-1.0V

20% tCYC(MIN)

VIL

TEST CONDITIONS

(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T

A

=0to70°C)

PARAMETER

VALUE

0 to 3.0V

0 to 2.5V

1.0V/ns

1.5V

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

VDDQ/2

See Fig. 1

Rev. 3.0 February 2006

- 13 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

/+2.5V for 2.5V I/O

RL=50Ω

Dout

VL=1.5V for 3.3V I/O

VDDQ/2 for 2.5V I/O

319Ω / 1667Ω

30pF*

Dout

Zo=50Ω

353Ω / 1538Ω

5pF*

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 to 70°C)

-25

-20

-16

-13

PARAMETER

SYMBOL

UNIT

MIN

4.0

-

MAX

MIN

5.0

-

MAX

MIN

6.0

-

MAX

MIN

7.5

-

MAX

Cycle Time

tCYC

tCD

-

ns

Clock Access Time

2.6

3.2

3.5

4.2

Output Enable to Data Valid

Clock High to Output Low-Z

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

tOE

-

2.6

-

3.2

-

3.5

-

4.2

ns

tLZC

tOH

1.5

0

-

1.5

0

-

1.5

0

-

1.5

0

-

ns

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

2.6

-

3.0

-

3.0

-

3.5

ns

-

2.6

-

3.0

-

3.0

-

3.5

-

ns

1.7

1.2

0.3

2

2.0

1.4

0.4

2

2.2

1.5

0.5

2

3.0

1.5

0.5

2

ns

Clock Low Pulse Width

tCL

-

ns

Address Setup to Clock High

CKE Setup to Clock High

tAS

-

ns

tCES

tDS

-

ns

Data Setup to Clock High

-

ns

Write Setup to Clock High (WE, BWX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

CKE Hold from Clock High

tWS

-

ns

tADVS

tCSS

tAH

-

ns

-

ns

-

ns

tCEH

tDH

-

ns

Data Hold from Clock High

-

ns

Write Hold from Clock High (WE, BWX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

-

ns

tADVH

tCSH

tPDS

tPUS

-

ns

-

ns

-

cycle

ZZ Low to Power Up

2

-

2

-

2

-

2

-

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled

low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

4. To avoid bus contention, At a given voltage and temperature t^LZCis more than tHZC.

The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions

(0°C,3.465V) than t^HZC, which is a Max. parameter(worst case at 70°C,3.135V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

Rev. 3.0 February 2006

- 14 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

SLEEP MODE

SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SLEEP MODE is dictated by the length of time the ZZ is in a High state.

After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z

The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP

MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-

ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given

while the SRAM is transitioning out of SLEEP MODE.

SLEEP MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

CONDITIONS

SYMBOL

ISB2

MIN

MAX

UNITS

mA

Current during SLEEP MODE

ZZ ≥ VIH

60

ZZ active to input ignored

tPDS

2

cycle

tPUS

ZZ inactive to input sampled

ZZ active to SLEEP current

ZZ inactive to exit SLEEP current

tZZI

2

tRZZI

0

SLEEP MODE WAVEFORM

K

tPDS

tPUS

ZZ setup cycle

ZZ recovery cycle

ZZ

tZZI

Isupply

ISB2

tRZZI

All inputs

Deselect or Read Only

(except ZZ)

Normal

operation

cycle

Outputs

(Q)

High-Z

DON′T CARE

Rev. 3.0 February 2006

- 15 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

IDCODE

SAMPLE-Z

BYPASS

SAMPLE

Boundary Scan Register

Identification Register

Boundary Scan Register

Bypass Register

1

3

2

4

5

6

4

0

1

Boundary Scan Register

1

RESERVED Do Not Use

SRAM

CORE

1

BYPASS

Bypass Register

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

TDI

BYPASS Reg.

Identification Reg.

Instruction Reg.

TDO

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V^SSwhen BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

Control Signals

TAP Controller

TMS

TCK

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

1

Run Test Idle

Select DR

0

Capture DR

0

Shift DR

1

Exit1 DR

0

Select IR

0

1

Capture IR

0

Shift IR

1

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 IR

1

Exit2 DR

1

0

Update DR

0

Update IR

1

Rev. 3.0 February 2006

- 16 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

SCAN INFORMATION (165 FBGA )

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

1 bits

ID Register

32 bits

Boundary Scan

76 bits

1Mx36

2Mx18

3 bits

1 bits

76 bits

ID REGISTER DEFINITION

Revision Number Part Configuration Vendor Definition Samsung JEDEC Code

Part

Start Bit(0)

(31:28)

(27:18)

(17:12)

XXXXXX

(11: 1)

1Mx36

2Mx18

0000

01000 00100

01001 00011

00001001110

1

BOUNDARY SCAN EXIT ORDER

BIT

PIN ID(x18)

PIN ID(x36)

BIT

PIN ID(x18)

PIN ID(x36)

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1A

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1A

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

1K

1L

1M

2J

2K

2L

2M

1N

2R

1R

3P

3R

4R

4P

6P

6R

1

2

3

4

5

6

7

8

6N

8P

8R

9R

9P

6N

8P

8R

9R

9P

10P

10R

11R

11P

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

11C

10F

10E

10D

10G

11A

11B

10A

10B

9A

10P

10R

11R

11P

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

10G

10F

10E

10D

11C

11A

11B

10A

10B

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

1K

1L

1M

1N

2K

2L

2M

2J

2R

1R

3P

3R

4R

4P

6P

6R

9B

8A

8B

7A

7B

6B

9B

8A

8B

7A

7B

6B

Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don′t care).

Rev. 3.0 February 2006

- 17 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

JTAG DC OPERATING CONDITIONS

Parameter

Symbol

Min

3.135

2.0 / 1.7

-0.3

Typ

Max

3.465

Unit

V

Note

Power Supply Voltage

VDD

VIH

3.3

Input High Level ( 3.3V I/O / 2.5V I/O )

Input Low Level ( 3.3V I/O / 2.5V I/O )

Output High Voltage( 3.3V I/O / 2.5V I/O )

Output Low Voltage( 3.3V I/O / 2.5V I/O )

-

VDD+0.3

0.8 / 0.7

-

V

VIL

V

VOH

VOL

2.4 / 2.0

-

V

0.4 / 0.4

V

NOTE : The input level of SRAM pin is to follow the SRAM DC specification.

JTAG AC TEST CONDITIONS

Parameter

Symbol

VIH/VIL

TR/TF

Min

Unit

V

Note

Input High/Low Level( 3.3V I/O , 2.5V I/O )

Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )

Input and Output Timing Reference Level

3.0/0 , 2.5/0

1.0/1.0 , 1.0/1.0

VDDQ/2

ns

V

JTAG AC Characteristics

Parameter

Symbol

Min

50

20

5

Max

Unit

Note

TCK Cycle Time

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

5

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCLCH

tCHCL

tMVCH

tCHMX

tCHDX

TMS

TDI

tDVCH

tSVCH

tCHSX

PI

(SRAM)

tCLQV

TDO

Rev. 3.0 February 2006

- 18 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

Rev. 3.0 February 2006

- 19 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

Rev. 3.0 February 2006

- 20 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

Rev. 3.0 February 2006

- 21 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

Rev. 3.0 February 2006

- 22 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

Rev. 3.0 February 2006

- 23 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

PACKAGE DIMENSIONS

Units ; millimeters/Inches

100-TQFP-1420A

22.00

20.00

±

0.30

0.20

0~8°

+ 0.10

- 0.05

±

0.127

16.00

14.00

±

0.30

0.10 MAX

±0.20

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30

±0.10

0.10 MAX

1.40

±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

Rev. 3.0 February 2006

- 24 -

K7N323601M

K7N321801M

1Mx36 & 2Mx18 Pipelined NtRAM^TM

165 FBGA PACKAGE DIMENSIONS

15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

A

B

Top View

C

Side View

D

A

F

E

B

Bottom View

G

∅ H

E

Symbol

Value

17 ± 0.1

Units

mm

Note

Symbol

Value

1.0

Units

mm

Note

A

B

C

D

E

F

15 ± 0.1

1.3 ± 0.1

0.35 ± 0.05

14.0

10.0

G

H

0.5 ± 0.05

Rev. 3.0 February 2006

- 25 -


型号：	K7N321845M-FC130
厂家：	SAMSUNG
描述：	ZBT SRAM, 2MX18, 4.2ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165 静态存储器内存集成电路
文件：	总25页 (文件大小：1117K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7N321845M-FC130 [SAMSUNG]

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