K7J160882B-FC300_技术文档

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

Document Title

512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM

Revision History

Draft Date

Remark

Rev. No.

History

Advance

Dec. 16, 2002

Dec. 26, 2002

Jan. 27, 2003

Mar. 20, 2003

0.0

1. Initial document.

Preliminary

0.1

1. Change the JTAG Block diagram

1. Add the speed bin (-25)

0.2

0.3

1. Correct the JTAG ID register definition

2. Correct the AC timing parameter (delete the tKHKH Max value)

Preliminary

April. 4, 2003

0.4

0.5

1. Change the Maximum Clock cycle time.

2. Correct the 165FBGA package ball size.

June. 20, 2003

1. Add the power up/down sequencing comment.

2. Update the DC current parameter (Icc and Isb).

3. Change the Max. speed bin from -33 to -30.

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

June. 2003

Rev 0.5

- 1 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM

FEATURES

• 1.8V+0.1V/-0.1V Power Supply.

Part

Cycle Access

Organization

Unit

• DLL circuitry for wide output data valid window and future

freguency scaling.

Number

Time

K7J163682B-FC30

K7J163682B-FC25

K7J163682B-FC20

K7J163682B-FC16

K7J161882B-FC30

K7J161882B-FC25

K7J161882B-FC20

K7J161882B-FC16

K7J160882B-FC30

K7J160882B-FC25

K7J160882B-FC20

K7J160882B-FC16

3.3

4.0

5.0

6.0

3.3

4.0

5.0

6.0

3.3

4.0

5.0

6.0

0.45

0.50

0.45

0.50

0.45

0.50

ns

• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,

1.8V+0.1V/-0.1V for 1.8V I/O.

• Separate independent read and write data ports

• HSTL I/O

X36

X18

• Synchronous pipeline read with self timed late write.

• Registered address, control and data input/output.

• Full data coherency, providing most current data.

• DDR(Double Data Rate) Interface on read and write ports.

• Fixed 2-bit burst for both read and write operation.

• Clock-stop supports to reduce current.

• Two input clocks(K and K) for accurate DDR timing at clock

rising edges only.

• Two input clocks for output data(C and C) to minimize

clock-skew and flight-time mismatches.

• Two echo clocks (CQ and CQ) to enhance output data

traceability.

X8

• Single address bus.

• Byte write (x18, x36) and nybble(x8) write function.

• Simple depth expansion with no data contention.

• Programmable output impedance.

• JTAG 1149.1 compatible test access port.

• 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm

FUNCTIONAL BLOCK DIAGRAM

36 (or 18)

18 (or 19)

DATA

REG

D(Data in)

ADDRESS

36 (or 18)

WRITE DRIVER

18

(or 19)

ADD

REG

36

(or 18)

36

72

(or 36)

512kx36

(1Mx18)

MEMORY

ARRAY

(or 18)

R/W

LD

CTRL

LOGIC

Q(Data Out)

4(or 2)

BWX

CQ, CQ

(Echo Clock out)

K

CLK

GEN

C

SELECT OUTPUT CONTROL

Notes: 1. Numbers in ( ) are for x18 device, x8 device also the same with appropriate adjustments of depth and width.

DDR II SRAM and Double Data Rate II comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsun g technology.

June. 2003

Rev 0.5

- 2 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7J163682B(512Kx36)

1

2

VSS/SA*

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

3

NC/SA*

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

SA

4

5

6

7

8

9

NC/SA*

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q9

10

VSS/SA*

Q17

Q7

11

CQ

Q8

D8

A

B

C

D

E

F

CQ

R/W

SA

BW2

BW3

SA

K

BW1

BW0

SA

LD

Q27

D27

D28

Q29

Q30

D30

Doff

D31

Q32

Q33

D33

D34

Q35

TDO

K

SA

VSS

VDDQ

VSS

SA

VSS

SA

C

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

VSS

D15

D6

D7

VDDQ

VSS

Q6

Q5

D5

Q14

D13

VREF

Q4

G

H

J

ZQ

D4

K

L

D3

Q3

Q2

D2

Q11

Q1

M

N

P

R

VSS

D9

D1

SA

D0

Q0

TDI

SA

C

SA

TMS

Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 72Mb, 9A for 36Mb, 10A for 144Mb and 2A for 288Mb.

2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35.

PIN NAME

SYMBOL

K, K

PIN NUMBERS

DESCRIPTION

Input Clock

NOTE

6B, 6A

C, C

6P, 6R

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Address Inputs

1

CQ, CQ

Doff

11A, 1A

1H

SA

4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L

9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N

1C,1D,2E,1G,1J,2K,1M,1N,2P

D0-35

Q0-35

Data Inputs

11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L

9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N

3P,1B,2C,1E,1F,2J,1K,1L,2M,1P

Data Outputs

Read, Write Control Pin, Read active

when high

R/W

LD

4A

8A

Synchronous Load Pin, bus Cycle

sequence is to be defined when low

BW0, BW1,BW2, BW3

7B,7A,5A,5B

Block Write Control Pin,active when low

Input Reference Voltage

VREF

ZQ

2H,10H

11H

Output Driver Impedance Control Input

Power Supply ( 1.8 V )

2

VDD

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

VDDQ

Output Power Supply ( 1.5V or 1.8V )

2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,

8M,4N,8N

VSS

Ground

TMS

TDI

10R

11R

2R

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Clock

TCK

TDO

NC

1R

JTAG Test Data Output

No Connect

3A, 9A

3

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

June. 2003

Rev 0.5

- 3 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7J161882B(1Mx18)

1

CQ

NC

Doff

NC

TDO

2

VSS/SA*

Q9

3

NC/SA*

D9

4

5

6

7

8

9

SA

NC

VDDQ

NC

SA

10

VSS/SA*

NC

11

CQ

Q8

D8

A

B

C

D

E

F

R/W

SA

BW1

NC

SA

K

NC

BW0

SA

LD

K

SA

NC

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

SA

VSS

VDDQ

VSS

SA

VSS

SA

C

VSS

Q7

D11

NC

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

VSS

NC

D7

VDDQ

VSS

D6

Q6

Q5

D5

Q12

D13

VREF

NC

G

H

J

NC

VREF

Q4

ZQ

D4

K

L

NC

D3

Q3

Q2

D2

Q15

NC

M

N

P

R

Q1

D17

NC

VSS

NC

D1

SA

D0

Q0

TDI

TCK

SA

C

SA

TMS

Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.

2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.

PIN NAME

SYMBOL

K, K

PIN NUMBERS

DESCRIPTION

Input Clock

NOTE

6B, 6A

C, C

6P, 6R

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Address Inputs

1

CQ, CQ

Doff

11A, 1A

1H

SA

9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,

3F,2G,3J,3L,3M,2N

D0-17

Q0-17

R/W

Data Inputs

11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,

2F,3G,3K,2L,3N,3P

Data Outputs

Read, Write Control Pin, Read active

when high

4A

8A

Synchronous Load Pin, bus Cycle

sequence is to be defined when low

LD

BW0, BW1

VREF

7B, 5A

Block Write Control Pin,active when low

Input Reference Voltage

2H,10H

11H

ZQ

Output Driver Impedance Control Input

Power Supply ( 1.8 V )

2

VDD

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

VDDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

VSS

TMS

TDI

2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

Ground

10R

11R

2R

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Clock

TCK

TDO

1R

JTAG Test Data Output

3A,7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,

10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M,

9M,1N,9N,10N,1P,2P,9P

NC

No Connect

3

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

June. 2003

Rev 0.5

- 4 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7J160882B(2Mx8)

1

CQ

NC

Doff

NC

TDO

2

VSS/SA*

NC

3

SA

4

5

6

7

8

9

SA

NC

VDDQ

NC

SA

10

Vss/SA*

NC

11

CQ

Q3

D3

A

B

C

D

E

F

R/W

SA

NW1

NC

SA

K

NC

NW 0

SA

LD

NC

Q4

K

SA

NC

VSS

VDDQ

VSS

SA

VSS

SA

C

VSS

NC

D4

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

VSS

NC

Q2

NC

ZQ

D1

NC

VDDQ

VSS

D2

NC

Q5

NC

G

H

J

D5

NC

VREF

NC

VDDQ

NC

D6

VREF

Q1

K

L

NC

Q0

D0

Q6

NC

M

N

P

R

NC

Q7

NC

D7

VSS

NC

TDI

NC

SA

NC

TCK

SA

C

SA

TMS

Notes: 1. * Checked No Connect(NC) pin is reserved for higher density address, i.e. 2A for 72Mb, 10A for 36Mb.

2. NW 0 controls write to D0:D3 and NW1 controls write to D4:D7.

PIN NAME

SYMBOL

K, K

PIN NUMBERS

DESCRIPTION

NOTE

6B, 6A

Input Clock

C, C

6P, 6R

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Address Inputs

1

CQ, CQ

Doff

11A, 1A

1H

SA

3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

11M,11J,10E,11C,2D,2G,3L,2N

11L,10J,11E,11B,3E,3G,2L,3P

D0-7

Q0-7

Data Inputs

Data Outputs

Read, Write Control Pin, Read active

when high

R/W

LD

4A

8A

Synchronous Load Pin, bus Cycle

sequence is to be defined when low

NW0, NW1

VREF

ZQ

7B, 5A

Nybble Write Control Pin,active when low

Input Reference Voltage

Output Driver Impedance Control Input

Power Supply ( 1.8 V )

2H,10H

11H

2

VDD

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

VDDQ

VSS

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

Ground

2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

TMS

TDI

10R

11R

2R

JTAG Test Mode Select

JTAG Test Data Input

TCK

TDO

JTAG Test Clock

1R

JTAG Test Data Output

7A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,11D

1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J

1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N

10N,11N,1P,2P,9P,10P,11P

NC

No Connect

3

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

June. 2003

Rev 0.5

- 5 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

GENERAL DESCRIPTION

The K7J163682B,K7J161882B and K7J160882B are 18,874,368-bits DDR Separate I/O

Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for K7J163682B, 1,048,576 words by 18 bits for K7J161882B and

2,097,152 words by 8bits for K7J160882B.

The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports.

Memory bandwidth is higher than DDR sram without separate input output as separate read and write ports

eliminate bus turn around cycle.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read data are referenced to echo clock ( CQ or CQ ) outputs.

Read address and write address are registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and late write enable high speed operations.

Simple depth expansion is accomplished by using LD for port selection.

Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.

Nybble write operation is supported with NW 0 and NW1 pins for x8 device.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7J163682B,K7J161882B and K7J160882B are implemented with SAMSUNG's high performance 6T CMOS technology

and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 8-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K insted of C and C.

When the LD is disabled after a read operation, the K7J163682B,K7J161882B and K7J160882B will first complete

burst read operation before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,

which are synchronized with internal data output.

Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transfered to external through same structures

as output driver.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied

simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ

does not exceed VDD by more than 0.5V during power-down.

June. 2003

Rev 0.5

- 6 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

Write Operations

Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.

Address is presented and stored in the write address register synchronized with next K clock.

For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 8-bit data words with each write command.

The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.

Next burst data is transfered and registered synchronous with following K clock rising edge.

Continuous write operations are initated with K rising edge.

And "late writed" data is presented to the device on every rising edge of both K and K clocks.

When the LD is disabled, the K7J163682B,K7J161882B and K7J160882B will enter into deselect mode.

The device disregards input data presented on the same cycle W disabled.

The K7J163682B and K7J161882B support byte write operations.

With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.

In K7J161882B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.

And in K7J163682B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.

The the K7J160882B support nybble write operations.

In K7J160882B, NW 0 controls write operation to D0:D3, NW1 controls write operation to D4:D7.

Programmable Impedance Output Buffer Operation

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).

The value of RQ (within 15%) is five times the output impedance desired.

For example, 250W resistor will give an output impedance of 50W.

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.

In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-

ior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the

SRAM needs 1024 non-read cycles.

Clock Consideration

K7J163682B,K7J161882B and K7J160882B utlizes internal DLL(Delay-Locked Loops) for maximum output data valid window.

It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.

Circuitry automatically resets the DLL when absence of input clock is detected.

Single Clock Mode

K7J163682B,K7J161882B and K7J160882B can be operated with the single clock pair K and K,

insted of C or C for output clocks.

To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high

during operation.

After power up, this device can¢t change to or from single clock mode.

System flight time and clock skew could not be compensated in this mode.

Depth Expansion

Separate input and output ports enables easy depth expansion.

Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal

for each bank.

Before chip deselected, all read and write pending operations are completed.

June. 2003

Rev 0.5

- 7 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

STATE DIAGRAM

POWER-UP

LOAD

NOP

LOAD

LOAD NEW ADDRESS

LOAD

READ

WRITE

LOAD

DDR READ

DDR WRITE

Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.

2. "LOAD" refers to read new address active status with LD=Low, "LOAD" refers to read new address inactive status with LD=High.

3. "READ" refers to read active read status with R/W=High, "WRITE" refers to write active status with R/W=Low

June. 2003

Rev 0.5

- 8 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

D

Q

K

LD

R/W

OPERATION

D(A0)

Previous state

X

D(A1)

Previous state

X

Q(A0)

Previous state

High-Z

Q(A1)

Previous state

High-Z

Stopped

X

H

X

Clock Stop

•

No Operation

•

H

L

X

DOUT at C(t+1)

High-Z

DOUT at C(t+2)

High-Z

Read

Write

L

Din at K(t+1)

Notes: 1. X means "Don¢t Care".

2. The rising edge of clock is symbolized by ( • ).

3. Before enter into clock stop status, all pending read and write operations will be completed.

WRITE TRUTH TABLE(x18)

K

BW0

L

BW1

L

OPERATION

•

WRITE ALL BYTEs ( K• )

WRITE BYTE 0 ( K• )

WRITE BYTE 1 ( K• )

WRITE NOTHING ( K• )

•

L

•

L

H

•

L

H

L

•

H

L

H

•

H

Notes: 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( • ).

3. Assumes a WRITE cycle was initiated.

4. This table illustates operation for x18 devices. x8 device operation is similar except that NW0 controls D0:D3 and NW 0 controls D4:D7.

WRITE TRUTH TABLE(x36)

K

BW0

L

BW 1

L

BW2

L

BW 3

L

OPERATION

WRITE ALL BYTEs ( K • )

WRITE ALL BYTEs ( K• )

WRITE BYTE 0 ( K• )

•

L

•

L

H

L

H

•

L

H

WRITE BYTE 0 ( K• )

H

L

H

WRITE BYTE 1 ( K• )

•

L

H

WRITE BYTE 1 ( K• )

H

L

WRITE BYTE 2 and BYTE 3 ( K• )

WRITE NOTHING ( K• )

•

H

L

H

•

H

Notes: 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( • ).

3. Assumes a WRITE cycle was initiated.

June. 2003

Rev 0.5

- 9 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on VDDQ Supply Relative to VSS

Voltage on Input Pin Relative to VSS

Storage Temperature

SYMBOL

VDD

RATING

-0.5 to 2.9

-0.5 to VDD

-0.5 to VDD+0.3

-65 to 150

0 to 70

UNIT

V

VDDQ

VIN

V

TSTG

°C

Operating Temperature

TOPR

TBIAS

Storage Temperature Range Under Bias

-10 to 85

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VDDQ must not exceed VDD during normal operation.

DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)

PARAMETER

Input Leakage Current

Output Leakage Current

SYMBOL

TEST CONDITIONS

VDD=Max ; VIN=VSS to VDDQ

Output Disabled,

MIN

MAX

+2

UNIT NOTE

IIL

-2

-

mA

IOL

+2

-30

-25

-20

-16

-30

-25

-20

-16

-30

-25

-20

-16

-30

-25

-20

-16

600

-

550

VDD=Max , IOUT=0mA

Operating Current

(x36) : DDR

ICC

ISB1

mA

1,5

1,6

Cycle Time ³ tKHKH Min

-

500

450

-

500

450

VDD=Max , IOUT=0mA

Operating Current

(x18) : DDR

Cycle Time ³ tKHKH Min

400

350

-

480

430

VDD=Max , IOUT=0mA

Operating Current

(x8) : DDR

Cycle Time ³ tKHKH Min

380

330

-

200

Device deselected,

-

180

IOUT=0mA, f=Max,

Standby Current(NOP): DDR

-

160

All Inputs£0.2V or ³ V DD-0.2V

-

140

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Input Low Voltage

Input High Voltage

VOH1

VOL1

VOH2

VOL2

VIL

VDDQ /2-0.12

VDDQ-0.2

VSS

VDDQ/2+0.12

VDDQ

0.2

V

2,7

3,7

4

IOH=-1.0mA

IOL=1.0mA

4

-0.3

VREF-0.1

VDDQ +0.3

8,9

8,10

VIH

VREF+0.1

Notes: 1. Minimum cycle. IOUT=0mA.

2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175W £ RQ £ 350W.

3. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175W £ RQ £ 350W.

4. Minimum Impedance Mode when ZQ pin is connected to VDDQ .

5. Operating current is calculated with 50% read cycles and 50% write cycles.

6. Standby Current is only after all pending read and write burst opeactions are completed.

7. Programmable Impedance Mode.

8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring

timing parameters.

9. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width £ 3ns).

10. VIH (Max)DC=VDDQ +0.3, VIH (Max)AC=VDDQ +0.85V(pulse width £ 3ns).

June. 2003

Rev 0.5

- 10 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)

PARAMETER

Input High Voltage

Input Low Voltage

MAX

UNIT

NOTES

1,2

SYMBOL

VIH (AC)

VIL (AC)

MIN

VREF + 0.2

-

V

VREF - 0.2

1,2

Notes: 1. This condition is for AC function test only, not for AC parameter test.

2. To maintain a valid level, the transitioning edge of the input must :

a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)

b) Reach at least the target AC level

c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)

Overershoot Timing

Undershoot Timing

20% tKHKH(MIN)

VIH

VDDQ+0.5V

VDDQ+0.25V

VDDQ

VSS

VSS-0.25V

VSS-0.5V

20% tKHKH(MIN)

VIL

Note: For power-up, VIH £ VDDQ+0.3V and VDD £ 1.7V and VDDQ £ 1.4V t £ 200ms

OPERATING CONDITIONS (0°C £ TA £ 70°C)

PARAMETER

SYMBOL

MIN

1.7

1.4

0.68

0

MAX

1.9

0.95

0

UNIT

VDD

V

Supply Voltage

VDDQ

VREF

VSS

Reference Voltage

Ground

AC TEST CONDITIONS

Parameter

Symbol

VDD

Value

1.7~1.9

1.4~1.9

1.25/0.25

0.75

Unit

V

AC TEST OUTPUT LOAD

Core Power Supply Voltage

Output Power Supply Voltage

Input High/Low Level

VDDQ

VIH/VIL

VREF

V

0.75V

VREF

VDDQ/2

V

Input Reference Level

V

50W

SRAM

Zo=50W

Input Rise/Fall Time

TR/TF

0.3/0.3

VDDQ/2

ns

V

Output Timing Reference Level

250W

ZQ

Note: Parameters are tested with RQ=250W

June. 2003

Rev 0.5

- 11 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)

-30

-25

-20

-16

PARAMETER

SYMBOL

UNIT NOTE

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock Cycle Time (K, K, C, C)

Clock Phase Jitter (K, K, C, C)

Clock High Time (K, K, C, C)

Clock Low Time (K, K, C, C)

Clock toClock (K• ® K• , C• ® C• )

Clock to data clock (K• ® C• , K• ® C• )

DLL Lock Time (K, C)

tKHKH

tKC var

tKHKL

3.30

5.25

0.20

4.00

6.30

0.20

5.00

7.88

0.20

6.00

8.40

0.20

ns

5

6

1.32

1.49

0.00

1024

30

1.60

1.80

0.00

1024

30

2.00

2.20

0.00

1024

30

2.40

2.70

0.00

1024

30

tKLKH

ns

tKHKH

tKHCH

tKC lock

tKC reset

ns

1.45

1.80

2.30

2.80

ns

cycle

ns

K Static to DLL reset

Output Times

C, C High to Output Valid

C, C High to Output Hold

C, C High to Echo Clock Valid

C, C High to Echo Clock Hold

CQ, CQ High to Output Valid

CQ, CQ High to Output Hold

C, High to Output High-Z

C, High to Output Low-Z

Setup Times

tCHQV

tCHQX

0.45

0.27

0.45

0.30

0.45

0.35

0.45

0.50

0.40

0.50

ns

3

-0.45

-0.27

-0.45

-0.30

-0.45

-0.35

-0.45

-0.50

-0.40

-0.50

tCHCQV

tCHCQX

tCQHQV

tCQHQX

tCHQZ

7

3

tCHQX1

Address valid to K rising edge

Control inputs valid to K rising edge

Data-in valid to K, K rising edge

Hold Times

tAVKH

tIVKH

tDVKH

0.40

0.30

0.50

0.35

0.60

0.40

0.70

0.50

ns

2

K rising edge to address hold

K rising edge to control inputs hold

K, K rising edge to data-in hold

tKHAX

tKHIX

0.40

0.30

0.50

0.35

0.60

0.40

0.70

0.50

ns

tKHDX

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.

2. Control singles are R, W,BW0,BW1 and (NW0, NW1, for x8) and (BW2, BW3, also for x36)

3. If C,C are tied high, K,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.

The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions

(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.

7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1ns variation from echo clock to data.

The data sheet parameters reflect tester guardbands and test setup variations.

June. 2003

Rev 0.5

- 12 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

PIN CAPACITANCE

PRMETER

Address Control Input Capacitance

Input and Output Capacitance

Clock Capacitance

SYMBOL

CIN

TESTCONDITION

Typ

4

MAX

Unit

pF

NOTES

VIN=0V

VOUT=0V

-

5

7

6

COUT

6

pF

CCLK

5

pF

Note: 1. Parameters are tested with RQ=250Wand VDDQ=1.5V.

2. Periodically sampled and not 100% tested.

THERMAL RESISTANCE

PRMETER

Junction to Ambient

SYMBOL

TYP

TBD

Unit

NOTES

qJA

qJC

qJB

°C/W

Junction to Case

Junction to Pins

Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site

thermal impedance. TJ=TA + PD x qJA

APPLICATION INRORMATION

2Mx18

SRAM#1

SRAM#4

R=250W

ZQ

Vt

Q0-17

D0-17

SA

D0-17

SA

R/W LD0BW0 BW1C C K K

R/WLD3BW0BW1 C C K K

R

Data In 0-71

Data Out 0-71

Address 0-65

R/W

Vt

R

LD0-3

BW0-7

MEMORY

CONTROLLER

Return CLK

Vt

Source CLK

Return CLK

Source CLK

R=50W Vt=VREF

June. 2003

Rev 0.5

- 13 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

TIMING WAVE FORMS OF READ,WRITE AND NOP

NOP

READ

(burst of 2)

READ

(burst of 2)

WRITE

(burst of 2)

WRITE

(burst of 2)

READ

(burst of 2)

NOP

1

2

3

4

5

6

7

8

K

tKHKL tKLKH

tKHKH

K

LD

R/W

A

tIVKH

tKHIX

A1

A2

A3

A4

A5

tAVKH

tKHAX

tKHDX

tDVKH

tKHDX

tDVKH

D3-1 D3-2 D4-1 D4-2

D

Qxx

Q1-1 Q1-2

Q2-1 Q2-2

Q5-1 Q5-2

Q

tKHCH

tCHQV

tCQ HQV

tCHQX

tCHQZ

tKHCH

tCHQX1

tCHQX

C

tKHKL tKLKH

tKHKH

C

tCHCQV

tCHCQX

CQ

tCHCQV

tCHCQX

Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.

2. Outputs are disabled one cycle after a NOP.

3. D3-1 refers to input to address A3+0, D3-2 refers to input to address A3+1, i.e the next internal burst address following A3+0.

4. If address A4=A5, data Q5-1=D4-1, data Q5-2=D4-2.

Write data is forwarded immediately as read results.

June. 2003

Rev 0.5

- 14 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

Boundary Scan Register

Identification Register

Boundary Scan Register

1

3

2

6

5

6

4

IDCODE

SAMPLE-Z

RESERVED Do Not Use

A,D

K,K

C,C

SAMPLE

Boundary Scan Register

RESERVED Do Not Use

SRAM

CORE

Q

CQ

BYPASS

Bypass Register

CQ

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

TDI

BYPASS Reg.

TDO

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

Identification Reg.

Instruction Reg.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

Control Signals

TAP Controller

TMS

TCK

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

1

Run Test Idle

Select DR

0

Select IR

0

1

Capture DR

0

Capture IR

0

Shift DR

1

Shift IR

1

Exit1 DR

0

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 DR

1

Exit2 IR

1

0

Update DR

0

Update IR

1

June. 2003

Rev 0.5

- 15 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

SCAN REGISTER DEFINITION

Part

512Kx36

1Mx18

2Mx8

Instruction Register

Bypass Register

ID Register

32 bits

Boundary Scan

107 bits

3 bits

1 bit

32 bits

107 bits

32 bits

107 bits

ID REGISTER DEFINITION

Revision Number

Part Configuration

(28:12)

Samsung JEDEC Code

(11: 1)

Part

Start Bit(0)

(31:29)

512Kx36

1Mx18

000

00def0wx0t0q0b0s0

00001001110

1

000

2Mx8

000

Note : Part Configuration

/def=001 for 18Mb, /wx=11 for x36, 10 for x18, 01 for x8

/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O

BOUNDARY SCAN EXIT ORDER

ORDER

PIN ID

ORDER

PIN ID

ORDER

73

PIN ID

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

2G

1J

1

6R

6P

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

10D

9E

74

2

75

3

6N

10C

11D

9C

76

4

7P

77

5

7N

78

6

7R

9D

79

7

8R

11B

11C

9B

80

8

8P

81

9

9R

82

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

11P

10P

10N

9P

10B

11A

Internal

9A

83

84

85

2J

86

3K

3J

10M

11N

9M

8B

87

7C

88

2K

1K

2L

6C

89

9N

8A

90

11L

11M

9L

7A

91

3L

7B

92

1M

1L

6B

93

10L

11K

10K

9J

6A

94

3N

3M

1N

2M

3P

2N

2P

1P

3R

4R

4P

5P

5N

5R

5B

95

5A

96

4A

97

9K

5C

98

10J

11J

11H

10G

9G

4B

99

3A

100

101

102

103

104

105

106

107

1H

1A

2B

11F

11G

9F

3B

1C

1B

10F

11E

10E

3D

3C

1D

Note: 1. NC pins are read as "X" ( i.e. don¢t care.)

June. 2003

Rev 0.5

- 16 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

JTAG DC OPERATING CONDITIONS

Parameter

Power Supply Voltage

Symbol

Min

1.7

Typ

Max

1.9

Unit

V

Note

VDD

VIH

VIL

1.8

Input High Level

1.3

-

VDD+0.3

0.5

V

Input Low Level

-0.3

1.4

V

Output High Voltage(IOH=-2mA)

Output Low Voltage(IOL=2mA)

VOH

VOL

VDD

V

VSS

0.4

V

Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.

JTAG AC TEST CONDITIONS

Parameter

Input High/Low Level

Symbol

VIH/VIL

TR/TF

Min

1.3/0.5

1.0/1.0

0.9

Unit

V

Note

Input Rise/Fall Time

ns

V

Input and Output Timing Reference Level

Note: 1. See SRAM AC test output load on page 11.

1

JTAG AC Characteristics

Parameter

TCK Cycle Time

Symbol

Min

50

20

5

Max

Unit

Note

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

-

5

-

5

-

5

-

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

-

5

-

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

TMS

TDI

tDVCH

tSVCH

tCHDX

tCHSX

PI

(SRAM)

tCLQV

TDO

June. 2003

Rev 0.5

- 17 -

K7J163682B

K7J161882B

K7J160882B

Preliminary

512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM

165 FBGA PACKAGE DIMENSIONS

13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

B

Top View

A

C

Side View

D

A

G

E

B

F

Bottom View

H Æ

E

Symbol

Value

13 ± 0.1

15 ± 0.1

1.3 ± 0.1

0.35 ± 0.05

Units

Note

Symbol

Value

1.0

Units

mm

Note

A

B

C

D

mm

E

F

14.0

mm

G

H

10.0

mm

0.5 ± 0.05

mm

June. 2003

Rev 0.5

- 18 -


型号：	K7J160882B-FC300
厂家：	SAMSUNG
描述：	DDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 双倍数据速率静态存储器内存集成电路
文件：	总18页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7J160882B-FC300 [SAMSUNG]

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