K7A401809A-QC270 [SAMSUNG]
Cache SRAM, 256KX18, 2.2ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;型号: | K7A401809A-QC270 |
厂家: | SAMSUNG |
描述: | Cache SRAM, 256KX18, 2.2ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 静态存储器 内存集成电路 |
文件: | 总17页 (文件大小:465K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
Document Title
128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Remark
Rev. No
History
Draft Date
Preliminary
Preliminary
Preliminary
0.0
0.1
0.2
Initial draft
Jan. 22. 2000
Feb. 10. 2000
April. 03. 2000
Add tCYC 300MHz.
1. Changed DC condition at Icc and ISB.
Icc ; from 540mA to 590mA at -30,
from 490mA to 540mA at -27,
from 440mA to 490mA at -25,
from 410mA to 460mA at -22,
from 390mA to 440mA at -20,
from 370mA to 420mA at -18,
ISB ; from 190mA to 200mA at -30,
from 180mA to 190mA at -27,
from 170mA to 180mA at -25,
from 160mA to 170mA at -22,
from 150mA to 160mA at -20,
from 140mA to 150mA at -18,
Final
May. 15. 2000
1.0
1. Final spec release
2. Changed input & output capacitance.
CIN
; from 6pF to 5pF,
COUT ; from 8pF to 7pF,
3.Changed part number
from K7A4036(18)00A -under 167MHz to K7A4036(18)09A -over183MHz
Final
Final
August. 17. 2000
August. 30. 2000
2.0
3.0
1. Changed Input setup at -275MHz and 300MHz
From 0.8ns to 0.75ns,
1. Changed Input setup at -300MHz
From 0.75ns to 0.6ns
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
The K7A403609A and K7A401809A are 4,718,592-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system¢s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
• 100-TQFP-1420A .
FAST ACCESS TIMES
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403609A and K7A401809A are fabricated using
SAMSUNG¢s high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
PARAMETER
Cycle Time
Symbol -30 -27 -25 -22 -20 -18 Unit
tCYC
tCD
3.3 3.6 4.0 4.4 5.0 5.4 ns
2.2 2.2 2.4 2.6 2.8 3.0 ns
2.2 2.2 2.4 2.6 2.8 3.0 ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
CLK
LBO
128Kx36 , 256Kx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0~A1
A2~A16
or A2~A17
ADDRESS
REGISTER
A0~A16
or A0~A17
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
OUTPUT
GW
BW
CONTROL
LOGIC
REGISTER
BUFFER
WEx
(x=a,b,c,d or a,b)
OE
ZZ
36 or 18
DQa0 ~ DQd7
DQPa ~ DQPd
or DQa0 ~ DQb7
DQPa ~ DQPb
- 2 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
ZZ
VDD
N.C.
VSS
K7A403609A(128Kx36)
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A16
Address Inputs
32,33,34,35,36,37
44,45,46,47,48,49
50,81,82,99,100
83
VDD
VSS
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b,c,d)
OE
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
No Connect
14,16,38,39,42,43,66
N.C.
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Clock
89
98
97
92
Chip Select
Chip Select
Chip Select
Byte Write Inputs
93,94,95,96
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
VDDQ
VSSQ
Output Enable
86
88
87
64
31
GW
BW
ZZ
LBO
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
- 3 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
N.C.
VDD
ZZ
(20mm x 14mm)
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7A401809A(256Kx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
VDD
VSS
N.C.
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,51,52,53,
56,57,66,75,78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b)
OE
Burst Address Advance
Address Status Processor 84
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
85
89
98
97
92
93,94
DQa0~a7
DQb0~b7
DQPa, Pb
VDDQ
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
Output Power Supply
(2.5V or 3.3V)
4,11,20,27,54,61,70,77
VSSQ
Output Ground
5,10,21,26,55,60,71,76
Output Enable
86
88
87
64
31
GW
BW
ZZ
LBO
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
- 4 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A403609A and K7A401809A are synchronous SRAM designed to support the burst address accessing sequence of the P6
and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start
and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
BQ TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
Notes
OPERATION
ZZ
H
L
OE
X
I/O STATUS
High-Z
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
Sleep Mode
L
DQ
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
- 5 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
X
OPERATION
READ
H
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
GW
H
BW
H
L
WEa
X
WEb
X
OPERATION
READ
H
H
H
READ
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 6 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE
PRESENT CYCLE
NEXT CYCLE
OPERATION
WRITE
OPERATION
Initiate Read Cycle
All L Address=An
CS1
WRITE OE
Write Cycle, All bytes
Read Cycle
Data=Qn
L
H
L
Address=An-1, Data=Dn-1
Data=Qn-1 for all bytes
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for all bytes
No carryover from
previous cycle
All L
All L
H
H
H
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=High-Z
No carryover from
previous cycle
H
Initiate Read Cycle
One L Address=An
Data=Qn-1 for one byte
Write Cycle, One byte
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
L
H
H
L
L
Write Cycle, One byte
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for one byte
No carryover from
previous cycle
One L
H
Notes : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.s
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
-0.3 to 4.6
-0.3 to VDD+0.5
-0.3 to VDDQ+0.5
2.2
UNIT
V
VDDQ
VIN
V
V
VIO
V
PD
W
°C
°C
°C
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C£ TA£70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.6
3.6
0
UNIT
V
V
V
VDDQ
VSS
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.6
2.9
0
UNIT
V
V
V
Supply Voltage
VDDQ
VSS
Ground
*Note : -36(275MHz) only support 2.5V I/O.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
pF
CIN
-
-
5
7
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
- 7 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
Input Leakage Current(except ZZ)
Output Leakage Current
SYMBOL
TEST CONDITIONS
MIN
MAX
+2
UNIT
mA
IIL
VDD = Max ; VIN=VSS to VDD
-2
-2
-
mA
IOL
Output Disabled, VOUT=VSS to VDDQ
+2
-30
-27
-25
-22
-20
-18
-30
-27
-25
-22
-20
-18
590
540
490
460
440
420
200
190
180
170
160
150
-
Device Selected, IOUT=0mA, ZZ£VIL,
All Inputs=VIL or VIH , Cycle Time ³ cyc Min
-
Operating Current
ICC
mA
-
-
-
-
-
-
Device deselected, IOUT=0mA,ZZ£VIL,
f=Max, All Inputs£0.2V or ³ VDD-0.2V
ISB
mA
-
-
Standby Current
-
Device deselected, IOUT=0mA, ZZ£0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
-
-
100
50
mA
mA
Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,
f=Max, All Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL = 8.0mA
IOH = -4.0mA
IOL = 1.0mA
IOH = -1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.5*
2.0
-0.3*
1.7
0.8
VIH
VIL
VDD+0.5**
0.7
VIH
VDD+0.5**
*
VIL(Min)=-2.0(Pulse Width £ tCYC/2)
** VIH(Max)=4.6(Pulse Width £ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
0 to 3V
0 to 2.5V
1ns
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
1ns
1.5V
VDDQ/2
See Fig. 1
- 8 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
Dout
RL=50W
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Z0=50W
353W / 1538W
5pF*
* Capacitive Load consists of all components of
the test environment.
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
-30
-27
-25
-22
-20
-18
PARAMETER
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Cycle Time
tCYC
tCD
3.3
-
-
2.2
2.2
-
3.6
-
-
2.2
2.2
-
4.0
-
-
2.4
2.4
-
4.4
-
-
2.6
2.6
-
5.0
-
-
2.8
2.8
-
5.4
-
-
3.0
3.0
-
ns
ns
ns
ns
ns
ns
ns
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
tOE
-
-
-
-
-
-
tLZC
tOH
0
0
0
0
0
0
0.8
0
-
0.8
0
-
0.8
0
-
1.0
0
-
1.0
0
-
1.0
0
-
tLZOE
-
-
-
-
-
-
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tHZOE
tHZC
tCH
-
2.2
-
2.2
-
2.4
-
2.6
-
2.8
-
3.0
0.8
1.5
1.5
0.6
0.6
2.2
0.8
2.2
0.8
1.7
1.7
0.8
0.8
2.4
1.0
2.0
2.0
1.2
1.2
2.6
1.0
2.0
2.0
1.2
1.2
2.8
1.0
2.4
2.4
1.2
1.2
3.0
ns
ns
ns
ns
ns
ns
-
-
-
-
-
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Clock Low Pulse Width
tCL
1.5
Address Setup to Clock High
tAS
0.75
0.75
Address Status Setup to Clock High
Data Setup to Clock High
tSS
0.6
0.6
0.6
0.6
0.75
0.75
0.75
0.75
0.8
0.8
0.8
0.8
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
tDS
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
tWS
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
tADVS
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
tCSS
tAH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
0.3
0.3
0.3
0.3
0.3
0.3
2
0.3
0.3
0.3
0.3
0.3
0.3
2
0.3
0.3
0.3
0.3
0.3
0.3
2
0.4
0.4
0.4
0.4
0.4
0.4
2
0.4
0.4
0.4
0.4
0.4
0.4
2
0.4
0.4
0.4
0.4
0.4
0.4
2
tSH
ns
Data Hold from Clock High
tDH
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
tWH
ns
tADVH
tCSH
tPDS
tPUS
ns
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
ns
cycle
cycle
2
2
2
2
2
2
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP
is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times
whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 9 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
- 10 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
- 11 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
- 12 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
- 13 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
- 14 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
I/O[0:71]
Data
Address
A[0:17]
A[17]
A[0:16]
A[17]
A[0:16]
Address Data
CS
Address Data
CS
CLK
2
2
CS2
CS2
64-Bits
Microprocessor
CLK
ADSC
WEx
OE
128Kx36
SPB
SRAM
CLK
ADSC
WEx
OE
128Kx36
SPB
SRAM
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A2
A1
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth
15 64K depth
Don¢t Care
Undefined
16 128K depth
17 256K depth
- 15 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx18 Synchronous Pipelinde Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
I/O[0:71]
Data
Address
A[18]
A[0:17]
A[18]
A[0:17]
A[0:18]
Address Data
CS
Address Data
CS
CLK
2
2
CS2
CS2
Microprocessor
CLK
ADSC
WEx
OE
256Kx18
SPB
SRAM
CLK
ADSC
WEx
OE
256Kx18
SPB
SRAM
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A2
A1
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Don¢t Care
Undefined
- 16 -
August 2000
Rev 3.0
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
- 17 -
August 2000
Rev 3.0
相关型号:
K7A401809B-PC250
Cache SRAM, 256KX18, 2.4ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100
SAMSUNG
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