K6X4008T1F-VF70 [SAMSUNG]
512Kx8 bit Low Power and Low Voltage CMOS Static RAM; 512Kx8位低功耗和低电压CMOS静态RAM型号: | K6X4008T1F-VF70 |
厂家: | SAMSUNG |
描述: | 512Kx8 bit Low Power and Low Voltage CMOS Static RAM |
文件: | 总9页 (文件大小:176K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6X4008T1F Family
CMOS SRAM
Document Title
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
Initial Draft
July 29, 2002
Preliminary
0.1
Revised
October 14, 2002
December 2, 2002
March 26, 2003
Preliminary
Preliminary
Preliminary
- Added 55ns product( Vcc = 3.0V~3.6V)
0.2
Revised
- Added Commercial product
0.21
Revised
- Errata correction : corrected commercial product family name from
K6X4008T1F-F to K6X4008T1F-B in PRODUCT FAMILY.
1.0
Finalized
September 16, 2003
Final
- Changed ICC from 4mA to 2mA
- Changed ICC1 from 4mA to 3mA
- Changed ICC2 from 30mA to 25mA
- Changed ISB1(Commercial) from 15mA to 10mA
- Changed ISB1(industrial) from 20mA to 10mA
- Changed ISB1(Automotive) from 30mA to 20mA
- Changed IDR(Commercial) from 15mA to 10mA
- Changed IDR(industrial) from 20mA to 10mA
- Changed IDR(Automotive) from 30mA to 20mA
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
512K´ 8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: Full CMOS
· Organization: 512K´ 8
The K6X4008T1F families are fabricated by SAMSUNG¢s
advanced full CMOS process technology. The families support
various operating temperature range and have various pack-
age types for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
· Power Supply Voltage: 2.7~3.6V
· Low Data Retention Voltage: 2V(Min)
· Three State Outputs
· Package Type: 32-SOP-525, 32-TSOP2-400F/R
32-TSOP1-0813.4F
PRODUCT FAMILY
Power Dissipation
Vcc
Range
Product Family Operating Temperature
Speed
PKG Type
Standby Operating
(ISB1, Max) (ICC2, Max)
K6X4008T1F-B
K6X4008T1F-F
Commercial(0~70°C)
Industrial(-40~85°C)
10mA
32-SOP-525, 32-TSOP1-0813.4F
551)/702)/85ns
702)/85ns
32-TSOP2-400F/R
10mA
20mA
2.7~3.6V
25mA
32-SOP-525, 32-TSOP1-0813.4F
32-TSOP2-400F
K6X4008T1F-Q Automotive(-40~125°C)
1. This parameter is measured in the voltage range of 3.0V~3.6V with 30pF test load.
2. This parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A18
A16
A14
A12
A7
VCC
A15
A17
WE
A13
A8
1
VCC
A15
A17
WE
A13
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
A18
A16
A14
A12
A7
Clk gen.
Precharge circuit.
2
3
3
4
4
5
5
A6
6
6
A6
A5
7
A9
A9
7
A5
32-TSOP2
(Reverse)
32-SOP
32-TSOP2
(Forward)
A4
8
A11
OE
A11
OE
8
A4
Row
Addresses
Row
select
A3
9
9
A3
Memory array
A2
10
11
12
13
14
15
16
A10
CS
A10
CS
10
11
12
13
14
15
16
A2
A1
A1
A0
I/O8
I/O7
I/O6
I/O5
I/O4
I/O8
I/O7
I/O6
I/O5
I/O4
A0
I/O1
I/O2
I/O3
VSS
I/O1
I/O2
I/O3
VSS
I/O1
I/O8
Data
cont
I/O Circuit
A11
A9
A8
1
2
3
4
5
6
7
8
9
32
OE
A10
CS
Column select
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
Data
cont
32-STSOP1
(Forward)
10
Column Addresses
11
12
13
14
15
16
A6
A5
A4
A1
A2
A3
CS
Control
logic
WE
OE
Name Function
Name Function
A0~A18 Address Inputs
Vcc
Vss
Power
WE
CS
OE
Write Enable Input
Chip Select Input
Output Enable Input
Ground
I/O1~I/O8 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°C)
Industrial Products(-40~85°C)
Automotive Products(-40~125°C)
Part Name
Function
Part Name
Function
Part Name
Function
K6X4008T1F-GB551)
K6X4008T1F-GB70
K6X4008T1F-GB85
K6X4008T1F-YB551)
K6X4008T1F-YB70
K6X4008T1F-YB85
K6X4008T1F-VB551)
K6X4008T1F-VB70
K6X4008T1F-VB85
K6X4008T1F-MB551)
K6X4008T1F-MB70
K6X4008T1F-MB85
K6X4008T1F-GF551)
K6X4008T1F-GF70
K6X4008T1F-GF85
K6X4008T1F-YF551)
K6X4008T1F-YF70
K6X4008T1F-YF85
K6X4008T1F-VF551)
K6X4008T1F-VF70
K6X4008T1F-VF85
K6X4008T1F-MF551)
K6X4008T1F-MF70
K6X4008T1F-MF85
K6X4008T1F-GQ70 32-SOP, 70ns, L
K6X4008T1F-GQ85 32-SOP, 85ns, L
K6X4008T1F-YQ70 32-sTSOP1-F, 70ns, L
K6X4008T1F-YQ85 32-sTSOP1-F, 85ns, L
K6X4008T1F-VQ70 32-TSOP2-F, 70ns, L
K6X4008T1F-VQ85 32-TSOP2-F, 85ns, L
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 85ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 85ns, LL
32-sTSOP1-F, 55ns, LL
32-sTSOP1-F, 70ns, LL
32-sTSOP1-F, 85ns, LL
32-sTSOP1-F, 55ns, LL
32-sTSOP1-F, 70ns, LL
32-sTSOP1-F, 85ns, LL
32-TSOP2-F, 55ns, LL
32-TSOP2-F, 70ns, LL
32-TSOP2-F, 85ns, LL
32-TSOP2-F, 55ns, LL
32-TSOP2-F, 70ns, LL
32-TSOP2-F, 85ns, LL
32-TSOP2-R, 55ns, LL
32-TSOP2-R, 70ns, LL
32-TSOP2-R, 85ns, LL
32-TSOP2-R, 55ns, LL
32-TSOP2-R, 70ns, LL
32-TSOP2-R, 85ns, LL
1. Operating voltage range is 3.0V~3.6V
FUNCTIONAL DESCRIPTION
CS
H
L
OE
WE
I/O
High-Z
High-Z
Dout
Mode
Power
X1)
H
X1)
H
Deselected
Output Disabled
Read
Standby
Active
Active
Active
L
L
H
L
X1)
L
Din
Write
1. X means don¢t care (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN, VOUT
VCC
-0.2 to VCC+0.3(max. 3.9V)
-0.2 to 3.9
1.0
-
V
-
PD
W
-
Storage temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
°C
-
K6F4008T1F-B
K6F4008T1F-F
K6F4008T1F-Q
Operating Temperature
TA
-40 to 85
-40 to 125
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Ground
Vcc
2.7
3.0/3.3
3.6
0
V
Vss
VIH
VIL
0
0
-
V
V
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
Note:
2.2
-0.23)
-
1. Commercial Product: TA=0 to 70°C, otherwise specified
Industrial Product: TA=-40 to 85°C, otherwise specified
Automotive Product: TA=-40 to 125°C, otherwise specified
2. Overshoot: VCC+2.0V in case of pulse width £ 30ns
3. Undershoot: -2.0V in case of pulse width £ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
-
-
pF
pF
Input/Output capacitance
CIO
VIO=0V
10
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
Output leakage current
Operating power supply current
VIN=Vss to Vcc
-1
-
-
-
-
-
-
-
-
-
-
-
1
1
mA
mA
mA
mA
mA
V
ILO
CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
-1
ICC
-
2
Cycle time=1ms, 100% duty, IIO=0mA CS£0.2V,VIN£0.2V or VIN³ Vcc-0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=2.1mA
ICC1
ICC2
VOL
VOH
ISB
-
3
Average operating current
-
25
0.4
-
Output low voltage
Output high voltage
Standby Current(TTL)
-
IOH=-1.0mA
2.4
V
CS=VIH, Other inputs = VIL or VIH
K6X4008T1F-B
-
-
-
-
0.3
10
10
20
mA
mA
mA
mA
Standby Current (CMOS)
ISB1
CS³ Vcc-0.2V, Other inputs=0~Vcc
K6X4008T1F-F
K6X4008T1F-Q
4
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
1)
CL =30pF+1TTL
1. Including scope and jig capacitance
1. 55ns, 70ns product
AC CHARACTERISTICS
(VCC=2.7~3.6V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C)
Speed Bins
55ns1)
Parameter List
Symbol
Units
70ns
85ns
Min
55
-
Max
Min
70
-
Max
Min
85
-
Max
Read cycle time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
-
85
85
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO
tOE
tLZ
-
-
-
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
Read
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
20
20
-
0
25
25
-
0
25
25
-
tOHZ
tOH
tWC
tCW
tAS
0
0
0
10
55
45
0
10
70
60
0
10
85
70
0
-
-
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
45
40
0
-
60
55
0
-
70
55
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
0
20
-
0
25
-
0
25
-
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
35
0
-
-
-
5
-
5
-
5
-
1. Voltage range is 3.0V~3.6V for commercial and industrial product.
DATA RETENTION CHARACTERISTICS
Typ1)
Item
Symbol
Test Condition
Min
Max
Unit
V
Vcc for data retention
VDR
CS³ Vcc-0.2V
2.0
-
-
3.6
10
10
20
-
K6X4008T1F-B
K6X4008T1F-F
K6X4008T1F-Q
mA
mA
mA
Data retention current
IDR
Vcc=3.0V, CS³ Vcc-0.2V
0.5
-
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
-
-
See data retention waveform
ms
-
1. Typical values are measured at TA = 25°C and not 100% tested.
5
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS
tHZ
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
tDH
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
7
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
11.43±0.20
0.450±0.008
14.12±0.30
0.556±0.012
0.80±0.20
0.031±0.008
+0.10
-0.05
#1
#16
0.20
2.74±0.20
0.108±0.008
20.87
0.822
+0.004
0.008
MAX
-0.002
3.00
0.118
MAX
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
1.27
0.050
0.71
0.028
+0.004
-0.002
0.05
0.002
(
)
0.016
MIN
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
+0.10
-0.05
0.20
13.40±0.20
0.528±0.008
0.008+0.004
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
0.15
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
8
Revision 1.0
September 2003
K6X4008T1F Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
0.010
(
)
#32
#17
0.45~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
#1
#16
0.50
0.020
(
)
+0.10
-0.05
+0.004
-0.002
0.15
21.35
0.841
1.00±0.10
0.039±0.004
MAX
0.006
1.20
0.047
20.95±0.10
0.825±0.004
MAX
0.10 MAX
0.004 MAX
0.05
0.002
MIN
1.27
0.050
0.95
0.037
0.40±0.10
0.016±0.004
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0~8°
0.25
0.010
(
)
#1
#16
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
#32
#17
0.50
0.020
(
)
+0.10
-0.05
+0.004
-0.002
0.15
21.35
0.841
1.00±0.10
0.039±0.004
MAX
0.006
1.20
0.047
20.95±0.10
0.825±0.004
MAX
0.10 MAX
0.004 MAX
1.27
0.050
0.05
0.002
0.40±0.10
0.016±0.004
0.95
0.037
MIN
(
)
9
Revision 1.0
September 2003
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