K6X1008T2D-TQ700 [SAMSUNG]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32;
| 型号： | K6X1008T2D-TQ700 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6X1008T2D Family
CMOS SRAM
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
0.1
Initial draft
July 15, 2002
Preliminary
Revised
December 4, 2002
Preliminary
- Deleted 32-TSOP1-0820R, 32-TSOP1-0813.4F/R Package Type.
- Added Commercial product.
- Added 55ns product( Vcc = 3.0V~3.6V)
0.2
1.0
Revised
June 23, 2003
Preliminary
Final
- Added Lead Free 32-SOP-525 Product
- Added Lead Free 32-TSOP1-0820F Product
Finalized
September 16, 2003
- Changed ICC from 3mA to 2mA
- Changed ICC2 from 25mA to 20mA
- Changed ISB1(Commercial) from 10µA to 6µA
- Changed ISB1(industrial) from 10µA to 6µA
- Changed ISB1(Automotive) from 20µA to 10µA
- Changed IDR(Commercial) from 10µA to 6µA
- Changed IDR(industrial) from 10µA to 6µA
- Changed IDR(Automotive) from 20µA to 10µA
2.0
Revised
March 27, 2005
Final
- Changed ISB1 of Automotive product from 10µA to 25µA
- Changed IDR of Automotive product from 10µA to 25µA
- Added Lead Free Products
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
128Kx8 bit Super Low Power and Low Voltage full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 128K x 8
The K6X1008T2D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
verious operating temperature ranges and have various pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
• Power Supply Voltage: 2.7~3.6V
• Low Data Retention Voltage: 1.5V(Min)
• Three state outputs
• Package Type: 32-SOP-525, 32-TSOP1-0820F
32-SOP-525, 32-TSOP1-0820F
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
Speed
PKG Type
Standby Operating
(ISB1, Max) (ICC2, Max)
K6X1008T2D-B
K6X1008T2D-F
Commercial(0~70°C)
Industrial(-40~85°C)
551)/702)/85ns
702)/85ns
6µA
32-SOP-525
32-TSOP1-0820F
2.7~3.6V
20mA
K6X1008T2D-Q Automotive(-40~125°C)
25µA
1. This parameter is measured in the voltage range of 3.0V~3.6V with 30pF test load.
2. This parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
VCC
A15
CS2
WE
A13
A8
1
32
NC
A16
A14
A12
A7
2
31
3
30
29
4
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
28
5
Row
select
Row
Addresses
Memory array
27
A6
6
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
26
A9
A5
7
32-SOP 25
A11
OE
A4
8
32-TSOP
24
23
22
21
20
19
18
17
A3
9
9
Type1-Forward
10
11
12
13
14
15
16
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A2
10
11
12
13
14
15
16
A1
A0
A6
A5
A4
A1
A2
A3
I/O1
I/O2
I/O3
VSS
I/O1
I/O8
Data
cont
I/O Circuit
Column select
Data
cont
Column Addresses
Name
A0~A16
WE
Function
Address Inputs
CS1
Control
logic
CS2
WE
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power
CS1,CS2
OE
OE
I/O1~I/O8
Vcc
Vss
Ground
NC
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°C)
Industrial Products(-40~85°C)
Atomotive Products(-40~125°C)
Part Name
Function
Part Name
Function
Part Name
Function
1)
1)
K6X1008T2D-GB55
K6X1008T2D-GB70
K6X1008T2D-GB85
K6X1008T2D-BB55
K6X1008T2D-BB70
K6X1008T2D-BB85
K6X1008T2D-TB55
K6X1008T2D-TB70
K6X1008T2D-TB85
K6X1008T2D-PB55
K6X1008T2D-PB70
K6X1008T2D-PB85
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 85ns, LL
K6X1008T2D-GF55
K6X1008T2D-GF70
K6X1008T2D-GF85
K6X1008T2D-BF55
K6X1008T2D-BF70
K6X1008T2D-BF85
K6X1008T2D-TF55
K6X1008T2D-TF70
K6X1008T2D-TF85
K6X1008T2D-PF55
K6X1008T2D-PF70
K6X1008T2D-PF85
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 85ns, LL
K6X1008T2D-GQ70
K6X1008T2D-GQ85
32-SOP, 70ns, L
32-SOP, 85ns, L
2)
K6X1008T2D-BQ70
K6X1008T2D-BQ85
K6X1008T2D-TQ70
K6X1008T2D-TQ85
K6X1008T2D-PQ70
K6X1008T2D-PQ85
32-SOP, 70ns, L, LF
32-SOP, 85ns, L, LF
32-TSOP-F, 70ns, L
32-TSOP-F, 85ns, L
32-TSOP-F, 70ns, L, LF
32-TSOP-F, 85ns, L, LF
1,2)
1,2)
2)
32-SOP, 55ns, LL, LF
32-SOP, 70ns, LL, LF
32-SOP, 85ns, LL, LF
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 85ns, LL
32-TSOP-F, 55ns, LL, LF
32-TSOP-F, 70ns, LL, LF
32-TSOP-F, 85ns, LL, LF
32-SOP, 55ns, LL, LF
32-SOP, 70ns, LL, LF
32-SOP, 85ns, LL, LF
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 85ns, LL
32-TSOP-F, 55ns, LL, LF
32-TSOP-F, 70ns, LL, LF
32-TSOP-F, 85ns, LL, LF
2)
2)
2)
2)
1)
1)
2)
2)
1,2)
2)
1,2)
2)
2)
2)
1. Operating voltage range is 3.0V~3.6V
2. Lead Free Product
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Deselected
Deselected
Output Disabled
Read
Power
Standby
Standby
Active
X1)
L
X1)
X1)
H
High-Z
High-Z
High-Z
Dout
X1)
L
X1)
H
X1)
H
H
H
H
L
L
L
H
L
Active
X1)
Din
Write
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-0.2 to VCC+0.3V(Max. 3.9V)
V
-
-0.2 to 3.9
1.0
V
-
PD
W
°C
°C
°C
°C
-
Storage temperature
TSTG
-65 to 150
0 to 70
-
K6X1008T2D-B
K6X1008T2D-F
K6X1008T2D-Q
Operating Temperature
TA
-40 to 85
-40 to 125
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
Max
3.6
0
Unit
V
Supply voltage
Ground
3.0/3.3
Vss
0
-
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
Note:
VIH
2.2
V
-0.23)
VIL
-
V
1. Commercial Product: TA=0 to 70°C, Otherwise specified
. Industrial Product: TA=-40 to 85°C, Otherwise specified
Automotive Product: TA=-40 to 125°C, Otherwise specified
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
2
µA
µA
Output leakage current
Operating power supply current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read
ICC
mA
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2≥Vcc-0.2V,
VIN≤0.2V or VIN≥VCC-0.2V
ICC1
ICC2
-
-
-
-
3
mA
Average operating current
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,
VIN=VIH or VIL
20 mA
Output low voltage
Output high voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL=2.1mA
-
-
-
-
-
-
-
0.4
-
V
V
IOH=-1.0mA
2.4
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
-
-
0.3 mA
K6X1008T2D-B
6
6
µA
µA
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V,
Other inputs=0~Vcc
Standby Current(CMOS)
ISB1
K6X1008T2D-F
K6X1008T2D-Q
25 µA
4
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=2.7~3.6V, Commercial product:TA=0 to 70°C, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C )
Speed Bins
)
Parameter List
Symbol
Units
1
70ns
Max
85ns
Max
55ns
Min
Max
Min
70
-
Min
85
-
Read Cycle Time
tRC
tAA
55
-
-
55
55
25
-
-
70
70
35
-
-
85
85
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
-
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
-
-
-
Read
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
25
25
-
0
25
25
-
0
25
25
-
tOHZ
tOH
tWC
tCW
tAS
0
0
0
10
55
45
0
10
70
60
0
15
85
70
0
-
-
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
-
-
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
50
0
-
70
60
0
-
-
-
-
Write
Write Recovery Time
-
-
-
Write to Output High-Z
0
25
-
0
25
-
0
30
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
20
0
25
0
35
0
-
-
-
tOW
5
-
5
-
5
-
1. Voltage range is 3.0V~3.6V for commercial and industrial product.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
V
CS1≥Vcc-0.2V1)
Vcc for data retention
VDR
2.0
-
-
-
3.6
6
K6X1008T2D-B
K6X1008T2D-F
K6X1008T2D-Q
-
-
µA
µA
µA
Vcc=3.0V, CS1≥Vcc-0.2V1)
Data retention current
IDR
6
25
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
-
-
See data retention waveform
ms
-
1. CS1≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V
5
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
7
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data Valid
Data in
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
2.7V
CS2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
8
Revision 2.0
March 2005
K6X1008T2D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
14.12±0.30
0.556±0.012
11.43±0.20
0.450±0.008
#1
#16
0.80±0.20
+0.10
0.20
2.74±0.20
0.031±0.008
-0.05
20.87
MAX
0.108±0.008
+0.004
0.822
0.008
-0.002
3.00
0.118
MAX
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
0.71
0.028
1.27
0.050
+0.004
-0.002
(
)
0.05
0.002
0.016
MIN
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
0.008+0.004
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
9
Revision 2.0
March 2005
相关型号：
K6X4008C1F-BB550
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.525 INCH, LEAD FREE, PLASTIC, SOP-32
SAMSUNG
K6X4008C1F-BB700
Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, 0.525 INCH, LEAD FREE, PLASTIC, SOP-32
SAMSUNG
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