K6T4016C3B-RF10 [SAMSUNG]
256Kx16 bit Low Power CMOS Static RAM; 256Kx16位低功耗CMOS静态RAM
| 型号： | K6T4016C3B-RF10 |
| 厂家： | 
SAMSUNG |
| 描述： | 256Kx16 bit Low Power CMOS Static RAM |
| 文件： | 总9页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SRAM
K6T4016C3B Family
Document Title
256Kx16 bit Low Power CMOS Static RAM
Revision History
Revision No.
History
Draft Data
Remark
0.0
Initial draft
June 28, 1996
Advance
0.1
Revise
September 19, 1996
Preliminary
- Die name change ; A to B
1.0
2.0
Finalize
December 17, 1996
February 17, 1997
Final
Final
Revise
- Operating current update and release.
ICC(Read/Write) = 30/60 ® 15/75mA
ICC1(Read/Write) = 30/60 ® 15/75mA
ICC2 = 160 ® 130mA
3.0
4.0
Revise
February 17, 1998
June 22, 1998
Final
Final
- Change datasheet format
- Remove ICC write value from table.
Revise
- Change test load at 55ns: 100pF ® 50pF
4.01
5.0
Errarta correction
August 8, 1998
May 22, 2001
Revise
Final
- Add 55ns product for industrial temperature
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
256Kx16 bit Low Power CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
The K6T4016C3B families are fabricated by SAMSUNG¢s
advanced CMOS process technology. The families support
various operating temperature ranges and small package
types for user flexibility of system design. The families also
support low data retention voltage for battery back-up opera-
tion with low data retention current.
· Organization: 256Kx16
· Power Supply Voltage: 4.5~5.5V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 44-TSOP2-400F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
551)/70ns
K6T4016C3B-B
K6T4016C3B-F
Commercial(0~70°C)
Industrial(-40~85°C)
20mA
50mA
4.5~5.5V
130mA
44-TSOP2-400F/R
551)/70/100ns
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A4
A3
A2
A1
A0
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
A4
A3
A2
A1
A0
CS
A5
A6
A7
OE
UB
LB
A5
A6
A7
OE
UB
Clk gen.
Precharge circuit.
A13
A14
A0
Vcc
Vss
CS
LB
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
A1
9
Memory array
1024 rows
256´ 16 columns
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A16
A17
A2
10
11
Row
select
44-TSOP2
Forward
44-TSOP2
Reverse
12
13
14
15
16
17
18
19
20
21
22
A3
A4
Data
cont
I/O Circuit
Column select
I/O1~I/O8
Data
cont
I/O9~I/O16
Data
cont
A8 A9 A10 A5 A6 A7 A4 A12
Name
CS
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Name
Function
Power
Ground
Vcc
Vss
UB
LB
OE
WE
OE
UB
LB
WE
Upper Byte(I/O9~16)
Lower Byte (I/O1~8)
No Connection
Control
logic
A0~A17
I/O1~I/O16 Data Inputs/Outputs
NC
CS
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
PRODUCT LIST
Commercial Temperature Product(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T4016C3B-TB55
K6T4016C3B-TB70
K6T4016C3B-RB55
K6T4016C3B-RB70
44-TSOP2-F, 55ns, LL-pwr
44-TSOP2-F, 70ns, LL-pwr
44-TSOP2-R, 55ns, LL-pwr
44-TSOP2-R, 70ns, LL-pwr
K6T4016C3B-TF55
K6T4016C3B-TF70
K6T4016C3B-TF10
K6T4016C3B-RF55
K6T4016C3B-RF70
K6T4016C3B-RF10
44-TSOP2-F, 55ns, LL-pwr
44-TSOP2-F, 70ns, LL-pwr
44-TSOP2-F, 100ns, LL-pwr
44-TSOP2-R, 55ns, .LL-pwr
44-TSOP2-R, 70ns, .LL-pwr
44-TSOP2-R, 100ns, LL-pwr
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
X1)
H
L
L
L
H
L
L
H
H
L
High-Z
Dout
L
L
H
L
L
Dout
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
High-Z
Din
L
L
L
L
Din
1. X means don¢t care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
-0.5 to 7.0
-0.5 to7.0
1.0
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-
V
-
PD
W
°C
°C
°C
-
-
Storage temperature
TSTG
-65 to 150
0 to 70
-
K6T4016C3B-B
K6T4016C3B-F
-
Operating Temperature
TA
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec(Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
4.5
0
Typ
Max
Unit
V
Supply voltage
Ground
5.0
5.5
0
Vss
0
-
V
Vcc+0.52)
0.8
Input high voltage
Input low voltage
VIH
2.2
-0.53)
V
VIL
-
V
Note:
1. Commercial Product: TA=0 to 70°C, otherwise specified
Industrial Product: TA=-40 to 85°C, otherwise specified
2. Overshoot: VCC+3.0V in case of pulse width £ 30ns
3. Undershoot: -3.0V in case of pulse width £ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Symbol
ILI
Min
-1
-1
-
Typ
Max Unit
Item
Test Conditions
Input leakage current
Output leakage current
Operating power supply
VIN=Vss to Vcc
-
-
-
-
-
-
-
-
-
-
1
mA
mA
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
1
ICC
15
15
75
mA
Read
Write
-
Cycle time=1ms, 100% duty, IIO=0mA
CS£0.2V, VIN£0.2V or VIN³ Vcc-0.2V
ICC1
mA
Average operating current
-
ICC2
VOL
VOH
ISB
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=2.1mA
-
130 mA
Output low voltage
-
2.4
-
0.4
-
V
V
Output high voltage
Standby Current (TTL)
Standby Current(CMOS)
IOH=-1.0mA
CS=VIH, Other inputs=VIL or VIH
CS³ Vcc-0.2V, Other inputs=0~Vcc
3
mA
mA
201)
ISB1
-
1. Industrial Product = 50mA
4
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=50pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
55ns
Max
70ns
Max
100ns
Min
55
-
Min
70
-
Min
Max
Read cycle time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
100
-
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO
tOE
-
-
-
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
UB, LB enable to low-Z output
Chip disable to high-Z output
Output Disable to High-Z Output
UB, LB disable to high-Z output
Output hold from address change
LB, UB valid to data output
Write cycle time
-
-
-
tLZ
10
5
10
5
10
5
tOLZ
tBLZ
tHZ
-
-
-
Read
5
-
5
-
5
-
0
20
20
20
-
0
25
25
25
-
0
30
30
30
-
tOHZ
tBHZ
tOH
tBA
0
0
0
0
0
0
10
-
10
-
10
-
25
-
35
-
50
-
tWC
tCW
tAS
55
45
0
70
60
0
100
80
0
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
45
0
-
60
55
0
-
80
70
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
0
20
-
0
25
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
25
0
30
0
40
0
-
-
-
tOW
tBW
5
-
5
-
5
-
45
-
60
-
-
80
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
Test Condition
CS³ Vcc-0.2V
Vcc=3.0V
Min
Typ
Max
Unit
V
2.0
-
-
-
-
-
5.5
151)
-
IDR
mA
tSDR
0
See data retention waveform
ms
tRDR
5
-
1. Industrial Product: 20mA
5
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tWR(4)
tCW(2)
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
7
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
WE
tAS(3)
tWP(1)
tDH
tDW
Data Valid
Data in
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
8
Revision 5.0
May 2001
CMOS SRAM
K6T4016C3B Family
Units: millimeter(inch)
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
0.010
(
)
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
0.020
(
)
#1
#22
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35±0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0~8°
0.25
0.010
(
)
#1
#22
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
)
(
0.020
#44
#23
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35±0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
9
Revision 5.0
May 2001
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