K6R1016V1D-FI12 [SAMSUNG]
Standard SRAM, 64KX16, 12ns, CMOS, PBGA48;
| 型号： | K6R1016V1D-FI12 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 64KX16, 12ns, CMOS, PBGA48 静态存储器 |
| 文件： | 总11页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No.
History
Draft Data
Remark
Rev. 0.0
Rev. 0.1
Rev. 0.2
Initial document.
Speed bin modify
Current modify
May. 11. 2001
June. 18. 2001
September. 9. 2001
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 0.2
September 2001
- 1 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL)
(CMOS) : 5mA(Max.)
Operating K6R1016V1D- 08: 80mA(Max.)
K6R1016V1D-10: 65mA(Max.)
K6R1016V1D-12: 55mA(Max.)
• Single 3.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
GENERAL DESCRIPTION
The K6R1016V1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits.
The K6R1016V1D uses 16 common input and output lines and
has at output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control (UB, LB). The device is
fabricated using SAMSUNG¢s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The K6R1016V1D is packaged in a 400mil 44-pin plastic SOJ
or TSOP2 forward or 48-TBGA.
: 20mA(Max.)
• 2V Mimimum Data Retention ( Idr=1mA )
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16
• Standard Pin Configuration:
K6R1016V1D-J: 44-SOJ-400
K6R1016V1D-T: 44-TSOP2-400BF
K6R1016V1D-F: 48-TBGA ( 6.0mm X 7.0mm )
with 0.75mm ball pitch
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
K6R1016V1D-C08/C10/C12
Commercial Temp.
Industrial Temp.
Clk Gen.
Pre-Charge Circuit
K6R1016V1D-I08/I10/I12
A0
A1
A2
A3
A4
Memory Array
512 Rows
128x16 Columns
A5
A6
A7
A8
PIN FUNCTION
Pin Name
Pin Function
Address Inputs
Data
Cont.
I/O Circuit &
Column Select
I/O1~I/O8
A0 - A15
WE
Write Enable
Chip Select
Data
Cont.
I/O9~I/O16
CS
Gen.
CLK
OE
Output Enable
A9 A10 A11 A12 A13 A14 A15
LB
Lower-byte Control(I/O1~I/O8)
Upper-byte Control(I/O9~I/O16)
Data Inputs/Outputs
Power(+3.3V)
UB
I/O1 ~ I/O16
VCC
WE
OE
VSS
Ground
UB
LB
N.C
No Connection
CS
Revision 0.2
September 2001
- 2 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
PIN CONFIGURATION(TOP VIEW)
1
LB
2
3
4
5
6
A0
A1
1
2
3
4
5
6
7
8
9
44 A15
43 A14
42 A13
41 OE
A
B
C
D
E
F
OE
UB
A0
A3
A1
A4
A2
N.C
I/O9
I/O10
Vcc
A2
A3
I/O1
CS
A4
40 UB
CS
I/O1
I/O2
I/O3
39 LB
I/O2
Vss
I/O3
I/O4
I/O5
I/O6
N.C
A8
A5
A6
I/O11
I/O12
I/O13
I/O14
WE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 N.C
27 A12
26 A11
25 A10
24 A9
N.C
N.C
A14
A12
A9
A7
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A5 18
SOJ/
Vcc
I/O7
I/O8
N.C
N.C
A15
A13
A10
Vss
TSOP2
I/O15
I/O16
N.C
G
H
A11
A6 19
A7 20
48-TBGA ( Top View )
A8 21
N.C 22
23 N.C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
Unit
V
-0.5 to 4.6
-0.5 to 4.6
1
V
Pd
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Commercial
Operating Temperature
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70°C)
Parameter
Supply Voltage
Symbol
Min
3.15
3.0
Typ
3.3
3.3
0
Max
3.6
Unit
V
(1)
VCC
(2)
Supply Voltage
Ground
3.6
V
VCC
0
0
V
VSS
VIH
VIL
VCC+0.3(3)
0.8
Input High Voltage
Input Low Voltage
2.0
-
V
-0.3(4)
-
V
(1) For K6R1016V1D-08 only.
(2) For all speed grades except K6R1016V1D-08.
(3) VIH(Max) = VCC + 2.0V a.c(Pulse Width £ 8ns) for I £ 20mA
(4) VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
Revision 0.2
September 2001
- 3 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
*DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise specfied)
Min
Max
Parameter
Symbol
Test Conditions
Unit
Input Leakage Current
ILI
VIN=VSS to VCC
-2
2
mA
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
Output Leakage Current
ILO
ICC
-2
2
mA
8ns
10ns
12ns
-
80
65
55
20
5
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA
Operating Current
-
mA
-
ISB
ISB1
VOL
VOH
Min. Cycle, CS=VIH
-
-
mA
mA
V
Standby Current
f=0MHz, CS ³ VCC-0.2V,VIN³ VCC-0.2V or VIN£0.2V
Output Low Voltage Level
Output High Voltage Level
IOL=8mA
-
0.4
-
IOH=-4mA
2.4
V
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
CI/O
Test Conditions
VI/O=0V
MIN
Max
Unit
Input/Output Capacitance
Input Capacitance
-
-
8
6
pF
pF
VIN=0V
CIN
* Capacitance is sampled and not 100% tested.
AC CHARACTERISTICS(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
0V to 3V
3ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
Output Loads(A)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
RL = 50W
DOUT
319W
VL = 1.5V
30pF*
DOUT
ZO = 50W
353W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
Revision 0.2
September 2001
- 4 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
READ CYCLE*
K6R1016V1D-08 K6R1016V1D-10 K6R1016V1D-12
Parameter
Symbol
Unit
Min
Max
Min
10
-
Max
Min
12
-
Max
Read Cycle Time
tRC
tAA
8
-
-
8
8
4
4
-
-
10
10
5
-
12
12
6
6
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tBA
-
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
-
-
-
5
-
Chip Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
tLZ
3
0
0
-
3
0
0
0
0
0
3
0
-
-
3
0
0
0
0
0
3
0
-
tBLZ
tOLZ
tHZ
-
-
-
-
-
-
4
4
4
-
5
6
6
6
-
tOHZ
tBHZ
tOH
tPU
-
5
-
5
3
0
-
-
-
-
-
tPD
8
10
12
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
K6R1016V1C-08
K6R1016V1C-10
K6R1016V1C-12
Parameter
Symbol
Unit
Min
8
Max
Min
10
7
Max
Min
12
8
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
-
6
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
6
0
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB, LB Valid to End of Write
Write Recovery Time
tAW
tWP
tWP1
tBW
tWR
tWHZ
tDW
tDH
6
7
8
6
7
8
8
10
7
12
8
6
0
0
0
Write to Output High-Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
4
5
6
0
0
0
tOW
3
3
3
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
Revision 0.2
September 2001
- 5 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
tHZ(3,4,5)
tBHZ(3,4,5)
tOHZ
CS
tBA
UB, LB
OE
tBLZ(4,5)
tOE
tOLZ
tLZ(4,5)
Data out
High-Z
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)
tWC
tAW
Address
tWR(5)
OE
CS
tCW(3)
tBW
UB, LB
tAS(4)
WE
tWP(2)
tDW
tDH
High-Z
High-Z
Data in
Valid Data
tOHZ(6)
Data out
Revision 0.2
September 2001
- 6 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
tBW
CS
UB, LB
WE
tWP1(2)
tAS(4)
tDW
tDH
High-Z
Valid Data
Data in
(9)
(10)
tWHZ(6)
tOW
High-Z
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
CS
tAW
tWR(5)
tCW(3)
tBW
UB, LB
tAS(4)
WE
tWP(2)
tDH
tDW
High-Z
High-Z
Data in
Valid Data
tLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
Revision 0.2
September 2001
- 7 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
CS
tAW
tCW(3)
tWR(5)
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDH
tDW
High-Z
Data in
Valid Data
tBLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE
going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
I/O Pin
CS
WE
OE
LB
UB
Mode
Supply Current
I/O1~I/O8
I/O9~I/O16
H
L
L
X
H
X
X*
H
X
X
H
L
X
X
H
H
L
Not Select
High-Z
High-Z
ISB, ISB1
ICC
Output Disable
High-Z
High-Z
X
DOUT
High-Z
DOUT
DIN
High-Z
DOUT
DOUT
High-Z
DIN
L
L
H
L
L
Read
Write
ICC
ICC
H
L
L
L
H
L
X
H
L
High-Z
DIN
L
DIN
* X means Don¢t Care.
Revision 0.2
September 2001
- 8 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
Symbol
Test Condition
CS³ VCC-0.2V
Min.
Typ.
Max.
Unit
VCC for Data Retention
VDR
2.0
-
3.6
V
VCC=3.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
-
-
-
-
1.5
1.0
Data Retention Current
IDR
mA
VCC=2.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
Data Retention Set-Up Time
Recovery Time
tSDR
tRDR
See Data Retention
Wave form(below)
0
-
-
-
-
ns
5.0
ms
* The above parameters are also guaranteed at industrial temperature range.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Revision 0.2
September 2001
- 9 -
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
Units:millimeters/Inches
PACKAGE DIMENSIONS
44-SOJ-400
#44
#23
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
0.20
-0.05
0.008 +0.004
-0.002
#1
#22
28.98
1.141
0.69
MIN
MAX
0.027
25.58 ±0.12
1.125 ±0.005
1.19
)
(
0.047
3.76
1.27
MAX
0.148
(
)
0.050
0.10
0.004
MAX
+0.10
-0.05
0.43
+0.10
-0.05
0.71
0.017 +0.004
0.95
0.0375
1.27
0.050
-0.002
(
)
0.028+0.004
-0.002
44-TSOP2-400BF
Units:millimeters/Inches
0~8°
0.25
0.010
TYP
#23
#44
0.45 ~0.75
0.018 ~ 0.030
11.76 ±0.20
0.463 ±0.008
0.50
0.020
(
)
#1
#22
18.81
0.741
MAX
+ 0.075
- 0.035
+ 0.003
- 0.001
0.125
0.005
18.41 ±0.10
0.725 ±0.004
1.00 ±0.10
0.039 ±0.004
1.20
0.047
MAX
0.10
0.004
MAX
+0.10
- 0.05
+0.004
- 0.002
0.05
0.002
0.30
MIN
0.80
0.0315
0.805
0.032
(
)
0.012
Revision 0.2
September 2001
- 10
Preliminary
for AT&T
CMOS SRAM
K6R1016V1D-C/D-I/D-P
Unit: millimeters
PACKAGE DIMENSION
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View
B
Bottom View
B
B1
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.45
0.90
0.55
0.35
-
Max
-
A
B
-
5.90
-
Notes.
6.10
-
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
B1
C
6.90
-
7.10
-
C1
D
4. Typ: Typical
0.40
0.80
-
0.50
1.00
-
5. Y is coplanarity: 0.08(Max)
E
E1
E2
Y
0.30
-
0.40
0.08
Revision 0.2
September 2001
- 11
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