K6R1004V1A-JC15 [SAMSUNG]
Standard SRAM, 256KX4, 15ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
| 型号： | K6R1004V1A-JC15 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 256KX4, 15ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
K6R1004V1A-C
CMOS SRAM
Document Title
256Kx4 High Speed Static RAM(3.3V Operating), Revolutionary Pin out.
Revision History
Rev.No.
Rev. 0.0
Rev. 1.0
History
Draft Data
Remark
Initial release with Design Target.
Jan. 18th, 1995
Apr. 22th, 1995
Design Target
Preliminary
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Rev. 2.0
Rev. 3.0
Release to final Data Sheet.
2.1. Delete Preliminary.
Feb. 29th, 1996
Jul. 16th, 1996
Final
Final
Add Low Power Product and update D.C parameters.
3.1. Add Low Power Products with ISB1=0.5mA and Data Retention
Mode(L-ver. only).
3.2. Update D.C parameters.
Previous spec.
(12/15/17/20ns part)
160/155/150/145mA
30mA
Updated spec.
(12/15/17/20ns part)
130/125/125/120mA
20mA
ITEMS
ICC
ISB
ISB1
10mA
5mA
Rev. 4.0
Add Industrial Temperature Range parts.
Jun. 2nd, 1997
Final
4.1. Add Industrial Temperature Range parts with the same parame-
ters as Commercial Temperature Range parts.
4.1.1. Add K6R1004V1A parts for Industrial Temperature
Range.
4.1.2. Add ordering information.
4.1.3. Add the condition for operating at Industrial Temp. Range.
4.2. Add timing diagram to define tWP as ²(Timing Wave Form of
Write Cycle(CS=Controlled)².
Rev. 5.0
5.1. Delete L-version.
Feb. 25th, 1998
Final
5.2. Delete Data Rentention Characteristics and Wavetorm.
5.3. Delete 17ns Part.
5.4. Delete TSOP2 Package.
5.5. Delete Industrial Temperature Range Part.
5.6. Add Capacitive load of the test environment in A.C test load.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 5.0
February 1998
- 1 -
PRELIMINARY
CMOS SRAM
K6R1004V1A-C
256K x 4 Bit(with OE) High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
The K6R1004V1A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits. The
K6R1004V1A uses 4 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG¢s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
Standby (TTL)
(CMOS)
: 20mA(Max.)
5mA(Max.)
:
Operating K6R1004V1A-12 : 130mA(Max.)
K6R1004V1A-15 : 125mA(Max.)
K6R1004V1A-20 : 120mA(Max.)
• Single 3.3 ± 0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
high-density
high-speed
system
applications.
The
K6R1004V1A is packaged in a 400 mil 32-pin plastic SOJ.
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R1004V1A-J : 32-SOJ-400
PIN CONFIGURATION(Top View)
A17
A16
A15
A14
A13
OE
N.C
A0
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTIONAL BLOCK DIAGRAM
A1
A2
Clk Gen.
Pre-Charge Circuit
A3
CS
I/O1
Vcc
Vss
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O4
Vss
Vcc
I/O3
A12
A11
A10
A9
SOJ
Memory Array
512 Rows
512x4 Columns
I/O2 10
WE 11
A4
A5
A6
A7
12
13
14
15
Data
Cont.
I/O Circuit &
Column Select
I/O1~I/O4
A8
N.C
N.C 16
CLK
Gen.
A10
A12
A14 A16
A13 A15 A17
PIN FUNCTION
A9
A11
Pin Name
A0 - A17
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
WE
OE
CS
OE
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
I/O1 ~ I/O4
VCC
VSS
N.C
No Connection
Rev 5.0
February 1998
- 2 -
PRELIMINARY
CMOS SRAM
K6R1004V1A-C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
Unit
V
V
PD
W
Storage Temperature
TSTG
-65 to 150
0 to 70
°C
°C
Operating Temperature
TA
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Supply Voltage
Symbol
VCC
VSS
Min
3.0
0
Typ
Max
Unit
V
3.3
3.6
Ground
0
-
0
VCC + 0.3**
0.8
V
V
Input High Voltage
Input Low Voltage
VIH
2.2
-0.3*
V
VIL
-
* VIL(Min) = -2.0V a.c(Pulse Width £ 10ns) for I £ 20mA
** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 10ns) for I £ 20mA
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Test Conditions
Min
Max
Unit
ILI
VIN = VSS to VCC
-2
2
mA
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC
-2
2
mA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL,
IOUT=0mA
12ns
15ns
20ns
-
-
-
-
-
130
125
120
20
mA
Standby Current
ISB
Min. Cycle, CS=VIH
mA
mA
ISB1
f=0MHz, CS ³ VCC-0.2V,
5
VIN ³ VCC-0.2V or VIN£0.2V
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
0.4
-
V
V
IOH=-4mA
2.4
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
VI/O=0V
MIN
Max
8
Unit
Input/Output Capacitance
Input Capacitance
CI/O
CIN
-
-
pF
pF
VIN=0V
6
* Capacitance is sampled and not 100% tested.
Rev 5.0
February 1998
- 3 -
PRELIMINARY
CMOS SRAM
K6R1004V1A-C
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
RL = 50W
DOUT
319W
VL = 1.5V
DOUT
30pF*
ZO = 50W
353W
5pF*
* Including Scope and Jig Capacitance
* Capacitive Load consists of all components of the
test environment.
READ CYCLE
Parameter
K6R1004V1A-12 K6R1004V1A-15 K6R1004V1A-20
Symbol
Unit
Min
12
-
Max
Min
15
-
Max
Min
20
-
Max
Read Cycle Time
tRC
tAA
tCO
tOE
tLZ
-
12
12
6
-
15
15
7
-
20
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
-
3
-
3
-
3
-
tOLZ
tHZ
tOHZ
tOH
tPU
0
-
0
-
0
-
0
6
0
7
0
9
0
6
0
7
0
9
3
-
3
-
3
-
0
-
0
-
0
-
tPD
-
12
-
15
-
20
Rev 5.0
February 1998
- 4 -
PRELIMINARY
CMOS SRAM
K6R1004V1A-C
WRITE CYCLE
Parameter
K6R1004V1A-12
K6R1004V1A-15
K6R1004V1A-20
Symbol
Unit
Min
12
8
Max
Min
15
10
0
Max
Min
20
12
0
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
8
10
10
15
0
12
12
20
0
8
12
0
Write to Output High-Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
6
7
9
0
0
0
tOW
3
3
3
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tOHZ
tOH
tOE
OE
tOLZ
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
Rev 5.0
February 1998
- 5 -
PRELIMINARY
CMOS SRAM
K6R1004V1A-C
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured space ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100%
tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Data out
Valid Data
tOHZ(6)
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(9)
(10)
High-Z(8)
Data out
Rev 5.0
February 1998
- 6 -
PRELIMINARY
K6R1004V1A-C
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDH
tDW
High-Z
High-Z
Data in
Valid Data
tLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don¢t Care.
Rev 5.0
February 1998
- 7 -
PRELIMINARY
CMOS SRAM
K6R1004V1A-C
Units:millimeters/Inches
PACKAGE DIMENSIONS
32-SOJ-400
#32
#17
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
-0.05
0.20
0.008 +0.004
#1
#16
-0.002
0.69
0.027
21.36
0.841
MIN
MAX
20.95 ±0.12
0.825 ±0.005
1.30
0.051
1.30
0.051
(
(
)
)
0.10
0.004
3.76
0.148
MAX
MAX
+0.10
-0.05
+0.10
0.71
0.43
-0.05
1.27
0.050
0.95
0.0375
0.028 +0.004
(
)
+0.004
-0.002
0.017
-0.002
Rev 5.0
February 1998
- 8 -
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